Matt Turner [Wed, 16 Apr 2014 05:46:55 +0000 (22:46 -0700)]
i965/fs: Reduce restrictions on interference in register coalescing.
We previously only allowed coalescing registers that interfere (i.e.,
whose live ranges overlap) if the destination register's live range was
entirely inside the source's live range. This is unnecessary -- we only
need to check for interfering writes in the intersection of their live
ranges.
total instructions in shared programs: 1639470 -> 1638453 (-0.06%)
instructions in affected programs: 84751 -> 83734 (-1.20%)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Wed, 16 Apr 2014 01:59:24 +0000 (18:59 -0700)]
i965/fs: Give up in interference check if we see a WHILE.
Rather than any old control flow. Muchnick's algorithm just checks for
interfering writes between the MOV and the end of the program. Handling
this when you have backward branches is hard, so don't, but there's no
reason to bail if you see forward branches.
instructions in affected programs: 4270 -> 4248 (-0.52%)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Wed, 9 Apr 2014 21:31:10 +0000 (14:31 -0700)]
i965/fs: Simplify interference scan in register coalescing.
We were starting at the beginning of the instruction list, rather than
with the MOV instruction itself. This allows us to coalesce after
control flow.
Excluding the shaders from an unreleased title, the shader-db results:
total instructions in shared programs: 1603791 -> 1594215 (-0.60%)
instructions in affected programs: 678772 -> 669196 (-1.41%)
GAINED: 5
LOST: 0
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Wed, 9 Apr 2014 21:23:07 +0000 (14:23 -0700)]
i965/fs: Unindent can_coalesce_vars().
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Wed, 16 Apr 2014 01:15:59 +0000 (18:15 -0700)]
i965/fs: Recognize nop-MOV instructions early.
And avoid rewriting other instructions unnecessarily. Removes a few
self-moves we weren't able to handle because they were components of a
large VGRF.
instructions in affected programs: 830 -> 826 (-0.48%)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Tue, 15 Apr 2014 23:28:04 +0000 (16:28 -0700)]
i965/fs: Only sweep NOPs if register coalescing made progress.
Otherwise there's nothing to do.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Marek Olšák [Fri, 18 Apr 2014 11:25:11 +0000 (13:25 +0200)]
r600g,radeonsi: don't skip the context flush if a fence should be returned
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77589
Brian Paul [Thu, 17 Apr 2014 22:15:37 +0000 (16:15 -0600)]
svga: fix comment for emit_adjusted_vertex_attribs()
Brian Paul [Thu, 17 Apr 2014 18:27:53 +0000 (11:27 -0700)]
svga: compute need_swvfetch in svga_create_vertex_elements_state()
This saves us doing it at state validation time.
Reviewed-by: Matthew McClure <mcclurem@vmware.com>
Brian Paul [Thu, 17 Apr 2014 16:00:29 +0000 (09:00 -0700)]
svga: add VS code to set attribute W component to 1
There's a few 3-component vertex attribute formats that have no
equivalent SVGA3D_DECLTYPE_x format. Previously, we had to use
the swtnl code to handle them. This patch lets us use hwtnl for
more vertex attribute types by fetching 3-component attributes as
4-component attributes and explicitly setting the W component to 1.
This lets us handle PIPE_FORMAT_R16G16B16_SNORM/UNORM and
PIPE_FORMAT_R8G8B8_UNORM vertex attribs without using the swtnl path.
Fixes piglit normal3b3s GL_SHORT test.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Thu, 17 Apr 2014 15:54:47 +0000 (08:54 -0700)]
svga: implement support for signed byte vertex attributes
There's no SVGA3D_DECLTYPE that directly corresponds to
PIPE_FORMAT_R8G8B8_SNORM. Previously, we used the swtnl fallback
path to handle this but that's slow and causes invariance issues.
Now we fetch the attribute as SVGA3D_DECLTYPE_UBYTE4N and insert
some extra VS instructions to remap the attributes from the range
[0,1] to the range[-1,1].
Fixes Sauerbraten sw fallback.
Fixes piglit normal3b3s-invariance test.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Thu, 17 Apr 2014 15:45:25 +0000 (08:45 -0700)]
svga: move translated vertex declaration types into svga_velems_state
Now only translate the formats once in svga_create_vertex_elements_state().
And rename the array and use the proper SVGA3dDeclType type.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Tue, 15 Apr 2014 16:28:16 +0000 (09:28 -0700)]
Revert "svga: add work-around for Sauerbraten Z fighting issue"
This reverts commit
c875d6e57a817bb6a8163a8a98ebd2768ee91848.
Conflicts:
src/gallium/drivers/svga/svga_context.c
This work-around will no longer be needed after the next patch
which properly supports signed-byte vertex attributes.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Tue, 15 Apr 2014 16:18:46 +0000 (09:18 -0700)]
svga: use new inst_token_setp() helper function
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Tue, 15 Apr 2014 16:13:04 +0000 (09:13 -0700)]
svga: use new inst_token_predicated() helper function
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Kenneth Graunke [Thu, 17 Apr 2014 03:15:23 +0000 (20:15 -0700)]
i965: Retype pre-Gen6 varying pull load destination to UW.
This sets up the proper execution mask for sends in SIMD16 mode.
Fixes Piglit's glsl-fs-normalmatrix, glsl-fs-uniform-array-2,
glsl-fs-uniform-array-6, and glsl-fs-uniform-array-7 on Ironlake,
which regressed when I enabled SIMD16 pull parameter support in
commit
b207e88b25e526d0f1ada7b19605b880a27866dc.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Anuj Phogat [Fri, 4 Apr 2014 01:29:52 +0000 (18:29 -0700)]
mesa: Fix error condition for multisample proxy texture targets
Fixes failures in Khronos OpenGL CTS test proxy_textures_invalid_samples
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Anuj Phogat [Fri, 4 Apr 2014 23:49:19 +0000 (16:49 -0700)]
i965: Add glBlitFramebuffer to commands affected by conditional rendering
Fixes failures in Khronos OpenGL CTS test conditional_render_test9
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Anuj Phogat [Mon, 7 Apr 2014 18:20:55 +0000 (11:20 -0700)]
swrast: Add glBlitFramebuffer to commands affected by conditional rendering
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Anuj Phogat [Fri, 11 Apr 2014 17:56:50 +0000 (10:56 -0700)]
i965: Fix component mask and varying_to_slot mapping for gl_ViewportIndex
gl_ViewportIndex doesn't get its own varying slot. It is stored
in VARYING_SLOT_PSIZ.z. This patch fixes the issue for both gen7
and gen8 because gen7_upload_3dstate_so_decl_list() is shared
between them.
Fixes failures in OpenGL Khronos CTS test transform_feedback_builtins.
Makes new piglit test glsl-1.50-transform-feedback-builtins pass for
'gl_ViewportIndex'.
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Anuj Phogat [Fri, 11 Apr 2014 17:55:38 +0000 (10:55 -0700)]
i965: Fix component mask and varying_to_slot mapping for gl_Layer
gl_Layer doesn't get its own varying slot. It is stored in
VARYING_SLOT_PSIZ.y. This patch fixes the issue for both gen7
and gen8 because gen7_upload_3dstate_so_decl_list() is shared
between them.
Fixes failures in OpenGL Khronos CTS test transform_feedback_builtins.
Makes new piglit test glsl-1.50-transform-feedback-builtins pass for
'gl_Layer'.
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Anuj Phogat [Mon, 14 Apr 2014 21:09:32 +0000 (14:09 -0700)]
i965: Put an assertion to check valid varying_to_slot[varying]
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Darren Powell [Mon, 31 Mar 2014 22:00:28 +0000 (18:00 -0400)]
radeonsi: Added Diag Handler to receive LLVM Error messages
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Marek Olšák [Wed, 16 Apr 2014 12:02:26 +0000 (14:02 +0200)]
winsys/radeon: remove some unused code
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Mon, 14 Apr 2014 13:32:39 +0000 (15:32 +0200)]
winsys/radeon: remove is_handle_added array
Use index -1 if a buffer is not added.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Mon, 14 Apr 2014 13:25:43 +0000 (15:25 +0200)]
winsys/radeon: remove local variable reloc from radeon_get_reloc
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Mon, 14 Apr 2014 13:24:04 +0000 (15:24 +0200)]
winsys/radeon: remove parameter reloc from radeon_get_reloc
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
José Fonseca [Wed, 16 Apr 2014 16:45:56 +0000 (17:45 +0100)]
util: Add __declspec(noreturn) to _debug_assert_fail().
Mostly for consistency; as MSVC's static source code analysis doesn't
seem to rely on assertions, but instead on different kind of source
annotations( http://msdn.microsoft.com/en-us/library/hh916383.aspx ).
Reviewed-by: Brian Paul <brianp@vmware.com>
José Fonseca [Wed, 16 Apr 2014 16:36:51 +0000 (17:36 +0100)]
auxiliary/os,auxiliary/util: Fix the `‘noreturn’ function does return` warning.
Now that _debug_assert_fail() has the noreturn attribute, it is better
that execution truly never returns. Not just for sake of silencing the
warning, but because the code at the return IP address may be invalid or
lead to inconsistent results.
This removes support for the GALLIUM_ABORT_ON_ASSERT debugging
environment variable, but between the usefulness of
GALLIUM_ABORT_ON_ASSERT and better static code analysis I think better
static code analysis wins.
Reviewed-by: Brian Paul <brianp@vmware.com>
José Fonseca [Wed, 16 Apr 2014 16:26:05 +0000 (17:26 +0100)]
scons: Enable building through Clang Static Analyzer.
Same intent as commit
a45a50a4828e1357e9555474bc127c5585b3a420,
but this the C compiler is detected via C-preprocessor macros,
similar to how autotools do it, as that seems to be the most
reliable method.
Reviewed-by: Brian Paul <brianp@vmware.com>
Maarten Lankhorst [Thu, 17 Apr 2014 08:34:10 +0000 (10:34 +0200)]
gallium glsl: Fix crash with piglit fs-deref-literal-array-of-structs.shader_test
This allows the following shader code to work without a weird crash:
struct Foo {
int value[1];
};
int actual_value = Foo[2](Foo(int[1](100)), Foo(int[1](200)))[i].value[0];
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Maarten Lankhorst [Tue, 15 Apr 2014 15:35:31 +0000 (17:35 +0200)]
nouveau/vdec: small fixes to h264 handling
nouveau_vp3_inter_sizes requires sliec_count as argument just
as the other places that call it from h264 code do. Hopefully
fixes something.
Fix the status_vp code to allow status == 0 too, when processing
hasn't started yet.
set h264->second_field correctly.
Thomas Hellstrom [Tue, 8 Apr 2014 20:48:51 +0000 (16:48 -0400)]
st/xa: Cache render target surface
Otherwise it will trick the gallium driver into thinking that the render
target has actually changed (due to different pipe_surface pointing to
same underlying pipe_resource). This is really badness for tiling GPUs
like adreno.
This also appears to fix a rendering error with Motif on vmwgfx.
Why that is is still under investigation.
Based on an idea by Rob Clark.
Cc: "10.0 10.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Tue, 8 Apr 2014 20:48:50 +0000 (16:48 -0400)]
st/xa: scissor to help tilers
Keep track of the maximal bounds of all the operations and set scissor
accordingly. For tiling GPU's this can be a big win by reducing the
memory bandwidth spent moving pixels from system memory to tile buffer
and back.
You could imagine being more sophisticated and splitting up disjoint
operations. But this simplistic approach is good enough for the common
cases.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
Rob Clark [Tue, 8 Apr 2014 20:48:49 +0000 (16:48 -0400)]
st/xa: remove unneeded args
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
Iago Toral Quiroga [Tue, 15 Apr 2014 10:30:40 +0000 (12:30 +0200)]
glsl: Small optimization for constant conditionals
Once the relevant branch has been identified do not iterate over the
instructions in the branch, do a linked list insertion instead to avoid the
loop.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Mon, 14 Apr 2014 07:14:23 +0000 (09:14 +0200)]
glsl: Fix incorrect indentation.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Chris Forbes [Wed, 16 Apr 2014 02:15:27 +0000 (14:15 +1200)]
meta: Clip src/dest rects in BlitFramebuffer, using the scissor
Fixes piglit's fbo-blit-stretch test on drivers which use the meta path.
(i965: should fix Broadwell, but also fixes Sandybridge/Ivybridge/Haswell
since this test falls off the blorp path now due to format conversion)
V2: Use scissor instead of just mangling the rects, to avoid texcoord
rounding problems. (Thanks Marek)
V3: Rebase on Eric's CTSI meta changes; re-add _mesa_update_state in the
CTSI path so that _mesa_clip_blit sees the correct bounds.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77414
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Tested-by: Anuj Phogat <anuj.phogat@gmail.com>
Samuel Iglesias Gonsalvez [Thu, 3 Apr 2014 06:30:06 +0000 (08:30 +0200)]
mesa: fix check for dummy renderbuffer in _mesa_FramebufferRenderbufferEXT()
According to the spec:
<renderbuffertarget> must be RENDERBUFFER and <renderbuffer>
should be set to the name of the renderbuffer object to be
attached to the framebuffer. <renderbuffer> must be either
zero or the name of an existing renderbuffer object of type
<renderbuffertarget>, otherwise an INVALID_OPERATION error is
generated.
This patch changes the previous returned GL_INVALID_VALUE to
GL_INVALID_OPERATION.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76894
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Matt Turner [Wed, 9 Apr 2014 20:38:14 +0000 (13:38 -0700)]
i965: Don't make instructions with a null dest a barrier to scheduling.
Now that we properly track accumulator dependencies, the scheduler is
able to schedule instructions between the mach and mov in the common
the integer multiplication pattern:
mul acc0, x, y
mach null, x, y
mov dest, acc0
Since a null destination implies no dependency on the destination, we
can also safely schedule instructions (that don't write the accumulator)
between the mul and mach.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Juha-Pekka Heikkila [Fri, 28 Mar 2014 13:28:33 +0000 (15:28 +0200)]
i965/fs: Change fs_visitor::emit_lrp to use MAC for gen<6
This allows us to emit ADD/MUL/MAC instead of MUL/ADD/MUL/ADD,
saving one instruction and two temporary registers.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Juha-Pekka Heikkila [Fri, 28 Mar 2014 13:28:32 +0000 (15:28 +0200)]
i965/fs: Add support for the MAC instruction.
This allows us to generate the MAC (multiply-accumulate) instruction,
which can be used to implement some expressions in fewer instructions
than doing a series of MUL and ADDs.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Juha-Pekka Heikkila [Fri, 28 Mar 2014 13:28:31 +0000 (15:28 +0200)]
i965/vec4: Change vec4_visitor::emit_lrp to use MAC for gen<6
This allows us to emit ADD/MUL/MAC instead of MUL/ADD/MUL/ADD,
saving one instruction and two temporary registers.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Juha-Pekka Heikkila [Fri, 28 Mar 2014 13:28:30 +0000 (15:28 +0200)]
i965/vec4: Add support for the MAC instruction.
This allows us to generate the MAC (multiply-accumulate) instruction,
which can be used to implement some expressions in fewer instructions
than doing a series of MUL and ADDs.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Juha-Pekka Heikkila [Fri, 4 Apr 2014 13:51:59 +0000 (16:51 +0300)]
i965: Add writes_accumulator flag
Our hardware has an "accumulator" register, which can be used to store
intermediate results across multiple instructions. Many instructions
can implicitly write a value to the accumulator in addition to their
normal destination register. This is enabled by the "AccWrEn" flag.
This patch introduces a new flag, inst->writes_accumulator, which
allows us to express the AccWrEn notion in the IR. It also creates a
n ALU2_ACC macro to easily define emitters for instructions that
implicitly write the accumulator.
Previously, we only supported implicit accumulator writes from the
ADDC, SUBB, and MACH instructions. We always enabled them on those
instructions, and left them disabled for other instructions.
To take advantage of the MAC (multiply-accumulate) instruction, we
need to be able to set AccWrEn on other types of instructions.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Juha-Pekka Heikkila [Wed, 9 Apr 2014 19:08:12 +0000 (12:08 -0700)]
i965: Add is_accumulator() function.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Matt Turner [Wed, 9 Apr 2014 19:01:49 +0000 (12:01 -0700)]
i965: Add reads_accumulator_implicitly() function.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Anuj Phogat [Wed, 19 Mar 2014 00:01:19 +0000 (17:01 -0700)]
mesa: Add error condition for integer formats in glGetTexImage()
OpenGL 4.0 spec, page 306 suggests an INVALID_OPERATION in glGetTexImage
if :
"format is one of the integer formats in table 3.3 and the internal
format of the texture image is not integer, or format is not one of
the integer formats in table 3.3 and the internal format is integer."
V2: Use helper function _mesa_is_format_integer()
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Anuj Phogat [Tue, 25 Mar 2014 20:00:12 +0000 (13:00 -0700)]
mesa: Add helper function _mesa_is_format_integer()
This function will be used in the following patch.
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Anuj Phogat [Thu, 13 Mar 2014 01:16:21 +0000 (18:16 -0700)]
mesa: Fix glGetVertexAttribi(GL_VERTEX_ATTRIB_ARRAY_SIZE)
mesa currently returns 4 when GL_VERTEX_ATTRIB_ARRAY_SIZE is queried
for a vertex array initially set up with size=GL_BGRA. This patch
makes changes to return size=GL_BGRA as required by the spec.
Fixes Khronos OpenGL CTS test: vertex_array_bgra_basic.test
V2: Use array->Format instead of adding a new variable
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Anuj Phogat [Sat, 8 Mar 2014 00:48:35 +0000 (16:48 -0800)]
glsl: Fix copy-paste error in linker_warning()
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Michel Dänzer [Wed, 16 Apr 2014 06:00:09 +0000 (15:00 +0900)]
r600g: Disable LLVM by default at runtime for graphics
For graphics, the LLVM compiler backend currently has many shortcomings
compared to the non-LLVM one. E.g. it can't handle geometry shaders yet,
but that's just the tip of the iceberg.
So building Mesa with --enable-r600-llvm-compiler is currently not
recommended for anyone who doesn't want to work on fixing those issues.
However, for protection of users who end up enabling it anyway for some
reason, let's disable the LLVM backend at runtime by default. It can be
enabled with the environment variable R600_DEBUG=llvm.
Cc: "10.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Roland Scheidegger [Wed, 16 Apr 2014 01:46:20 +0000 (03:46 +0200)]
gallivm: fix compilation with llvm 3.5 r206241+
Just adjust to the ever-changing API, pass in MCContext when creating the
MCDisassembler.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
José Fonseca [Wed, 16 Apr 2014 12:13:48 +0000 (13:13 +0100)]
Revert "scons: Enable building through Clang Static Analyzer."
This reverts commit
a45a50a4828e1357e9555474bc127c5585b3a420.
Unfortunately gcc dumps argv[0] as the first word of --version, so it is
unreliable for detecting gcc.
In particular `cc --version` and `i686-w64-mingw32-gcc --version` give
wrong results.
A better solution needs to be found -- most likely using C-preprocessing
like autotools does. Revert for now.
Marek Olšák [Sat, 12 Apr 2014 16:12:11 +0000 (18:12 +0200)]
r600g,radeonsi: share some of gfx flush code
Reviewed-by: Christian König <christian.koenig@amd.com>
Marek Olšák [Sat, 12 Apr 2014 15:57:32 +0000 (17:57 +0200)]
r600g,radeonsi: share r600_flush_from_st
Reviewed-by: Christian König <christian.koenig@amd.com>
Marek Olšák [Sat, 12 Apr 2014 15:53:57 +0000 (17:53 +0200)]
r600g: merge r600_flush with r600_context_flush
Reviewed-by: Christian König <christian.koenig@amd.com>
Marek Olšák [Sat, 12 Apr 2014 15:34:44 +0000 (17:34 +0200)]
radeonsi: merge si_flush with si_context_flush
This also removes si_flush_gfx_ring.
Reviewed-by: Christian König <christian.koenig@amd.com>
Marek Olšák [Sat, 12 Apr 2014 15:01:52 +0000 (17:01 +0200)]
gallium/radeon: create and return a fence in the flush function
All flush functions get a fence parameter. cs_create_fence is removed.
Reviewed-by: Christian König <christian.koenig@amd.com>
Marek Olšák [Fri, 11 Apr 2014 20:40:14 +0000 (22:40 +0200)]
r600g: remove redundant r600_flush_dma_from_winsys
Reviewed-by: Christian König <christian.koenig@amd.com>
Marek Olšák [Fri, 11 Apr 2014 20:14:27 +0000 (22:14 +0200)]
winsys/radeon: fold cs_set_flush_callback into cs_create
Reviewed-by: Christian König <christian.koenig@amd.com>
Marek Olšák [Fri, 11 Apr 2014 19:51:12 +0000 (21:51 +0200)]
radeonsi: cleanup redundant computation of flush flags and rename a function
Reviewed-by: Christian König <christian.koenig@amd.com>
Marek Olšák [Fri, 11 Apr 2014 19:41:05 +0000 (21:41 +0200)]
r600g: remove redundant r600_flush_from_winsys
Reviewed-by: Christian König <christian.koenig@amd.com>
Marek Olšák [Fri, 11 Apr 2014 18:34:46 +0000 (20:34 +0200)]
winsys/radeon: remove cs_write_reloc, add simpler cs_get_reloc
The only difference is that it doesn't write to the CS and only returns
the index.
Reviewed-by: Christian König <christian.koenig@amd.com>
Marek Olšák [Fri, 11 Apr 2014 11:20:02 +0000 (13:20 +0200)]
winsys/radeon: consolidate hash table lookup
I should have done this long ago.
Reviewed-by: Christian König <christian.koenig@amd.com>
José Fonseca [Mon, 14 Apr 2014 13:31:02 +0000 (14:31 +0100)]
scons: Add an analyze option.
For Clang static code analyzer, the scan-build script will produce more
comprehensive output. Nevertheless you can invoke it as
CC=clang CXX=clang++ scons analyze=1
For MSVC this is the best way to use its static code analysis. Simply
invoke as
scons analyze=1
Reviewed-by: Brian Paul <brianp@vmware.com>
José Fonseca [Mon, 14 Apr 2014 11:13:32 +0000 (12:13 +0100)]
util/u_debug: Add noreturn attribute to _debug_assert_fail().
As recommended by
http://clang-analyzer.llvm.org/annotations.html#attr_noreturn
Reviewed-by: Brian Paul <brianp@vmware.com>
José Fonseca [Mon, 14 Apr 2014 11:10:25 +0000 (12:10 +0100)]
scons: Enable building through Clang Static Analyzer.
By accurately detecting gcc/clang through --version option instead
of executable name.
Clang Static Analyzer reports many issues, most false positives, but it
found at least one real and subtle use-after-free issue
in st_texture_get_sampler_view():
http://people.freedesktop.org/~jrfonseca/scan-build-2014-04-14-1/report-869047.html#EndPath
Reviewed-by: Brian Paul <brianp@vmware.com>
Iago Toral Quiroga [Fri, 4 Apr 2014 13:11:15 +0000 (15:11 +0200)]
glsl: Properly handle blocks that define the same field name.
Currently we can have name space collisions between blocks that define the same
fields. For example:
in block
{
vec4 Color;
} In[];
out block
{
vec4 Color;
} Out;
These two blocks will assign the same interface name (block.Color) to the Color
field in flatten_named_interface_blocks_declarations.cpp, leading to havoc.
This was breaking badly the gl-320-primitive-shading test from ogl-samples.
The patch uses the block instance name to avoid collisions, producing names
like block.In.Color and block.Out.Color to avoid the name clash.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76394
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Michel Dänzer [Tue, 15 Apr 2014 05:45:13 +0000 (14:45 +0900)]
r600g/radeonsi: Map transfer staging texture unsynchronized when possible
The transfer staging texture is always freshly allocated, so for write-only
transfers we don't need to explicitly wait for the BO to become idle.
Squeezes a few hundered MB/s more out of x11perf -shmput500 with glamor.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Matt Turner [Wed, 16 Apr 2014 00:27:55 +0000 (17:27 -0700)]
Revert "i965/fs: Only sweep NOPs if register coalescing made progress."
This reverts commit
f092e8951ce5212ba3cbb382ce3a6666eb6c9bed.
Didn't mean to push this...
Matt Turner [Tue, 15 Apr 2014 23:28:04 +0000 (16:28 -0700)]
i965/fs: Only sweep NOPs if register coalescing made progress.
Otherwise there's nothing to do.
Eric Anholt [Mon, 14 Apr 2014 23:52:43 +0000 (16:52 -0700)]
i965: Fix buffer overruns in MSAA MCS buffer clearing.
This manifested as rendering failures or sometimes GPU hangs in
compositors when they accidentally got MSAA visuals due to a bug in the X
Server. Today we decided that the problem in compositors was equivalent
to a corruption bug we'd noticed recently in resizing MSAA-visual
glxgears, and debugging got a lot easier.
When we allocate our MCS MT, libdrm takes the size we request, aligns it
to Y tile size (blowing it up from 300x300=900000 bytes to 384*320=122880
bytes, 30 pages), then puts it into a power-of-two-sized BO (131072 bytes,
32 pages). Because it's Y tiled, we attach a 384-byte-stride fence to it.
When we memset by the BO size in Mesa, between bytes 122880 and 131072 the
data gets stored to the first 20 or so scanlines of each of the 3 tiled
pages in that row, even though only 2 of those pages were allocated by
libdrm. In the glxgears case, the missing 3rd page happened to
consistently be the static VBO that got mapped right after the first MCS
allocation, so corruption only appeared once window resize made us throw
out the old MCS and then allocate the same BO to back the new MCS.
Instead, just memset the amount of data we actually asked libdrm to
allocate for, which will be smaller (more efficient) and not overrun.
Thanks go to Kenneth for doing most of the hard debugging to eliminate a
lot of the search space for the bug.
Cc: "10.0 10.1" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77207
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Sat, 1 Mar 2014 00:39:03 +0000 (16:39 -0800)]
meta: Add support for MSAA resolves from 2D_MS_ARRAY textures.
We don't have any piglit tests for this currently.
v2: Use vec3s for the texcoords so it has some hope of working.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Fri, 28 Feb 2014 21:23:25 +0000 (13:23 -0800)]
meta: Add an accelerated glCopyTexSubImage using glBlitFramebuffer.
You'll note from the previous commits that there's something of a loop
here: You call CTSI, which calls BlitFB, then if things go wrong that
falls back to CTSI. As a result, meta CTSI reaches over into blitfb to
tell it "no, don't try that fallback".
v2: Drop the _mesa_update_state(), which was only necessary due to use of
_mesa_clip_blit() in _mesa_meta_BlitFramebuffer() in another patch
series.
v3: Drop an _EXT suffix I copy-and-pasted.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v2)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Tue, 8 Apr 2014 20:34:39 +0000 (13:34 -0700)]
meta: Add support for CUBE_MAP_ARRAY to generatemipmap.
I added support to bind_fbo_image in the process of building meta
CopyTexSubImage, and found that it broke generatemipmap because previously
we would just throw a GL error there and then end up with an incomplete
FBO and fallback.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Mon, 17 Mar 2014 23:45:48 +0000 (16:45 -0700)]
meta: Infer bind_fbo_image parameters from an incoming image.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Mon, 17 Mar 2014 23:26:42 +0000 (16:26 -0700)]
meta: Move bind_fbo_image() code back to meta.c, to reuse it elsewhere.
I need to do the same code again for CopyTexSubImage().
v2: Drop incorrect, not-terribly-useful comment (review by Ken)
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v1)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Fri, 28 Feb 2014 20:47:54 +0000 (12:47 -0800)]
meta: Refactor the BlitFramebuffer depth CopyTexImage fallback.
This avoids a ReadPixels() if there's accelerated CopyTexImage present.
It now requires GLSL as opposed to just fragment programs, but we don't
have any drivers that do ARB_fp but not GLSL.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Fri, 28 Feb 2014 20:36:02 +0000 (12:36 -0800)]
meta: Refactor the BlitFramebuffer color CopyTexImage fallback.
There shouldn't be anything special about copying out a subset of the src
rb to a temp before texturing from it, so just do it when we're figuring
out our src texture binding.
This drops Anuj's change to copy an extra border of 1 pixel around the src
area. I can't see how that change could be valid, and presumably if
there's some filtering problem at edges we just need to set the right
wrap mode.
v2: Don't fall back to swrast on non-2D/RECT/2D_MS textures when we can
still CopyTexSubImage. Fixes a segfault regression on i965 with
gl-3.2-layered-rendering-blit.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v1)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
Tested-by: Anuj Phogat <anuj.phogat@gmail.com>
Eric Anholt [Fri, 28 Feb 2014 20:19:09 +0000 (12:19 -0800)]
meta: Drop blit src size fallback.
I think we can assert that renderbuffer size is <= maximum 2D texture
size. Our source coordinates should have already been clipped to the src
renderbuffer size, but haven't actually (so we could potentially have
trouble if there's scaling, and we're in the CopyTexImage path that tries
to use src size). However, this texture size dependency was blocking the
next refactors, so I'm not sure if we want to go ahead with this series
before we get the clipping sorted out or not.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Mike Stroyan [Thu, 13 Feb 2014 00:24:55 +0000 (17:24 -0700)]
i965: Avoid dependency hints on math opcodes
Putting NoDDClr and NoDDChk dependency control on instruction
sequences that include math opcodes can cause corruption of channels.
Treat math opcodes like send opcodes and suppress dependency hinting.
Signed-off-by: Mike Stroyan <mike@LunarG.com>
Tested-by: Tony Bertapelli <anthony.p.bertapelli@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Matt Turner <mattst88@gmail.com>
Matt Turner [Sat, 12 Apr 2014 05:27:31 +0000 (22:27 -0700)]
i965: Expand INTEL_DEBUG to uint64_t.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Sat, 12 Apr 2014 04:11:38 +0000 (21:11 -0700)]
dri: Expand driParseDebugString return value to uint64_t.
Users will downcast if they don't have >32 debug flags.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Mon, 14 Apr 2014 18:18:59 +0000 (11:18 -0700)]
i965/fs: Remove dead_code_eliminate_local().
Subsumed by the new dead_code_eliminate() function. No shader-db
changes.
Reviewed-by: Eric Anholt <eric@anholt.net>
Matt Turner [Mon, 14 Apr 2014 18:17:13 +0000 (11:17 -0700)]
i965/fs: Clear variable from live-set if it's completely overwritten.
One program affected:
instructions in affected programs: 246 -> 244 (-0.81%)
Reviewed-by: Eric Anholt <eric@anholt.net>
Matt Turner [Sun, 13 Apr 2014 00:40:18 +0000 (17:40 -0700)]
i965/fs: Reimplement dead_code_elimination().
total instructions in shared programs: 1653399 -> 1651790 (-0.10%)
instructions in affected programs: 92157 -> 90548 (-1.75%)
GAINED: 2
LOST: 2
Also significantly reduces the number of optimization loop iterations:
total loop iterations in shared programs: 39724 -> 31651 (-20.32%)
loop iterations in affected programs: 21617 -> 13544 (-37.35%)
Including some great pathological cases, like 29 -> 3 in Strike Suit
Zero and 24 -> 3 in Dota2.
Reviewed-by: Eric Anholt <eric@anholt.net>
Matt Turner [Mon, 24 Mar 2014 20:23:13 +0000 (13:23 -0700)]
i965/vec4: Let DCE eliminate dead writes in other basic blocks.
We previously stopped searching for unread writes after encountering
control flow, but we can instead just search backwards until we hit
control flow.
instructions in affected programs: 22854 -> 22194 (-2.89%)
Matt Turner [Sun, 30 Mar 2014 00:44:45 +0000 (17:44 -0700)]
i965/gs: Add dummy source to prepare_channel_masks instruction.
The generator uses its destination as a source implicitly, which breaks
some assumptions in dead code elimination. Giving the instruction a
source allows us to reason about it better.
Matt Turner [Sun, 6 Apr 2014 05:03:04 +0000 (22:03 -0700)]
glsl: Use M_PI_* macros.
Notice our multiple values for M_PI_2, which rounded ...32 up to
...4 and ...5.
Kenneth Graunke [Sun, 13 Apr 2014 21:19:03 +0000 (14:19 -0700)]
i965: Disable Z16 in all APIs.
We originally thought that GL 3.0 required GL_DEPTH_COMPONENT16 to map
exactly to Z16. However, we misread the specification, thanks in part
to LaTeX reordering the tables in the PDF.
Page 180 of the GL 3.0 specification (glspec30.
20080923.pdf) says:
"[...] memory allocation per texture component is assigned by the GL to
match the allocations listed in tables 3.16-3.18 as closely as possible.
[...]
Required Texture Formats
[...]
In addition, implementations are required to support the following sized
internal formats. Requesting one of these internal formats for any
texture type will allocate exactly the internal component sizes and
types shown for that format in tables 3.16-3.17:"
Notably, however, GL_DEPTH_COMPONENT16 does /not/ appear in table 3.16
or table 3.17. It appears in table 3.18, where the "exact" rule doesn't
apply, and it falls back to the "closely as possible" rule.
The confusing part is that the ordering of the tables in the PDF is:
Table 3.16 (pages 182-184)
Table 3.18 (bottom of page 184 to top of 185)
Table 3.17 (page 185)
Presumably, people saw table 3.16, then saw the table immediately
following with DEPTH_COMPONENT* formats, and assumed it was 3.17.
Based on a patch by Chia-I Wu, but without the driconf option to force
Z16 to be used. It's not required, and there's apparently no benefit
to actually using it.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chia-I Wu <olv@lunarg.com>
Kenneth Graunke [Sun, 13 Apr 2014 21:15:49 +0000 (14:15 -0700)]
i965: Update comments about Z16 being slow.
We've learned a few things since we originally disabled Z16; this attempts
to summarize the issue. I am no expert on this subject, though, so the
comment may not be totally accurate.
I did some benchmarking on GM45 and Ironlake, and discovered that for
GLBenchmark 2.7 EgyptHD, using Z16 was 3% slower on GM45 (n=15), and
4.5% slower on Ironlake (n=95). So, we can drop the "on Ivybridge"
aspect of the comment - it's always slower.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chia-I Wu <olv@lunarg.com>
Michel Dänzer [Thu, 10 Apr 2014 09:15:55 +0000 (18:15 +0900)]
r600g/radeonsi: Use caching buffer manager for textures as well
Significantly reduces BO allocation / destruction overhead for transfers,
e.g. measurable via x11perf -shm{ge,pu}t* with glamor.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Jordan Justen [Sat, 12 Apr 2014 00:22:46 +0000 (17:22 -0700)]
i965/gen8: add debug code to show FS disasm with jump locations
Copied from similar code in gen8_vec4_generator.cpp.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Chia-I Wu [Thu, 10 Apr 2014 06:59:05 +0000 (14:59 +0800)]
ilo: remove GPE state size estimation
Use size defines from genhw.
Chia-I Wu [Wed, 9 Apr 2014 18:45:23 +0000 (02:45 +0800)]
ilo: remove GPE command size estimation
Use size defines from genhw.
Chia-I Wu [Sun, 13 Apr 2014 16:55:01 +0000 (00:55 +0800)]
ilo: remove unused headers
Remove intel_*.h. brw_*.h is still needed by the state dumper and
disassembler.
Chia-I Wu [Sun, 13 Apr 2014 12:07:40 +0000 (20:07 +0800)]
ilo: use only defines from genhw headers
Stop including classic driver headers in genhw.h, with some formatting fixes.
Chia-I Wu [Sun, 13 Apr 2014 15:37:04 +0000 (23:37 +0800)]
ilo: scripted conversion to genhw headers
Hopefully my four hundred line sed script is correct.
Chia-I Wu [Sat, 12 Apr 2014 16:33:00 +0000 (00:33 +0800)]
ilo: add genhw headers
All except genhw.h are generated by https://github.com/olvaffe/envytools/.
intel_chipset.h is deprecated.