Xiang, Haihao [Tue, 8 Jan 2013 02:31:43 +0000 (10:31 +0800)]
Always set Fix_Prev_Mb_skipped in AVC_BSD_OBJECT command
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=57720
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Tobias Jakobi [Sun, 30 Dec 2012 11:44:28 +0000 (12:44 +0100)]
naive fix in avc_get_first_mb_bit_offset_with_epb
Bugzilla:://bugs.freedesktop.org/show_bug.cgi?id=58875
Signed-off-by: Tobias Jakobi <liquid.acid@gmx.net>
Gwenole Beauchesne [Thu, 3 Jan 2013 14:57:25 +0000 (15:57 +0100)]
subpicture: don't overallocate palette on 64-bit systems.
Allocate the exact amount of memory for VA image palettes on 64-bit
systems. No more.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Gwenole Beauchesne [Thu, 3 Jan 2013 14:47:40 +0000 (15:47 +0100)]
subpicture: fix creation of IA88/AI88 subpicture images.
IA88 format is 16bpp, with one byte for alpha and one byte for the color
index. Besides, a palette with 256 entries is also needed.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Gwenole Beauchesne [Thu, 3 Jan 2013 14:23:42 +0000 (15:23 +0100)]
subpicture: expose "global-alpha" is supported.
Make sure vaQuerySubpictureFormats() reports that "global-alpha" is
supported, along with "screen-coords".
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Xiang, Haihao [Fri, 21 Dec 2012 02:25:57 +0000 (10:25 +0800)]
Render: Update the maximum number of WM threads
The number is stolen from Mesa.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=57323
Signe-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Tested-by: zaverel <zaverel@free.fr>
Xiang, Haihao [Fri, 21 Dec 2012 01:48:47 +0000 (09:48 +0800)]
Add IS_SNB_GT1/IS_SNB_GT2/IS_IVB_GT1/IS_IVB_GT2 and remove IS_HSW_ULT and IS_HSW_GT2_PLUS
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Li, Xiaowei A [Tue, 27 Nov 2012 02:28:41 +0000 (10:28 +0800)]
Fix H264 YUV400 surface render issue
All decoded frame are considered as NV12 format in driver's,
for YUV400 format senerios, we need set the chroma component
of NV12 to a constant value(0x80), otherwise the converted ARGB
from NV12 format is not correct and cause render issue.
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
(cherry picked from commit
3ac4256d3aba3db757d086a7e7496d95cd8b0da4)
Li,Xiaowei [Tue, 27 Nov 2012 01:08:29 +0000 (09:08 +0800)]
Render: Add four subpicture support
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
(cherry picked from commit
a7c42530c312bdb1c53cce49b6a86f47de2ccb65)
Conflicts:
src/i965_drv_video.c
Li,Xiaowei [Fri, 23 Nov 2012 07:24:26 +0000 (15:24 +0800)]
Render: Add AI88/IA88 surface foramt support for subpicture
Signed off by: Li,Xiaowei A <xiaowei.a.li@intel.com>
(cherry picked from commit
6a641d0feda6ded2abcd907c4ceb5a45f134990d)
Conflicts:
src/i965_drv_video.h
Li,Xiaowei [Fri, 23 Nov 2012 03:13:48 +0000 (11:13 +0800)]
Render: Add global alpha support for subpicture
Signed-off-by: Li Xiaowei A <xiaowei.a.li@intel.com>
(cherry picked from commit
06998b16f470ba49c2af0372e2ef7fee74b1d5b6)
Joe Konno [Tue, 20 Nov 2012 15:42:27 +0000 (07:42 -0800)]
configure: add missing dependency to libm.
Build broke when trying to compile with expressive debug CFLAGS (-g3).
This was root-caused to the lack of the "-lm" linker flag. By adding a
simple autoconf check we ensure that libm is linked.
More specifically, recent VEBOX changes depend on cos() and sin() math
functions.
Signed-off-by: Joe Konno <joe.konno@intel.com>
Rob Bradford [Fri, 19 Oct 2012 17:49:56 +0000 (18:49 +0100)]
wayland: port to 1.0 protocol.
Previously some of the functions that this code relied upon were exported as
symbols from the wayland-client .so. However those are now autogenerated
instead and are thus included as static inlines in the header file. Therefore
we must recreated the desired functions using the function pointers found in
the vtable.
Also following the removal of the globals hash from the client code it is
necessary to setup a registry with a listener on it to receive the global
objects.
Signed-off-by: Rob Bradford <rob@linux.intel.com>
Xiang, Haihao [Fri, 9 Nov 2012 01:59:32 +0000 (09:59 +0800)]
Bump new version for development
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 9 Nov 2012 01:42:46 +0000 (09:42 +0800)]
intel driver 1.0.19
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Gwenole Beauchesne [Mon, 5 Nov 2012 08:32:22 +0000 (09:32 +0100)]
Fix build and remaining compilation warnings.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Gwenole Beauchesne [Mon, 5 Nov 2012 08:29:01 +0000 (09:29 +0100)]
NEWS: minor wording fixes.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Xiang, Haihao [Fri, 2 Nov 2012 01:31:28 +0000 (09:31 +0800)]
Update NEWS
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 1 Nov 2012 07:41:20 +0000 (15:41 +0800)]
Warning fixes
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 1 Nov 2012 06:27:06 +0000 (14:27 +0800)]
Encoding: use a separated command buffer
The command buffer is adaptive to the size of the frame.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 2 Mar 2012 07:40:51 +0000 (15:40 +0800)]
Add two helper functions for batchbuffer
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
695c0b25d4f77d0b443ec97cfcb42f59b4df7e71)
Xiang, Haihao [Thu, 1 Nov 2012 01:39:29 +0000 (09:39 +0800)]
Encoding: modify function to fill command into a specified batch buffer
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Zhao Yakui [Wed, 31 Oct 2012 08:47:57 +0000 (16:47 +0800)]
Allow to create batchbuffer based on the expected buffer size
This is to support the 4Kx4K encoding on Haswell. Otherwise the default batch
buffer size can't hold the encoding command for 4Kx4K encoding.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Wed, 31 Oct 2012 08:47:55 +0000 (16:47 +0800)]
Remove the hard coded value to suppor the 4Kx4K encoding
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Wed, 31 Oct 2012 08:47:54 +0000 (16:47 +0800)]
Fix the issue in i965_UnlockSurface to lock it next time
It uses the variable of locked_image_id to check whether one surface is locked
or not. But as the locked_image_id is not assigned correctly, it causes that
it can't lock one surface next time although it calls the vaUnlockSurfaces.
Then the libva trace log can't dump the content of decoded/
encoded surface even after adding LIBVA_TRACE_SURFACE=XXX.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Gwenole Beauchesne <gb.devel@gmail.com>
Li, Xiaowei A [Wed, 31 Oct 2012 01:49:12 +0000 (09:49 +0800)]
VPP: refine code to resolve building warnings
Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>
Li, Xiaowei A [Wed, 31 Oct 2012 01:25:53 +0000 (09:25 +0800)]
VPP: add vebox context init and deinit
Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>
Li, Xiaowei A [Tue, 30 Oct 2012 23:19:53 +0000 (07:19 +0800)]
VPP: Alloc I965 batch buffer before initialization
Li, Xiaowei A [Tue, 30 Oct 2012 23:13:07 +0000 (07:13 +0800)]
VPP: Fix the surface flags and type setting
Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>
Li, Xiaowei A [Tue, 30 Oct 2012 03:17:08 +0000 (11:17 +0800)]
VPP: fix the usage of pp_static_parameter
Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>
Zhao Halley [Thu, 2 Aug 2012 09:22:33 +0000 (12:22 +0300)]
VPP: work around hw limitation(dword alignment)
work around for horizontal offset on dst surface
left edge for load/save procedure
Signed-off-by: Zhao,Halley <halley.zhao@intel.com>
Li, Xiaowei A [Tue, 30 Oct 2012 02:31:35 +0000 (10:31 +0800)]
VPP: Remove useless shader and refine shader list
Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>
Xiang, Haihao [Thu, 25 Oct 2012 07:09:13 +0000 (15:09 +0800)]
VPP: CSC on Haswell
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 25 Oct 2012 07:07:37 +0000 (15:07 +0800)]
VPP: Build VPP shaders for Haswell
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Gwenole Beauchesne [Fri, 18 May 2012 09:40:59 +0000 (11:40 +0200)]
VPP: haswell: fix video post-processing setup.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Xiang, Haihao [Wed, 12 Sep 2012 07:27:46 +0000 (03:27 -0400)]
VPP: The block mask workaround is only available for Sandy bridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Zhao Halley [Thu, 2 Aug 2012 09:28:48 +0000 (12:28 +0300)]
VPP:work around hw limitation(dword alignment)
work around for horizontal offset on dst surface left edge for nv12 scaling (not avs)
Signed-off-by: Zhao,Halley <halley.zhao@intel.com>
Zhao Halley [Thu, 2 Aug 2012 09:04:37 +0000 (12:04 +0300)]
VPP: work around hw limitation(dword alignment)
work around for horizontal offset on dst surface left edge (nv12 avs)
Signed-off-by: Zhao,Halley <halley.zhao@intel.com>
Zhao Halley [Thu, 26 Jul 2012 08:27:45 +0000 (11:27 +0300)]
VPP: Enable horizontal and vertical mask for bottom/right boundary blocks
Signed-off-by: Zhao,Halley <halley.zhao@intel.com>
- usually it is 0xff/0xffff for common blocks in grf5
- one mask is setup in object_walker when the last group of blocks are met
- another mask should setup when the last block (in a group) is met.
it will be done in asm code, we make it ready in grf6
Xiang, Haihao [Wed, 29 Aug 2012 05:24:00 +0000 (01:24 -0400)]
VPP: Adjust vertical scaling step for AVS on IVB
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 29 Aug 2012 05:29:44 +0000 (01:29 -0400)]
VPP: AVS workaround on IVB
Update AVS shaders and add CURBE parameters for AVS workaround
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 23 Aug 2012 02:55:00 +0000 (22:55 -0400)]
VPP: Update the shader for DI on IVB
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 29 Jun 2012 08:51:00 +0000 (16:51 +0800)]
VPP: Add support DN on IVB
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 22 Aug 2012 06:51:40 +0000 (02:51 -0400)]
VPP: New combined shaders for Ivybridge
In addtion, add the license header.
You need the latest intel-gen4asm to build these shaders
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Zhao Halley [Thu, 19 Jul 2012 09:49:08 +0000 (12:49 +0300)]
VPP: distinguish first plane width in pixel or in byte
Signed-off-by: Zhao,Halley <halley.zhao@intel.com>
Xiang, Haihao [Thu, 28 Jun 2012 04:01:32 +0000 (12:01 +0800)]
VPP: Add support for UYVY in image process
Tested on SNB and IVB.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 28 Jun 2012 03:54:24 +0000 (11:54 +0800)]
VPP: color conversion between planar and packed formats on IVB
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 28 Jun 2012 03:35:50 +0000 (11:35 +0800)]
VPP: New shaders for color conversion between packed and planar YUV on IVB
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Zhao Halley [Wed, 27 Jun 2012 06:45:21 +0000 (09:45 +0300)]
VPP: Support NV12/I420/YV12->I420/YV12 conversion
Signed-off-by: Zhao,Halley <halley.zhao@intel.com>
Zhao halley [Thu, 17 May 2012 07:39:43 +0000 (15:39 +0800)]
VPP: add YV12 to YUY2 conversion
Signed-off-by: Zhao,Halley <halley.zhao@intel.com>
Xiang, Haihao [Wed, 27 Jun 2012 07:20:22 +0000 (15:20 +0800)]
VPP: Fix the width of the UV surface for AVS on IVB
The width is specified in units of pixel.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 26 Jun 2012 07:20:50 +0000 (15:20 +0800)]
VPP: Only update u/v offset for some video processes
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 26 Jun 2012 07:03:38 +0000 (15:03 +0800)]
VPP: Fix the parameter initialization for IVB
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 30 May 2012 01:21:38 +0000 (09:21 +0800)]
VPP: Don't render the target surface with background if alpha value is 0
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Zhao halley [Thu, 31 May 2012 09:00:29 +0000 (17:00 +0800)]
VPP: update image width of packed format
Signed-off-by: Zhao,Halley <halley.zhao@intel.com>
Zhao halley [Thu, 17 May 2012 07:49:34 +0000 (15:49 +0800)]
VPP: Add yuyv->nv12 conversion in image processing
Signed-off-by: Zhao,Halley <halley.zhao@intel.com>
Zhao halley [Thu, 17 May 2012 07:28:16 +0000 (15:28 +0800)]
VPP: add NV12 to YUY2 color conversion for video process
Signed-off-by: Zhao,Halley <halley.zhao@intel.com>
Xiang, Haihao [Tue, 26 Jun 2012 04:51:29 +0000 (12:51 +0800)]
VPP: Update the PA shader for ILK/SNB
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Zhao halley [Thu, 31 May 2012 09:00:26 +0000 (17:00 +0800)]
VPP: fix a mistake in PA_Load_8x8.asm
Signed-off-by: Zhao,Halley <halley.zhao@intel.com>
Zhao halley [Wed, 16 May 2012 23:58:31 +0000 (07:58 +0800)]
VPP: add YUYV to NV12 conversion shaders for gen5_6
Signed-off-by: Zhao,Halley <halley.zhao@intel.com>
Zhao halley [Thu, 31 May 2012 09:00:24 +0000 (17:00 +0800)]
VPP: add pa_load_save_pl3 for YUY2-->YV12 conversion (SNB/ILK)
Signed-off-by: Zhao,Halley <halley.zhao@intel.com>
Zhao halley [Thu, 3 May 2012 02:50:51 +0000 (10:50 +0800)]
VPP: add pl3_load_save_pa.asm etc
Signed-off-by: Zhao, Halley <halley.zhao@intel.com>
Halley Zhao [Fri, 27 Apr 2012 05:54:13 +0000 (13:54 +0800)]
VPP: add NV12 load save PA shader for gen5_6
Signed-off-by Zhao,Halley <halley.zhao@intel.com>
Xiang, Haihao [Fri, 4 May 2012 08:33:47 +0000 (16:33 +0800)]
VPP: pass the origin of source region to vpp kernel
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 4 May 2012 02:58:48 +0000 (10:58 +0800)]
VPP: Render target surface with background color
Currently ignore alpha value. We will fix it once the
alpha blend kernel is ready
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 19 Apr 2012 05:11:44 +0000 (13:11 +0800)]
Don't use DNDI kernel on Ivybridge temporarily
We will integrate the right kernel for DN/DI on Ivybridge as soon as possible.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 22 Mar 2012 01:31:05 +0000 (09:31 +0800)]
VPP: Use AVS kernel to implement normal scaling on Sandybridge
Set parameter nlas to 0 to disable NLAS
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
0b38176cda6047b05cf0eacd913f57ce501f4fdf)
Xiang, Haihao [Thu, 1 Mar 2012 04:57:21 +0000 (12:57 +0800)]
VPP: Fix map/unmap mismatches in video process
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
918f26fc0c5c38fb8c1002dd48c857897931c5d5)
Xiang, Haihao [Mon, 6 Feb 2012 06:36:21 +0000 (14:36 +0800)]
VPP: Pixel format conversion for IMC1/IMC3
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 1 Feb 2012 06:22:56 +0000 (14:22 +0800)]
VPP: Fix the base offset of cr(V) surface
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 30 Jan 2012 07:17:30 +0000 (15:17 +0800)]
VPP: Reuse AVS kernel for pixel format conversion on Ivybridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 19 Jan 2012 02:44:33 +0000 (10:44 +0800)]
VPP: Build new shaders for Ivybridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 13 Jan 2012 00:44:46 +0000 (08:44 +0800)]
VPP: use AM_V_GEN to generate files quietly on Ivybridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 30 Jan 2012 07:07:58 +0000 (15:07 +0800)]
VPP: Add support for I420/YV12/IMC1/IMC3 input/output surface for AVS on Ivybridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 30 Jan 2012 05:52:51 +0000 (13:52 +0800)]
VPP: Normal scaling on Ivybridge
Need to adjust parameters later
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 30 Jan 2012 05:33:06 +0000 (13:33 +0800)]
VPP: Clear target surface with specified color
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 30 Jan 2012 05:42:09 +0000 (13:42 +0800)]
VPP: Fix AVS parameters for Ivybridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Li, Xiaowei A [Mon, 29 Oct 2012 18:57:33 +0000 (02:57 +0800)]
VPP: Refine the Makefile.am in gen5_6
Signed-off-by: Xiang,Haihao <haihao.xiang@intel.com>
Li, Xiaowei A [Mon, 29 Oct 2012 18:43:57 +0000 (02:43 +0800)]
VPP: avoid depending on va_backend.h for some file
Signed-off-by: Xiang, Haihai <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 24 Nov 2011 06:21:03 +0000 (14:21 +0800)]
VPP: Fix parameters for SCALING & AVS
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 17 Nov 2011 02:47:45 +0000 (10:47 +0800)]
VPP: Fixed surface height for DN/DI
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 16 Nov 2011 06:16:38 +0000 (14:16 +0800)]
VPP: Update DNDI kernel and DNDI states on Sandybridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 26 Oct 2011 06:02:20 +0000 (14:02 +0800)]
VPP: Update surface state, sampler state and kernel for AVS on Sandybridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 16 Sep 2011 07:37:31 +0000 (15:37 +0800)]
VPP: update AVS kernel
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Li, Xiaowei A [Mon, 29 Oct 2012 03:09:51 +0000 (11:09 +0800)]
VPP: Support video process on Ivybridge
Only AVS enabled currently on Ivybridge.
Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>
Li, Xiaowei A [Mon, 29 Oct 2012 03:08:12 +0000 (11:08 +0800)]
VPP: Update the gen7 shader Makefile.am
Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>
Li, Xiaowei A [Mon, 29 Oct 2012 01:28:51 +0000 (09:28 +0800)]
VPP: Add support for field and frame mixed content
Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>
Li, Xiaowei A [Sun, 28 Oct 2012 20:11:56 +0000 (04:11 +0800)]
VPP: Support DN only on Ironlake and Sandybridge
signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 15 Aug 2011 08:17:15 +0000 (16:17 +0800)]
VPP: Emit base address command before other commands
This fixes potential GPU hang issue on SandyBridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 15 Aug 2011 06:45:02 +0000 (14:45 +0800)]
VPP: set surface base address for post processing
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Li, Xiaowei A [Tue, 30 Oct 2012 18:49:54 +0000 (02:49 +0800)]
VPP: Add image format conversion function
Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>
Li, Xiaowei A [Tue, 30 Oct 2012 18:43:36 +0000 (02:43 +0800)]
VPP: code refine for video process
Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>
Li, Xiaowei A [Fri, 26 Oct 2012 01:34:38 +0000 (09:34 +0800)]
VPP: Add shaders for video process on Ivybridge.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Li, Xiaowei A [Fri, 26 Oct 2012 01:03:55 +0000 (09:03 +0800)]
VPP: Add NV12<->PL3 load and save shaders to gen5_6/
Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>
Li, Xiaowei A [Thu, 25 Oct 2012 23:21:06 +0000 (07:21 +0800)]
VPP: move all vpp shaders to new gen5_6/ directory.
Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>
Li, Xiaowei A [Tue, 30 Oct 2012 19:52:57 +0000 (03:52 +0800)]
VPP: Modify the definition for PP module number
Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>
Xiang, Haihao [Wed, 31 Oct 2012 08:14:56 +0000 (16:14 +0800)]
Update the check for intel-gen4asm to support Haswell
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 30 Oct 2012 00:31:20 +0000 (08:31 +0800)]
Remove the dependence of va_vpp.h
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 24 Oct 2012 08:47:53 +0000 (16:47 +0800)]
Make it built against the current upstream libdrm
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Li,Xiaowei [Fri, 28 Sep 2012 14:35:55 +0000 (22:35 +0800)]
VEBox: setup haswell vebox pipeline for video post process
Currently, deinterlacing, denoise, color balance, color space conversion
are supported by vebox pipeline, and only deinterlace is exposed to video
post process on haswell.
Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>
projects / platform / upstream / libva-intel-driver.git / log