nouveau: reuse tgsi_get_gl_frag_result_semantic().

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Tested-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3506>

nouveau: Reuse tgsi_get_sysval_semantic().

It's now in a place accessible from the nouveau driver.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Tested-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3506>

mesa/st: Move the SYSTEM_VALUE -> TGSI_SEMANTIC map to tgsi_from_mesa.

This will let us reuse the table from nir-to-tgsi.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3506>

freedreno/a6xx: Implement layout for DRM_FORMAT_MOD_QCOM_COMPRESSED

This brings back fd6_fill_ubwc_buffer_sizes() to implement
layout_resource_for_modifier for DRM_FORMAT_MOD_QCOM_COMPRESSED.

Fixes: ecd62ff766 "freedreno: Allow UBWC on textures with multiple mipmap levels."
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3704>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3704>

freedreno: Add layout_resource_for_modifier screen vfunc

This function is responsible for completing the layout for an imported
resource with the given modifier.  Returns 0 on success or -1 If the
modifier is unsupported, invalid or the input parameters are not
compatible with the modifier.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3704>

freedreno: Set up supported modifiers in fd*_resource_screen_init()

Keep the modifier logic together.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3704>

freedreno/a6xx: Add fd6_resource_screen_init()

We'll move a few things here in the next commits.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3704>

glsl,nir: Switch the enum representing shader image formats to PIPE_FORMAT.

This means you can directly use format utils on it without having to have
your own GL enum to number-of-components switch statement (or whatever) in
your vulkan backend.

Thanks to imirkin for fixing up the nouveau driver (and a couple of core
details).

This fixes the computed qualifiers for EXT_shader_image_load_store's
non-integer sizeNxM qualifiers, which we don't have tests for.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> (v3d)
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3355>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3355>

intel/isl: Move iris's pipe-to-isl format function to isl.

This will get reused in the shader compiler once we switch it over to pipe
formats instead of GL enums.  We can't easily deduplicate i965's
mesa-to-isl mapping because of cases like A32_FLOAT that are mapped
differently.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3355>

mesa: Clean up some endianness adapters for shader image formats.

We already had a uint version in formats.h, move the snorm/unorm ones
there, too.

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3355>

gallium/swr: Fix various asserts and security issues

To improve the robustness of the code, we want to better
detect issues in testing (using asserts) and use more
secure techniques.

Reviewed-by: Krzysztof Raszkowski <krzysztof.raszkowski@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3710>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3710>

pan/midgard: Fix scheduling issue with csel + render target reference

Fixes dEQP-GLES3.functional.shaders.fragdepth.write.dynamic_conditional_write

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3697>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3697>

panfrost: Set the MALI_WRITES_{Z,S} flags when needed

In order to make Z/S writes from fragment shaders effective, we need
to set the MALI_WRITES_{Z,S} flags when the shader has a
FRAG_RESULT_{DEPTH,STENCIL} output variable.

Now that shaders can change the S value, we can expose the
STENCIL_EXPORT cap.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3697>

panfrost: Add the MALI_WRITES_{Z,S} flags

We discovered 2 new shader flags used when a fragment shader updates
the depth/stencil value through a ZS writeout. If those flags are not
set, the depth/stencil value stored in the depth/stencil tilebuffer
remain unchanged.

While at it, rename unknown2 into flags_hi and rename flags into
flags_lo.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3697>

panfrost: Z24 variants should be sampled as R32UI

Midgard has no dedicated samplers for Z24S8 and Z24X8 formats, and the
GPU expects the depth to be encoded in an IEEE 32-bit float. Turn all
Z24_UNORM variants into R32UI and let the shader do the conversion
using bfe+fmul instructions.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3697>

pan/midgard: Add nir_intrinsic_store_zs_output_pan support

ZS fragment stores are done like color fragment stores, except it's
using a different RT id (0xFF), the depth and stencil values are stored
in r1.x and r1.y.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
[Fix the scheduling part]

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3697>

pan/midgard: Turn Z/S stores into zs_output_pan intrinsics

Midgard can't write depth and stencil separately. It has to happen in
a single store operation containing both. Let's add a panfrost specific
intrinsic and turn all depth/stencil stores into a packed depth+stencil
one.

Note that this intrinsic is not yet handled in emit_intrinsic(), but
we'll address that later.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3697>

intel/fs: Don't count integer instructions as being possibly coissue

Integer instructions don't coissue.  Before e64be391dd0
("intel/compiler: generalize the combine constants pass"), this pass
only looked at float sources.  There's no shader-db data in that commit,
so I collected some.  The results are not good:

    Haswell
    total instructions in shared programs: 11898805 -> 11908127 (0.08%)
    instructions in affected programs: 1218680 -> 1228002 (0.76%)
    helped: 2
    HURT: 5171
    helped stats (abs) min: 12 max: 111 x̄: 61.50 x̃: 61
    helped stats (rel) min: 1.59% max: 9.20% x̄: 5.40% x̃: 5.40%
    HURT stats (abs)   min: 1 max: 311 x̄: 1.83 x̃: 1
    HURT stats (rel)   min: 0.02% max: 9.91% x̄: 1.05% x̃: 0.70%
    95% mean confidence interval for instructions value: 1.55 2.05
    95% mean confidence interval for instructions %-change: 1.02% 1.08%
    Instructions are HURT.

    total cycles in shared programs: 221664974 -> 221404750 (-0.12%)
    cycles in affected programs: 120012620 -> 119752396 (-0.22%)
    helped: 3464
    HURT: 3159
    helped stats (abs) min: 1 max: 428160 x̄: 314.55 x̃: 16
    helped stats (rel) min: <.01% max: 57.33% x̄: 3.40% x̃: 1.28%
    HURT stats (abs)   min: 1 max: 87846 x̄: 262.54 x̃: 14
    HURT stats (rel)   min: <.01% max: 85.57% x̄: 3.01% x̃: 0.77%
    95% mean confidence interval for cycles value: -224.23 145.65
    95% mean confidence interval for cycles %-change: -0.50% -0.19%
    Inconclusive result (value mean confidence interval includes 0).

    total spills in shared programs: 9804 -> 10047 (2.48%)
    spills in affected programs: 6869 -> 7112 (3.54%)
    helped: 2
    HURT: 41

    total fills in shared programs: 19863 -> 20319 (2.30%)
    fills in affected programs: 17428 -> 17884 (2.62%)
    helped: 2
    HURT: 41

    LOST:   20
    GAINED: 13

This also prevents regressions in "intel/fs: Promote integer constants
after lowering integer multiplication" (note: that patch will probably
not be committed).  When the passes are reorderd, code like

    mul(8)      acc0<1>D    g9<8,8,1>D  -2078209981D    { align1 1Q };

gets turned into

    mov(1)      g23<1>D     2078209981D                 { align1 WE_all 1N };
    ...
    mul(8)      acc0<1>D    g13<8,8,1>D  -g23<0,1,0>D   { align1 1Q compacted };

It's not 100% clear why, but these produce different results.  Note that
-2078209981 & 0x0ffff = 0x0843, and -(2078209981 & 0x0ffff) =
0xffff0843.  It seems like the upper 16-bits of the negation should be
ignored.

Fixes: e64be391dd0 ("intel/compiler: generalize the combine constants pass")
Cc: Iago Toral Quiroga <itoral@igalia.com>
Suggested-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
The shaders with spills or fills hurt are the usual suspects.  A couple
compute shaders in Dirt Showdown and a compute shader in Bioshock
Infinite.  On Haswell, a compute shader (that appears twice in
shader-db) from Aztec Ruins was also hurt for spill and fills.

Haswell
total instructions in shared programs: 11573934 -> 11568335 (-0.05%)
instructions in affected programs: 828623 -> 823024 (-0.68%)
helped: 2825
HURT: 6
helped stats (abs) min: 1 max: 134 x̄: 2.16 x̃: 1
helped stats (rel) min: 0.02% max: 9.05% x̄: 0.84% x̃: 0.61%
HURT stats (abs)   min: 1 max: 216 x̄: 81.83 x̃: 56
HURT stats (rel)   min: 0.16% max: 8.65% x̄: 4.21% x̃: 4.68%
95% mean confidence interval for instructions value: -2.31 -1.64
95% mean confidence interval for instructions %-change: -0.85% -0.80%
Instructions are helped.

total cycles in shared programs: 187573593 -> 187004633 (-0.30%)
cycles in affected programs: 82816107 -> 82247147 (-0.69%)
helped: 2186
HURT: 1741
helped stats (abs) min: 1 max: 35230 x̄: 326.96 x̃: 16
helped stats (rel) min: <.01% max: 46.11% x̄: 3.11% x̃: 0.90%
HURT stats (abs)   min: 1 max: 6138 x̄: 83.73 x̃: 16
HURT stats (rel)   min: <.01% max: 104.11% x̄: 2.73% x̃: 0.75%
95% mean confidence interval for cycles value: -197.13 -92.64
95% mean confidence interval for cycles %-change: -0.72% -0.33%
Cycles are helped.

total spills in shared programs: 7870 -> 7743 (-1.61%)
spills in affected programs: 2260 -> 2133 (-5.62%)
helped: 31
HURT: 5

total fills in shared programs: 6320 -> 6263 (-0.90%)
fills in affected programs: 3547 -> 3490 (-1.61%)
helped: 31
HURT: 6

LOST:   9
GAINED: 9

Ivybridge
total instructions in shared programs: 11863372 -> 11859793 (-0.03%)
instructions in affected programs: 757183 -> 753604 (-0.47%)
helped: 2236
HURT: 3
helped stats (abs) min: 1 max: 81 x̄: 1.86 x̃: 1
helped stats (rel) min: 0.03% max: 5.26% x̄: 0.74% x̃: 0.48%
HURT stats (abs)   min: 11 max: 301 x̄: 192.33 x̃: 265
HURT stats (rel)   min: 1.55% max: 10.51% x̄: 6.89% x̃: 8.62%
95% mean confidence interval for instructions value: -2.01 -1.18
95% mean confidence interval for instructions %-change: -0.77% -0.70%
Instructions are helped.

total cycles in shared programs: 178377378 -> 177946087 (-0.24%)
cycles in affected programs: 76261390 -> 75830099 (-0.57%)
helped: 1635
HURT: 1395
helped stats (abs) min: 1 max: 34796 x̄: 333.53 x̃: 16
helped stats (rel) min: <.01% max: 47.15% x̄: 2.82% x̃: 0.64%
HURT stats (abs)   min: 1 max: 4315 x̄: 81.74 x̃: 18
HURT stats (rel)   min: <.01% max: 49.98% x̄: 1.99% x̃: 0.53%
95% mean confidence interval for cycles value: -197.06 -87.62
95% mean confidence interval for cycles %-change: -0.78% -0.43%
Cycles are helped.

total spills in shared programs: 4188 -> 4182 (-0.14%)
spills in affected programs: 1557 -> 1551 (-0.39%)
helped: 30
HURT: 3

total fills in shared programs: 5056 -> 5245 (3.74%)
fills in affected programs: 2708 -> 2897 (6.98%)
helped: 30
HURT: 3

LOST:   5
GAINED: 1

No shader-db changes on any other Intel platform.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3544>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3544>

tu: Move vsc_data and vsc_data2 allocation into the device

In addition to preparing us for dynamically resizing them, which has to
be controlled by the device, this greatly reduces the memory usage when
allocating large numbers of command buffers, making
dEQP-VK.api.object_management.max_concurrent.command_buffer_primary go
from crash -> pass.

Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3621>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3621>

freedreno: Fix CP_COND_EXEC

Noticed while looking at a trace of the Vulkan blob.

Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3600>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3600>

freedreno: Add CP_REG_WRITE documentation

Document the first DWORD, which at least for the Vulkan blob on a640
isn't always 2.

Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3600>

freedreno: Fix CP_COND_REG_EXEC bit positions

Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3600>

gitlab-ci: Build radeonsi & RADV in the ppc64el job

This requires cross-building libdrm for ppc64el.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3643>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3643>

gitlab-ci: Add ppc64el and s390x cross-build jobs

Using LLVM 8 for ppc64el and 7 for s390x (which hits some coroutine
related issues with LLVM 8).

There are some test failures we need to ignore for now. Also, the
timeout needs to be bumped from the default 30s for some tests, because
they can take longer under emulation.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3643>

gitlab-ci: Merge ccache and libxml2-utils into main apt-get install

The motivation for this is that we want to make use of the meson cross
files in this script, which have the ccache compiler paths.

We need to remove the ccache directory at the end, it would just waste
space in the image for no benefit.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3643>

gitlab-ci: Pass -j4 to make

Might speed up x86_build docker image build a little.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3643>

gitlab-ci: Update to latest ci-templates HEAD

Among other things, this increases robustness when copying a docker
image from the main Mesa project to a forked project, avoiding spurious
image rebuilds from scratch.

Also drop the comment about .gitlab-ci/lava-gitlab-ci.yml, it doesn't
include the templates anymore.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3643>

radeonsi/ngg: add VGT_FLUSH when enabling fast launch

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2418
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2426
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2434
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3675>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3675>

util/disk_cache: check for write() failure in the zstd path

CoverityID: 1458074
Fixes: a8d941091f72923561a6 ("util: Use ZSTD for shader cache if possible")
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3672>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3672>

dri: delete gen-symbol-redefs.py

Introduced in ba10d79cca8d93c9f366 but it looks like it was never wired
into anything.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3669>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3669>

anv: implement gen12 post sync pipe control workaround

Same as Skylake.

v2: Restrict to A0

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3405>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3405>

anv: implement gen9 post sync pipe control workaround

We've been missing this workaround for a while and since it's required
for Gen12, let's implement it for Gen9 first.

v2: Update comment for Gen9.

v3: Fix clearing of bits... (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3405>

iris: implement gen12 post sync pipe control workaround

Like Skylake, Gen12 requires a workaround for PIPE_CONTROLs using a
post-sync operation.

v2: Restrict to A0

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3405>

freedreno: allow ctx->batch to be NULL

This was mostly true already, now that we use `fd_context_batch()` for
first access to batch in draw/clear/grid paths.  So we can drop the old
code in `batch_flush()` that tried to prevent `ctx->batch` from being
NULL.

Fixes a crash with a large number of tabs in chromium.

Cc: "20.0" mesa-stable@lists.freedesktop.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3700>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3700>

freedreno: Allow UBWC on textures with multiple mipmap levels.

This is a backport of Jonathan Marek's UBWC work on turnip to GL.

Performance highlights from our trace set (320 frames sampled)
traces/glmark2/texture-texture-filter=mipmap.rdc:    +9.1% +/-   2.2%
traces/android/trex.rdc:                             +8.7% +/-   0.4%
traces/glmark2/desktop-effect=shadow:windows=4.rdc:  +4.2% +/-   2.5%

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3059>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3059>

freedreno: Disable UBWC on Z24S8 if not TEXTURE_2D.

Fixes two of our three remaining GLES CTS failures, and avoids more
regressions once we enable UBWC mipmaps.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3059>

freedreno: Blit all array levels when uncompressing UBWC.

Fixes regressions in GLES CTS's format_reintepret once we enable UBWC
with mipmaps.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3059>

freedreno: Swap the whole resource layout in shadowing.

Let's not have to worry about whether this unusual code path gets
updated whenever we adjust what is in the layout struct.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3059>

freedreno/a6xx: Disable the core layer-size setup.

This was getting in the way of UBWC mipmap handling.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3059>

freedreno: Rename the UBWC layer size field and store it as bytes.

This makes the field description match its usage in the code, matches tu's
usage of the field, and avoids storing values in surprising units.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3059>

freedreno: Include the layer size in layout debug.

It's been many of my bugs so far.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3059>

freedreno: Move the layout debug under FD_MESA_DEBUG=layout.

I keep wanting to turn this on while debugging layout stuff, and I
suspect krh and robclark could use it too.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3059>

radv: Do not set SX DISABLE bits for RB+ with unused surfaces.

The extra bits in CB_SHADER_MASK break dual source blending in
SkQP on a Stoney device. However:

- As far as I can tell, some other dual source blend tests are passing
  before and after the change.
- A hacked around skqp passes on my Vega desktop and Raven laptop
- Getting Skqp to give any useful info or to run it outside of Android
  on ChromeOS is proving difficult.

I have confirmed 3 strategies that seem to work:
- The old radv behavior of setting CB_SHADER_MASK to 0xF
- AMDVLK: CB_SHADER_MASK = 0xFF, and the 3 RB+ regs
  are 0.
- radeonsi: CB_SHADER_MASK = 0xFF, but does not set DISABLE
  bits in SX_BLEND_OPT_CONTROL for CB 1-7.

Let us use the radeonsi solution as that solution also seems like the correct
thing to do for holes. I have tested on my Raven laptop that setting the high
surfaces to not disabled and downconvert to 32_R does not imply a performance
penalty.

Fixes: e9316fdfd48 "radv: fix setting CB_SHADER_MASK for dual source blending"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3670>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3670>

mesa: implement missing display list functions while switching to the template

The vbo_init_tmp.h template tells us which functions are unimplemented.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3611>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3611>

vbo: move reusable code from vbo_attrib_tmp.h into vbo_util.h

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3611>

vbo: use the template for save GLvertexformat initialization

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3611>

vbo: use the template for noop GLvertexformat initialization

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3611>

vbo: move GLvertexformat initialization into a template header file for reuse

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3611>

freedreno/perfcntrs: fix fd leak

CoverityID: 1110568, 1458071
Fixes: 5a13507164a26fc796f0 ("freedreno/perfcntrs: add fdperf")
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3671>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3671>

util: Drop unpacking from int signed to unsigned and vice versa.

After all the previous cleanups, it's clear that the callers only ever
ask for SINT->SINT or UINT->UINT.  Cuts 20k of compiled text from
gallium drivers.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2744>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2744>

gallium: Refactor some single-pixel util_format_read/writes.

We can use the new row helpers to cut down on the noise.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2744>

gallium: Add and use a helper for packing uc from a color_union.

The same pattern kept coming up, and we don't need to hit
util_format_write_4* to do it when we have util_format_pack_rgba().

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2744>

softpipe: Refactor pipe_get/put_tile_rgba_* paths.

We always want the same behavior of choosing which unpack to do to
generate our 4x32-bit RGBA values, so just sink that choice down below
the pipe_get/put_tile API.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2744>

softpipe: Drop the raw_to* part of the tile cache interface.

Nothing else uses it, so make it static.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2744>

gallium/util: Remove pipe_get_tile_z/put_tile_z.

The previous caller wasn't using it as tiled, just row-at-a-time, and
didn't want the clipping (since copytexsubimage comes in clipped).  If
someone wanted these functions again in the future, they should be
rewritten on u_format_pack/unpack.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2744>

mesa/st: Use direct util_format_pack/unpack instead of u_tile.

We're doing a row at a time, and don't need u_tile's clipping.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2744>

util: Make helper functions for pack/unpacking pixel rows.

Almost all users of the unpack functions don't have strides to plug in
(and many are only doing one pixel!), and this will help simplify
them.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2744>

clover: add trivial clCreateCommandQueueWithProperties implementation

It's not adding 2.0 features, but it's enough to run the 2.0 CTS on top of
clover and probably most CL applications using it.

We just fail if we hit unknown properties and that's probably good enough
until we implement the other bits properly.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2370>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2370>

gallium/osmesa: Try to fix the test for big-endian.

Our packed expected values will be byte-swapped for the (mostly) array
formats we're testing.

Reviewed-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3216>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3216>

gallium/osmesa: Fill out other format tests.

Move expected values/bpp into the test params, add more formats now that
we've fixed context setup so that they work.

Reviewed-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3216>

gallium/osmesa: Fix MakeCurrent of non-8888 contexts.

OSMesa is weird and you only get the type (byte/ubyte/565/etc.) at
MakeCurrent time, having only a channel order at CreateContext time.  The
code was setting up a visual at CreateContext time, and then at
MakeCurrent it would fail to validate against the visual.

Reviewed-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3216>

gallium/osmesa: Fix a typo in the unit test's test names.

Reviewed-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3216>

osmesa/tests: Cover OSMESA_RGB GL_UNSIGNED_BYTE case

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3216>

st/mesa: Handle the rest renderbuffer formats from OSMesa

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2189
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/989
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2036
CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3216>

util/os_socket: fix header unavailable on windows

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2464
Fixes: e62c3cf350a8b169e640 ("util/os_socket: Include unistd.h to fix build error")
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Krzysztof Raszkowski <krzysztof.raszkowski@intel.com>

i965: Do not set front_buffer_dirty if there is no front buffer

Otherwise there will be a warning:
 "libEGL warning: FIXME: egl/x11 doesn't support front buffer rendering."

Happens with EGL_KHR_surfaceless_context:

 eglMakeCurrent(egl_display, EGL_NO_SURFACE, EGL_NO_SURFACE, egl_context)
 eglMakeCurrent(egl_display, egl_surface, egl_surface, egl_context)
 glFlush() // Here will be a warning

Cc: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1525
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3628>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3628>

gitlab-ci: Switch kernel for LAVA jobs to 5.5

All fixes we were carrying in our branch have been merged already.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3692>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3692>

panfrost: Use size0 when calculating the offset to a depth level

Previously, we were using cubemap_stride and sometimes overwriting other
BOs such as shaders.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3692>

panfrost: Only clamp the LOD to disable mipmapping when needed

Otherwise, we may be incrementing max_lod over the limit, causing a
DATA_INVALID_FAULT.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3692>

panfrost: Fix decoding of tiled 3D textures

From decoding cmd streams generated by the blob, the pointers in the
payload don't seem to include those that refer to different depth levels
when the texture is in tiled format.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3692>

st/mesa: use uint-result for sampling stencil buffers

Otherwise, we end up mismatching the result-type and the sampler-type.

Fixes: 642125edd97 ("st/mesa: use uint-samplers for sampling stencil buffers")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3680>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3680>

pan/midgard: Remove unused variable

../src/panfrost/midgard/mir.c: In function ‘mir_bytemask_of_read_components_index’:
../src/panfrost/midgard/mir.c:471:18: warning: unused variable ‘mask’ [-Wunused-variable]
  471 |         uint16_t mask = 0;

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3684>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3684>

pan/midgard: Check for null consts

Valid shaders shouldn't hit this, but Coverity doesn't know that.

CID 1458029:    (FORWARD_NULL)
Passing null pointer "consts" to "print_scalar_field", which dereferences it.

Tomeu: Fix name of variable

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3684>

panfrost: Avoid overlapping copy

CID 1457486:  Memory - corruptions  (OVERLAPPING_COPY)

Assigning "(*attr).extra_flags = (*attr).size = 0U" to "(*attr).stride",
which have overlapping memory +locations.

Coverity.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3684>

etnaviv: Destroy rsc->pending_ctx set in etna_resource_destroy()

Destroy rsc->pending_ctx set in etna_resource_destroy(), otherwise
the memory is allocated, never free'd, and becomes unreachable. This
fixes a memory leak.

Fixes: 9e672e4d20fb ("etnaviv: keep references to pending resources")
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3633>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3633>

turnip: Be explicit about converting vk compare func to a6xx

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3686>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3686>

nir: Remove always-true assert

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3686>

glsl: Use 'using' to be explicit about visitor overloads

Clang has a warning about overloading virtuals that triggers when a
derived class defines a virtual function that's an overload of
function in the base class.  This kind of thing:

  struct chart; // let's pretend this exists
  struct Base
  {
      virtual void* get(char* e);
  };

  struct Derived: public Base {
      virtual void* get(chart* e); // typo, we wanted to override the same function
  };

The solution is to use

  using Base::get;

to be explicit about the intention to reuse the base class virtual.
We hit this a lot with out glsl ir_hierarchical_visitor visitor
pattern, so let's adds some 'using' to calm down the compiler.

See-also: https://stackoverflow.com/questions/18515183/c-overloaded-virtual-function-warning-by-clang)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3686>

spirv/opencl: Cast opcode up front to avoid warnings

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3686>

freedreno/fdperf: Cast away some ignored return values

This is developer tool, it can crash and burn if it fails to allocate.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3686>

nir: Make unroll pragma work on clang

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3686>

nir: Delete unused is_var_constant() helper

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3686>

Revert "gitlab-ci: disable a630 tests as mesa-cheza is down"

This reverts commit f38851d84c583b1c62ea95edbc42eb5e2ad14fa8

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3687>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3687>

clover: Use explicit conversion from llvm::StringRef to std::string

Fixes build after llvm 777180a32b61070a10dd330b4f038bf24e916af1
("[ADT] Make StringRef's std::string conversion operator explicit")

CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

zink: disallow depth-stencil blits with format-change

The Vulkan spec says this about vkCmdBlitImage:

   "No format conversion is supported between depth/stencil images. The
    formats must match."

So yeah, let's stop trying to do this.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3681>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3681>

zink: be more careful about the mask-check

We currently disallow blits that we can support. Let's be more accurate
when checking the mask.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3681>

panfrost: Fix the damage box clamping logic

When the rendering are is not covering the whole FBO, and the biggest
damage rect is empty, we can have damage.max{x,y} > damage.min{x,y},
which leads to invalid reload boxes.

Fixes: 65ae86b85422 ("panfrost: Add support for KHR_partial_update()")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3676>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3676>

pan/midgard: Stop leaking instruction objects in mir_schedule_alu()

Allocate those instructions with ralloc() instead of using mem_dup.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3676>

pan/midgard: Don't check 'branch && branch->writeout' twice in mir_schedule_alu()

There's a writeout bool storing the result of this test. Use it instead
of duplicating the test.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3676>

pan/midgard: Lower bitfield extract to shifts

Let's lower bitfield extract to shifts until we figure out if it can be
natively supported.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3676>

pan/midgard: Make sure we pass the right RT id to emit_fragment_store()

nir_intrinsic_base() is assigned nir_variable.data.driver_location,
which is assigned a unique ID based on the variable position in the
shader variable list. There's no guarantee that this position will
match the RT id we want to pass to emit_fragment_store().

Add a search_var() helper to retrieve a nir_variable based on its driver
location, so we can pass the right RT value to emit_fragment_store().

We also make sure the shader output is color, since emit_fragment_store()
is not ready for depth/stencil stores yet.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3676>

pan/midgard: Add an enum to describe the render targets

We are about to add a special ZS render target, let's add a enum so we
can easily know which render target we're dealing with.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3676>

util/os_socket: Include unistd.h to fix build error

Fixes

In file included from ../src/util/os_socket.c:8:
../src/util/os_socket.h:26:1: error: unknown type name ‘ssize_t’; did you mean ‘size_t’?
 ssize_t os_socket_recv(int socket, void *buffer, size_t length, int flags);

seen with gcc version 8.3.0 (Buildroot 2019.11) and uClibc 1.0.32.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Fixes: ef5266ebd50e7fa65c56 ("util/os_socket: Add socket related functions.")
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3659>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3659>

gitlab-ci: disable a630 tests as mesa-cheza is down

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3677>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3677>

nv50: report max lod bias of 15.0

The blob returns 15, the state creation code clamps it to 15, but since
the dawn of time we've returned 4.0. Setting this to 15 also fixes

GTF-GL33.gtf21.GL3Tests.texture_lod_bias.texture_lod_bias_clamp_m_le_M

which is sensitive to these limits.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

egl: put full path to libEGL_mesa.so in GLVND json

This is useful when installing to a non-standard path.

glvnd_icd.py copied & adapted from src/intel/vulkan/anv_icd.py

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3038>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3038>

radv: Allow non-dedicated linear images and buffer.

Requested for virtualized Vulkan as they need to export memory to
map it.

Since radeonsi and the kernel assume an image without metadata is
linear, this should work just fine.

Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3583>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3583>

pan/midgard: Implement mixed-type constant packing

Lot of churn but mostly just specializes types per source instead of per
instruction.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3653>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3653>

pan/midgard: Break out one-src read_components

For constant packing, this is interesting to break down further.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3653>

panfrost: Fix non-debug builds

For non-debug builds, where assertions are compiled out, GCC complains
about the end of the non-void function panfrost_translate_channel_width
being reached.

Fixes: 226c1efe9a8 ("panfrost: Add more info to some assertions")
Reported-by: Piotr Oniszczuk
Suggested-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3665>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3665>