Samuel Pitoiset [Thu, 10 Dec 2020 13:06:58 +0000 (14:06 +0100)]
radv: fix TC-compat HTILE images with DST_OPTIMAL on the compute queue
This is probably rare but can happen if someone performs a depth-stencil
copy on the compute queue. This might work (untested by CTS) but it
looks more conservative to decompress before perfoming the operation.
Found by inspection.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8039>
Samuel Pitoiset [Wed, 9 Dec 2020 16:51:10 +0000 (17:51 +0100)]
radv: add radv_htile_get_initial_value() and document the HTILE dword
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8039>
Samuel Pitoiset [Wed, 9 Dec 2020 16:48:56 +0000 (17:48 +0100)]
radv: fix potential HTILE issues for TC-compat images on GFX8
We can only use the entire HTILE buffer if TILE_STENCIL_DISABLE is
TRUE. On GFX8+, this is only true if the depth image has no stencil
and if it's not TC-compatible because of the ZRANGE_PRECISION issue.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8039>
Samuel Pitoiset [Wed, 9 Dec 2020 16:28:40 +0000 (17:28 +0100)]
radv: always clear the SR0/SR1 bits of the HTILE buffer
To make sure the stencil compare state is properly initialized and
cleared when the driver performs a fast depth clear.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8039>
Pierre-Eric Pelloux-Prayer [Fri, 18 Dec 2020 14:48:51 +0000 (15:48 +0100)]
mesa/st: fix redundant initialization
https://gitlab.freedesktop.org/mesa/mesa/-/issues/3966
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7846>
Pierre-Eric Pelloux-Prayer [Fri, 18 Dec 2020 14:48:05 +0000 (15:48 +0100)]
radeonsi: fix redundant initializations
See https://gitlab.freedesktop.org/mesa/mesa/-/issues/3966
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7846>
Pierre-Eric Pelloux-Prayer [Tue, 1 Dec 2020 10:04:16 +0000 (11:04 +0100)]
gallium/vl: merge identical h264/h265 enums
Use h2645 notations for shared enums to reduce duplication and
fix a clang warning.
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7846>
Pierre-Eric Pelloux-Prayer [Wed, 25 Nov 2020 14:45:02 +0000 (15:45 +0100)]
tesselator: remove unused variable
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7846>
Pierre-Eric Pelloux-Prayer [Wed, 25 Nov 2020 14:44:53 +0000 (15:44 +0100)]
amd/addrlib: use cpp.has_argument() to filter compiler arguments
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7846>
Pierre-Eric Pelloux-Prayer [Tue, 1 Dec 2020 17:09:44 +0000 (18:09 +0100)]
vdpau: fix invalid enum usage
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7846>
Pierre-Eric Pelloux-Prayer [Wed, 25 Nov 2020 14:32:36 +0000 (15:32 +0100)]
vdpau: fix -Wabsolute-value warning
vdpau specifies that top-left is x0/y0, bottom-right is x1/y1 and that x0/y0 are
inclusive while x1/y1 are exclusive.
This commit remove the abs() usage and instead verifies that the VdpRects passed
by the user matche the documentation. When they don't they're treated as empty
rectangles.
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7846>
Rhys Perry [Mon, 4 Jan 2021 13:06:15 +0000 (13:06 +0000)]
ac/nir: use llvm.readcyclecounter for LLVM9+
Unlike llvm.amdgcn.s.memtime, this works on GFX10.3
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4033
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8306>
Eric Anholt [Wed, 30 Dec 2020 23:33:45 +0000 (15:33 -0800)]
gallium/tgsi_exec: Remove unused MaxGeometryShaderOutputs.
Just an indirection from the value you should be grepping for (the one
that controls the allocation of the output buffer).
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8283>
Eric Anholt [Tue, 22 Dec 2020 21:45:33 +0000 (13:45 -0800)]
gallium/tgsi_exec: Clean up storage of the pixel kill mask.
We need one dword per exec, rather than one per channel, since it's the
bitmask of channels killed. Removes the remainder of the
TGSI_EXEC_NUM_TEMP_EXTRAS!
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8283>
Eric Anholt [Tue, 22 Dec 2020 21:40:53 +0000 (13:40 -0800)]
gallium/tgsi_exec: Drop the unused scratch temp regs.
I suspect this was used back in the SSE2 backend days. Definitely dead
now.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8283>
Eric Anholt [Tue, 22 Dec 2020 21:37:54 +0000 (13:37 -0800)]
gallium/tgsi_exec: Stop doing the weird allocation of the Addrs array.
Saves an indirection on referencing the address regs, and also my sanity.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8283>
Eric Anholt [Tue, 22 Dec 2020 21:02:20 +0000 (13:02 -0800)]
gallium/tgsi_exec: Simplify GS output vertex count tracking.
We had this strange 5-dword-per-stream storage for the single dword
current vertex count, due to copy and paste. We can make much cleaner
code by just having a 4-element array in the machine.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8283>
Samuel Pitoiset [Tue, 5 Jan 2021 07:37:56 +0000 (08:37 +0100)]
radv: remove unused radv_image::aspects
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8324>
Samuel Pitoiset [Tue, 5 Jan 2021 07:36:59 +0000 (08:36 +0100)]
radv: fix clearing images with vkCmdClear{Color,DepthStencil}Image()
The image aspects field is actually never set and we should use the
range aspect anyways.
Fixes:
1a7b7b17ad0 ("radv: avoid oob read during clear")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8324>
Pierre-Eric Pelloux-Prayer [Mon, 7 Dec 2020 16:34:18 +0000 (17:34 +0100)]
vbo/dlist: use a shared index buffer
Draws can be merged by u_threaded if they share the same IB.
This improves performance in SPECviewperf13 snx-03: tests fps
are improved by a 1.2x - 2.0x factor.
v2: reworked error handling
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v2)
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com> (v2)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8111>
Marek Olšák [Fri, 1 Jan 2021 19:01:25 +0000 (14:01 -0500)]
mesa: fix a second bug in merging light state parameters with unpacked uniforms
The memcpy size should be packed even if the allocated parameter size
is padded to 4 components.
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8017>
Marek Olšák [Fri, 1 Jan 2021 19:00:13 +0000 (14:00 -0500)]
mesa: fix a bug in merging light state parameters with unpacked uniforms
This code is not enabled yet.
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8017>
Marek Olšák [Fri, 1 Jan 2021 17:13:28 +0000 (12:13 -0500)]
mesa: add STATIC_ASSERTs to the STATE_LIGHT_ATTRIBS case
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8017>
Marek Olšák [Sat, 28 Nov 2020 08:46:30 +0000 (03:46 -0500)]
st/mesa: fix a defect when st_validate_state was invoked for unused states
This fixes a small performance issue. Discovered with piglit/drawoverhead.
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8017>
Marek Olšák [Sun, 29 Nov 2020 08:03:50 +0000 (03:03 -0500)]
st/mesa: simplify checking whether to pin threads to L3
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8017>
Marek Olšák [Sat, 28 Nov 2020 09:18:32 +0000 (04:18 -0500)]
util: replace UTIL_MAX_CPUS by util_cpu_caps.num_cpu_mask_bits
to reduce overhead when setting thread affinity.
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8017>
Alexander von Gluck IV [Wed, 30 Dec 2020 00:46:59 +0000 (18:46 -0600)]
glsl/builtin_functions: Rename int64 function to int64_avail
* int64 is a core type on Haiku (and potentially other platforms)
* rename to int64_avail matching other similar calls
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Alexander von Gluck IV [Wed, 30 Dec 2020 00:46:45 +0000 (18:46 -0600)]
meson: Add _GNU_SOURCE for Haiku to activate non-posix functions
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Marek Olšák [Thu, 24 Dec 2020 12:42:12 +0000 (07:42 -0500)]
radeonsi: take color interpolation into account for shader variants
Fixes:
- Sample shading now uses per-sample interpolation for colors if colors
are the only inputs. (this is the only case that was broken)
Optimizations:
- BC_OPTIMIZE (barycentric optimization) is now enabled with MSAA if colors
are qualified with both center and centroid. (BC_OPTIMIZE means that
the hardware skips initializing centroid (i,j) if they are equal to
center (i,j))
- If MSAA is disabled and at least 2 out of (center, centroid, sample) are
used by all inputs now including colors, center is forced for all inputs.
- If INTERP_MODE_COLOR is not used and the legacy GL shade model is flat,
the shader variant for flat shading is not generated.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8225>
Marek Olšák [Thu, 24 Dec 2020 12:04:07 +0000 (07:04 -0500)]
radeonsi: add driconf options to enable/disable Smart Access Memory
so that anybody can test it if they have Above 4G Decoding and compare
performance.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8225>
Marek Olšák [Thu, 24 Dec 2020 11:14:11 +0000 (06:14 -0500)]
ac,radeonsi: limit Smart Access Memory to Zen 3 and GFX10.3 due to perf issues
Many people experience performance degradation on some systems.
There will be a driconf option to enable SAM on other chips as well as
disable it on enabled systems.
Fixes:
d3d6d381450 - ac: add radeon_info::all_vram_visible for Smart Access Memory
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3982
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8225>
Marek Olšák [Thu, 24 Dec 2020 10:43:25 +0000 (05:43 -0500)]
util: add AMD CPU family enums and enable L3 cache pinning on Zen3
Based on: https://en.wikichip.org/wiki/amd/cpuid
The only reason it's nominated as a fix is because Zen3 might underperform
because the CPU detection ignored it.
Fixes:
15fa2c5e359 - gallium/u_cpu_detect: get the number of cores per L3 cache for AMD Zen
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8225>
Vinson Lee [Fri, 1 Jan 2021 02:01:10 +0000 (18:01 -0800)]
radeonsi: Fix typos.
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8289>
Ian Romanick [Tue, 16 Jun 2020 21:29:58 +0000 (14:29 -0700)]
nir/algebraic: Move the flrp -> bcsel rule earlier
If multiple rules could match, the rule that appears first in the file
is used.
Only Tiger Lake and Ice Lake are affected. Other platforms either have
a LRP instruction or can't run any shaders from shader-db that would
benefit.
v2: Fix issues created when this commit was rebased on top of
3c8934a644b8 ("nir/algebraic: add flrp patterns for 16 and 64 bits").
Noticed by Caio.
Tiger Lake and Ice Lake had similar results.
total instructions in shared programs:
20908672 ->
20908661 (<.01%)
instructions in affected programs: 419 -> 408 (-2.63%)
helped: 5
HURT: 0
helped stats (abs) min: 1 max: 3 x̄: 2.20 x̃: 3
helped stats (rel) min: 1.85% max: 3.19% x̄: 2.49% x̃: 2.65%
95% mean confidence interval for instructions value: -3.56 -0.84
95% mean confidence interval for instructions %-change: -3.24% -1.73%
Instructions are helped.
total cycles in shared programs:
473513940 ->
473513793 (<.01%)
cycles in affected programs: 7176 -> 7029 (-2.05%)
helped: 12
HURT: 0
helped stats (abs) min: 5 max: 22 x̄: 12.25 x̃: 12
helped stats (rel) min: 0.84% max: 3.24% x̄: 2.09% x̃: 1.80%
95% mean confidence interval for cycles value: -15.43 -9.07
95% mean confidence interval for cycles %-change: -2.57% -1.61%
Cycles are helped.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6358>
Ian Romanick [Wed, 19 Feb 2020 20:47:21 +0000 (12:47 -0800)]
nir/algebraic: Mark comparisons generated from lowered fsign precise
This prevents other transformations from converting them to 'a != 0'.
For example, both of these transformations can do this:
(('~flt', 0.0, ('fabs', a)), ('fne', a, 0.0)),
(('~flt', ('fneg', ('fabs', a)), 0.0), ('fne', a, 0.0)),
Both fsign(fabs(NaN)) and fsign(fneg(fabs(NaN))) should produce zero,
but, since 'NaN != 0.0' is true, cascading these transformations could
cause them to generate 1.0 or -1.0 respecively.
No shader-db or fossil-db changes on any Intel platform.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6358>
Ian Romanick [Tue, 18 Feb 2020 20:52:42 +0000 (12:52 -0800)]
nir/algebraic: Fix broken NaN and -0.0 behavior
No shader-db or fossil-db changes on any Intel platform.
v2: Add a coding line to fix SCons build problems caused by the ±
character.
Fixes:
25bfba3335d ("nir/algebraic: Recognize open-coded copysign(1.0, a)")
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6358>
Ian Romanick [Wed, 5 Aug 2020 02:43:52 +0000 (19:43 -0700)]
spir-v: Mark floating point comparisons exact
OpenGL GLSL, OpenGL ARB assembly shaders, and DX9 are pretty loose about
the behavior in the presence of NaNs. Many GPUs that implement these
specifications do not even have a representation of NaN. However,
OpenCL and Vulkan SPIR-V are not so lax. Both actually have some
required behavior in the presence of NaN, and, of the two, OpenCL is the
most strict.
For years we have implemented SPIR-V by using the same comparison
opcodes as we use for OpenGL GLSL and OpenGL assembly shaders. This has
repeatedly caused problems where an optimization that is valid in the
NaN-relaxed world is not valid in Vulkan or OpenCL. To fix this, set
the "exact" flag on comparisons instructions generated from SPIR-V.
This will block optimizations that may have different NaN behavior.
v2: Set the exact flag in the nir_builder, not in the vtn_builder.
v3: Add an assertion in vtn_handle_constant that the exact flag wasn't
set (because it's ignored). Rebase on
80163bbec3a ("nir/vtn: Support
OpOrdered and OpUnordered opcodes"). Mark the NIR generated for those
opcodes as exact as well.
v4: s/unused_exact/exact/ in a couple places, and assert that exact has
the expected value (true in one place, false in the other). Suggested
by Caio.
Closes: #3345
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Tested-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Fixes:
8513b12590c ("nir/opt_if: split ALU from Phi more aggressively")
This commit doesn't really fix anything in
8513b12590c. However,
without
8513b12590c, a regression is triggered in RADV on No Man's
Sky. I want to ensure that this change is only applied on top of
8513b12590c, and Fixes: seems the safest way to do that.
No shader-db changes on any Intel platform. This only affects SPIR-V,
and we have no OpenGL SPIR-V shaders in shader-db.
124 shaders in Shadow of the Tomb Raider (Steam "native") were hurt by 1
spill and 1 fill each.
All Intel platforms had similar results. (Tiger Lake shown)
Instructions in all programs:
155668276 ->
155685764 (+0.0%)
SENDs in all programs: 6474570 -> 6474570 (+0.0%)
Loops in all programs: 35271 -> 35271 (+0.0%)
Cycles in all programs:
3198055373 ->
3198628031 (+0.0%)
Spills in all programs: 231522 -> 231646 (+0.1%)
Fills in all programs: 347571 -> 347695 (+0.0%)
Vega
Totals:
SGPRs:
20955712 ->
20956756 (+0.00%); split: -0.02%, +0.03%
VGPRs:
13476920 ->
13473132 (-0.03%); split: -0.07%, +0.04%
CodeSize:
613371940 ->
613339348 (-0.01%); split: -0.06%, +0.05%
MaxWaves: 3111886 -> 3112481 (+0.02%); split: +0.02%, -0.00%
Instrs:
120723785 ->
120746991 (+0.02%); split: -0.04%, +0.06%
Cycles:
626658992 ->
626862708 (+0.03%); split: -0.05%, +0.08%
VMEM:
216330854 ->
216343196 (+0.01%); split: +0.04%, -0.04%
SMEM:
32079391 ->
32081972 (+0.01%); split: +0.05%, -0.04%
VClause: 2688784 -> 2688789 (+0.00%); split: -0.03%, +0.03%
SClause: 6554669 -> 6556251 (+0.02%); split: -0.01%, +0.03%
Copies: 5356667 -> 5353283 (-0.06%); split: -0.36%, +0.29%
Branches: 954466 -> 954716 (+0.03%); split: -0.01%, +0.04%
PreSGPRs: 9078300 -> 9081626 (+0.04%); split: -0.01%, +0.05%
PreVGPRs:
10972090 ->
10966576 (-0.05%); split: -0.06%, +0.01%
Totals from 48239 (12.08% of 399432) affected shaders:
SGPRs: 2713984 -> 2715028 (+0.04%); split: -0.16%, +0.19%
VGPRs: 1997804 -> 1994016 (-0.19%); split: -0.46%, +0.27%
CodeSize:
172094092 ->
172061500 (-0.02%); split: -0.21%, +0.19%
MaxWaves: 337327 -> 337922 (+0.18%); split: +0.20%, -0.02%
Instrs:
33053657 ->
33076863 (+0.07%); split: -0.15%, +0.22%
Cycles:
254961228 ->
255164944 (+0.08%); split: -0.12%, +0.20%
VMEM:
15165226 ->
15177568 (+0.08%); split: +0.59%, -0.51%
SMEM: 3304938 -> 3307519 (+0.08%); split: +0.49%, -0.41%
VClause: 766225 -> 766230 (+0.00%); split: -0.12%, +0.12%
SClause: 1332645 -> 1334227 (+0.12%); split: -0.04%, +0.16%
Copies: 2040651 -> 2037267 (-0.17%); split: -0.94%, +0.77%
Branches: 743668 -> 743918 (+0.03%); split: -0.01%, +0.05%
PreSGPRs: 1697667 -> 1700993 (+0.20%); split: -0.07%, +0.27%
PreVGPRs: 1718424 -> 1712910 (-0.32%); split: -0.39%, +0.07%
Polaris
Totals:
SGPRs:
21349172 ->
21354376 (+0.02%); split: -0.02%, +0.04%
VGPRs:
13690680 ->
13686920 (-0.03%); split: -0.07%, +0.04%
CodeSize:
613745824 ->
613704988 (-0.01%); split: -0.06%, +0.05%
MaxWaves: 2775012 -> 2775189 (+0.01%); split: +0.01%, -0.00%
Instrs:
120735079 ->
120756209 (+0.02%); split: -0.04%, +0.06%
Cycles:
627906100 ->
628076156 (+0.03%); split: -0.05%, +0.08%
VMEM:
216623065 ->
216641838 (+0.01%); split: +0.04%, -0.04%
SMEM:
32295618 ->
32299338 (+0.01%); split: +0.05%, -0.04%
VClause: 2711025 -> 2711141 (+0.00%); split: -0.03%, +0.04%
SClause: 6545185 -> 6546769 (+0.02%); split: -0.01%, +0.03%
Copies: 5387723 -> 5383249 (-0.08%); split: -0.37%, +0.29%
Branches: 953775 -> 953954 (+0.02%); split: -0.01%, +0.03%
PreSGPRs: 9148814 -> 9153211 (+0.05%); split: -0.01%, +0.06%
PreVGPRs:
11029429 ->
11023915 (-0.05%); split: -0.06%, +0.01%
Totals from 48239 (12.00% of 402052) affected shaders:
SGPRs: 2682056 -> 2687260 (+0.19%); split: -0.16%, +0.35%
VGPRs: 1994436 -> 1990676 (-0.19%); split: -0.46%, +0.27%
CodeSize:
170857060 ->
170816224 (-0.02%); split: -0.21%, +0.19%
MaxWaves: 295429 -> 295606 (+0.06%); split: +0.07%, -0.01%
Instrs:
32808802 ->
32829932 (+0.06%); split: -0.16%, +0.22%
Cycles:
254633252 ->
254803308 (+0.07%); split: -0.13%, +0.20%
VMEM:
14897934 ->
14916707 (+0.13%); split: +0.65%, -0.52%
SMEM: 3289726 -> 3293446 (+0.11%); split: +0.53%, -0.42%
VClause: 775318 -> 775434 (+0.01%); split: -0.11%, +0.13%
SClause: 1304867 -> 1306451 (+0.12%); split: -0.04%, +0.16%
Copies: 2026334 -> 2021860 (-0.22%); split: -0.99%, +0.77%
Branches: 742554 -> 742733 (+0.02%); split: -0.02%, +0.04%
PreSGPRs: 1690887 -> 1695284 (+0.26%); split: -0.07%, +0.33%
PreVGPRs: 1717709 -> 1712195 (-0.32%); split: -0.40%, +0.07%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6358>
Ian Romanick [Tue, 11 Aug 2020 01:34:37 +0000 (18:34 -0700)]
nir/algebraic: Add some compare-with-zero optimizations that are exact
This prevents some fossil-db regressions in "spir-v: Mark floating point
comparisons exact".
v2: Note that the patterns and replacements produce the same value when
isnan(b). Suggested by Caio.
v3: Use C99 isfinite() instead of (obsolete) BSD finite(). Fixes
various Windows builds.
No fossil-db changes on any Inetl platform, Vega, or Polaris10.
All Intel platforms had similar results. (Tiger Lake shown)
total instructions in shared programs:
20908670 ->
20908672 (<.01%)
instructions in affected programs: 69 -> 71 (2.90%)
helped: 0
HURT: 1
total cycles in shared programs:
473515288 ->
473513940 (<.01%)
cycles in affected programs: 4942 -> 3594 (-27.28%)
helped: 2
HURT: 0
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6358>
Ian Romanick [Wed, 8 Jul 2020 19:53:07 +0000 (12:53 -0700)]
nir/algebraic: Mark some logic-joined comparison reductions as exact
This also prevents some fossil-db regressions in "spir-v: Mark floating
point comparisons exact".
v2: Mark the fmin / fmax in the replacement exact to prevent other
optimizations from ruining the NaN-clensing property of the fmin / fmax.
Suggested by Rhys. Don't assume that constants are not NaN because some
components of a vector might be NaN while others are numbers. Noticed
by Rhys. This causes ~8 more shaders in Age of Wonders III (dxvk) to
regress on cycles (not instructions) by less than 1% when "spir-v: Mark
floating point comparisons exact" is applied. This difference is too
small to care.
All Intel platforms had similar results. (Tiger Lake shown)
total instructions in shared programs:
20908668 ->
20908670 (<.01%)
instructions in affected programs: 9196 -> 9198 (0.02%)
helped: 10
HURT: 5
helped stats (abs) min: 1 max: 2 x̄: 1.40 x̃: 1
helped stats (rel) min: 0.02% max: 5.41% x̄: 2.20% x̃: 2.16%
HURT stats (abs) min: 2 max: 6 x̄: 3.20 x̃: 3
HURT stats (rel) min: 2.44% max: 16.67% x̄: 9.39% x̃: 12.50%
95% mean confidence interval for instructions value: -1.22 1.49
95% mean confidence interval for instructions %-change: -2.08% 5.41%
Inconclusive result (value mean confidence interval includes 0).
total cycles in shared programs:
473515330 ->
473515288 (<.01%)
cycles in affected programs: 67146 -> 67104 (-0.06%)
helped: 10
HURT: 7
helped stats (abs) min: 1 max: 36 x̄: 15.90 x̃: 17
helped stats (rel) min: 0.01% max: 1.29% x̄: 0.66% x̃: 0.89%
HURT stats (abs) min: 1 max: 48 x̄: 16.71 x̃: 4
HURT stats (rel) min: 0.08% max: 1.94% x̄: 0.87% x̃: 0.19%
95% mean confidence interval for cycles value: -13.88 8.94
95% mean confidence interval for cycles %-change: -0.56% 0.49%
Inconclusive result (value mean confidence interval includes 0).
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6358>
Ian Romanick [Tue, 18 Feb 2020 20:34:15 +0000 (12:34 -0800)]
nir: Correctly constant fold fsign(NaN) and fsign(-0)
GLSL and SPIR-V GLSL.std.450 don't have any requirements for fsign(NaN),
and both only require that FSign(-0.0) == 0.0. OpenCL, on the other
hand, requires sign(-0.0) be exactly -0.0. It also requires that
sign(NaN) be exactly 0.0.
In practice, this change is difficult to test. Our GLSL frontend
already constant folds sign(NaN) to 0.0 before even getting to NIR. As
far as I can tell, glslang does the same. I don't have a good way to
run an OpenCL SPIR-V test. Maybe SPIR-V GLSL.std.450 assembly?
No shader-db or fossil-db changes on any Intel platform.
Acked-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6358>
Ian Romanick [Sat, 25 Jan 2020 01:10:07 +0000 (17:10 -0800)]
nir/algebraic: Don't add reordered version of patterns for commutative instructions
The reordered are automatically considered by nir_algebraic rules for
commutative instructions.
No shader-db or fossil-db changes on any Intel platform.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6358>
Ian Romanick [Fri, 12 Jun 2020 01:48:41 +0000 (18:48 -0700)]
Revert "nir: Replace an odd comparison involving fmin of -b2f"
I originally noticed that
3b308147916 ("nir/algebraic: Optimize 1-bit
Booleans") caused this pattern no longer be matched by incorrectly
replacing b@32 with b@1. Making that correct had no effect on
shader-db. When this pattern originally was added, it only affected 4
shaders, so it's not worth the effort to debug further.
This reverts commit
f50400cc8040cf2d07de97e76d9b1ed144c5c8b4.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6358>
Ian Romanick [Wed, 8 Jul 2020 00:30:42 +0000 (17:30 -0700)]
nir/algebraic: Make some notes about comparison rearrangements versus infinity
The original comment was a little terse and a little incorrect. The
rearrangements are fine w.r.t. NaN. However, they produce incorrect
results if one operand is +Inf and the other is -Inf.
A later commit, "nir/algebraic: Add some compare-with-zero optimizations
that are exact", will add some more patterns here. It may be reasonable
to squash this commit (forward) into that commit.
v2: Fix some incorrect comparisons operators in the comment (<= vs >=).
Add commentary that subtraction works like addition w.r.t. NaN. Both
noticed / suggested by Caio.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6358>
Ian Romanick [Tue, 18 Feb 2020 18:18:57 +0000 (10:18 -0800)]
nir: Make some notes about fsign versus NaN
This commit only documents the current behavior, even if that behavior
is not the behavior preferred by the relevant specs.
In SPIR-V, there are two flavors of the sign instruction, and each lives
in an extended instruction set. The GLSL.std.450 FSign instruction is
defined as:
Result is 1.0 if x > 0, 0.0 if x = 0, or -1.0 if x < 0.
This also matches the GLSL 4.60 definition.
However, the OpenCL.ExtendedInstructionSet.100 sign instruction is
defined as:
Returns 1.0 if x > 0, -0.0 if x = -0.0, +0.0 if x = +0.0, or -1.0 if
x < 0. Returns 0.0 if x is a NaN.
There are two differences. Each treats -0.0 differently, and each also
treats NaN differently. Specifically, GLSL.std.450 FSign does not
define any specific behavior for NaN.
There has been some discussion in Khronos about the NaN behavior of
GLSL.std.450 FSign. As part of that discussion, I did some research
into how we treat NaN for nir_op_fsign, and this commit just captures
some of those notes.
v2: Document the expected behavior of nir_op_fsign more thoroughly.
Suggested by Rhys. Note that the current implementation of constant
folding does not produce the expected result for NaN. Suggested by
Caio.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> [v1]
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6358>
Andrii Simiklit [Mon, 28 Dec 2020 13:58:24 +0000 (15:58 +0200)]
st/mesa: don't affect original st_CompressedTexSubImage parameters
The fallback path is still possible here so let keep them as is.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3952
Fixes:
4b02f165 ("st/mesa: implement PBO upload for glCompressedTex(Sub)Image")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8258>
Marek Olšák [Sat, 28 Nov 2020 05:44:19 +0000 (00:44 -0500)]
gallium: remove PIPE_CAP_INFO_START_WITH_USER_INDICES and fix all drivers
Drivers aren't allowed to ignore start with user index buffers anymore.
This is required by the new fast path where mesa/main is using pipe_draw_info.
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7679>
Marek Olšák [Tue, 3 Nov 2020 18:04:03 +0000 (13:04 -0500)]
st/mesa: implement Driver.DrawGallium callbacks
This is the new fast path replacing the _mesa_prim path.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7679>
Marek Olšák [Sun, 22 Nov 2020 03:08:50 +0000 (22:08 -0500)]
virgl: fix handling draw info
index_bias is undefined if index_size == 0.
index bounds are undefined if index_bounds_valid == false.
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7679>
Marek Olšák [Sun, 22 Nov 2020 06:45:11 +0000 (01:45 -0500)]
v3d: don't use index_bias if not indexed
index_bias is undefined if index_size == 0.
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7679>
Marek Olšák [Sun, 22 Nov 2020 06:53:18 +0000 (01:53 -0500)]
vc4: don't use index_bias if indexed
index_bias is undefined if index_size == 0.
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7679>
Marek Olšák [Sun, 22 Nov 2020 07:09:58 +0000 (02:09 -0500)]
svga: fix handling draw info
index_bias is undefined if index_size == 0.
index bounds are undefined if index_bounds_valid == false.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7679>
Marek Olšák [Sun, 22 Nov 2020 07:01:18 +0000 (02:01 -0500)]
swr: fix handling draw info
index_bias is undefined if index_size == 0.
index bounds are undefined if index_bounds_valid == false.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7679>
Marek Olšák [Sun, 22 Nov 2020 06:40:26 +0000 (01:40 -0500)]
r600: fix handling draw info
has_user_indices is undefined if index_size == 0.
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7679>
Marek Olšák [Sun, 22 Nov 2020 03:21:26 +0000 (22:21 -0500)]
panfrost: don't use index_bias if not indexed
index_bias is undefined if index_size == 0.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7679>
Marek Olšák [Sun, 22 Nov 2020 07:22:45 +0000 (02:22 -0500)]
nouveau: fix handling draw info
index_bias is undefined if index_size == 0.
index bounds are undefined if index_bounds_valid == false.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7679>
Marek Olšák [Sun, 22 Nov 2020 06:37:34 +0000 (01:37 -0500)]
iris: don't use index_bias if not indexed
index_bias is undefined if index_size == 0.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7679>
Marek Olšák [Sun, 22 Nov 2020 02:49:00 +0000 (21:49 -0500)]
freedreno: fixes handling draw info
index_bias is undefined if index_size == 0.
index bounds are undefined if index_bounds_valid == false.
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7679>
Marek Olšák [Sun, 22 Nov 2020 04:26:43 +0000 (23:26 -0500)]
gallium: fix draw info setup in draw and utilities
index_bias is undefined if index_size == 0.
index bounds are undefined if index_bounds_valid == false.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7679>
Marek Olšák [Tue, 17 Nov 2020 22:19:06 +0000 (17:19 -0500)]
gallium: remove and emulate PIPE_CAP_MULTI_DRAW
To remove PIPE_CAP checking in the common code.
It's better if drivers lower multi draws even if the hardware doesn't
support it beause the multi draw loop can be moved deeper into the driver
to remove more overhead.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7679>
Marek Olšák [Sun, 22 Nov 2020 03:19:46 +0000 (22:19 -0500)]
gallium/u_threaded: clear vertices_per_patch if prim type != PATCHES
We use memcmp when combining back-to-back draws into a multi draw.
Clear vertices_per_patch if it's irrelevant to help memcmp return
a match.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7679>
Marek Olšák [Mon, 2 Nov 2020 07:00:37 +0000 (02:00 -0500)]
vbo: switch immediate Begin/End to DrawGallium
This makes gallium faster because st/mesa doesn't have to translate
_mesa_prim.
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7679>
Marek Olšák [Mon, 2 Nov 2020 06:46:24 +0000 (01:46 -0500)]
vbo: remove _mesa_prim parameter from vbo_copy_vertices
glBegin/End won't use _mesa_prim, so we need to stop using it.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7679>
Marek Olšák [Mon, 2 Nov 2020 06:46:24 +0000 (01:46 -0500)]
vbo: remove _mesa_prim parameter from vbo_merge_draws
glBegin/End won't use _mesa_prim, so we need to stop using it.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7679>
Marek Olšák [Mon, 2 Nov 2020 06:46:24 +0000 (01:46 -0500)]
vbo: remove _mesa_prim parameter from vbo_try_prim_conversion
glBegin/End won't use _mesa_prim, so we need to stop using it.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7679>
Marek Olšák [Sun, 1 Nov 2020 22:07:03 +0000 (17:07 -0500)]
mesa: switch MultiDrawElements(BaseVertex) to DrawGallium*
This makes gallium faster because st/mesa doesn't have to translate
_mesa_prim.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7679>
Marek Olšák [Sun, 1 Nov 2020 21:37:23 +0000 (16:37 -0500)]
mesa: switch Draw(Range)Elements(BaseVertex) calls to DrawGallium
This makes gallium faster because st/mesa doesn't have to translate
_mesa_prim.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7679>
Marek Olšák [Tue, 3 Nov 2020 16:02:51 +0000 (11:02 -0500)]
mesa: switch (Multi)DrawArrays to DrawGallium
This makes gallium faster because st/mesa doesn't have to translate
_mesa_prim.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7679>
Marek Olšák [Tue, 3 Nov 2020 18:03:28 +0000 (13:03 -0500)]
vbo: add vbo_get_minmax_indices_gallium
to be used by st/mesa to get index bounds because it won't have _mesa_prim
with the new draw interface.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7679>
Marek Olšák [Sun, 1 Nov 2020 20:39:16 +0000 (15:39 -0500)]
mesa: add a fallback for drivers not implementing Driver.DrawGallium*
This is for classic drivers and it translates pipe_draw_info to the old
interface using _mesa_prim.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7679>
Marek Olšák [Tue, 1 Dec 2020 18:51:09 +0000 (13:51 -0500)]
gallium: add pipe_draw_info::index::gl_bo
mesa/main will fill pipe_draw_info but it has no access to pipe_resources,
so we need gl_buffer_object here.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7679>
Marek Olšák [Tue, 3 Nov 2020 17:14:12 +0000 (12:14 -0500)]
mesa: add Driver.DrawGallium* functions to be used by main/draw.c
This is a new Draw interface using the same parameters as draw_vbo.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7679>
Marek Olšák [Sun, 1 Nov 2020 19:46:53 +0000 (14:46 -0500)]
vbo: change the parameters of vbo_get_minmax_index to get rid of _mesa_prim
This will be used by a new Draw interface.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7679>
Marek Olšák [Mon, 2 Nov 2020 06:57:48 +0000 (01:57 -0500)]
vbo: only set count and end when closing _mesa_prim
It's already set everywhere except vbo_exec_wrap_buffers.
This is a small optimization removing superfluous code.
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7679>
Marek Olšák [Wed, 4 Nov 2020 04:15:41 +0000 (23:15 -0500)]
mesa: fix an overflow check for MultiDrawElements
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7679>
Jesse Natalie [Mon, 28 Dec 2020 19:04:31 +0000 (11:04 -0800)]
CI: Enable d3d12 driver for Linux CI builds
Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8251>
Jesse Natalie [Mon, 28 Dec 2020 19:21:06 +0000 (11:21 -0800)]
CI: Install DirectX-Headers package for x86 container
Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8251>
Adam Jackson [Fri, 18 Dec 2020 14:45:41 +0000 (09:45 -0500)]
drisw: Use debug_screen_wrap like everybody else
I tried to use GALLIUM_TRACE with llvmpipe and it didn't work, because
we were never letting the debug wrappers initialize.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8166>
Jesse Natalie [Thu, 19 Nov 2020 22:44:08 +0000 (14:44 -0800)]
microsoft/clc: Fix const violations from ralloc_steal
Fixes:
ff05da7f8dc ("microsoft: Add CLC frontend and kernel/compute support to DXIL converter")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7697>
Adam Jackson [Wed, 16 Dec 2020 23:24:52 +0000 (18:24 -0500)]
virgl: Enable GL_EXT_texture_sRGB_RG8
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8060>
Adam Jackson [Wed, 16 Dec 2020 22:54:31 +0000 (17:54 -0500)]
zink: Enable GL_EXT_texture_sRGB_RG8
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8060>
Adam Jackson [Wed, 16 Dec 2020 22:53:49 +0000 (17:53 -0500)]
zink: Enable GL_EXT_texture_sRGB_R8
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8060>
Adam Jackson [Tue, 15 Dec 2020 18:49:37 +0000 (13:49 -0500)]
mesa: Implement GL_EXT_texture_sRGB_RG8 for softpipe and llvmpipe
sRGB_RG8 is not registered for big-GL yet, see this Khronos issue
for updates on that:
https://github.com/KhronosGroup/OpenGL-Registry/issues/450
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8060>
Adam Jackson [Tue, 15 Dec 2020 17:35:33 +0000 (12:35 -0500)]
mesa: Cosmetic cleanups to GL_EXT_texture_sRGB_R8
This extension dates to 2015 not 2018, and since there's only one
texture format to check for the additional GL_TRUE is meaningless.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8060>
Adam Jackson [Thu, 17 Dec 2020 16:07:30 +0000 (11:07 -0500)]
treewide: Disambiguate various variables named "debug_options"
Name them after what they control so 'vi -t' can take you somewhere
useful.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8165>
Mike Blumenkrantz [Fri, 24 Jul 2020 13:52:34 +0000 (09:52 -0400)]
zink: handle gl_SampleMaskIn loading in ntv
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8316>
Mike Blumenkrantz [Mon, 3 Aug 2020 15:53:44 +0000 (11:53 -0400)]
zink: set PIPE_CAP_MAX_VIEWPORTS
enables ARB_viewport_array
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8311>
Mike Blumenkrantz [Fri, 24 Jul 2020 12:43:08 +0000 (08:43 -0400)]
zink: handle fs interpolation functions in ntv
basically load_deref but with different ops
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8203>
Erik Faye-Lund [Mon, 4 Jan 2021 15:27:59 +0000 (16:27 +0100)]
zink: only emit each cap once
This just prevents us from emitting some caps a bunch of times. Since
there's few caps in use, it seems reasonable to use this mechanism for
all caps, as it's unlikely to add up to anything worth worrying about.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8312>
Mauro Rossi [Sat, 2 Jan 2021 12:20:46 +0000 (13:20 +0100)]
android: pan/bi: Remove old IR opcode table
Fixes the following building error:
clang: error: no such file or directory: 'external/mesa/src/panfrost/bifrost/bi_tables.c'
clang: error: no input files
Fixes:
b691aeaacf93 ("pan/bi: Remove old IR opcode table")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8294>
Mauro Rossi [Sat, 2 Jan 2021 12:19:56 +0000 (13:19 +0100)]
android: pan/bi: Remove NIR->old IR
Fixes the following building error:
clang: error: no such file or directory: 'external/mesa/src/panfrost/bifrost/bi_special.c'
clang: error: no input files
Fixes:
e5ec0dc18320 ("pan/bi: Remove NIR->old IR")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8294>
Mauro Rossi [Sat, 2 Jan 2021 12:18:50 +0000 (13:18 +0100)]
android: pan/bi: Remove old IR packs
Necessary for Android build after commit
a1e150fc4d4e
Fixes:
a1e150fc4d4e ("pan/bi: Remove old IR packs")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8294>
Mauro Rossi [Sat, 2 Jan 2021 12:17:42 +0000 (13:17 +0100)]
android: pan/bi: Remove combine lowering
Fixes the following building error:
clang: error: no such file or directory: 'external/mesa/src/panfrost/bifrost/bi_lower_combine.c'
clang: error: no input files
Fixes:
8b0d0a931b80 ("pan/bi: Remove combine lowering")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8294>
Mauro Rossi [Sat, 2 Jan 2021 12:16:48 +0000 (13:16 +0100)]
android: pan/bi: Generate instruction packer for new IR
Necessary for Android build after commit
82328a524519
Fixes:
82328a524519 ("pan/bi: Generate instruction packer for new IR")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8294>
Mauro Rossi [Sat, 2 Jan 2021 11:08:34 +0000 (12:08 +0100)]
android: pan/bi: Generate builder routines
Fixes the following building error:
external/mesa/src/panfrost/bifrost/bifrost_compile.c:38:10: fatal error: 'bi_builder.h' file not found
^~~~~~~~~~~~~~
1 error generated.
Fixes:
8ef0d411708a ("pan/bi: Generate builder routines")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8294>
Mauro Rossi [Sat, 2 Jan 2021 11:01:36 +0000 (12:01 +0100)]
android: pan/bi: Generate instruction printer
To avoid building errors in Android
Fixes:
1893a3805e41 ("pan/bi: Generate instruction printer")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8294>
Samuel Pitoiset [Mon, 4 Jan 2021 15:22:23 +0000 (16:22 +0100)]
radv: disable A2 SNORM/SSCALED/SINT for texel buffers & images on all gens
AMDVLK and AMDGPU-PRO also don't support these formats for texel
buffers and images.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3386
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8315>
Rhys Perry [Mon, 4 Jan 2021 10:41:39 +0000 (10:41 +0000)]
aco: fix incorrect address calculation for load_barycentric_at_sample
Fix address calculation for indirect load_barycentric_at_sample on GFX6-8
with a uniform sample index.
A non-zero uniform sample index does not seem to be tested by CTS.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3966
Fixes:
93c8ebfa780 ("aco: Initial commit of independent AMD compiler")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8302>
Alyssa Rosenzweig [Mon, 4 Jan 2021 15:22:27 +0000 (10:22 -0500)]
pan/bi: Fix TEXS register counts
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Fixes:
cffc1d90da0 ("pan/bi: Add staging register counts to ISA.xml")
Reported-by: Icecream95
Tested-by: macc24
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8310>
Boris Brezillon [Fri, 18 Dec 2020 13:40:31 +0000 (14:40 +0100)]
panfrost: Allow 3D AFBC on Bifrost v7
This feature doesn't seem to work properly on Midgard, and is flagged
as unsupported on Bifrost v6.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8125>
Boris Brezillon [Wed, 16 Dec 2020 13:48:57 +0000 (14:48 +0100)]
panfrost: Fix calculation of body/header pointers for 3D AFBC
When using 3D AFBC, all headers are placed at the beginning instead of
being interleaved with each surface body, which forces us to adjust
the calculation in that case.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8125>