Artem Belevich [Wed, 7 Dec 2022 23:46:12 +0000 (15:46 -0800)]
[NVPTX] Minor cleanups and typo fixes.
Leonard Chan [Thu, 8 Dec 2022 00:07:00 +0000 (00:07 +0000)]
[compiler-rt][hwasan] Add unused attribute to GetRegisters
This is unused in the android toolchain and fixes
https://lab.llvm.org/buildbot/#/builders/77/builds/23883
Aart Bik [Wed, 7 Dec 2022 21:57:04 +0000 (13:57 -0800)]
[mlir][sparse] introduce sparse vectorization to the sparse compiler pipeline
Reviewed By: Peiming
Differential Revision: https://reviews.llvm.org/D139581
Roman Lebedev [Wed, 7 Dec 2022 23:50:31 +0000 (02:50 +0300)]
[NFC][Attributor] Fix warning in last commit
```
/repositories/llvm-project/llvm/include/llvm/Transforms/IPO/Attributor.h:5076:47: note: cast one or both operands to int to silence this warning
1 warning generated.
[ 89% 599/666][ 75% 00:48 + 00:15] Building CXX object lib/Passes/CMakeFiles/LLVMPasses.dir/PassBuilderPipelines.cpp.o
In file included from /repositories/llvm-project/llvm/lib/Passes/PassBuilderPipelines.cpp:42:
/repositories/llvm-project/llvm/include/llvm/Transforms/IPO/Attributor.h:5076:47: warning: use of bitwise '|' with boolean operands [-Wbitwise-instead-of-logical]
bool isWriteOrAssumption() const { return isWrite() | isAssumption(); }
^~~~~~~~~~~~~~~~~~~~~~~~~~
||
```
Keith Smiley [Wed, 7 Dec 2022 19:13:03 +0000 (11:13 -0800)]
[bazel] Add fenv_darwin_impl.h to target
Fixes https://github.com/llvm/llvm-project/issues/59378
Differential Revision: https://reviews.llvm.org/D139563
Johannes Doerfert [Mon, 11 Jul 2022 22:15:22 +0000 (17:15 -0500)]
[Attributor] Introduce assumption accesses in AAPointerInfo
Assumptions can help us reason about memory content. This patch teaches
AAPointerInfo to reason about memory assumptions of the following form:
```
%x = load %ptr
... code not writing memory, may include branches ...
%c = %x == %val
... code not writing memory, may include branches ...
llvm.assume(%c)
```
Assumption accesses are recognized from the involved load (%x above).
Assumption accesses are treated special and neither as ordinary read or
write. We use read encoding with an extra flag. Reads are not impacting
other reads or writes. Writes could do that. We don't want assumptions
to impact other writes as they themselves only confirm a value, not
write it. So the "other" write might be required as the assumption only
confirms the effect of that write.
Roman Lebedev [Wed, 7 Dec 2022 23:27:40 +0000 (02:27 +0300)]
[NFC] Port all Util tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:38 +0000 (02:27 +0300)]
[NFC] Port all StraightLineStrengthReduce tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:37 +0000 (02:27 +0300)]
[NFC] Port all SimplifyCFG tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:37 +0000 (02:27 +0300)]
[NFC] Port all SimpleLoopUnswitch tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:37 +0000 (02:27 +0300)]
[NFC] Port all SeparateConstOffsetFromGEP tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:37 +0000 (02:27 +0300)]
[NFC] Port all ScalarizeMaskedMemIntrin tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:36 +0000 (02:27 +0300)]
[NFC] Port all SampleProfile tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:36 +0000 (02:27 +0300)]
[NFC] Port all SROA tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:36 +0000 (02:27 +0300)]
[NFC] Port all SLPVectorizer tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:36 +0000 (02:27 +0300)]
[NFC] Port all SCCP tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:35 +0000 (02:27 +0300)]
[NFC] Port all Reassociate tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:34 +0000 (02:27 +0300)]
[NFC] Port all PhaseOrdering tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:34 +0000 (02:27 +0300)]
[NFC] Port all PartiallyInlineLibCalls tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:34 +0000 (02:27 +0300)]
[NFC] Port all PartialInlining tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:33 +0000 (02:27 +0300)]
[NFC] Port all NewGVN tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:33 +0000 (02:27 +0300)]
[NFC] Port all NaryReassociate tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:32 +0000 (02:27 +0300)]
[NFC] Port all MergeICmps tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:32 +0000 (02:27 +0300)]
[NFC] Port all MakeGuardsExplicit tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:31 +0000 (02:27 +0300)]
[NFC] Port all LowerWidenableCondition tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:31 +0000 (02:27 +0300)]
[NFC] Port all LowerInvoke tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:30 +0000 (02:27 +0300)]
[NFC] Port all LowerGuardIntrinsic tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:30 +0000 (02:27 +0300)]
[NFC] Port all LowerGlobalDestructors tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:30 +0000 (02:27 +0300)]
[NFC] Port all LowerExpectIntrinsic tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:30 +0000 (02:27 +0300)]
[NFC] Port all LowerConstantIntrinsics tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:30 +0000 (02:27 +0300)]
[NFC] Port all LowerAtomic tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:30 +0000 (02:27 +0300)]
[NFC] Port all LoopVersioningLICM tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:29 +0000 (02:27 +0300)]
[NFC] Port all LoopVersioning tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:29 +0000 (02:27 +0300)]
[NFC] Port all LoopVectorize tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:29 +0000 (02:27 +0300)]
[NFC] Port all LoopUnrollAndJam tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:29 +0000 (02:27 +0300)]
[NFC] Port all LoopUnroll tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:29 +0000 (02:27 +0300)]
[NFC] Port all LoopTransformWarning tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:28 +0000 (02:27 +0300)]
[NFC] Port all LoopSimplifyCFG tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:28 +0000 (02:27 +0300)]
[NFC] Port all LoopSimplify tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:28 +0000 (02:27 +0300)]
[NFC] Port all LoopRotate tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:28 +0000 (02:27 +0300)]
[NFC] Port all LoopReroll tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:28 +0000 (02:27 +0300)]
[NFC] Port all LoopPredication tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:28 +0000 (02:27 +0300)]
[NFC] Port all LoopLoadElim tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:27 +0000 (02:27 +0300)]
[NFC] Port all LoopInterchange tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:27 +0000 (02:27 +0300)]
[NFC] Port all LoopIdiom tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:27 +0000 (02:27 +0300)]
[NFC] Port all LoopFusion tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:27 +0000 (02:27 +0300)]
[NFC] Port all LoopFlatten tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:27 +0000 (02:27 +0300)]
[NFC] Port all LoopDistribute tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:26 +0000 (02:27 +0300)]
[NFC] Port all LoopDeletion tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:26 +0000 (02:27 +0300)]
[NFC] Port all LoopDataPrefetch tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:26 +0000 (02:27 +0300)]
[NFC] Port all LoopBoundSplit tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:26 +0000 (02:27 +0300)]
[NFC] Port all LoadStoreVectorizer tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:26 +0000 (02:27 +0300)]
[NFC] Port all LICM tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:25 +0000 (02:27 +0300)]
[NFC] Port all LCSSA tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:25 +0000 (02:27 +0300)]
[NFC] Port all JumpThreading tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:24 +0000 (02:27 +0300)]
[NFC] Port all InstSimplify tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:24 +0000 (02:27 +0300)]
[NFC] Port all InstMerge tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:24 +0000 (02:27 +0300)]
[NFC] Port all InstCombine tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:23 +0000 (02:27 +0300)]
[NFC] Port all IndVarSimplify tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:22 +0000 (02:27 +0300)]
[NFC] Port all IRCE tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:22 +0000 (02:27 +0300)]
[NFC] Port all GuardWidening tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:21 +0000 (02:27 +0300)]
[NFC] Port all GlobalOpt tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:21 +0000 (02:27 +0300)]
[NFC] Port all GlobalDCE tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:21 +0000 (02:27 +0300)]
[NFC] Port all GVNSink tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:21 +0000 (02:27 +0300)]
[NFC] Port all GVNHoist tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:20 +0000 (02:27 +0300)]
[NFC] Port all GVN tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:20 +0000 (02:27 +0300)]
[NFC] Port all FunctionSpecialization tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:20 +0000 (02:27 +0300)]
[NFC] Port all FunctionAttrs tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:19 +0000 (02:27 +0300)]
[NFC] Port all ForcedFunctionAttrs tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:19 +0000 (02:27 +0300)]
[NFC] Port all Float2Int tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:18 +0000 (02:27 +0300)]
[NFC] Port all DivRemPairs tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:18 +0000 (02:27 +0300)]
[NFC] Port all DeadStoreElimination tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:18 +0000 (02:27 +0300)]
[NFC] Port all DeadArgElim tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:18 +0000 (02:27 +0300)]
[NFC] Port all DFAJumpThreading tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:17 +0000 (02:27 +0300)]
[NFC] Port all CrossDSOCFI tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:17 +0000 (02:27 +0300)]
[NFC] Port all CorrelatedValuePropagation tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:17 +0000 (02:27 +0300)]
[NFC] Port all Coroutines tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:17 +0000 (02:27 +0300)]
[NFC] Port all ConstraintElimination tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:16 +0000 (02:27 +0300)]
[NFC] Port all ConstantHoisting tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:16 +0000 (02:27 +0300)]
[NFC] Port all CodeExtractor tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:16 +0000 (02:27 +0300)]
[NFC] Port all CanonicalizeFreezeInLoops tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:15 +0000 (02:27 +0300)]
[NFC] Port all CallSiteSplitting tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:15 +0000 (02:27 +0300)]
[NFC] Port all BlockExtractor tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:14 +0000 (02:27 +0300)]
[NFC] Port all Attributor tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:14 +0000 (02:27 +0300)]
[NFC] Port all ArgumentPromotion tests to `-passes=` syntax
Roman Lebedev [Wed, 7 Dec 2022 23:27:13 +0000 (02:27 +0300)]
[NFC] Port all ADCE tests to `-passes=` syntax
Tue Ly [Wed, 7 Dec 2022 19:24:46 +0000 (14:24 -0500)]
[libc] Fix undefined behavior in UInt<>::shift_right.
Fix undefined behavior of left-shifting uint64_t by 64 in
`UInt<>::shift_right` implementation.
Reviewed By: michaelrj, sivachandra
Differential Revision: https://reviews.llvm.org/D139566
Akira Hatanaka [Wed, 16 Nov 2022 22:20:23 +0000 (14:20 -0800)]
Add support for a backdoor driver option that enables emitting header
usage information in JSON to a file
Each line in the file is a JSON object that has the name of the main
source file followed by the list of system header files included
directly or indirectly from that file.
For example:
{"source":"/tmp/foo.c",
"includes":["/usr/include/stdio.h", "/usr/include/stdlib.h"]}
To reduce the amount of data written to the file, only the system
headers that are directly included from a non-system header file are
recorded.
In order to emit the header information in JSON, it is necessary to set
the following environment variables:
CC_PRINT_HEADERS_FORMAT=json CC_PRINT_HEADERS_FILTERING=only-direct-system
The following combination is equivalent to setting CC_PRINT_HEADERS=1:
CC_PRINT_HEADERS_FORMAT=textual CC_PRINT_HEADERS_FILTERING=none
Differential Revision: https://reviews.llvm.org/D137996
Krzysztof Parzyszek [Wed, 7 Dec 2022 18:04:25 +0000 (10:04 -0800)]
[Bitcode(Reader|Writer)] Convert Optional to std::optional
bixia1 [Wed, 7 Dec 2022 20:54:50 +0000 (12:54 -0800)]
[mlir][sparse] Add dependence on bufferization.
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D139571
Mahesh Ravishankar [Wed, 7 Dec 2022 01:00:37 +0000 (01:00 +0000)]
[mlir][Transforms] Simplify region before simplifying operation in CSE.
This covers more options for CSE. It also ensures that two operations
that have same operands but different regions to begin with, but same
regions after `simplifyRegions`, don't get both added to the list of
`knownValues`.
Fixes #59135
Differential Revision: https://reviews.llvm.org/D139490
Leonard Chan [Wed, 7 Dec 2022 23:09:53 +0000 (23:09 +0000)]
[compiler-rt][hwasan] Let CheckAddressSized eventually call HandleTagMismatch on Fuchsia
Any hwasan tag checking done through runtime calls like __hwasan_mem* or
__hwasan_load/store* currently raise a sigtrap on a tag mismatch. Hwasan
dumps as much information it knows on the tag mismatch by placing
important values in specific registers before the brk and encoding the
access information in the optional argument supplied to the brk. If the
platform hwasan runs on uses signal handlers, then users can see the
typical pretty hwasan error report, but Fuchsia doesn't use signal
handlers, so it's left up to the platform exception handler to print all
this encoded information.
This patch attempts to enter the regular error reporting path via
HandleTagMismatch if a new macro CAN_GET_REGISTERS is set. For now this
is only defined for Fuchsia + aarch64, but can be expanded for other
platforms.
Differential Revision: https://reviews.llvm.org/D139377
Johannes Doerfert [Tue, 4 Oct 2022 12:45:21 +0000 (05:45 -0700)]
[AMDGPU] Annotate the intrinsics to be default and nocallback
Differential Revision: https://reviews.llvm.org/D135155
Jakub Kuderski [Wed, 7 Dec 2022 22:21:41 +0000 (17:21 -0500)]
[mlir][arith] Fix comment typo. NFC.
Jakub Kuderski [Wed, 7 Dec 2022 22:15:55 +0000 (17:15 -0500)]
[mlir][arith] Rename addui_carry to addui_extended
The goal is to make the naming of the future `_extended` ops more
consistent. With unsigned addition, the carry value/flag and overflow
bit are the same, but this is not true when it comes to signed addition.
Also rename the second result from `carry` to `overflow`.
Reviewed By: antiagainst
Differential Revision: https://reviews.llvm.org/D139569
Jon Chesterfield [Wed, 7 Dec 2022 22:02:53 +0000 (22:02 +0000)]
[amdgpu] Reimplement LDS lowering
Renames the current lowering scheme to "module" and introduces two new
ones, "kernel" and "table", plus a "hybrid" that chooses between those three
on a per-variable basis.
Unit tests are set up to pass with the default lowering of "module" or "hybrid"
with this patch defaulting to "module", which will be a less dramatic codegen
change relative to the current. This reflects the sparsity of test coverage for
the table lowering method. Hybrid is better than module in every respect and
will be default in a subsequent patch.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D139433
Alexander Belyaev [Wed, 7 Dec 2022 17:30:36 +0000 (18:30 +0100)]
[mlir] Make patterns for folding tensor.empty optional.
At the moment, they are a part of EmptyOp::getCanonicalizationPatterns. When
extract_slice(tensor.empty) is rewritten as a new tensor.empty, it could
happen that we end up with two tensor.empty ops, since the original
tensor.empty can have two users. After bufferization such cases result in two
allocations.
Differential Revision: https://reviews.llvm.org/D139308
Simon Pilgrim [Wed, 7 Dec 2022 21:52:06 +0000 (21:52 +0000)]
[llvm-exegesis][x86] Add test coverage for Issue #38507
Ensure that the PBLENDVBrr0 destination register is never xmm0
Bran Hagger [Wed, 7 Dec 2022 10:00:15 +0000 (12:00 +0200)]
Enable kmpc_atomic functions for arm64
Define the same kmpc_atomic functions for arm and arm64 that are defined for x86 and x64.
Reviewed By: mstorsjo
Differential Revision: https://reviews.llvm.org/D139139
Chris Bieneman [Mon, 5 Dec 2022 20:21:41 +0000 (14:21 -0600)]
Generate DXIL Shader hash
DXIL shader bitcode is hashed and the hash is placed into the final
output object file in its own data part.
This change modifies the DXContainerGlobals pass to compute the shader
hash (just an MD5 of the bitcode) and put the shader hash data into a
global for the HASH part.
This also sets the hash flag as appropriate for if the hashed shader
contained debug information. There is additional handling required to
get debug information in shaders working correctly with our tooling,
but that will be addressed in subsequent patches.
Reviewed By: python3kgae
Differential Revision: https://reviews.llvm.org/D139357