st/mesa: fix incorrect size of UBO declarations

UniformBufferSize is in bytes so we need to divide by 16 to get the
number of constant buffer slots.  Also, the ureg_DECL_constant2D()
function takes first..last parameters so we need to subtract one
for the last value.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

st/mesa: don't use address register for constant-indexed ir_binop_ubo_load

Before, we were always using the address register and indirect addressing
to index into a UBO constant buffer.  With this change we only do that
when necessary.

Using the piglit bin/arb_uniform_buffer_object-rendering test as an
example:

Shader code:
  uniform ub_rot {float rotation; };
  ...
  m[1][1] = cos(rotation);

Before:
  IMM[1] INT32 {0, 1, 0, 0}
  1: UARL ADDR[0].x, IMM[1].xxxx
  2: MOV TEMP[0].x, CONST[3][ADDR[0].x].xxxx
  3: COS TEMP[1].x, TEMP[0].xxxx

After:
  0: COS TEMP[0].x, CONST[3][0].xxxx

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

st/mesa: allow 2D indexing for all shader types in translate_src()

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

st/mesa: don't ignore const buf index in src_register()

Otherwise, if we were creating a const buffer src register for a UBO
the index into the UBO was always zero.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

nvc0: expose 4 vertex streams, use stream ids in xfb

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0/ir: only merge emit/restart for identical streams

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0/ir: avoid creating restarts with non-0 stream

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0/ir: fix emitting vertex stream

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

mesa/st: add vertex stream support

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

gallium: add a cap for max vertex streams

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

gallium: add an index argument to create_query

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

gallium: add support for stream in so info

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

gallium: add vertex stream argument to EMIT/ENDPRIM

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

i965/fs: Mark predicated PLN instructions with dependency hints.

To implement the unlit_centroid_workaround, previously we emitted

   (+f0) pln(8) g20<1>F g16.4<0,1,0>F g4<8,8,1>F { align1 1Q };
   (-f0) pln(8) g20<1>F g16.4<0,1,0>F g2<8,8,1>F { align1 1Q };

where the flag register contains the channel enable bits from g0.

Since the predicates are complementary, the pair of pln instructions
write to non-overlapping components of the destination, which is the
case that the dependency control hints are designed for.

Typically setting dependency control hints on predicated instructions
isn't safe (if an instruction doesn't execute due to the predicate, it
won't update the scoreboard, leaving it in a bad state) but since we
must have at least one channel executing (i.e., +f0 is true for some
channel) by virtue of the fact that the thread is running, we can put
the +f0 pln instruction last and set the hints:

   (-f0) pln(8) g20<1>F g16.4<0,1,0>F g2<8,8,1>F { align1 NoDDClr 1Q };
   (+f0) pln(8) g20<1>F g16.4<0,1,0>F g4<8,8,1>F { align1 NoDDChk 1Q };

Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/fs: Predicate PLN instructions used in unlit centroid WA.

Maybe lets us skip some PLN instructions if whole subspans are disabled?

Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/fs: Add no_dd_{clear,check} fields to fs_inst.

And plumb them through. Also make the assert in the generator look like
the vec4 one.

Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/fs: Let sat-prop ignore live ranges if producer already has sat.

This sequence (where both x and w are used afterwards) wasn't handled.

   mul.sat x, y, z
   ...
   mov.sat w, x

We assumed that if x was used after the mov.sat, that we couldn't
propagate the saturate modifier, but in fact x was already saturated.

So ignore the live range check if the producing instruction already
saturates its result. Cuts one instruction from hundreds of TF2 shaders.

total instructions in shared programs: 1995631 -> 1994951 (-0.03%)
instructions in affected programs:     155248 -> 154568 (-0.44%)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Pass const references to emit functions.

Cuts 10k of .text and saves a bunch of useless struct copies.

i965/vec4: Pass const references to instruction functions.

   text    data     bss     dec     hex filename
4231165  123200   39648 4394013  430c1d i965_dri.so
4186277  123200   39648 4349125  425cc5 i965_dri.so

Cuts 43k of .text and saves a bunch of useless struct copies.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/vec4: Pass const references to vec4_instruction().

   text    data     bss     dec     hex filename
4244821  123200   39648 4407669  434175 i965_dri.so
4231165  123200   39648 4394013  430c1d i965_dri.so

Cuts 13k of .text and saves a bunch of useless struct copies.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Pass const references to instruction functions.

   text    data     bss     dec     hex filename
4270747  123200   39648 4433595  43a6bb i965_dri.so
4244821  123200   39648 4407669  434175 i965_dri.so

Cuts 25k of .text and saves a bunch of useless struct copies.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

radeonsi: Use dma_copy when possible for si_blit.

This improves GLX DRI3 GPU offloading significantly on CPU
bound benchmarks particularly.
No performance impact for DRI2 GPU offloading.

v2: Add missing tests

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Marek Olšák<marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

glx/dri3: add GPU offloading support.

The differences with DRI2 GPU offloading are:
a) There's no logic for GPU offloading needed in the Xserver

b) for DRI2, the card would render to a back buffer, and
the content would be copied to the front buffer (the same buffers
everytime). Here we can potentially use several back buffers and copy
to buffers with no tiling to share with X. We send them with the
Present extension.

That means than the DRI2 solution is forced to have tearings with GPU
offloading. In the ideal scenario, this DRI3 solution doesn't have this
problem.

However without dma-buf fences, a race can appear (if the card is slow
and the rendering hasn't finished before the server card reads the buffer),
and then old content is displayed. If a user hits this, he should probably
revert to the DRI2 solution (LIBGL_DRI3_DISABLE). Users with cards fast
enough seem to not hit this in practice (I have an Amd hd 7730m, and I
don't hit this, except if I force a low dpm mode)

c) for non-fullscreen apps, the DRI2 GPU offloading solution requires
compositing. This DRI3 solution doesn't have this requirement. Rendering
to a pixmap also works.

d) There is no need to have a DDX loaded for the secondary card.

V4: Fixes some piglit tests

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Signed-off-by: Dave Airlie <airlied@redhat.com>

loader: Use drirc device_id parameter in complement to DRI_PRIME

DRI_PRIME is not very handy, because you have to launch the executable
with it set, which is not always easy to do.
By using drirc, the user specifies the target executable
and the device to use. After that the program will be launched everytime
on the target device.

For example if .drirc contains:

<driconf>
    <device driver="loader">
        <application name="Glmark2" executable="glmark2">
            <option name="device_id" value="pci-0000_01_00_0" />
        </application>
    </device>
</driconf>

Then glmark2 will use if possible the render-node of
ID_PATH_TAG pci-0000_01_00_0.

v2: Fix compilation issue
v3: Add "-lm" and rebase.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

loader: add gpu selection code via DRI_PRIME.

v2: Fix the leak of device_name
v3: Rebased

It enables to use the DRI_PRIME env var to specify
which gpu to use.
Two syntax are supported:
If DRI_PRIME is 1 it means: take any other gpu than the default one.
If DRI_PRIME is the ID_PATH_TAG of a device: choose this device if
possible.

The ID_PATH_TAG is a tag filled by udev.
You can check it with 'udevadm info' on the device node.
For example it can be "pci-0000_01_00_0".

Render-nodes need to be enabled to choose another gpu,
and they need to have the ID_PATH_TAG advertised.
It is possible for not very recent udev that the tag
is not advertised for render-nodes, then
ones need to add a file containing:

SUBSYSTEM=="drm", IMPORT{builtin}="path_id"

in /etc/udev/rules.d/

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

drirc: Add string support

Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Axel Davy <axel.davy@ens.fr>

dri: remove GL types from config queries

This in theory changes ABI for the boolean->bool I think,
but nothing in the tree uses configQueryb AFAICS.

Reviewed-by: Axel Davy <axel.davy@ens.fr>
Signed-off-by: Dave Airlie <airlied@redhat.com>

dri/xmlconfig: remove GL types.

This just drops all the GL types from the xmlconfig and use
std C types from stdint and stdbool.

v2: drop further double and header include.

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>

dri3: cache pointer to back instead of looking up.

This is just prep work for the dri3 prime patches.

Signed-off-by: Dave Airlie <airlied@redhat.com>

configure.ac: (trivial) Fixing a typo

Signed-off-by: Alexandre Demers <alexandre.f.demers@gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>

targets/egl-static: use inline_drm_helper and Automake.inc helpers

Update all three build systems, and add freedreno to the android
build. Pending future work on the ST we can convert egl-static
to provide either static or dynamic access to the pipe-drivers.

There is no functional change with this patch.

v2: Don't add freedreno to android build, drop the wrapper winsys.

Cc: Chia-I Wu <olv@lunarg.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

targets/gbm: convert to static/shared pipe-driver

Move the gbm "target" code to the state-tracker, similar
to other - dri, omx, vdpau... ST.

v2: Drop inclusion of the wrapper winsys and softpipe/llvmpipe.

Cc: Chia-I Wu <olv@lunarg.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

targets/xa: provide alternative(static) xa target

Now we can build the xa target (libxatracker) with either static
pipe-drivers or shared ones. Currently we default to static.

 - Remove the unused CFLAGS/CPPFLAGS.
 - Use GALLIUM_TARGET_CFLAGS where applicable.

v2: Update the printout messages at configure.
v3: Drop inclusion of the wrapper winsys and softpipe/llvmpipe.

Cc: Jakob Bornecrantz <jakob@vmware.com>
Cc: Rob Clark <robclark@freedesktop.org>
Cc: Thomas Hellstrom <thellstrom@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

i965/disasm: Fix INTEL_DEBUG=fs on Broadwell for ARB_fp applications.

Apparently INTEL_DEBUG=fs has crashed on Broadwell for anything using
ARB_fragment_program since commit 9cee3ff5.  We need to NULL-check the
right field.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>

i965/disasm: Delete gen8_disasm.c.

The functionality has been merged into brw_disasm.c; use that instead.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Stop using gen8_disassemble in favor of brw_disassemble.

At this point, brw_disassemble can do everything gen8_disassemble can
do - and, thanks to the new brw_inst API, it supports all generations.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Improve render target write message disassembly.

Previously, we decoded render target write messages as:

   render ( RT write, 0, 16, 12, 0) mlen 8 rlen 0

which made you remember (or look up) what the numbers meant:

1. The binding table index
2. The raw message control, undecoded:
   - Last Render Target Select
   - Slot Group Select
   - Message Type (SIMD8, normal SIMD16, SIMD16 replicate data, ...)
3. The dataport message type, again (already decoded as "RT write")
4. The write commit bit (0 or 1)

Needless to say, having to decipher that yourself is annoying.  Now, we
do:

   render RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0

with optional "Hi" and "WriteCommit" for slot group/write commit.

Thanks to the new brw_inst API, we can also stop duplicating code on a
per-generation basis.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Rename msg_target to SFID.

We haven't used the name "message target" in a while - there are a lot
of things called "target", and it gets confusing.  SFID ("Shared
Function ID") is the term commonly used in the modern documentation.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Fix typo in RT UNORM write message.

The name of this message is "Render Target UNORM Write" (Sandybridge
PRM, Volume 4 Part 1, Page 210).  Drop the bogus 'c'.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Use Gen6+ SFID case labels.

Most developers will recognize the Gen6+ SFID names more quickly than
the Gen4-5 ones.  Given that they're the same values, just use the new
names.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: "Handle" Gen8+ HF/DF immediate cases.

We should print something properly, but I'm not sure how to properly
print an HF, and we don't have any DFs today to test with.

This is at least better than the current Gen8 disassembler, which would
simply assert fail.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/disasm: Cut piles of duplicate swizzle printing.

Making a helper function saves us from cut and pasting this four times.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Properly decode negate source modifiers on Broadwell.

This is a port of Abdiel's 6f9f916b9b042a294813ab0542390846a38739da
to brw_disasm.c.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Improve disassembly of atomic messages on Haswell+.

This backports the atomic message disassembly support from
gen8_disasm.c, which additionally offers support for decoding atomic
surface read/write messages, and showing SIMD modes and other details.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Actually disassemble Gen7+ URB opcodes.

I never bothered implementing the disassembler for Gen7+ URB opcodes, so
we were just disassembling them as Ironlake/Sandybridge ones.  This
looked pretty bad when running Paul's GS EndPrimitive tests, as the
"write OWord" message was decoded at ff_sync, which doesn't exist.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Decode Broadwell's invm/rsqrtm math functions.

We don't use these yet, but we may as well disassemble them.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Properly disassemble the "atomic" ThreadCtrl value.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Properly disassemble all32h/any32h align1 predicates.

While we're adding things, use symbolic constants rather than magic
numbers.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965: Add #defines for any32h/all32h predication.

These have existed since Ivybridge.  We don't use them today, but the
Gen8+ disassembler supports them, and I'd like to use symbolic names
rather than magic numbers.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Mark ELSE as having UIP on Gen8+.

This makes brw_disasm.c able to disassemble ELSE instructions correctly
on Broadwell.  (gen8_disasm.c already handles this correctly.)

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Properly disassemble jump targets on Gen4-5.

Previously, our dissasembly for flow control instructions looked like:

0x00000040: else(8)         ip          65540D     { align16 switch };

It didn't print InstCount properly for ELSE/ENDIF, and didn't even
attempt to disassemble PopCount.

Now it looks like:

0x00000040: else(8)         Jump: 4     Pop: 1     { align16 switch };

which is much more readable.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Improve disassembly of jump targets on Gen6+.

Previously, flow control instructions generated output like:

(+f0) if(8) 12 8  null         0x000c0008UD { align16 WE_normal 1Q };

which included a dissasembly of the register fields, even though those
are meaningless for flow control instructions---those bits are reused
for another purpose.

It also wasn't immediately obvious which number was UIP and which was
JIP.

With this patch, we instead output:

(+f0) if(8)       JIP: 8       UIP: 12      { align16 WE_normal 1Q };

which is much clearer.

The patch also introduces has_uip/has_jip helper functions which clear
up a some generation/opcode checking mess.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Add support for new Gen8+ register types.

While we're at it, use proper names rather than magic numbers for the
existing fields.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965: Restyle brw_disasm.c.

brw_disasm.c basically wasn't following the Mesa coding style at all.
It used 4-space indent instead of 3-space, didn't cuddle braces, didn't
put function return types on a separate line, put extra spaces in
function calls (between the name and parenthesis), and a number of other
things.

This made it fairly obnoxious to work on, since my editor is configured
to follow Mesa style in the Mesa source repository.  Fixing it to follow
a consistent style now should save time dealing with it later.

These modifications were originally generated by:
$ indent -br -i3 -npcs -ce -cs -l80 --no-tabs
with some manual changes afterwards to fit our style better.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Create an "opcode" temporary.

This saves typing brw_inst_opcode(brw, inst) everywhere.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Eliminate opcode pointer.

opcode is just a pointer to opcode_descs; we may as well use that
directly.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

Remove the ATI_envmap_bumpmap extension

As far as I can tell, the Intel mesa driver is the only driver in the world
still supporting this legacy extension.  If someone wants to do bump
mapping, they can use shaders.

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> [v1]
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
Reviewed-by: Ian Romanick <idr@freedesktop.org> [v3]

meta: Use AMD_vertex_shader_layer instead of a GS for layered clears.

On i965, enabling and disabling the GS is not free: you have to do a
full pipeline stall, reconfigure the URB and push constant space, and
emit a bunch of state.  Most clears aren't layered, so the GS isn't
needed in the common case.  But we turned it on universally.

Using AMD_vertex_shader_layer allows us to skip setting up the GS
altogether, while achieving the same effect.

According to Ilia, current nVidia GPUs can't do AMD_vertex_shader_layer.
However, since nouveau is Gallium-based, they're unlikely to ever care
about this path.  Intel and AMD GPUs both support the extension.

Since i965 is the only driver using this path which does layered
rendering, we may as well target it at that.

v2: Improve commit message.  No code changes.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

docs: mark "Geometry shader multiple streams" as done for i965

Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

i965: Enable vertex streams up to MAX_VERTEX_STREAMS.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: Enable simultaneous queries on different streams.

It should be possible to query the number of primitives written to each
individual stream by a geometry shader in a single draw call. For that
we need to have up to MAX_VERTEX_STREAM separate query objects.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965: Implement GL_PRIMITIVES_GENERATED with non-zero streams.

So far we have been using CL_INVOCATION_COUNT to resolve this query but this
is no good with streams, as only stream 0 reaches the clipping stage. Instead
we will use SO_PRIM_STORAGE_NEEDED which can keep track of the primitives sent
to each individual stream.

Since SO_PRIM_STORAGE_NEEDED is related to the SOL stage and according to
ARB_transform_feedback3 we need to be able to query primitives generated in
each stream whether transform feedback is active or not what we do is to
enable the SOL unit even if transform feedback is not active but disable all
output buffers in that case. This effectively disables transform feedback
but permits activation of statistics enabling SO_PRIM_STORAGE_NEEDED even
when transform feedback is not active.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

i965: Implement GL_TRANSFORM_FEEDBACK_PRIMITIVES_WRITTEN with non-zero streams.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

mesa: Include stream information in indexed queries.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: include streamId when reading/printing ir_variable IR.

Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: include streamId when reading/printing emit-vertex and end-primitive IR.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965/gs: Set control data bits for vertices emitted in stream mode.

In stream mode we have to set control data bits with the StreamID
information for every vertex.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

glsl: Validate vertex emission in geometry shaders.

Check if non-zero streams are used. Fail to link if emitting to unsupported
streams or emitting to non-zero streams with output type other than GL_POINTS.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

glsl: Add support for EmitStreamVertex() and EndStreamPrimitive().

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

glsl: Modify ir_end_primitive to have a stream.

This will be necessary to implement EndStreamPrimitive().
EndPrimitive() will produce an ir_end_primitive with the default stream 0.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

glsl: Modify ir_emit_vertex to have a stream.

This will be necessary to implement EmitStreamVertex().
EmitVertex() will produce an ir_emit_vertex with the default stream 0.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

i965/gs: Set number of control data bits for stream mode.

If the geometry shader is indeed using streams then we need 2 control data
bits per vertex for the StreamID. If the shader is not using streams then
we don't need control data bits.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Store info about geometry shaders that emit vertices to non-zero streams.

On Intel hardware when a geometry shader outputs GL_POINTS primitives we
only need to emit vertex control bits if it emits vertices to non-zero
streams, so use a flag to track this.

This flag will be set to TRUE when a geometry shader calls EmitStreamVertex()
or EndStreamPrimitive() with a non-zero stream parameter in a later patch.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Only geometry shader outputs can be associated with non-zero streams.

This should be ensured by the parser, so assert on that.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Two varyings can't write to the same buffer from different streams.

If this is detected, fail to link.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Add methods to retrive a varying's name and streamId.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Fail to link if inter-stage input/outputs are not assigned to stream 0

Outputs that are linked to inputs in the next stage must be output to stream 0,
otherwise we should fail to link.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Assign GLSL StreamIds to transform feedback outputs.

Inter-shader outputs must be on stream 0, which is the default.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

i965: Enable transform feedback for streams > 0

Configure hardware to read vertex data for all streams and have all streams
write their varyings to the corresponsing output buffers.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: add StreamId information to transform feedback outputs.

For now initialized to the default stream 0.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Add parsing support for multi-stream output in geometry shaders.

This implements parsing requirements for multi-stream support in
geometry shaders as defined in ARB_gpu_shader5.

Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

st/omx: strcpy the string into the allocated buffer

This fixes commit a001ca98e15(st/omx: keep the name,
(name|role)_specific strings dynamically allocated) in which we
dynamically allocated the buffers for name and (name|role)_specific
yet forgot to copy the encoder strings into them.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80614
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

mesa: expose ARB_seamless_cubemap_per_texture when supported

All of the bits appear to already be in place to support this in the
sampler (which the original AMD version didn't allow).

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

st/omx: keep the name, (name|role)_specific strings dynamically allocated

... as it's caller (the external program omxregister-bellagio) is the one
who frees all of the allocated memory.

Reported-by: Pedretti Fabio <pedretti.fabio@gmail.com>
Tested-by: Fabio Pedretti <pedretti.fabio@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

docs: Update the status of a few things in GL3.txt

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>

nv50: fix dri3 prime buffer creation

This is the same fix than
"nvc0: fix dri3 prime buffer creation"

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Dave Airlie <airlied@redhat.com>

nvc0: fix dri3 prime buffer creation

We need to place shared buffers into GART.

Reviewed-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Dave Airlie <airlied@redhat.com>

gallium/dri2: implement blitImage

V3: call flush_resource before flush
V4: Add new flags

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

dri/image: add blitImage to the specification

It allows to blit two __DRIimages.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

gallium: Add __DRIimageDriverExtension support to gallium

__DRIimageDriverExtension is used by GLX DRI3 and Wayland.

This patch is a rewrite of
http://lists.freedesktop.org/archives/mesa-dev/2014-May/060318.html
and
http://lists.freedesktop.org/archives/mesa-dev/2014-May/060317.html

Previous patches were:
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

dri3: use invalidate.

This doesn't change anything to the intel DRI3 implementation,
but enables the gallium implementation to use dri2.stamp instead
of relying on the stamp shared with the st backend.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

dri3: fix image extension checking.

Move the image extension setup in with all the others in
bind_extensions, and improve the check to both version
and function pointer.

Reviewed-by: Axel Davy <axel.davy@ens.fr>
Signed-off-by: Dave Airlie <airlied@redhat.com>

glxext: Send the Drawable's ID in the GLX_BufferSwapComplete event

While the official INTEL_swap_event specification says that the drawable
field should contain the GLXDrawable, not the Drawable, the existing
DRI2 code in dri2.c that translates from DRI2_BufferSwapComplete sends out
GLX_BufferSwapComplete with the Drawable's ID, so existing codebases
like Clutter/Cogl rely on getting the Drawable.

Match DRI2's error here and stuff the event with the X Drawable, not
the GLX drawable.

This fixes apps seeing wrong drawables through an indirect GLX context
or with DRI3, which uses the GLX_BufferSwapComplete event directly on
the wire instead of translates Present in mesa.

At the same time, also modify the structure for the event to make sure
that clients don't make the same mistake. This is not an API or ABI
break, as GLXDrawable and Drawable are both typedefs for XID.

Signed-off-by: Jasper St. Pierre <jstpierre@mecheye.net>
Reviewed-by: Axel Davy <axel.davy@ens.fr>
Cc: "10.1 10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

i965: Enable compressed multisample support (CMS) on Broadwell.

Everything is in place and appears to be working.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965: Add 2x MSAA support to the MCS allocation function.

2x MSAA also uses 8 bits, just like 4x.  More bits are unused.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965: Hook up the MCS buffers in SURFACE_STATE on Broadwell.

MCS buffers are never allocated on Broadwell, so this does nothing for
now, but puts the infrastructure in place for when they do exist.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

i965: Drop SINT workaround for CMS layout on Broadwell.

According to the documentation, we don't need this SINT workaround on
Broadwell.  (Or at least, it doesn't mention that we need it.)

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

i965: Add plumbing for Broadwell's auxiliary surface support.

Broadwell generalizes the MCS fields to allow for multiple kinds of
auxiliary surfaces.  This patch adds the plumbing to set those values,
but doesn't yet hook any up.

v2: (by Jordan Justen) Use mt for qpitch; pitch is tiles - 1.
v3: Don't forget to subtract 1 from aux_mt->pitch.
v4: Drop unnecessary aux_mt->offset (caught by Jordan Justen).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

i965: Add auxiliary surface field #defines for Broadwell.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

i965: Disassemble all of DP write message control bits on Gen6.

Prior to the new brw_inst API, the brw_instruction structure split off
bits 4 and 5 of msg_control for specific fields, and we failed to
disassemble them.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>