Peng Fan [Tue, 5 May 2020 12:28:37 +0000 (20:28 +0800)]
imx: imx8qm/qxp: reserving DDR memory for M4
The DDR memory from 0x88000000 to 0x8FFFFFFF is assigned to M4 on
QM and QXP. The M4 can allocate this memory by two ways,
in SCD or u-boot.
In this patch, u-boot addes the memory reserve node to DTB to pass
the info to kernel, no matter the M4 memory is reserved in SCD
or u-boot. So kernel won't access M4 reserved memory.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Han Xu [Wed, 6 May 2020 12:59:19 +0000 (20:59 +0800)]
mtd: nand: raw: mxs_nand changes for nandbcb
Add more BCH setting mode and remove the unnecessary platform constrain
Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Han Xu [Tue, 5 May 2020 14:04:04 +0000 (22:04 +0800)]
nandbcb: read boot search count from fuse for imx8qxp
add support for imx8qxp to read boot search count from fuse in nandbcb
Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Han Xu [Tue, 5 May 2020 14:04:03 +0000 (22:04 +0800)]
cmd: nandbcb: Reconstruct the nandbcb tool for all platforms
The original nandbcb tool was designed for imx6 only, when trying to
leverage it to replace the kobs-ng tool, we found the design is not
friendly for supporting all platforms. To support all iMX6/7/8 platforms
and for easy further maintain, I reconstruct the structure of the tool.
The main changes including:
1. Use platform_data to determine the logic branches rather than simply
use SOC name.
2. More data structures as parameter for functions.
3. Global variables to define the FCB/DBBT/FW locations.
4. Implement the kobs-ng default 4 FCB/4 DBBT/2 FW layout.
5. Support Hamming coding/ 40bit BCH/ 62bit BCH coding FCB.
6. Dump and compare all written FCB/DBBT to verify data integrity.
The tool has been verified on iMX6Q/DL, 6SX, 7D, 6ULL, iMX8QX, iMX8MM.
Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Alice Guo [Tue, 5 May 2020 14:04:02 +0000 (22:04 +0800)]
nandbcb: add nandbcb dump command for i.MX6
Verify/dump boot structures.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Alice Guo [Tue, 5 May 2020 14:04:01 +0000 (22:04 +0800)]
nandbcb: add nandbcb dump command for i.MX8MM
Verify/dump boot structures written to NAND Flash chip.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Alice Guo [Tue, 5 May 2020 14:04:00 +0000 (22:04 +0800)]
nandbcb: support i.MX8M
Tested on i.MX8MM EVK, imx8mm evk uses BCH
encoding and randomizer
modify macro and print size_t with %zx
use CONFIG_IMX8M because it should apply to imx8mq/mm/mn
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Han Xu [Tue, 5 May 2020 14:03:59 +0000 (22:03 +0800)]
nandbcb: fix the issue cannot support gf_14 NAND boot
bchtype in FCB should be associated to the gf_13/14 settings in BCH, fix
the issue and test on Micron 29F64G08CBABB, it can boot after the
change.
Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Leonard Crestez [Mon, 4 May 2020 13:16:54 +0000 (21:16 +0800)]
imx8: Replace SC_R_LAST with SC_R_NONE in DTB
We are currently using SC_R_LAST as a marker for imx8 power domain tree
nodes without a resource attached. This value is compiled into dtb as
part of the linux build and used by uboot.
The SC_R_LAST constant changes frequently as SCFW resources are added
(by design) and every time we need to update linux and uboot headers
together or boot can fail.
Fix this by replacing SC_R_LAST usage with a new constant SC_R_NONE
defined to be 0xFFF0.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Mon, 4 May 2020 13:16:53 +0000 (21:16 +0800)]
power: imx8: Check owned resource in power on
When fspi is assigned to M4, we have to let the fspi probe failed when
its power domain is failed to power up. Because not all devices have power
domain (for example, external devices on the board). Current checking
resource owner in power domain probe is not good, change to check it in
power on.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Mon, 4 May 2020 13:16:52 +0000 (21:16 +0800)]
power: imx8: remove the resource owned check before power off
For all the devices used and set ACTIVE in U-Boot, U-Boot needs
to power off all of them without the check of resource owner.
When we create software partition before booting Linux, the resource
own checkw will return false, and cause the power domain not powered
off. If without the check of resource owner, the power domain in
the other software partition could be powered off with parent
partition could access child partition resources.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Mon, 4 May 2020 13:16:51 +0000 (21:16 +0800)]
power: imx8-power-domain: Set DM_FLAG_DEFAULT_PD_CTRL_OFF flag
If without this flag, calling dev_power_domain_ctrl will iteratively remove
the power domain device will causes iteratively power off parent PD. This is
not expected by imx8-power-domain-legacy driver. Power off parent PD is
controlled by the driver internally.
So set DM_FLAG_DEFAULT_PD_CTRL_OFF to avoid such issue
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Mon, 4 May 2020 13:16:50 +0000 (21:16 +0800)]
imx8: power: Add PD device lookup interface to power domain uclass
Add power_domain_lookup_name interface to power domain uclass to find
a power domain device by its DTB node name, not using its associated
client device.
Through this interface, we can operate the power domain devices directly.
This is needed for non-DM drivers.
Modified from Ye's NXP downstream patch
only for legacy imx8 power domain driver, since we have not migrated
to use new power domain driver.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Mon, 4 May 2020 13:16:49 +0000 (21:16 +0800)]
dt-bindings: imx_rsrc: add SC_R_NONE
Add SC_R_NONE entry
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Adam Ford [Sun, 3 May 2020 13:11:33 +0000 (08:11 -0500)]
imx: Add support for i.MX8MM Beacon EmbeddedWorks devkit.
Beacon EmbeddedWorks, formerly known as Logic PD, is releasing
a devkit based on the i.MX8M Mini SoC consisting of baseboard +
SOM.
It supports eMMC on the SOM, microSD on the baseboard, various
GPIO, the PINCTRL, and UART.
Signed-off-by: Adam Ford <aford173@gmail.com>
Alice Guo [Mon, 4 May 2020 14:09:03 +0000 (22:09 +0800)]
nand: enable the Randomizer module for i.mx7 and i.mx8
To enable the Randomizer module, set GPMI_ECCCTRL[RANDOMIZER_ENABLE] to
1, then set GPMI_ECCCOUNT[RANDOMIZER_PAGE] to select randomizer page
number needed to be randomized.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Han Xu [Mon, 4 May 2020 14:09:02 +0000 (22:09 +0800)]
mxs_nand: don't check zero count when ECC reading with randomizer
When enabled randomizer during ECC reading, the controller reported it's
erased page. Checking zero count will cause data get modified to all
0xFF. Stop checking during randomizer to workaround this issue.
Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Mon, 4 May 2020 14:09:01 +0000 (22:09 +0800)]
MXS_NAND: Add clock support for iMX8
Since iMX8 has enabled clock uclass, we can parse the clocks from DTB
and enable them in GPMI driver.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Mon, 4 May 2020 14:09:00 +0000 (22:09 +0800)]
mtd: nand: support GPMI NAND driver for i.MX8
enable the GPMI NAND driver for i.MX8, i.MX8 use similar controller as
i.MX8M
- register definition for i.mx8
- DMA structure must be 32bit address
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Alice Guo [Mon, 4 May 2020 14:08:59 +0000 (22:08 +0800)]
nand: mxs_nand: make imx8mm can use hardware BCH and randomizer
imx8mm needs to BCH encode and set NAND page number needed to be
randomized
modify conditional compilation
Use CONFIG_IMX8M, so it apply to imx8mq/mm/mn
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Han Xu [Mon, 4 May 2020 14:08:58 +0000 (22:08 +0800)]
mtd: mxs_nand: fix the gf_13/14 definition issue
gf_13/14 mask was not set correctly in register definition.
Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Han Xu [Mon, 4 May 2020 14:08:57 +0000 (22:08 +0800)]
mtd: nand: mxs_nand: add i.MX6QP compatible string
add the dedicate compatible string for i.MX6QP
Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Mon, 4 May 2020 14:08:56 +0000 (22:08 +0800)]
mxs_nand: Update compatible string for i.MX6SX
The iMX6SX uses compatible string "fsl,imx6sx-gpmi-nand" for gpmi
node in DTS, so update the driver for the string
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Mon, 4 May 2020 14:08:55 +0000 (22:08 +0800)]
nand: Update SPL MXS NAND mini driver
Update the mini driver to add support for getting ecc info from ONFI and
support read image data from page unaligned NAND address.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Mon, 4 May 2020 14:08:54 +0000 (22:08 +0800)]
mxs_nand: Add support for i.MX8M
Update the gpmi/apbh_dma/bch drivers and relevant registers for i.MX8M.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Mon, 4 May 2020 14:08:53 +0000 (22:08 +0800)]
nand: mxs: correct bitflip for erased NAND page
This patch is a porting of
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/
commit/?h=imx_4.1.15_1.0.0_ga&id=
e4dacc44d22e9474ec456cb330df525cd805ea38
"
i.MX6QP and i.MX7D BCH module integrated a new feature to detect the
bitflip number for erased NAND page. So for these two platform, set the
erase threshold to gf/2 and if bitflip detected, GPMI driver will
correct the data to all 0xFF.
Also updated the imx6qp dts file to ditinguish the GPMI module for i.MX6Q
with the one for i.MX6QP.
"
In this patch, i.MX6UL is added and threshold changed to use ecc_strength.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Mon, 4 May 2020 14:08:52 +0000 (22:08 +0800)]
nand: mxs: fix the bitflips for erased page when uncorrectable error
This patch is porting from linux:
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/
?h=imx_4.1.15_1.0.0_ga&id=
3d42fcece496224fde59f9343763fb2dfc5b0768
"
We may meet the bitflips in reading an erased page(contains all 0xFF),
this may causes the UBIFS corrupt, please see the log from Elie:
-----------------------------------------------------------------
[ 3.831323] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry
[ 3.845026] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry
[ 3.858710] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry
[ 3.872408] UBI error: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read 16384 bytes
...
[ 4.011529] UBIFS error (pid 36): ubifs_recover_leb: corrupt empty space LEB 27:237568, corruption starts at 9815
[ 4.021897] UBIFS error (pid 36): ubifs_scanned_corruption: corruption at LEB 27:247383
[ 4.030000] UBIFS error (pid 36): ubifs_scanned_corruption: first 6569 bytes from LEB 27:247383
-----------------------------------------------------------------
This patch does a check for the uncorrectable failure in the following steps:
[0] set the threshold.
The threshold is set based on the truth:
"A single 0 bit will lead to gf_len(13 or 14) bits 0 after the BCH
do the ECC."
For the sake of safe, we will set the threshold with half the gf_len, and
do not make it bigger the ECC strength.
[1] count the bitflips of the current ECC chunk, assume it is N.
[2] if the (N <= threshold) is true, we continue to read out the page with
ECC disabled. and we count the bitflips again, assume it is N2.
(We read out the whole page, not just a chunk, this makes the check
more strictly, and make the code more simple.)
[3] if the (N2 <= threshold) is true again, we can regard this is a erased
page. This is because a real erased page is full of 0xFF(maybe also has
several bitflips), while a page contains the 0xFF data will definitely
has many bitflips in the ECC parity areas.
[4] if the [3] fails, we can regard this is a page filled with the '0xFF'
data.
"
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Mon, 4 May 2020 14:08:51 +0000 (22:08 +0800)]
mtd: gpmi: provide the option to use legacy bch geometry
Provide an option in DT to use legacy bch geometry, which compatible
with the 3.10 kernel bch setting. To enable the feature, adding
"fsl,legacy-bch-geometry" under gpmi-nand node.
NOTICE: The feature must be enabled/disabled in both u-boot and kernel.
Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Mon, 4 May 2020 14:08:50 +0000 (22:08 +0800)]
mtd: gpmi: change the BCH layout setting for large oob NAND
The code change updated the NAND driver BCH ECC layout algorithm to
support large oob size NAND chips(oob > 1024 bytes) and proposed a new
way to set ECC layout.
Current implementation requires each chunk size larger than oob size so
the bad block marker (BBM) can be guaranteed located in data chunk. The
ECC layout always using the unbalanced layout(Ecc for both meta and
Data0 chunk), but for the NAND chips with oob larger than 1k, the driver
cannot support because BCH doesn’t support GF 15 for 2K chunk.
The change keeps the data chunk no larger than 1k and adjust the ECC
strength or ECC layout to locate the BBM in data chunk. General idea for
large oob NAND chips is
1.Try all ECC strength from the minimum value required by NAND spec to
the maximum one that works, any ECC makes the BBM locate in data chunk
can be chosen.
2.If none of them works, using separate ECC for meta, which will add one
extra ecc with the same ECC strength as other data chunks. This extra
ECC can guarantee BBM located in data chunk, of course, we need to check
if oob can afford it.
Previous code has two methods for ECC layout setting, the
legacy_calc_ecc_layout and calc_ecc_layout_by_info, the difference
between these two methods is, legacy_calc_ecc_layout set the chunk size
larger chan oob size and then set the maximum ECC strength that oob can
afford. While the calc_ecc_layout_by_info set chunk size and ECC
strength according to NAND spec. It has been proved that the first
method cannot provide safe ECC strength for some modern NAND chips, so
in current code,
1. Driver read NAND parameters first and then chose the proper ECC
layout setting method.
2. If the oob is large or NAND required data chunk larger than oob size,
chose calc_ecc_for_large_oob, otherwise use calc_ecc_layout_by_info
3. legacy_calc_ecc_layout only used for some NAND chips does not contains
necessary information. So this is only a backup plan, it is NOT
recommended to use these NAND chips.
Signed-off-by: Han Xu <b45815@freescale.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sun, 3 May 2020 14:31:47 +0000 (22:31 +0800)]
misc: scu: Increase the timeout for MU communication
When power on some sources in Video system, current timeout 10ms is
too short and returns before SCU response. So increase the timeout
to 1s.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sun, 3 May 2020 14:31:46 +0000 (22:31 +0800)]
misc: fuse: Update imx8 fuse driver for 8QM
Add the second ECC fuse area for 8QM which is different with 8QXP
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sun, 3 May 2020 14:19:57 +0000 (22:19 +0800)]
imx: cpu: support tmu
Support tmu when print cpu info
Signed-off-by: peng Fan <peng.fan@nxp.com>
Peng Fan [Sun, 3 May 2020 14:19:56 +0000 (22:19 +0800)]
imx: regs: add more fuse bank structure
Add more fuse bank structure for use.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sun, 3 May 2020 14:19:55 +0000 (22:19 +0800)]
imx8mp: Set default SNSR25C for TMU probe1
So far u-boot only load SNSR25C for TMU main probe (probe 0). However,
kernel enables two probes. So it also needs to set default SNSR25C of
TCALIV1 for blank samples.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sun, 3 May 2020 14:19:54 +0000 (22:19 +0800)]
imx: load calibration parameters from fuse for i.MX8MP
i.MX8MP thermal which has two probes and supports temperature range
from -40 to 125. The driver still uses default 1p HW
calibration at 25C and loads calibration parameters from fuse.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sun, 3 May 2020 14:19:53 +0000 (22:19 +0800)]
imx: i.MX8MN: Enable loading TASR and TCALIV from fuse
Like iMX8MM, iMX8MN also needs SW to load TMU TASR and TCALIV registers
value from fuse before enabling TMU calibration. Otherwise the calibration
is not exact.
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sun, 3 May 2020 14:19:52 +0000 (22:19 +0800)]
imx8mm: Load fuse for TMU TCALIV and TASR
On iMX8MM, the default value of TMU registers TCALIV and TASR need
be loaded from fuse. HW won't do this, it expect SW loads them before
using TMU.
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sun, 3 May 2020 14:19:51 +0000 (22:19 +0800)]
thermal: imx_tmu: support i.MX8MP
Support i.MX8MP thermal which has two probes and supports
temperature range from -40 to 125. Still uses default 1p HW
calibration at 25C and loads calibration parameters from fuse.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sun, 3 May 2020 14:19:50 +0000 (22:19 +0800)]
thermal: imx_tmu: Check the TEMP range for iMX8MM
On iMX8MM, the V flag in TRISTR register only reflect the state of SNSR
value, not the calibrated TEMP value. So checking this flag is not
reliable. Per IC suggestion, change to read the TEMP/AVG_TEMP directly
and check whether it in valid range 10-125C.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sun, 3 May 2020 14:19:49 +0000 (22:19 +0800)]
thermal: imx_tmu: Fix for temperature out of range
When the temperature is out of sensor's range, the Valid bit won't be
set in TRITSR register. So the polling loop won't go out.
Change the codes to retry 10 times with 100ms interval for the Valid bit.
If the timeout, we give a warning for the invalid data.
Modifed from Ye's NXP patch
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sun, 3 May 2020 14:19:48 +0000 (22:19 +0800)]
thermal: imx_tmu: support TMU arch level initialization
i.MX8MM TMU needs to load some registers from fuse, this is arch
dependent operation and may vary on different platforms. So add
a interface for arch level initialization.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sun, 3 May 2020 14:19:47 +0000 (22:19 +0800)]
thermal: imx_tmu: Add support for thermal sensor on iMX8MM
The analog sensors on iMX8MM are new, used for 14LPP process. So the
Temperature Sensor Monitoring Unit (TMU) has some change accordingly.
We use version 2 in TMU driver to represent the new TMU, so the one
driver can service for both i.MX8MQ/M.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sun, 3 May 2020 14:19:46 +0000 (22:19 +0800)]
thermal: Add thermal driver for i.MX8M
The driver is ported form Linux Kernel and support driver model.
Users need to provide the tmu node and sensors nodes in DTB.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sun, 3 May 2020 14:19:45 +0000 (22:19 +0800)]
thermal: imx_scu_thermal: Update driver for i.MX8QM thermal sensor
Add iMX8QM thermal compatible string and its driver data.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sun, 3 May 2020 14:41:20 +0000 (22:41 +0800)]
eQos: Implement the read_rom_hwaddr callback
Implement the read_rom_hwaddr callback to load MAC address from fuse
for imx8m platforms.
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sun, 3 May 2020 14:41:19 +0000 (22:41 +0800)]
fec: Move imx_get_mac_from_fuse declare to imx file
imx_get_mac_from_fuse is used to load MAC address from fuse. On imx8mp,
we have two different ENET controllers and both need to call this
function. So decouple its declare from fec driver.
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Fugang Duan [Sun, 3 May 2020 14:41:18 +0000 (22:41 +0800)]
net: eqos: implement callbaks to get interface and set txclk rate
Implement the callbacks to get phy mode interface and txclk
rate configuration.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Fugang Duan [Sun, 3 May 2020 14:41:17 +0000 (22:41 +0800)]
net: dwc_eth_qos: add dwc eqos for imx support
Add dwc eqos for imx support.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Fugang Duan [Sun, 3 May 2020 14:41:16 +0000 (22:41 +0800)]
net: phy: realtek: add rx delay support for RTL8211F
Add RX delay enable support for RTL8211F PHY.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sun, 3 May 2020 14:41:15 +0000 (22:41 +0800)]
net: Update eQos driver and FEC driver to use eth phy interfaces
Update eQoS and fec ethernet drivers to support shared MDIO framework
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sun, 3 May 2020 14:41:14 +0000 (22:41 +0800)]
net: Add eth phy generic driver for shared MDIO
For dual ethernet controllers, the HW design may connect ETH phys to
one MDIO ports. So two different ethernet drivers have to share MDIO bus.
Since two ethernet drivers are independent, we can't ensure their probe
order.
To resolve this problem, introduce an eth phy generic driver and uclass.
After eth-uclass binds, we search the mdio node and binds the phy node
with the eth-phy-generic driver.
When one eth driver get its phy device, the parent of phy device will
probe prior than phy device. So this ensure the eth driver ownes the
MDIO bus will be probed before using its MDIO.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sun, 3 May 2020 14:41:13 +0000 (22:41 +0800)]
net: eth-uclass: add return value check
Add return value check
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sun, 3 May 2020 13:01:27 +0000 (21:01 +0800)]
pinctrl: nxp: scu: Check the pad partition before set pinmux
If a pad is not owned by current partition we should not set its
pinmux.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Fabio Estevam [Fri, 1 May 2020 20:46:36 +0000 (17:46 -0300)]
imx8mq_phanbell: Run SPL with caches enabled
It is safe to run SPL with caches enabled on i.MX8M, so
remove such restriction.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Peng Fan [Fri, 1 May 2020 14:08:37 +0000 (22:08 +0800)]
net: fec: add fuse check
Add fuse check for fec. If the fuse indicates the module
will not work in the SoC, let's fail the initialization.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Peng Fan [Fri, 1 May 2020 14:08:36 +0000 (22:08 +0800)]
usb: mx6: add fuse check
Add fuse check for USB. If the fuse indicates the module
will not work in the SoC, let's fail the initialization.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Fri, 1 May 2020 14:08:35 +0000 (22:08 +0800)]
i2c: mxc: add fuse check
Add fuse check for I2C. If the fuse indicates the module
will not work in the SoC, let's fail the initialization.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Fri, 1 May 2020 14:08:34 +0000 (22:08 +0800)]
imx: add module fuse support
There are different parts from one SoC. Take i.MX6ULL for example,
some part might not have ENET, some might have; some might not have
USB, some might have. The information could be got from OCOTP,
to make one image support the different parts, we need runtime
disable linux kernel dts node and uboot driver probe if the
corresponding module not exists in the part.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Marek Vasut [Wed, 29 Apr 2020 18:09:08 +0000 (20:09 +0200)]
ARM: imx: pico-imx8mq: Add support for Technexion Pico-iMX8MQ
Add initial support for Technexion Pico-iMX8MQ SoM on PicoPI carrier
board. Currently working is ethernet, serial, eMMC. DT is imported
from Linux 5.4.28 ("
462afcd6e7ea") .
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Stefano Babic [Sun, 10 May 2020 11:03:56 +0000 (13:03 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot
Tom Rini [Fri, 8 May 2020 22:58:19 +0000 (18:58 -0400)]
Merge branch '2020-05-08-assorted-fixes'
Heinrich Schuchardt [Wed, 6 May 2020 16:26:08 +0000 (18:26 +0200)]
test: fix naming of test functions in the log test suite
Both the nolog as well as the syslog tests were not found by Python
function generate_ut_subtest() due to not following the nameing
requirements imposed by the regular expression used to find linker
generated list entries in file u-boot.sym.
Adjust the naming of test functions.
With the patch the following tests are executed successfully for
sandbox_defconfig:
test/py/tests/test_ut.py::test_ut[ut_log_syslog_debug] PASSED
test/py/tests/test_ut.py::test_ut[ut_log_syslog_err] PASSED
test/py/tests/test_ut.py::test_ut[ut_log_syslog_info] PASSED
test/py/tests/test_ut.py::test_ut[ut_log_syslog_nodebug] PASSED
test/py/tests/test_ut.py::test_ut[ut_log_syslog_notice] PASSED
test/py/tests/test_ut.py::test_ut[ut_log_syslog_warning] PASSED
The nolog tests are only executed if CONFIG_LOG=n and
CONFIG_CONSOLE_RECORD=y.
Reported-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Wed, 6 May 2020 16:26:07 +0000 (18:26 +0200)]
test: describe naming conventions for macro UNIT_TEST
Strict naming conventions have to be followed for Python function
generate_ut_subtest() to collect C unit tests to be executed via
command 'ut'.
Describe the requirements both on the C as well on the Python side.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Rasmus Villemoes [Thu, 26 Mar 2020 23:02:00 +0000 (00:02 +0100)]
env/sf.c: honour CONFIG_SPL_SAVEENV
Deciding whether to compile the env_sf_save() function based solely on
CONFIG_SPL_BUILD is wrong: For U-Boot proper, it leads to a build
warning in case CONFIG_CMD_SAVEENV=n (because the initialization of
the .save member is guarded by CONFIG_CMD_SAVEENV, while the
env_sf_save() function is built if !CONFIG_SPL_BUILD - and even
without the CONFIG_CMD_SAVEENV guard, the env_save_ptr() macro would
just expand to NULL, with no reference to env_sf_save visible to the
compiler). And for SPL, when one selects CONFIG_SPL_SAVEENV, one
obviously expects to actually be able to save the environment.
The compiler warning can be fixed by using a "<something> ?
env_sf_save : NULL" construction instead of a macro that just eats its
argument and expands to NULL. That way, if <something> is false,
env_sf_save gets eliminated as dead code, but the compiler still sees
the reference to it.
For <something>, we can use CONFIG_IS_ENABLED(SAVEENV), which is true
precisely:
- For U-Boot proper, when CONFIG_CMD_SAVEENV is set (because
CONFIG_SAVEENV is a hidden config symbol that gets set if and only
if CONFIG_CMD_SAVEENV is set).
- For SPL, when CONFIG_SPL_SAVEENV is set.
As a bonus, this also removes quite a few preprocessor conditionals.
This has been run-time tested on a mpc8309-derived board to verify
that saving the environment does indeed work in SPL with these patches
applied.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Ye Li [Sun, 3 May 2020 14:27:03 +0000 (22:27 +0800)]
sata: dwc_ahsata: Fix memory issue in reset_sata
The reset_sata should reset the sata device info and free the
probe_ent memory. Otherwise, it will cause memory leak if we
init the sata again.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sun, 3 May 2020 14:27:02 +0000 (22:27 +0800)]
sata: dwc_ahsata: Fix incorrect free
Fix coverity issue CID 43665: Free of address-of expression (BAD_FREE)
incorrect_free: free frees incorrect pointer pp.
pp points the port array field of struct ahci_uc_priv, should not free it.
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Ye Li [Sun, 3 May 2020 14:27:01 +0000 (22:27 +0800)]
sata: ahsata: Fix wrong operand for checking SERR DIAG_X
Fix coverity issue CID 3261683: Wrong operator used
(CONSTANT_EXPRESSION_RESULT) operator_confusion:
({...; __v;}) |
67108864 is always 1/true regardless of the values
of its operand. This occurs as the logical operand of !
When DIAG_X is set, the PHY COMINIT signal is detected, so
should use '&' to check whether it is set.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Ye Li [Sun, 3 May 2020 14:27:00 +0000 (22:27 +0800)]
sata: ahsata: Fix resource leak
Fix coverity issue CID 3606684: Resource leak (RESOURCE_LEAK)
leaked_storage: Variable uc_priv going out of scope leaks the storage it points to
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Fri, 8 May 2020 18:56:23 +0000 (14:56 -0400)]
Merge tag 'efi-2020-07-rc2-3' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2020-07-rc2-3
This series contains bug fixes and code simplifications.
Following clarification in the discussion of the EBBR specification
device trees will be passed as EfiACPIReclaimMemory to UEFI applications.
Tom Rini [Fri, 8 May 2020 17:48:37 +0000 (13:48 -0400)]
Merge branch '2020-05-07-more-kconfig-migrations'
- Migrate CONFIG_SET_DFU_ALT_INFO, CONFIG_SYS_MTDPARTS_RUNTIME and
finish the rest of the memtest related options.
Ashok Reddy Soma [Mon, 4 May 2020 13:26:21 +0000 (15:26 +0200)]
treewide: mem: Move mtest related defines to Kconfig
Move below defines which are used by mtest utility to Kconfig.
CONFIG_SYS_MEMTEST_START
CONFIG_SYS_MEMTEST_END
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
[trini: Fix kmcoge5ne board, re-run migration as well]
Signed-off-by: Tom Rini <trini@konsulko.com>
Michal Simek [Mon, 4 May 2020 13:26:20 +0000 (15:26 +0200)]
treewide: mem: Enable MEMTEST via defconfig
There is no reason to enable MEMTEST from headers when was converted to
Kconfig already.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 4 May 2020 13:26:19 +0000 (15:26 +0200)]
treewide: mem: Remove alternate memtest setup from Mox and x530
The commit
e89f8aae3d67 ("treewide: Migrate CONFIG_SYS_ALT_MEMTEST to Kconfig")
setup correct dependency on MEMTEST that's why there is no reason to enable
enable alternate memtest without mtest command.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 4 May 2020 11:54:40 +0000 (13:54 +0200)]
cmd: mem: Remove CONFIG_SYS_MEMTEST_SCRATCH mapping
There is no real need to exactly define space for saving patterns for
alternate memory test. It is much easier to allocate space on the stack and
use it instead of trying to find out space where pattern should be saved.
For example if you want to test the whole DDR memory you can't save patter
to DDR and you need to find it out. On Xilinx devices DDR or OCM addresses
were chosen but that means that OCM needs to be mapped and U-Boot has
access permission there.
It is easier to remove this limitation and simply save it on stack because
it is very clear that memory test can't rewrite U-Boot and U-Boot has also
full access to memory where runs from.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
Patrick Delaunay [Wed, 26 Feb 2020 09:28:42 +0000 (10:28 +0100)]
configs: migrate CONFIG_SYS_MTDPARTS_RUNTIME to defconfigs
Move CONFIG_SYS_MTDPARTS_RUNTIME into Kconfig done by moveconfig.py.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Wed, 26 Feb 2020 09:28:41 +0000 (10:28 +0100)]
configs: migrate CONFIG_SET_DFU_ALT_INFO to defconfigs
Move CONFIG_SET_DFU_ALT_INFO into Kconfig done by moveconfig.py.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Tom Rini [Fri, 8 May 2020 13:08:39 +0000 (09:08 -0400)]
configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Thu, 7 May 2020 18:51:44 +0000 (14:51 -0400)]
Merge branch '2020-05-07-atheros-phy-improvements'
Heinrich Schuchardt [Thu, 7 May 2020 15:57:43 +0000 (17:57 +0200)]
efi_loader: crypto/pkcs7_parser.h is not a local include
User <> and not "" for referencing a global include.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Patrick Wildt [Thu, 7 May 2020 00:17:14 +0000 (02:17 +0200)]
efi_loader: pkcs7_parse_message() returns error pointer
Since pkcs7_parse_message() returns an error pointer, we must not
check for NULL. We have to explicitly set msg to NULL in the error
case, otherwise the call to pkcs7_free_message() on the goto err
path will assume it's a valid object.
Signed-off-by: Patrick Wildt <patrick@blueri.se>
Add missing include linux/err.h
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Patrick Wildt [Thu, 7 May 2020 00:13:18 +0000 (02:13 +0200)]
efi_loader: efi_variable_parse_signature() returns NULL on error
efi_variable_parse_signature() returns NULL on error, so IS_ERR()
is an incorrect check. The goto err leads to pkcs7_free_message(),
which works fine on a NULL ptr.
Signed-off-by: Patrick Wildt <patrick@blueri.se>
Reviewed-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Heinrich Schuchardt [Wed, 6 May 2020 18:32:31 +0000 (20:32 +0200)]
efi_loader: put device tree into EfiACPIReclaimMemory
According to the UEFI spec ACPI tables should be placed in
EfiACPIReclaimMemory. Let's do the same with the device tree.
Suggested-by: Ard Biesheuvel <ardb@kernel.org>
Cc: Grant Likely <grant.likely@arm.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Wed, 6 May 2020 00:01:34 +0000 (02:01 +0200)]
efi_loader: use logical and in do_env_print_efi()
If we want to check if two booleans are true, we should use a logical
conjunction (&&) and not a bitwise and-operator (&).
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Tue, 5 May 2020 23:51:04 +0000 (01:51 +0200)]
efi_loader: do not unnecessarily use EFI_CALL()
There is no need to call efi_get_variable() instead of
efi_get_variable_common(). So let's use the internal function.
Move forward declarations to the top of the file.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Tue, 5 May 2020 23:37:25 +0000 (01:37 +0200)]
efi_loader: error handling in efi_set_variable_common().
Fix unreachable code. Free memory on error.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Tue, 5 May 2020 23:28:08 +0000 (01:28 +0200)]
efi_loader: remove redundant assignment in dp_fill()
The value of dp is overwritten without being used.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Jan Kiszka [Mon, 4 May 2020 12:38:29 +0000 (14:38 +0200)]
kbuild: efi: Avoid rebuilding efi targets
Add a couple of missing targets so that helloworld and other efi targets
are not needlessly rebuilt.
CC: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Michael Walle [Wed, 6 May 2020 22:11:59 +0000 (00:11 +0200)]
phy: atheros: consolidate {ar8031|ar8035}_config()
The two functions are now exactly the same, remove one of them.
Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Michael Walle [Wed, 6 May 2020 22:11:58 +0000 (00:11 +0200)]
phy: atheros: ar8035: remove static clock config
We can configure the clock output in the device tree. Disable the
hardcoded one in here. This is highly board-specific and should have
never been enabled in the PHY driver.
If bisecting shows that this commit breaks your board it probably
depends on the clock output of your Atheros AR8035 PHY. Please have a
look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set
"clk-out-frequency = <
125000000>" because that value was the hardcoded
value until this commit.
Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Michael Walle [Wed, 6 May 2020 22:11:57 +0000 (00:11 +0200)]
phy: atheros: add device tree bindings and config
Add support for configuring the CLK_25M pin as well as the RGMII I/O
voltage by the device tree.
By default the AT803x PHYs outputs the 25MHz clock of the XTAL input.
But this output can also be changed by software to other frequencies.
This commit introduces a generic way to configure this output.
Also the PHY supports different RGMII I/O voltages: 1.5V, 1.8V and 2.5V.
An internal LDO is able to provide 1.5V (default) and 1.8V. The 2.5V
option needs an external supply voltage. This commit adds support to
switch the internal LDO to 1.8V.
Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Michael Walle [Wed, 6 May 2020 22:11:56 +0000 (00:11 +0200)]
phy: atheros: move delay config to common function
Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Michael Walle [Wed, 6 May 2020 22:11:55 +0000 (00:11 +0200)]
phy: atheros: introduce debug read and write functions
Provide functions to read and write the Atheros debug registers.
Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Michael Walle [Wed, 6 May 2020 22:11:54 +0000 (00:11 +0200)]
phy: atheros: use defines for PHY IDs
Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Michael Walle [Wed, 6 May 2020 22:11:53 +0000 (00:11 +0200)]
phy: atheros: fix AR8021 PHY ID mask
The upper bits are all the OUI.
Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Vladimir Oltean [Wed, 6 May 2020 22:11:52 +0000 (00:11 +0200)]
phy: atheros: Clarify the intention of ar8021_config
Debug register 5 contains TX_CLK DELAY at bit 8 and reserved values at
the other bit positions, just like the other PHYs in the family do.
Therefore, it is not necessary to hardcode the reserved values, but
instead simply follow the read-modify-write procedure from the common
function.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Vladimir Oltean [Wed, 6 May 2020 22:11:51 +0000 (00:11 +0200)]
phy: atheros: Explicitly disable RGMII delays
To eliminate any doubts about the out-of-reset value of the PHY, that
the driver previously relied on.
If bisecting shows that this commit breaks your board you probably have
a wrong PHY interface mode. You probably want the
PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Vladimir Oltean [Wed, 6 May 2020 22:11:50 +0000 (00:11 +0200)]
phy: atheros: Clarify the configuration of the CLK_25M output pin
Also take the opportunity to use the phy_read_mmd and phy_write_mmd
convenience functions.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Vladimir Oltean [Wed, 6 May 2020 22:11:49 +0000 (00:11 +0200)]
phy: atheros: Use common functions for RGMII internal delays
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Vladimir Oltean [Wed, 6 May 2020 22:11:48 +0000 (00:11 +0200)]
phy: atheros: Make RGMII Tx delays actually configurable for AR8035
Delete the extraneous write to debug reg 5 that enables Tx delay
When the driver was originally introduced in commit "
6027384a phylib:
Add Atheros AR8035 GETH PHY support", the Tx delay was being
unconditionally enabled.
Then during "
2ec4d10b phy: atheros: add support for RGMII_ID, RGMII_TXID
and RGMII_RXID", the author did not notice that code for enabling Tx
delay code was already. Therefore, the if condition for Tx delay has
always been useless for this PHY since this commit introduced it.
Prior to this patch, every AR8035 PHY in U-boot had Tx delay enabled.
After this patch, only those who define the interface as RGMII_TXID or
RGMII_ID will. This is to be expected, but will nonetheless break the
setups of those who didn't know they rely on Tx delay implicitly.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tom Rini [Thu, 7 May 2020 13:02:28 +0000 (09:02 -0400)]
Merge branch '2020-05-06-master-imports'
- ARM Juno updates
- Assorted bugfixes