review.tizen.org Git - platform/upstream/mesa.git/log

freedreno: swap ->valid when shadowing resources.

The valid flag indicates whether the bo has had any data written to it.
Failure to swap it meant that if for some reason we fell back to SW
mappings during the blit from shadow, the PIPE_MAP_READ staging blit would
get dropped.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11544>

freedreno: Update comments about PIPE_BUFFER shadowing.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11544>

docs/release-calendar: add a few more 21.1 releases

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11660>

docs: update calendar and link releases notes for 21.1.4

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11660>

docs: add release notes for 21.1.4

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11660>

aco: remove resource flags

After disabling SMEM stores, nir_opt_access() now does the same analysis
and we don't need this anymore. Doing it in isel is also too late if we
want to lower descriptor loads in NIR.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11652>

i915g: Set up the cube map texture wrap modes.

There are HW limits on what you're allowed to do. No change on dEQP, but
one less thing for me to worry about with our busted cubes.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11648>

i915g: Add curly braces for normal mesa style (and helps clang-format)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11648>

i915g: Delete redundant i915_hw_sampler_views atom.

The i915_hw_samplers atom already updated both samplers and maps, since
both samplers and maps depend on parts of both the gallium sampler state
and the sampler view. Just move the samplers+views atom down to the
bottom of the file for legibility, and delete the views-only one.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11648>

i915g: Fix FS debug dumping for declarations.

Samplers have a type, and non-samplers have a destination writemask.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11648>

i915g: Add the nice cube map layout comments from i915c.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11648>

i915g: Finish the uint -> uint32_t conversion.

My sed job missed a few.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11648>

freedreno/a6xx: Fix framebuffer_barrier crash

This is emitting cmdstream, it should take the submit lock to (a) ensure
we actually have a batch, and (b) prevent it from being flushed from
under it. This was overlooked in the conversion.

Fixes: 02298ed1fc6 ("freedreno: Add submit lock")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11658>

egl: android: add IMapper@4 metadata API buffer_info getter

Starting from Android-11 Google introduces generalized API
to access buffer information. This API is a part of IMapper@4 HAL.

Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6045>

egl: android: prepare code for adding more buffer_info getters

Instead of calling droid_create_image_ for every gralloc implementation,
create struct buffer_info which contains all required field for invoking
createImageFromDmaBufs2() and let the getters to fill this structure.
Since createImageFromDmaBufs2() is called now only once, the code looks
cleaner and more robust.

Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6045>

intel: fix leaking memory on shader creation

ralloc_adopt takes care of all the shader's children, but shader itsel ends up
orphaned and never gets free'd.

Fixes: ef5bce9253e ("intel: Drop the last uses of a mem_ctx in nir_builder_init_simple_shader().")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4951

Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11651>

intel/fs: Lower uniform pull constant load message to LSC dataport

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11600>

intel/fs: Lower varying pull constant load message to LSC dataport

Co-authored-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11600>

intel/fs: Lower A64 atomic messages to LSC dataport

Co-authored-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11600>

intel/fs: Lower A64 byte scattered r/w messages to LSC dataport

Co-authored-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11600>

intel/fs: Lower A64 untyped r/w messages to LSC when available

We set the ex_desc to 0, since the address surface type is FLAT.

v2 (Sagar Ghuge):
- Fix message descriptor encoding

v2 (Jason Ekstrand):
- Drop support for block messages

Co-authored-by: Sagar Ghuge <sagar.ghuge@intel.com>
Co-authored-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11600>

intel/fs: Lower Byte scattered r/w messages to LSC when available

v2 (Jason Ekstrand):
- Squash in brw_scheduler changes
- Update brw_ir_performance

Co-authored-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11600>

intel/fs: Lower untyped float atomic messages to LSC when available

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11600>

intel/fs: Lower untyped atomic messages to LSC when available

Bspec programming note metions that "Atomic messages are always forced
to "un-cacheable" in the L1 cache". We can make the L1 cache
un-cacheable and L3 with write-back policy.

v2: (Sagar Ghuge):
- Fix caching policy for atomic messages
- Fix simd exec size

v3: (Sagar Ghuge):
- Add atomic messages to brw_schedule_instructions

v4: (Jason Ekstrand):
- Rebase on lsc_msg_desc reworks

Co-authored-by: Sagar Ghuge <sagar.ghuge@intel.com>
Co-authored-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11600>

intel/fs: Lower DW untyped r/w messages to LSC when available

This puts the basic infrastructure in place for lowering logical
dataport messages to LSC messages. We start with the two most obvious
opcodes and add more in later patches.

v2 (Sagar Ghuge):
- Pass required params to message desc
- Remove duplicate mlen calculation
- Change commit message.

v3 (Jason Ekstrand):
- Drop TGM support

Co-authored-by: Jason Ekstrand <mark.a.janes@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11600>

intel/compiler: Add LSC messages to brw_schedule_instructions

v2 (Jason Ekstrand):
- Use lsc_msg_desc_opcode()
- Drop all opcodes for now and add them in later patches.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11600>

intel/compiler: Add LSC to messages brw_ir_performance

This adds framework only. No opcodes.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11600>

intel/disasm: Disassemble LSC message extended descriptors

v2 (Mark Janes):
- changed to lsc convention

v3 (Jason Ekstrand):
- Use lsc_msg_desc_addr_type

Co-authored-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11600>

intel/disasm: Disassmeble LSC messages

v2 (Jordan Justen):
- Use PRIu64

v3 (Jason Ekstrand):
- Drop ranged fence ops, Jason

v4: (Mark Janes)
- fixed missing parameter to brw_message_desc_cmask_or_vector
- changed to use lsc methods to extract fields

v5 (Jason Ekstrand):
- Squash original disassembler patch and fixes togetherk
- Use lsc_opcode_has_cmask
- Prefix atomic ops with "atomic_"

Co-authored-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11600>

intel/compiler: Add getter helpers for LSC message descriptor fields

v2: (Sagar Ghuge):
- rename addr_reg_size to src0_len to match with bspec

v3 (Jason Ekstrand):
- Re-arrange things in increasing bit order

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11600>

intel/compiler: Add helpers for LSC message descriptors

v2 (Jason Ekstrand):
- Squash all the similar patches together
- Re-arrange and rename some things to be more consistent
- Add a lsc_opcode_has_cmask helper
- Drop is_one_addr_reg

v3 (Jason Ekstrand):
- Add transpose
- Re-order arguments to make more logical sense
- Switch from `write` to `has_dest`

Co-authored-by: Mark Janes <mark.a.janes@intel.com>
Co-authored-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11600>

intel/compiler: Add support for LSC fence operations

v2 (Jason Ekstrand):
- Squash SLM and global fence ops together

v3 (Jason Ekstrand):
- Rework to use message descriptors instead of instruction fields

v4 (Jason Ekstrand):
- Don't pass BTI into back-end emit function. Always use FLAT.

Co-authored-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11600>

intel/compiler: Define new LSC data port encodings

Xe-HPG comes with a massively reworked dataport.  The new thing, called
Load/Store Cache or LSC, has a significantly improved interface.
Instead of bespoke messages for every case, there's basically one or two
messages with different bits to control things like address size, how
much data is read/written, etc.  It's way nicer but also means we get to
rewrite all our dataport encoding/decoding code.  This patch kicks off
the party with all of the new enums.

v2 (Jason Ekstrand, Mark Janes):
- Rename to LSC

v3 (Jason Ekstrand):
- Add numbers to all enums

Co-authored-by: Mark Janes <mark.a.janes@intel.com>
Co-authored-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11600>

intel/devinfo: Add a has_lsc bit

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11600>

radeon/vcn: calc_dpb_size should be based on dpb_type

This patch will fix the dpb size calculated for each dpb_type.
Current implementaion always calculating based on DPB_MAX_RES.To fix
this dpb_type should be decided before calc_dpb_size.

Signed-off-by: SureshGuttula <suresh.guttula@amd.corp-partner.google.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11633>

radv: pre-calc vertex buffer descriptor size on pipeline object

util_bitcount has a nonzero cost, and calling it like this in a hotpath
generates unnecessary overhead

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11525>

zink: attempt to handle some resource unmap cases in 32bit envs

address space is limited here, so in some cases it's worthwhile to
unmap resources

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11594>

zink: cache visible vram

yolo

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11594>

zink: uncap mem caching

if it fits, it sits

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11594>

zink: make mem cache limits dynamically scalable

this removes the hardcoded count of 5 mem blocks to cache and replaces
it with a value that's based on the number of allocations seen

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11594>

zink: don't align device-local buffer memory

this can't be mapped

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11594>

zink: try for better buffer allocation heaps

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11594>

r600/sfn: initialize all texture lower options

Fixes: d1edf3cdf285f62c153c6bb910fc0a2c40c4e159
r600/sfn: Lower offset in TXF instructions

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11650>

anv: drop unused argument of anv_descriptor_set_address

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11577>

anv: handle push descriptor sets when they are sent with push constants

When vkCmdPushDescriptorSetKHR is used, the descriptor set is allocated
internally without belonging to any pool. Such descriptor set will be
visible on the GPU side because it's a part of the dynamic state stream,
but we still have to store its address in the array of descriptor sets.

Complements: 379b9bb7b04 ("anv: Support fetching descriptor addresses from push constants")

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11577>

anv: keep descriptor set's address directly in anv_descriptor_set

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11577>

util/disk_cache: delete more cache items in one go when full

Currently the cache just deletes enough items when the cache is
full to make room for the new item being stored. This hasn't
been too much of a problem in practice but for things like running
piglit where we have thousands of unique shaders and all threads
being utilised we end up with a pretty big bottle neck.

With this change rather than just brute forcing our way to having
enough room for the new item, we instead grab 10% of the least
recently used items in the random directory we chose and delete
them all. This should only be around 0.04% of total cache items
but should hopefully releave some of the pressure on system calls
like fstatat().

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11523>

CI: Disable LAVA devices for maintenance

LAVA will be unavailable for probably most of the day today due to
scheduled maintenance; doing some spring cleaning to upgrade to a new
version, clean out the database, etc.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11649>

radv: fix fd leak in vkAcquireImageANDROID()

Copied from ANV.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4915
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11518>

vulkan/wsi: prefer the Wayland linux-dmabuf protocol

When the linux-dmabuf protocol is available, prefer it over the old
wl_drm protocol. Previously wl_drm was used when modifiers aren't
supported, however linux-dmabuf supports formats without modifiers too.
In this case, linux-dmabuf will send a DRM_FORMAT_MOD_INVALID modifier
for each supported format [1].

All of this allows compositors to better handle these buffers, getting a
DMA-BUF and implementing features like direct scan-out.

A similar logic has been implemented for EGL [2].

In this patch, we bind to linux-dmabuf even if the driver doesn't support
modifiers. In this case the formats advertised by the compositor will
still be added to the display->dmabuf.formats list.

In wsi_wl_image_init, drop the assertions that display->drm_wrapper and
display->dmabuf.wl_dmabuf can't be both present. If the driver doesn't
support modifiers, the modifier is already set to DRM_FORMAT_MOD_INVALID.
If the parent compositor doesn't support modifiers, the modifiers list
passed to wsi_create_native_image will be empty, and the common code
will ensure that the image's modifier is set to DRM_FORMAT_MOD_INVALID.

In wsi_wl_surface_create_swapchain, create the wl_proxy proxy if we've
bound to it earlier. Don't decide to create the proxy depending on the
number of supported modifiers.

[1]: https://gitlab.freedesktop.org/wayland/wayland-protocols/commit/fb9b2a87317c77e26283da5f6c9559d709f6fdcd
[2]: https://gitlab.freedesktop.org/mesa/mesa/-/commit/c376865f5eeca535c4aa8e33bcf166052c1ce2f2

Signed-off-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4942>

vulkan/wsi: unify format logic in dmabuf_handle_modifier

This function has a switch which currently duplicates the format
handling logic.

Move this logic out of the switch.

This avoids repeating the same code for each supported format and
prepares the work for proper DRM_FORMAT_MOD_INVALID handling.

Signed-off-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4942>

zink: split dummy buffer creation and populate

populate requires the queue to be set up, but the resources must be created
before descriptor init

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11591>

zink: add direct conversion from pipe_shader_type->VkPipelineStageFlags

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11592>

crocus: disable Z16 unorm textures on pre-gen8 as well.

This fixes:
dEQP-GLES3.functional.fbo.completeness.renderable.texture.depth.depth_component_unsigned_short

as gallium will try an allocate a DS usage, but fallback to just
a sampling usage if that fails.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11646>

crocus/gen8: add back z16 support for gen8

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11646>

freedreno+ir3: Enable INT16

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11545>

nir: Add pass to lower phi precision

In addition to register pressure benefits from getting more fp16/int16,
this avoids i2imp's from standing in the way of loop unrolling.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11545>

microsoft/compiler: Add support for get_ssbo_size to translator

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11629>

nir/lower_packing: use shader_instructions_pass

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11615>

nir: return progress from nir_lower_packing

Compiling with clang warns about an unused variable in
nir_lower_packing.

Tracking progress was added to nir_lower_packing in
adb157ddfd52ab495878a8b2b1bf70586d773aa2 but the function
will ignore the progress from impl calls and always return
false.

This patch changes it to return the progress. It fixes the
warning and should enable validation calls in NIR_PASS when
progress is made.

Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Fixes: adb157ddfd52 "nir: Return progress from nir_lower_64bit_pack()"
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11615>

radeonsi/driconf: add workaround for SpaceEngine

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4483
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11625>

ac/surface: don't print stencil info if tex has no stencil

color/zs are stored in a union so testing for zs.stencil_offset
isn't the correct way to test for stencil.

Fixes: 988f148db3c ("ac/surface: overlap color and Z/S fields using a union in gfx9_surf_layout")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11625>

radeonsi/gfx7: always sync pfp/me

Workaround for https://gitlab.freedesktop.org/mesa/mesa/-/issues/4764

Fixes: c5326164 ("radeonsi: add SI_CONTEXT_PFP_SYNC_ME to skip syncing PFP for image operations")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11625>

radeonsi: fix fb_too_small condition

fb->num_layers can be 0 so use util_num_layers(tex) instead.

Fixes: f7c58559f57 ("radeonsi: refine fast clears for small buffers, always use them for large HTILE")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4764
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11625>

ac/llvm: call the callback in all return paths of ac_cull_triangle

Fixes: 12d2df15f17 ("ac/llvm: add a callback to ac_cull_triangle to generate code in inner-most block")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4959
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11625>

ci: bare-metal: drop webdav support

The NFS method is much faster.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11611>

iris/bufmgr: Stop changing mapping modes on buffers

With discrete GPUs, we aren't able to change mapping modes after we've
created a buffer. This is a limitation of TTM. However, we already
have a buffer cache and it's pretty likely that stuff in any given
memzone will end up with just the one mapping type anyway so this
shouldn't have much of a cost.

Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11583>

intel: Early exit from inst_is_in_block().

Surely the compiler would sort that out, you would think. But no, my
debugoptimized build improves
dEQP-GLES31.functional.ubo.random.all_per_block_buffers.13 runtime by 25%
on my SKL from this change.

This was the slowest test in the GLES31 tests on APL in CI, at 22s. And
yes, we were spending around half of our runtime in this function.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11631>

virgl: Enable ASTC formats also for 3D textures

The texture compression can also be used for 2D arrays and
3D textures.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11634>

docs/envvars: fix RADV_TEX_ANISO

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11640>

r600/sfn: Lower offset in TXF instructions

Closes: #4960
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11639>

radv: fix RADV_FORCE_VRS for 2x1 and 1x2

The rates were inverted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11578>

ci/vc4: update piglit failures

Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11521>

broadcom/compiler: use nir_sort_variables_with_modes

Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11624>

aco/tests: fix 32-bit build

"call of overloaded ‘Operand(long unsigned int)’ is ambiguous"

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11627>

radv: ignore redundant variable descriptor counts (v2)

The Vulkan specification says: "If VkDescriptorSetAllocateInfo::pSetLayouts[i]
does not include a variable count descriptor binding, then
pDescriptorCounts[i] is ignored". The previous code triggered an assertion
in such cases, and this patch fixes it.

v2: removed the offending assertion that is now always satisfied and
reworded the commit message with a reference to Vulkan spec.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4992
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11576>

ir3/lower_parallelcopy: Use SWZ

shader-db results on a650:

total instructions in shared programs: 1575484 -> 1574866 (-0.04%)
instructions in affected programs: 32579 -> 31961 (-1.90%)
helped: 75
HURT: 0
helped stats (abs) min: 1 max: 98 x̄: 8.24 x̃: 7
helped stats (rel) min: 0.41% max: 30.12% x̄: 2.47% x̃: 1.13%
95% mean confidence interval for instructions value: -10.97 -5.51
95% mean confidence interval for instructions %-change: -3.44% -1.51%
Instructions are helped.

total nops in shared programs: 355742 -> 355628 (-0.03%)
nops in affected programs: 18635 -> 18521 (-0.61%)
helped: 55
HURT: 147
helped stats (abs) min: 1 max: 14 x̄: 4.76 x̃: 6
helped stats (rel) min: 1.41% max: 100.00% x̄: 8.13% x̃: 4.76%
HURT stats (abs) min: 1 max: 2 x̄: 1.01 x̃: 1
HURT stats (rel) min: 0.56% max: 25.00% x̄: 2.09% x̃: 1.20%
95% mean confidence interval for nops value: -0.98 -0.15
95% mean confidence interval for nops %-change: -1.93% 0.55%
Inconclusive result (%-change mean confidence interval includes 0).

total non-nops in shared programs: 1219742 -> 1219238 (-0.04%)
non-nops in affected programs: 61125 -> 60621 (-0.82%)
helped: 220
HURT: 0
helped stats (abs) min: 1 max: 99 x̄: 2.29 x̃: 1
helped stats (rel) min: 0.19% max: 29.17% x̄: 0.90% x̃: 0.40%
95% mean confidence interval for non-nops value: -3.26 -1.32
95% mean confidence interval for non-nops %-change: -1.24% -0.56%
Non-nops are helped.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11565>

ir3: Add min gen for multi-mov instructions

swz works on a5xx/a6xx but not a3xx according to CI. I don't have any
access to a4xx HW so I can't tell whether it works there.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11565>

ir3: Print multi-mov instructions

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11565>

ir3/validate: Support multi-mov instructions

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11565>

ir3: Use correct flags for movmsk & multi-mov

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11565>

ir3/legalize: Support multi-mov instructions

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11565>

ir3/postsched: Support multi-mov instructions

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11565>

ir3/delay: Support multi-mov instructions

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11565>

ir3: Support multi-mov instructions

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11565>

ir3: Add foreach_dst/foreach_dst_n

And cleanup a few places I know of that are open-coding it

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11565>

ir3: Prepare dest helpers for multi-dst instructions

Assert in dest_regs() that dst_count == 1, since most users of it will
blow up if they encounter multiple destinations, and split out the core
of writes_gpr() so that we can easily make code using it multi-dst
aware.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11565>

ir3: Stop creating dummy dest registers

These were a holdover from before the src/dst split and are no longer
necessary. Just don't create any dest registers for instructions that
never have a destination.

This has the side-effect that it becomes easier to replace uses of
dest_regs() with a per-register thing, once we start adding support for
multiple destinations.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11565>

v3dv: expose support for basic subgroup operations

Relevant CTS tests (requires Vulkan 1.1):
dEQP-VK.subgroups.builtin_var.compute.*
dEQP-VK.subgroups.basic.compute.*

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11620>

v3dv: expose correct subgroup size

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11620>

broadcom/util: don't use compute supergroup packing with subgroups

When using subgroups there are additional restrictions to consider,
so for now we keep it simple and disable supergroup packing in that
scenario.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11620>

broadcom/compiler: track if a compute shader uses subgroup functionality

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11620>

broadcom/compiler: add a set_a_flags_for_subgroup helper

We will need this in the future to implement more subgroup operations,
so make this code available in a helper.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11620>

broadcom/compiler: add a ntq_emit_cond_to_bool helper

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11620>

broadcom/compiler: implement more subgroup intrinsics

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11620>

broadcom/compiler: add FLAFIRST and FLNAFIRST opcodes

We will at least need the former to implement subgroupElect()

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11620>

broadcom/compiler: lower nir_intrinsic_load_num_subgroups

The number of subgroups is the local workgroup size divided by the
dispatch width.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11620>

broadcom/compiler: implement nir_intrinsic_load_subgroup_id correctly

For some reason, this was implemented with the bulk of the compute
shader enablement, but this intrinsic is specific to subgroups and
thus was not really used. Also, its implementation was not correct,
since it was returning the element index within the subgroup, not
the subgroup index itself, which is the index of the batch in the
dispatch.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11620>

intel/perf: use the right popcount for 64bits

We're currently using the 32bit version which is dropping half the
bits of the 64bits values.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11607>