Emma Anholt [Thu, 5 May 2022 23:28:34 +0000 (16:28 -0700)]
glsl: Make all drivers take the GLSLOptimizeConservatively path.
Now that all consumers of GLSL use NIR, make the remaining drivers take
the path that relies on NIR to really do optimization.
nouveau steam shader-db runtime -6.69631% +/- 1.29235% (n=12).
No change on shader-db there.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16364>
Marek Olšák [Fri, 6 May 2022 02:35:59 +0000 (22:35 -0400)]
radeonsi: remove tautologies when setting CU_EN
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Ruijing Dong [Wed, 16 Mar 2022 14:43:29 +0000 (10:43 -0400)]
radeonsi/vcn: update av1 decoding to support vcn4
Apply changes of vcn4 on av1 decoding.
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Ruijing Dong [Thu, 10 Mar 2022 17:13:09 +0000 (12:13 -0500)]
radeonsi/vcn: Add support of array_mode for gfx11
Update array_mode for gfx11 in vcn decoder.
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
James Zhu [Sun, 20 Feb 2022 17:07:30 +0000 (12:07 -0500)]
radeonsi/vcn: add jpeg decode support for gfx11
Add jpeg decode support for gfx11.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Wed, 4 May 2022 00:24:48 +0000 (20:24 -0400)]
amd: add chip identification for gfx1100-1103
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Boyuan Zhang [Sun, 27 Feb 2022 00:50:40 +0000 (19:50 -0500)]
radeonsi/vcn: enable vcn 4.0 encode for gfx11 asic
Enable VCN 4.0 encode for supported Asics.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Boyuan Zhang [Sun, 27 Feb 2022 00:49:08 +0000 (19:49 -0500)]
radeonsi/vcn: add session init ib for vcn 4.0
Implement session init ib based on new interface for VCN 4.0.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Boyuan Zhang [Sun, 27 Feb 2022 01:14:30 +0000 (20:14 -0500)]
radeonsi/vcn: add encode context ib for vcn 4.0
Implement encode context ib based on new reconstructed picture and
interface for VCN 4.0, and modify dpb setup accordingly.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Boyuan Zhang [Sun, 27 Feb 2022 00:32:53 +0000 (19:32 -0500)]
radeonsi/vcn: add vcn 4.0 encode fw interface version
Add major and minor encode FW interface version for VCN 4.0.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Boyuan Zhang [Sun, 27 Feb 2022 00:29:16 +0000 (19:29 -0500)]
radeonsi/vcn: add vcn 4.0 encode support
Add new file "radeon_vcn_enc_4_0.c" for VCN 4.0 encode.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
James Zhu [Sun, 20 Feb 2022 16:46:48 +0000 (11:46 -0500)]
radeonsi/vcn: add decode software ring support for gfx11
Add decode software ring support for gfx11.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
James Zhu [Sun, 20 Feb 2022 16:42:29 +0000 (11:42 -0500)]
radeonsi/gfx11: update codec support for gfx11
Update codec support for gfx11.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
James Zhu [Sun, 20 Feb 2022 16:39:45 +0000 (11:39 -0500)]
amd: update headers to support decode software ring
Update headers to support decode software ring.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Tue, 3 May 2022 23:36:47 +0000 (19:36 -0400)]
radeonsi/gfx11: add a workaround for CB perf counters
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Tue, 3 May 2022 19:16:22 +0000 (15:16 -0400)]
radeonsi: inline si_cp_dma_prefetch in si_draw_vbo for lower overhead
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Wed, 30 Mar 2022 05:57:38 +0000 (01:57 -0400)]
radeonsi/gfx11: limit CP DMA to max 32KB sizes
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Tue, 3 May 2022 19:05:50 +0000 (15:05 -0400)]
radeonsi/gfx11: mark streamout as unimplemented for now
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Tue, 3 May 2022 19:04:44 +0000 (15:04 -0400)]
radeonsi/gfx11: resolve MSAA using u_blitter
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Thu, 28 Apr 2022 12:38:49 +0000 (08:38 -0400)]
radeonsi/gfx11: don't count the non-existent scratch_byte_offset SGPR
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Fri, 22 Apr 2022 16:12:42 +0000 (12:12 -0400)]
radeonsi/gfx11: change LDS allocation granularity for PS
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Sat, 2 Apr 2022 05:51:44 +0000 (01:51 -0400)]
radeonsi/gfx11: update the initialization of SGPR0/1 registers for HS and GS
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Sat, 2 Apr 2022 01:47:03 +0000 (21:47 -0400)]
radeonsi/gfx11: limit MSAA color buffers to the RGBA channel order
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Yogesh mohan marimuthu [Wed, 22 Dec 2021 20:33:48 +0000 (02:03 +0530)]
ac,radeonsi/gfx11: swizzle MRT0/1 for dual source blending
If dual source blending is enabled, use export targets 21 and 22.
Also we have to swap odd/even lanes between export target 21 and 22.
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Yogesh Mohan Marimuthu [Thu, 10 Feb 2022 19:54:56 +0000 (01:24 +0530)]
radeonsi/gfx11: export alpha through mrtz for alpha-to-coverage if mrtz is there
If both mrtz and alpha-to-coverage are enabled, the alpha channel must
be exported through mrtz.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Indrajit Kumar Das [Fri, 28 Jan 2022 05:55:01 +0000 (11:25 +0530)]
radeonsi/gfx11: VRS changes
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Sat, 22 Jan 2022 17:42:51 +0000 (12:42 -0500)]
radeonsi/gfx11: TF_RING_SIZE changed to a per-SE size
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Sat, 22 Jan 2022 14:57:20 +0000 (09:57 -0500)]
radeonsi/gfx11: don't use FLUSH_AND_INV_DB_META
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Sat, 22 Jan 2022 14:56:39 +0000 (09:56 -0500)]
radeonsi/gfx11: emit SQ_NON_EVENT for tessellation at the end of IBs
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Fri, 21 Jan 2022 09:05:25 +0000 (04:05 -0500)]
radeonsi/gfx11: don't set non-existent CP_COHER_START_DELAY
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Yogesh mohan marimuthu [Wed, 22 Dec 2021 14:43:25 +0000 (20:13 +0530)]
radeonsi/gfx11: program db render control register
Signed-off-by: Yogesh mohan marimuthu <yogesh.mohanmarimuthu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Tue, 21 Sep 2021 15:36:01 +0000 (11:36 -0400)]
radeonsi/gfx11: scattered register deltas
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Tue, 11 May 2021 04:50:43 +0000 (00:50 -0400)]
radeonsi/gfx11: implement attributes through memory
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Fri, 17 Dec 2021 17:30:58 +0000 (12:30 -0500)]
radeonsi/gfx11: don't set COMPR for exports, use 0x3 channel mask instead
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Yogesh Mohanmarimuthu [Tue, 5 Oct 2021 19:14:42 +0000 (00:44 +0530)]
radeonsi/gfx11: use PIXEL_PIPE_STATE_DUMP event instead of ZPASS_DONE
Use PIXEL_PIPE_STATE_CONTROL/DUMP event instead of ZPASS_DONE for gfx11.
Signed-off-by: Yogesh Mohanmarimuthu <yogesh.mohanmarimuthu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Thu, 23 Sep 2021 11:01:46 +0000 (07:01 -0400)]
radeonsi/gfx11: don't set non-existent SPI_SHADER_USER_DATA_VS_x
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Wed, 22 Sep 2021 09:07:26 +0000 (05:07 -0400)]
ac,radeonsi/gfx11: set SWIZZLE_ENABLE correctly
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Wed, 22 Sep 2021 08:37:34 +0000 (04:37 -0400)]
ac,radeonsi/gfx11: remove FMASK loads
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Fri, 7 May 2021 01:03:54 +0000 (21:03 -0400)]
radeonsi/gfx11: add CB deltas
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Sat, 18 Dec 2021 14:07:48 +0000 (09:07 -0500)]
radeonsi/gfx11: buffer descriptor changes
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Pierre-Eric Pelloux-Prayer [Tue, 27 Jul 2021 12:13:34 +0000 (14:13 +0200)]
radeonsi/gfx11: image descriptor changes
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Pierre-Eric Pelloux-Prayer [Tue, 27 Jul 2021 11:42:24 +0000 (13:42 +0200)]
radeonsi/gfx11: register changes
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Pierre-Eric Pelloux-Prayer [Tue, 27 Jul 2021 11:40:28 +0000 (13:40 +0200)]
radeonsi/gfx11: add assert in legacy vs path
Only ngg should be used.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Yogesh mohan marimuthu [Tue, 24 Aug 2021 07:23:06 +0000 (12:53 +0530)]
radeonsi/gfx11: program inst_pref_size for compute
For gfx11, program INST_PREF_SIZE value in SPI registers.
v2: move INST_PREF_SIZE reg programming (Marek Olšák)
Signed-off-by: Yogesh mohan marimuthu <yogesh.mohanmarimuthu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Thu, 16 Sep 2021 01:30:04 +0000 (21:30 -0400)]
radeonsi/gfx11: program inst_pref_size for graphics
For gfx11, program INST_PREF_SIZE value in SPI registers.
v4: fix mask value, code indendation (Marek Olšák)
v3: improve code for readability (Indrajit Das, Marek Olšák)
v2: ngg is always enabled in gfx11 (Marek Olšák)
Signed-off-by: Yogesh mohan marimuthu <yogesh.mohanmarimuthu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Yogesh mohan marimuthu [Sun, 22 Aug 2021 12:17:08 +0000 (17:47 +0530)]
radeonsi/gfx11: instruction cache line size is 128 bytes
In gfx11, instruction cache line size is 128 bytes. This patch makes
the neccessary code changes.
v2: instruction store line size is 64 bytes (Marek Olšák)
Signed-off-by: Yogesh mohan marimuthu <yogesh.mohanmarimuthu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Yogesh mohan marimuthu [Tue, 20 Jul 2021 19:12:59 +0000 (00:42 +0530)]
radeonsi/gfx11: interp changes for 16bit
make interp 16bit changes for gfx11
Signed-off-by: Yogesh mohan marimuthu <yogesh.mohanmarimuthu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Yogesh mohan marimuthu [Tue, 20 Jul 2021 18:46:57 +0000 (00:16 +0530)]
radeonsi/gfx11: interp changes for 32bit
make interp 32bit changes for gfx11
v2: fix coding indentation issue (Pierre-Eric)
Signed-off-by: Yogesh mohan marimuthu <yogesh.mohanmarimuthu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Yogesh mohan marimuthu [Tue, 15 Jun 2021 09:35:06 +0000 (15:05 +0530)]
radeonsi/gfx11: make flat_scratch changes for compute
make flat_scratch gen11 changes for compute
v5: optimize the code for size (Pierre-Eric)
v4: remove type cast from 64bit to 32bit (Marek Olšák)
use radeon_set_sh_reg_seq (Marek Olšák)
combine RSRC and scratch reg write packets (Marek Olšák)
v3: fix coding guidelines (Marek Olšák)
v2: do not skip si_resource_reference() call (Marek Olšák)
Signed-off-by: Yogesh mohan marimuthu <yogesh.mohanmarimuthu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Yogesh mohan marimuthu [Tue, 15 Jun 2021 09:22:51 +0000 (14:52 +0530)]
radeonsi/gfx11: make flat_scratch changes for graphics
gfx11 passes scratch base address using
SPI_GFX_SCRATCH_BASE_LO and _HI registers. Make the
code changes to support the same.
v5: remove type cast from 64bit to 32bit (Marek Olšák)
v4: combine scratch_memory and scratch_state atom (Marek Olšák)
v3: skip shader relocs for gfx11
v2: make atom for scratch_memory (Indrajit)
Signed-off-by: Yogesh mohan marimuthu <yogesh.mohanmarimuthu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Tue, 11 May 2021 04:44:00 +0000 (00:44 -0400)]
radeonsi/gfx11: use the new TCS WaveID SGPR to compute vs_rel_patch_id
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Fri, 7 May 2021 01:04:19 +0000 (21:04 -0400)]
radeonsi/gfx11: enable arbitrary DCC format reinterpretation
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Fri, 7 May 2021 00:57:52 +0000 (20:57 -0400)]
radeonsi/gfx11: enable NGG-only draw paths
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Thu, 6 May 2021 21:40:25 +0000 (17:40 -0400)]
radeonsi/gfx11: expect packed threadID VGPRs
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Thu, 6 May 2021 21:38:21 +0000 (17:38 -0400)]
radeonsi/gfx11: always allow DCC stores
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Wed, 11 Nov 2020 19:37:00 +0000 (14:37 -0500)]
radeonsi/gfx11: increase the hw screen offset alignment
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Fri, 7 May 2021 00:41:47 +0000 (20:41 -0400)]
ac/surface: add gfx11 support to modifiers tests
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Fri, 7 May 2021 09:54:26 +0000 (05:54 -0400)]
ac/surface: define gfx11 modifiers
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Fri, 7 May 2021 09:59:45 +0000 (05:59 -0400)]
ac/surface: gfx11 changes
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Wed, 8 Dec 2021 16:42:49 +0000 (11:42 -0500)]
ac/gpu_info: set cu_mask correctly for gfx11
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Wed, 27 Apr 2022 03:23:33 +0000 (23:23 -0400)]
ac/llvm: don't set GLC for stores on gfx11
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Tue, 22 Mar 2022 14:19:41 +0000 (10:19 -0400)]
ac/llvm: update pknorm and waitcnt for gfx11
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Fri, 11 Feb 2022 10:45:26 +0000 (05:45 -0500)]
ac/llvm: don't set DLC on gfx11 because it means something else there
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Fri, 17 Dec 2021 19:08:45 +0000 (14:08 -0500)]
ac/llvm: export mrt0 instead of null on gfx11
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Sun, 27 Feb 2022 02:32:42 +0000 (21:32 -0500)]
ac: implement register shadowing for gfx11
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Thu, 27 Jan 2022 04:36:30 +0000 (23:36 -0500)]
ac: scratch buffer register changes for gfx11
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Fri, 17 Dec 2021 16:28:54 +0000 (11:28 -0500)]
ac: implement ac_get_tbuffer_format for gfx11
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Pierre-Eric Pelloux-Prayer [Tue, 27 Jul 2021 12:36:30 +0000 (14:36 +0200)]
amd: update gfx10_format_table.py for gfx11
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Wed, 4 May 2022 00:32:27 +0000 (20:32 -0400)]
ac: don't align VGPRs to 8 or 16 for gfx11
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Fri, 7 May 2021 11:02:18 +0000 (07:02 -0400)]
amd: add Mesa-only addrlib changes
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Fri, 7 May 2021 10:12:19 +0000 (06:12 -0400)]
amd: import gfx11 addrlib
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Wed, 22 Sep 2021 08:58:53 +0000 (04:58 -0400)]
amd: add gfx11 to packet definitions
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Sun, 28 Mar 2021 06:12:47 +0000 (02:12 -0400)]
amd: enable gfx11 in header generator, fix drivers with renamed gfx6-10 defs
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Sun, 28 Mar 2021 08:59:54 +0000 (04:59 -0400)]
amd/registers: add gfx11-rsrc.json
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Sun, 28 Mar 2021 06:11:42 +0000 (02:11 -0400)]
amd/registers: add gfx11.json
Other files are also updated to due regeneration.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Sun, 28 Mar 2021 05:57:44 +0000 (01:57 -0400)]
amd/registers: add gfx11 to the json generator
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Marek Olšák [Tue, 3 May 2022 18:42:57 +0000 (14:42 -0400)]
amd/registers: hardcode GC base offsets in the json generator
gfx11 doesn't have the ip_offset file, so we have to do it this way.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
Dave Airlie [Mon, 9 May 2022 04:28:32 +0000 (14:28 +1000)]
radv: precalculate tess ring sizes/offsets.
These are all static per device, so just calculate at device init
time instead of preamble
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16392>
Dave Airlie [Mon, 9 May 2022 04:19:35 +0000 (14:19 +1000)]
radv: precalculate hs offchip parameters.
These are per device static, just just precalc them instead of
doing it on every command buffer submission.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16392>
Karol Herbst [Thu, 28 Apr 2022 20:08:00 +0000 (22:08 +0200)]
nir: add a nir_remove_non_entrypoints helper
This code just got duplicated a lot. There is still more, but the
remaining instances do a bit more than just removing other functions.
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16348>
Jason Ekstrand [Tue, 12 Apr 2022 17:41:14 +0000 (12:41 -0500)]
nir: Fix constant folding for non-32-bit ifind_msb and clz
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16348>
Karol Herbst [Tue, 12 Apr 2022 00:33:27 +0000 (02:33 +0200)]
iris/cs: take buffer offsets into account for CL
Sadly we pass in an offset, which the driver can't ignore
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16348>
Karol Herbst [Sun, 3 Apr 2022 10:47:58 +0000 (12:47 +0200)]
llvmpipe/fence: make the fence id counter atomic
Multiple threads can race on the function static variable
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16348>
Karol Herbst [Fri, 25 Feb 2022 05:11:22 +0000 (06:11 +0100)]
llvmpipe: PIPE_COMPUTE_CAP_GRID_DIMENSION is uint64_t
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16348>
Mike Blumenkrantz [Thu, 5 May 2022 17:34:47 +0000 (13:34 -0400)]
zink: split renderpasses for TextureBarrierNV() usage
if no fbfetch is present, then this is a draw -> sampler read barrier,
and zink does not emit a self-dependency for this by default
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16354>
Charmaine Lee [Mon, 9 May 2022 22:07:13 +0000 (15:07 -0700)]
svga/nir: enable PIPE_CAP_TGSI_TEXCOORD
Use texcoord semantic instead of generic with nir.
Fixes assert in nir_gather_info with offsetted varying slots.
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16414>
Michel Zou [Thu, 5 May 2022 17:51:10 +0000 (19:51 +0200)]
vulkan/wsi: fix missing unistd include
fixes:
c72ff19a
Closes #6428
Reviewed-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16353>
Emma Anholt [Thu, 5 May 2022 19:21:19 +0000 (12:21 -0700)]
ci/iris: Cut the glk-deqp test coverage in half.
It's taking 13-14 minutes of deqp-runner time, not counting booting, or
the LAVA-side job getting being queued behind other jobs. Well past our
10-minute runtime target, and we saw load on these boards causing the
queue to get quite long
(https://gitlab.freedesktop.org/mesa/mesa/-/issues/6409#note_1368750)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16359>
Alyssa Rosenzweig [Mon, 9 May 2022 20:09:59 +0000 (16:09 -0400)]
agx: Restore Valve copyright header
Parallel copy code is from ir3_lower_parallel_copy.c. This was attributed in the
commit message but lost in the copyright header due to a copypaste mistake.
Rectify this.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16413>
Rhys Perry [Fri, 6 May 2022 10:56:30 +0000 (11:56 +0100)]
aco: fix cmpswap global atomic definition on GFX6
Missed this one.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes:
2f0bb39e162 ("aco: ensure that definitions fixed to operands have matching regclasses")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16367>
Emma Anholt [Tue, 26 Apr 2022 04:11:38 +0000 (21:11 -0700)]
Revert "ci: remove nouveau from shader-db runs"
This reverts commit
0464117ad9bd47f079175058771220e8dad4f00b. Now that
the shim back-channel communicates with nouveau that the "GPU" is always
idle, we can get the nouveau compiler back into the CI path.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16150>
Emma Anholt [Wed, 8 Dec 2021 23:21:42 +0000 (15:21 -0800)]
nouveau: disable fences when running under drm-shim.
Otherwise, you get a hang at the end of shader-db.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16150>
Pavel Ondračka [Sun, 8 May 2022 16:04:37 +0000 (18:04 +0200)]
r300: skip draws instead of using a dummy vertex shader
When we fail to compile some vertex shader, we currently use a very
simple dummy one, setting gl_Position to (0,0,0,1), effectively
rendering nothing. Unfortunately, the dummy vertex shader leads to
hangs with RV370 in some rare circumstances. Instead of trying to
fix the shader, just skip the draws altogether when the compilation
fails.
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5870
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16387>
Emma Anholt [Wed, 20 Apr 2022 23:37:46 +0000 (16:37 -0700)]
glsl: Stop lowering ir_quadop_vector.
Now that everybody goes through NIR, glsl_to_nir is happy to handle the
instruction and turn it into nir_op_vec4 instead of going to a temp
variable and back.
No changes on freedreno shader-db.
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16363>
Charmaine Lee [Fri, 6 May 2022 00:11:12 +0000 (17:11 -0700)]
svga: fix shader IR type passed to draw create shader function
In the SVGA create shader functions, the original shader IR could have been
deleted after pipe_shader_state_to_tgsi_tokens() if it is to be converted
from NIR to TGSI. So to avoid accessing the deleted NIR IR,
set the shader state type to TGSI before passing the shader
state to the draw function.
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16365>
Alyssa Rosenzweig [Mon, 9 May 2022 14:40:46 +0000 (10:40 -0400)]
pan/va: Add whitespace after disassembled branches
To make the disassembly easier to read, add whitespace after disassembled
branches. This makes the basic blocks of the original control flow graph more
obvious, to aid comparison with the IR.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16409>
Alyssa Rosenzweig [Fri, 6 May 2022 16:57:14 +0000 (12:57 -0400)]
pan/va: Add some whitespace to Valhall disassembly
Makes it easier to read.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16409>
Sathishkumar S [Wed, 27 Apr 2022 13:12:57 +0000 (18:42 +0530)]
radeon/vcn: engage all available jpeg engines
use multiple contexts and submit in a round robin scheme to make
use of all the available jpeg engines simultaneously. During mjpeg
decode context need not be same across frames as they are discrete
jpeg images.
V2: number of ctx to be equal to number of engines and fix indent (Leo)
V3: decide ctx count in create_decoder, don't add a video param (Boyuan)
Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16355>
Mihai Preda [Mon, 9 May 2022 12:04:52 +0000 (15:04 +0300)]
Revert "gallivm: use LLVM opaque pointers in lp_bld_tgsi_soa.c"
This reverts commit
32a55651cf4ecb830801acafe6410df3f66afca9.
Fixes: #6439 #6453
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16400>
Rhys Perry [Wed, 4 May 2022 12:04:04 +0000 (13:04 +0100)]
ac/nir: skip s_barrier if TCS patches are within subgroup
fossil-db (Sienna Cichlid):
Totals from 538 (0.33% of 162293) affected shaders:
Instrs: 125288 -> 123682 (-1.28%)
CodeSize: 712384 -> 705960 (-0.90%)
Latency: 632139 -> 623596 (-1.35%)
InvThroughput: 218491 -> 215600 (-1.32%)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16356>
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