radeonsi: use wave size to determine index stride

Signed-off-by: Lang Yu <lang.yu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24920>

radeonsi: use AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32 to determine wave size

Signed-off-by: Lang Yu <lang.yu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24920>

amd/common: add AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32 property

This property can be used to determine wave size on gfx10+.

Signed-off-by: Lang Yu <lang.yu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24920>

freedreno/a7xx: Add CP_RESET_CONTEXT_STATE

Used by the kernel driver. Definition taken from kgsl.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24969>

egl: bind dri2_set_WL_bind_wayland_display for zink when necessary

Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24701>

egl: call dri3_x11_connect() for zink

Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24701>

egl/dri3: only set driver_name if not already set

Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24701>

ci/b2c: assert that install folder is present whether or not the tarball was extracted

We already `rm -rf install` at the beginning so it can't be a stale install folder.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24970>

ci/b2c: don't allow failures in test script preparation

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24970>

ci/b2c: skip install.tar extraction if the tarball is not present

This is the case when retrying after a B2C_TIMEOUT for instance.

Fixes: 85a8f03211090bc9a23a ("ci: delete install.tar after extracting it to avoid re-uploading it")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24970>

radv/rt: Pre-initialize instance address

It's not disallowed by spec to load instance-related data in case of a
miss where no instance was ever visited. Such loads make no sense, so we
can return garbage, but it mustn't hang the GPU. Initialize the instance
addresses to the TLAS base to make sure we always have valid memory to load from.

Partially fixes GPU hangs in RTX Remix games.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24971>

ci: document farm rules

Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24898>

rusticl/disk_cache: fix stack corruption

The length passed to mesa_bytes_to_hex is the one of the input, not output
data.

Fixes: fbe9a7ca3e7 ("rusticl/mesa: create proper build-id hash for the disk cache")
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24967>

anv: enable KHR_maintenance5

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24387>

anv: deal with new pipeline flags

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24387>

anv: add maintenance5 A8_UNORM/A1B5G5R5_UNORM support

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24387>

anv: implement GetDeviceImageSubresourceLayoutKHR/GetImageSubresourceLayout2KHR

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24387>

anv: add vkGetRenderingAreaGranularityKHR()

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24387>

anv: handle new VkBufferViewUsageCreateInfoKHR

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24387>

anv: implement vkCmdBindIndexBuffer2KHR

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24387>

vk/graphic_state, tu: Use dynamic blend count from subpass

A future spec clarification will state that pipelines will not have to
fill out the blend attachment count if every blend state is dynamic.
Instead, this comes from the subpass/rendering/inheritance info. To fix
this while still being able to use the same code to emit dynamic and
precompiled state, we have to set the attachment count in the blend
struct at the beginning of the subpass.

This will also help with ESO where it already worked like this.

Closes: #9709
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24957>

lavapipe: Fix the locking around cso destruction

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24956>

lavapipe: Avoid lowering shaders twice

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9726
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24956>

llvmpipe/fs: rewrite output finding using nir.

Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24817>

llvmpipe/fs: drop the simple shader logic

It's been turned off since 2013.

Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24817>

llvmpipe/fs: start using nir info in some places.

Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24817>

llvmpipe/analyse: drop TGSI path.

This drop the AERO path, this should probably be reworked using NIR.

Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24817>

llvmpipe/fs: switch to using tgsi->nir instead of handling tgsi

This just swaps, lots of cleanup after this.

Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24817>

android: Fix num_planes assignment in u_gralloc_fallback

That seems to be an uncaught porting issue from EGL code to a common.

Fixes: ee42e2166d8362 ("android: Introduce the Android buffer info abstraction")
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24953>

aco: do not fix_exports when program is prolog

Otherwise fix_export() will abort when find no export.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24712>

aco: add aco compile interface for radeonsi vs prolog

Radeonsi prolog does not need s_endpgm.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24712>

aco: add vs prolog instruction selection for radeonsi

Port from llvm si_llvm_build_vs_prolog().

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24712>

aco: prepare fix_ls_vgpr_init_bug to be used by gl vs prolog

Prolog does not have nir shader.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24712>

aco: pass sw_stage when setup_isel_context

We are going to add more shader parts.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24712>

aco: simplify setup_tcs_info

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24712>

ci: disable nouveau shaderdb

this has been timing out with some regularity

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24955>

vulkan/wsi: warn about unset present_mode in PresentModeCompatibilityExt

A bug in vulkan tools, https://github.com/KhronosGroup/Vulkan-Tools/issues/846
causes vulkaninfo to crash in Mesa under wayland since the changes
in 5ceba97c

Handle the crashing case on wayland similarly to how other WSIs
do (nonsensically claiming a single compatible mode), and log
the condition once for all WSIs.

Fixes 5ceba97c2

Signed-off-by: Derek Foreman <derek.foreman@collabora.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24888>

ci: add comment explaining which image tags to update for Fossilize

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24923>

ci: uprev Fossilize

This version was really old.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24923>

ci: uprev vkd3d-proton

This introduces more tests, especially coverage for
NV_device_generated_commands_compute.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24923>

radv: Use before/after_cf_list for entrypoints

Via Coccinelle patch:

    @@
    expression shader;
    @@

    -nir_before_cf_list(&nir_shader_get_entrypoint(shader)->body)
    +nir_before_impl(nir_shader_get_entrypoint(shader))

    @@
    expression shader;
    @@

    -nir_after_cf_list(&nir_shader_get_entrypoint(shader)->body)
    +nir_after_impl(nir_shader_get_entrypoint(shader))

Suggested-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24910>

treewide: Use nir_before/after_impl for more elaborate cases

Via Coccinelle patch:

    @@
    expression func_impl;
    @@

    -nir_before_block(nir_start_block(func_impl))
    +nir_before_impl(func_impl)

    @@
    expression func_impl;
    @@

    -nir_after_block(nir_impl_last_block(func_impl))
    +nir_after_impl(func_impl)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24910>

treewide: Use nir_before/after_impl in easy cases

These open-code the same idiom as the helper.

Via Coccinelle patch:

    @@
    expression func_impl;
    @@

    -nir_before_cf_list(&func_impl->body)
    +nir_before_impl(func_impl)

    @@
    expression func_impl;
    @@

    -nir_after_cf_list(&func_impl->body)
    +nir_after_impl(func_impl)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24910>

nir: Add nir_before/after_impl cursors

These are common enough to merit their own helpers.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24910>

panfrost: drop pan_nir_lower_64bit_intrin

It's dead code now.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24939>

rusticl: reduce global_invocation_id_zero_base to 32 bit

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24939>

amd/ci: update list of failures/flakes for glcts-vangogh-valve

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24952>

aco/spill: add all live-in to merge block spill candidates

Previously, only already spilled live-in or phis were added to the spill
candidates. Because of branch definitions, this might not be enough.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9722
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24949>

zink: add lavapipe flake

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24951>

pvr: Zero tail of cs buffers after linking when dumping cs

Dumps already force buffers to zero before they get written to, this
keeps up the pattern of making the contents easier to grok.

Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24692>

pvr: Do not require TA_STATE_HEADER.pres_ispctl_dbsc for {db,sc}enable

This was a faulty assumption and caused valid control streams to report
as invalid.

Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24692>

pvr: Don't override commands copied to new buffer when extending cs

The next pointer wasn't advanced past the start of the new buffer,
meaning anything overflowed into the new buffer would be overwritten
on the next emit.

Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24692>

virgl: Do not expose EXT_texture_mirror_clamp when using a GLES host

The GL_MIRROR_CLAMP_EXT wrap parameter is never available in GLES.

This fixes the `spec@!opengl 1.1@texwrap 2d proj` piglit test when using a GLES
host.

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Reviewed-by: Filip Gawin <filip.gawin@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24935>

ci: Add locked flag to bindgen-cli installation

Ensures that the bindgen-cli dependencies are not changing.

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24936>

radv/winsys: check amdgpu_create_bo_from_user_mem() for EINVAL

amdgpu_create_bo_from_user_mem() may fail for multiple reasons.
Only return VK_ERROR_INVALID_EXTERNAL_HANDLE if the kernel
returned EINVAL, which indicates a bad input parameter.

Signed-off-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24858>

radv: re-order IO slot layout for stages that aren't linked

Otherwise, if eg. PSIZ is exported the ESGS stride is wrong. This isn't
optimal yet but let's start with this to support separate compilation
of VS/TCS/TES/GS correctly first.

This fixes a bunch of issues when forcing separate compilation on RDNA2.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24908>

panfrost: drop 64 bit handling for cl workgroup intrinsics

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24905>

intel/compiler: drop 64 bit handling for cl workgroup intrinsics

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24905>

gallivm/nir: drop 64 bit handling for cl workgroup intrinsics

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24905>

ac: drop 64 bit handling for cl workgroup intrinsics

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24905>

nir: make num_workgroups 32 bit only

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24905>

nir: make workgroup_id 32 bit only

No backend supports 64 bit values natively anyway.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24905>

v3d,v3dv: use fquantize2f16 lowering in NIR

Ths is equivalent to what we have been doing in the backend.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24924>

ci: disable a660 jobs

They are not working right now and it's blocking:
- https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24936 (critical)
- https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24905

Signed-off-by: Karol Herbst <git@karolherbst.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24945>

zink+anv: add regression testing with pipeline libraries

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24716>

intel/fs: move lower of non-uniform at_sample barycentric to NIR

We use a non-uniform lowering loop in the backend which we can do
better in NIR because we can also use divergence analysis there.

This change also limits VGRF usage to a single VGRF to hold the sample
ID in the backend.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24716>

intel/fs: implement dynamic interpolation mode for dynamic persample shaders

There is no restriction for query per sample positions from the
interpolator when in non-per-sample dispatch mode. But apparently
that's not giving us the expected values for fragment shaders compiled
without per-sample dispatch knowledge (graphics pipeline libraries).

So when per-sample dispatch is dynamic and we're doing at_sample
interpolation, turn the interpolation back into at_offset at runtime
when we detect that the fragment shader is not run per sample.

Fixes a bunch of dEQP-GLES31.functional.shaders.multisample_interpolation.interpolate_at_sample.*

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: d8dfd153c5 ("intel/fs: Make per-sample and coarse dispatch tri-state")
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24716>

intel/compiler: fix dynamic alpha-to-coverage handling

Got the wrong logic operation. Let's reuse the nicer NIR builder
helper.

Fixes a bunch of KHR-GL46.sample_variables.mask.rgba8.*.samples*.mask*

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: fd7debc8bb ("intel/fs: make alpha_to_coverage a tristate")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9568
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24716>

intel/compiler: disable per-sample interpolation modes with non-per-sample dispatch

Fixes hangs in dEQP-GLES31.functional.shaders.multisample_interpolation.interpolate_at_sample.*

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 5644011f06 ("intel/compiler: Convert wm_prog_key::persample_interp to a tri-state")
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24716>

bin/ci_run_n_monitor: error out if both --project and --pipeline-url are passed

Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24937>

intel/fs: New VGRF packing scheme for constant combining

Each block is processed separately.  VGRF channels that are allocated to
values that are only used in a particular block are made available in
other blocks.

This is almost always an improvement, but there are some pessimal cases
where it goes horribly wrong.  Imagine a shader with two blocks.  In
that shader, the first block has 5 constants used in the first block and
the second block.  Three other constants are only used in the first
block.  The second block has 15 constants that are used only in the
block.  The static VGRF usage is 3 regardless of packing.  However,
scheduling may be able to shorten the live range of the first VGRF when
it only has values that came from the first block (because three of the
values are dead on entry to the second block).

This used to occurs in a Mad Max shader on Broadwell.  That shader
went from 0:0 spills:fills to 107:52.  Some changes over the last
year, I'm assuming !13734, have prevented this case from occuring.

This change created a lot of churn on Haswell and Ivy Bridge.  This
seems to be primarily due to all the extra constants used for coissue,
but I did not investigate very deeply.  On older platforms, there were
no changes to spills or fills.  As a result, this is only used on
Broadwell and newer platforms.

v2: Update expected checksum for pixmark-piano-v2.trace on
gl-zink-anv-tgl. See #9714 for more details.

shader-db results:

Tiger Lake
total instructions in shared programs: 21101332 -> 21102084 (<.01%)
instructions in affected programs: 863686 -> 864438 (0.09%)
helped: 463 / HURT: 437

total cycles in shared programs: 790573225 -> 790664391 (0.01%)
cycles in affected programs: 92546803 -> 92637969 (0.10%)
helped: 558 / HURT: 629

total spills in shared programs: 3959 -> 3951 (-0.20%)
spills in affected programs: 184 -> 176 (-4.35%)
helped: 2 / HURT: 0

total fills in shared programs: 2639 -> 2631 (-0.30%)
fills in affected programs: 184 -> 176 (-4.35%)
helped: 2 / HURT: 0

LOST:   1
GAINED: 5

Ice Lake and Skylake had similar results. (Ice Lake shown)
total instructions in shared programs: 19945216 -> 19944711 (<.01%)
instructions in affected programs: 139569 -> 139064 (-0.36%)
helped: 66 / HURT: 3

total cycles in shared programs: 858410082 -> 857381323 (-0.12%)
cycles in affected programs: 383825958 -> 382797199 (-0.27%)
helped: 1012 / HURT: 1055

total spills in shared programs: 6190 -> 6116 (-1.20%)
spills in affected programs: 891 -> 817 (-8.31%)
helped: 66 / HURT: 3

total fills in shared programs: 7382 -> 7238 (-1.95%)
fills in affected programs: 1538 -> 1394 (-9.36%)
helped: 66 / HURT: 3

LOST:   5
GAINED: 8

Broadwell
total instructions in shared programs: 17820886 -> 17812515 (-0.05%)
instructions in affected programs: 800512 -> 792141 (-1.05%)
helped: 385 / HURT: 1

total cycles in shared programs: 904482935 -> 903102070 (-0.15%)
cycles in affected programs: 422427015 -> 421046150 (-0.33%)
helped: 1091 / HURT: 812

total spills in shared programs: 17908 -> 16576 (-7.44%)
spills in affected programs: 9459 -> 8127 (-14.08%)
helped: 386 / HURT: 0

total fills in shared programs: 25397 -> 22354 (-11.98%)
fills in affected programs: 15504 -> 12461 (-19.63%)
helped: 385 / HURT: 1

LOST:   2
GAINED: 2

No shader-db changes on Haswell or older platforms.

fossil-db results:

Tiger Lake
Instructions in all programs: 156881463 -> 156890970 (+0.0%)
Instructions helped: 9033
Instructions hurt: 10285

Cycles in all programs: 7532597466 -> 7529647924 (-0.0%)
Cycles helped: 10548
Cycles hurt: 13667

Spills in all programs: 5490 -> 5110 (-6.9%)
Spills helped: 100
Spills hurt: 3

Fills in all programs: 6123 -> 5752 (-6.1%)
Fills helped: 100
Fills hurt: 3

Gained: 17
Lost: 47

Ice Lake
Instructions in all programs: 141309644 -> 141309603 (-0.0%)
Instructions helped: 9
Instructions hurt: 4

Cycles in all programs: 9095812690 -> 9097008049 (+0.0%)
Cycles helped: 14288
Cycles hurt: 16381

Spills in all programs: 7418 -> 7404 (-0.2%)
Spills helped: 9
Spills hurt: 4

Fills in all programs: 8326 -> 8321 (-0.1%)
Fills helped: 9
Fills hurt: 4

Skylake
Instructions in all programs: 131872347 -> 131870690 (-0.0%)
Instructions helped: 111
Instructions hurt: 3

Cycles in all programs: 8800835649 -> 8802483884 (+0.0%)
Cycles helped: 9415
Cycles hurt: 9678

Spills in all programs: 6917 -> 6476 (-6.4%)
Spills helped: 111
Spills hurt: 3

Fills in all programs: 7584 -> 7354 (-3.0%)
Fills helped: 111
Fills hurt: 3

Lost: 5

Tested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7698>

intel/fs: Combine constants for integer instructions too

v2: Remove type change for SHR with negation.  This was a leftover from
a previous attempt to deal with SHR and negation.  Now all right-shifts
with unsigned parameters are marked as not being able to have source
modifiers.

v3: Disallow negations on right shifts of unsigned sources by setting
the no_negations flag in add_candidate_immediate.  This eliminates the
need to exclude SHR in can_do_source_mods.

Tiger Lake
total instructions in shared programs: 21102817 -> 21099443 (-0.02%)
instructions in affected programs: 296796 -> 293422 (-1.14%)
helped: 92 / HURT: 356

total cycles in shared programs: 790564691 -> 790393358 (-0.02%)
cycles in affected programs: 36456886 -> 36285553 (-0.47%)
helped: 171 / HURT: 286

total spills in shared programs: 3951 -> 3959 (0.20%)
spills in affected programs: 176 -> 184 (4.55%)
helped: 0 / HURT: 2

total fills in shared programs: 2631 -> 2639 (0.30%)
fills in affected programs: 176 -> 184 (4.55%)
helped: 0 / HURT: 2

LOST:   0
GAINED: 4

Ice Lake
total instructions in shared programs: 19954204 -> 19949122 (-0.03%)
instructions in affected programs: 40301 -> 35219 (-12.61%)
helped: 23 / HURT: 2

total cycles in shared programs: 858377735 -> 858462082 (<.01%)
cycles in affected programs: 75537286 -> 75621633 (0.11%)
helped: 124 / HURT: 319

total spills in shared programs: 6255 -> 6190 (-1.04%)
spills in affected programs: 392 -> 327 (-16.58%)
helped: 1 / HURT: 2

total fills in shared programs: 7813 -> 7382 (-5.52%)
fills in affected programs: 942 -> 511 (-45.75%)
helped: 1 / HURT: 2

LOST:   0
GAINED: 3

Skylake
total instructions in shared programs: 18049362 -> 18044440 (-0.03%)
instructions in affected programs: 48317 -> 43395 (-10.19%)
helped: 26 / HURT: 2

total cycles in shared programs: 844884806 -> 844915655 (<.01%)
cycles in affected programs: 76137133 -> 76167982 (0.04%)
helped: 171 / HURT: 293

total spills in shared programs: 6148 -> 6149 (0.02%)
spills in affected programs: 595 -> 596 (0.17%)
helped: 4 / HURT: 2

total fills in shared programs: 7484 -> 7067 (-5.57%)
fills in affected programs: 1226 -> 809 (-34.01%)
helped: 4 / HURT: 2

LOST:   0
GAINED: 8

Broadwell
total instructions in shared programs: 17826844 -> 17821805 (-0.03%)
instructions in affected programs: 60687 -> 55648 (-8.30%)
helped: 28 / HURT: 8

total cycles in shared programs: 905332682 -> 904369499 (-0.11%)
cycles in affected programs: 76743509 -> 75780326 (-1.26%)
helped: 179 / HURT: 225

total spills in shared programs: 17922 -> 17908 (-0.08%)
spills in affected programs: 2495 -> 2481 (-0.56%)
helped: 6 / HURT: 8

total fills in shared programs: 26290 -> 25397 (-3.40%)
fills in affected programs: 2606 -> 1713 (-34.27%)
helped: 8 / HURT: 6

LOST:   1
GAINED: 1

Haswell
total instructions in shared programs: 16678878 -> 16674444 (-0.03%)
instructions in affected programs: 78458 -> 74024 (-5.65%)
helped: 87 / HURT: 6

total cycles in shared programs: 880189381 -> 880301043 (0.01%)
cycles in affected programs: 29956463 -> 30068125 (0.37%)
helped: 169 / HURT: 163

total spills in shared programs: 14428 -> 14378 (-0.35%)
spills in affected programs: 2384 -> 2334 (-2.10%)
helped: 8 / HURT: 6

total fills in shared programs: 16975 -> 16881 (-0.55%)
fills in affected programs: 1334 -> 1240 (-7.05%)
helped: 10 / HURT: 4

Ivy Bridge
total instructions in shared programs: 15706048 -> 15706035 (<.01%)
instructions in affected programs: 9941 -> 9928 (-0.13%)
helped: 13 / HURT: 0

total cycles in shared programs: 433618834 -> 433624637 (<.01%)
cycles in affected programs: 12926714 -> 12932517 (0.04%)
helped: 52 / HURT: 41

Sandy Bridge
total cycles in shared programs: 741223552 -> 741223443 (<.01%)
cycles in affected programs: 19814 -> 19705 (-0.55%)
helped: 14 / HURT: 0

No changes on Iron Lake or GM45

fossil-db changes:

Tiger Lake
Instructions in all programs: 156858030 -> 156905532 (+0.0%)
Instructions helped: 3915
Instructions hurt: 15411

Cycles in all programs: 7529667771 -> 7532117340 (+0.0%)
Cycles helped: 10260
Cycles hurt: 9990

Spills in all programs: 5610 -> 5457 (-2.7%)
Spills helped: 18

Fills in all programs: 6274 -> 6091 (-2.9%)
Fills helped: 18

Gained: 2
Lost: 16

Ice Lake
Instructions in all programs: 141308082 -> 141303083 (-0.0%)
Instructions helped: 574
Instructions hurt: 172

Cycles in all programs: 9091361325 -> 9094622766 (+0.0%)
Cycles helped: 8764
Cycles hurt: 11702

Spills in all programs: 7531 -> 7385 (-1.9%)
Spills helped: 19

Fills in all programs: 8462 -> 8294 (-2.0%)
Fills helped: 19

Gained: 22
Lost: 15

Skylake
Instructions in all programs: 131872162 -> 131867263 (-0.0%)
Instructions helped: 566
Instructions hurt: 172

Cycles in all programs: 8795095440 -> 8799676943 (+0.1%)
Cycles helped: 8333
Cycles hurt: 12182

Spills in all programs: 7006 -> 6884 (-1.7%)
Spills helped: 13

Fills in all programs: 7696 -> 7552 (-1.9%)
Fills helped: 13

Gained: 24
Lost: 1

Tested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7698>

intel/fs: Combine constants for SEL instructions too

It is very common to have bcsel where the second and third sources are
both constants.  This results in a situation where we would want to emit
a SEL with two constant sources, but that's not allowed.

Previously, we would load both constants into registers, then let
constant propagation copy the last constant into the SEL instruction.
This results in the constant using an entire SIMD register instead of a
single channel.

Instead, copy propagate both sources, then let the combine-constants
pass do its thing.  In the worst case, this stores the constant in a
single channel of the SIMD register.  In the best case, it reuses a
value that was loaded into a register to satisfy another instruction.

shader-db results:

Tiger Lake, Ice Lake, and Skylake had similar results. (Ice Lake shown)
total instructions in shared programs: 19951549 -> 19948709 (-0.01%)
instructions in affected programs: 482795 -> 479955 (-0.59%)
helped: 1184 / HURT: 3

total cycles in shared programs: 858584724 -> 858205341 (-0.04%)
cycles in affected programs: 356168375 -> 355788992 (-0.11%)
helped: 1448 / HURT: 1195

total spills in shared programs: 6569 -> 6255 (-4.78%)
spills in affected programs: 912 -> 598 (-34.43%)
helped: 58 / HURT: 0

total fills in shared programs: 8218 -> 7813 (-4.93%)
fills in affected programs: 1570 -> 1165 (-25.80%)
helped: 58 / HURT: 0

LOST:   6
GAINED: 16

Broadwell
total instructions in shared programs: 17819660 -> 17819389 (<.01%)
instructions in affected programs: 1078129 -> 1077858 (-0.03%)
helped: 1067 / HURT: 304

total cycles in shared programs: 904722624 -> 905035016 (0.03%)
cycles in affected programs: 362583117 -> 362895509 (0.09%)
helped: 1381 / HURT: 1123

total spills in shared programs: 17884 -> 17922 (0.21%)
spills in affected programs: 5088 -> 5126 (0.75%)
helped: 55 / HURT: 152

total fills in shared programs: 25533 -> 26290 (2.96%)
fills in affected programs: 12992 -> 13749 (5.83%)
helped: 61 /HURT: 295

LOST:   7
GAINED: 24

Haswell
total instructions in shared programs: 16678080 -> 16673976 (-0.02%)
instructions in affected programs: 1162893 -> 1158789 (-0.35%)
helped: 1584 / HURT: 7

total cycles in shared programs: 880180082 -> 879932525 (-0.03%)
cycles in affected programs: 364067522 -> 363819965 (-0.07%)
helped: 1226 / HURT: 976

total spills in shared programs: 14937 -> 14428 (-3.41%)
spills in affected programs: 7866 -> 7357 (-6.47%)
helped: 351 / HURT: 5

total fills in shared programs: 17572 -> 16975 (-3.40%)
fills in affected programs: 11028 -> 10431 (-5.41%)
helped: 350 / HURT: 3

LOST:   8
GAINED: 16

Ivy Bridge
total instructions in shared programs: 15704044 -> 15703158 (<.01%)
instructions in affected programs: 304513 -> 303627 (-0.29%)
helped: 707 / HURT: 0

total cycles in shared programs: 433560149 -> 433471118 (-0.02%)
cycles in affected programs: 19299650 -> 19210619 (-0.46%)
helped: 687 / HURT: 395

LOST:   2
GAINED: 9

Sandy Bridge
total instructions in shared programs: 13913386 -> 13912884 (<.01%)
instructions in affected programs: 195687 -> 195185 (-0.26%)
helped: 455 / HURT: 0

total cycles in shared programs: 741156272 -> 741136266 (<.01%)
cycles in affected programs: 10934349 -> 10914343 (-0.18%)
helped: 578 / HURT: 289

LOST:   9
GAINED: 4

Iron Lake and GM45 had similar results. (Iron Lake shown)
total instructions in shared programs: 8364056 -> 8364042 (<.01%)
instructions in affected programs: 5178 -> 5164 (-0.27%)
helped: 10 / HURT: 0

total cycles in shared programs: 248759794 -> 248757940 (<.01%)
cycles in affected programs: 4305246 -> 4303392 (-0.04%)
helped: 183 / HURT: 24

fossil-db results:

Tiger Lake
Instructions in all programs: 156943594 -> 156802601 (-0.1%)
Instructions helped: 20595
Instructions hurt: 23248

Cycles in all programs: 7512086950 -> 7528386387 (+0.2%)
Cycles helped: 29531
Cycles hurt: 27837

Spills in all programs: 13500 -> 5643 (-58.2%)
Spills helped: 394
Spills hurt: 22

Fills in all programs: 18943 -> 6306 (-66.7%)
Fills helped: 394
Fills hurt: 11

Gained: 93
Lost: 76

Ice Lake
Instructions in all programs: 141395899 -> 141249621 (-0.1%)
Instructions helped: 30067
Instructions hurt: 3

Cycles in all programs: 9097127057 -> 9089668235 (-0.1%)
Cycles helped: 32268
Cycles hurt: 24315

Spills in all programs: 13695 -> 7564 (-44.8%)
Spills helped: 403

Fills in all programs: 18400 -> 8494 (-53.8%)
Fills helped: 403

Gained: 114
Lost: 137

Skylake
Instructions in all programs: 131948328 -> 131826063 (-0.1%)
Instructions helped: 29968
Instructions hurt: 3

Cycles in all programs: 8794778440 -> 8793934844 (-0.0%)
Cycles helped: 32705
Cycles hurt: 23575

Spills in all programs: 10526 -> 7039 (-33.1%)
Spills helped: 403

Fills in all programs: 11025 -> 7728 (-29.9%)
Fills helped: 403

Gained: 102
Lost: 250

Tested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7698>

intel/fs: Completely re-write the combine constants pass

The is a squash of what in the original MR was "util: Add generic pass
that tries to combine constants" and "intel/fs: Switch to using
util_combine_constants".

The new algorithm uses a multi-pass greedy algorithm that attempts to
collect constants for loading in order of increasing degrees of freedom.
The first pass collects constants that must be emitted as-is (e.g.,
without source modifiers).

The second pass emits all constants that must be emitted (because they
are used in a source field that cannot be a literal constant) but that
can have a source modifier.

The final pass possibly emits constants that may not have to be emitted.
This is used for instructions where one of the fields is allowed to be a
constant.  This is not used in the current commit, but future commits
that enable SEL will use this.  The SEL instruction can have a single
constant, but when both sources are constant, one of the sources has to
be loaded into a register.

By loading constants in this order, required "choices" made in earlier
passes may be re-used in later passes.  This provides a more optimal
result.

At this point in the series, most platforms have the same results with
the new implementation.  Gen7 platforms see a significant number of
"small" changes.  Due to the coissue optimization on Gen7, each shader
is likely to have most constants affected by constant combining.

If a shader has only a single basic block, constants are packed into
registers in the order produced by the constant combining process.
Since each constant has a different live range in the shader, even
slightly different packing orders can have dramatic effects on the live
range of a register.  Even in cases where this does not affect register
pressure in a meaningful way, it can cause the scheduler to make very
different choices about the ordering of instructions.

From my analysis (using the `if (debug) { ... }` block at the end of
fs_visitor::opt_combine_constants), the old implementation and the new
implementation pick the same set of constants, but the order produced
may be slightly different.  For the smaller number of values in non-Gfx7
shaders, the orders are similar enough to not matter.

No shader-db or fossil-db changes on any non-Gfx7 platforms.

Haswell and Ivy Bridge had similar results. (Haswell shown)
total cycles in shared programs: 879930036 -> 880001666 (<.01%)
cycles in affected programs: 22485040 -> 22556670 (0.32%)
helped: 1879
HURT: 2309
helped stats (abs) min: 1 max: 6296 x̄: 258.54 x̃: 34
helped stats (rel) min: <.01% max: 54.63% x̄: 3.88% x̃: 0.87%
HURT stats (abs)   min: 1 max: 9739 x̄: 241.41 x̃: 40
HURT stats (rel)   min: <.01% max: 160.50% x̄: 6.01% x̃: 0.99%
95% mean confidence interval for cycles value: -1.04 35.25
95% mean confidence interval for cycles %-change: 1.23% 1.92%
Inconclusive result (value mean confidence interval includes 0).

LOST:   82
GAINED: 39

Tested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7698>

ci/android: remove strace output from cuttlefish-runner.sh

strace output is only used for debug and its output takes too much
space. Remove it to save resources.

Signed-off-by: Helen Koike <helen.koike@collabora.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Fixes: 7b51a583edb7 ("ci/android: add android to the ci")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24913>

ci: add --project option to ci_run_n_monitor.py

Now that we have drm-ci, add --project, so the script can also be used
to linux (and any other projects).

Let the default to "mesa" so it can keep behaving as before when the
option is not given.

Signed-off-by: Helen Koike <helen.koike@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24912>

ci/farm-rules: fix missing valve-infra jobs in scheduled pipelines

Fixes: 79f7882fc60451530235 ("ci: add quirk for GitLab assuming changes is always true for scheduled runs")
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24897>

nir/lower_shader_calls: Fix warning with clang

Implicit conversion warning.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24864>

nir/lower_shader_calls: Limit the remat chain length

There is no way we will rematerialize a 40k instruction long chain and
it also won't be beneficial. This improves the replay time if our CP2077
fossil by 350% when compiling only ray tracing pipelines.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24864>

panvk: catch unsupported arch in the panvk_physical_device_init

Suggested-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24201>

panvk: architecture isn't invalid, just unsupported

When we fail, tell users clearly why.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24201>

gallium/auxiliary/vl: Set vertex element src_stride in vl_deint_filter

Fixes: 76725452239 ("gallium: move vertex stride to CSO")

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24926>

aco/spill: skip p_branch in process_block

Fixes compilation of a Dead by Daylight shader.

fossil-db (gfx1100):
Totals from 58 (0.04% of 133461) affected shaders:
Instrs: 319824 -> 319421 (-0.13%); split: -0.13%, +0.00%
CodeSize: 1711260 -> 1708744 (-0.15%); split: -0.15%, +0.00%
SpillSGPRs: 2567 -> 2459 (-4.21%)
Latency: 3274930 -> 3274921 (-0.00%); split: -0.00%, +0.00%
InvThroughput: 924106 -> 924105 (-0.00%); split: -0.00%, +0.00%
Copies: 41883 -> 41757 (-0.30%); split: -0.31%, +0.00%
Branches: 9144 -> 9146 (+0.02%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9599
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24896>

ci/panfrost: add G52 simple_tests.partial_image_pot_same_format_noclear flake

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24922>

ci/freedreno: add another a530 flake

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24922>

ci/virgl: flakes in functional.draw_buffers_indexed group

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24922>

util: add radeonsi workaround for Nowhere Patrol

Cc: mesa-stable
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24919>

aco: fix emitting TCS epilogs end on GFX9+

With merged shaders, the long-jump should be emitted inside the
divergent if (ie. only for TCS invocations) and other non TCS
invocations should just end the program.

This fixes a bunch of failures with CTS by forcing TCS epilogs on
RDNA2.

Not sure how RadeonSI will handle that but maybe doing the merged
wave info thing in epilogs would help.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24832>

radv: remove the pipeline dependency for emitting VGT_GS_MODE

For shader object.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24865>

v3dv: re-enable sync_fd import/export on the simulator

On commit 29588fe11667 we re-enable sync_fd import/export. But only
with the real hw, because at that time there were wrong CTS tests
(that were calling vkSetEvent after submission) that needed to be
fixed.

Since this commit:
https://github.com/KhronosGroup/VK-GL-CTS/commit/717c051d4bcc9b71f13bc6b223e9926dcf9b7bd5

Those tests are fixed. That fix has been on CTS releases for some
time. So we can enable it on the simulator too.

With this change the pattern dEQP-VK.api.external.semaphore.sync_fd*
goes from 2 Passed/10 Not Supported to 12 Passed on the simulator.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24688>

radv: fix emitting TCS epilogs if TES and GS are linked on GFX9+

TES would be NULL because everything is merged to GS.
Found by inspection.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24890>

radv: small cleanups in radv_emit_patch_control_points()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24890>

radv: rename tcs_shader to tcs in radv_emit_tcs_epilog_state()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24890>

zink: remove sync TODO

after investigating, this is pointless and won't ever generate any value

fixes #9016

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24886>

zink: simplify some image barrier conditionals

no functional changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24886>

zink: make image barrier init functions void return

the return value was never used

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24886>

zink: reset unordered flags for image barriers on non-matching batch access

this allows more reordering when the first barrier in a new cmdbuf can
be reordered after previous ordered access exists

KHR-GLES3.copy_tex_image_conversions.required.texture2d_cubemap_negz:
before - ordered 68
after - ordered 16

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24886>

zink: force-reset unordered flags for buffer barriers on non-matching batch access

this should allow slightly better reordering

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24886>

vulkan/wsi/wayland: fix unset present_mode

chain->base.present_mode is unset at this point, ie. it's
zero-initialized. VK_PRESENT_MODE_IMMEDIATE_KHR happens to be 0,
so the WSI will attempt to use tearing-control on compositors that
don't support it.

Signed-off-by: Simon Ser <contact@emersion.fr>
Fixes: 5ceba97c2e18 ("vulkan/wsi/wayland: add support for IMMEDIATE")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24885>

zink: fix optimal_keys warning message

needs more newlines

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24894>