Alyssa Rosenzweig [Wed, 18 Mar 2020 13:58:59 +0000 (09:58 -0400)]
pan/bi: Pack BI_FMA ops
This is our first instruction we've emitted, requiring us to pipe
through registes/ports and various details from the IR. It's quite a bit
of code, but overall I'm happy with this structure. With some tedium we
should be able to emit the rest of the ALU ops this way, too.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
Alyssa Rosenzweig [Wed, 18 Mar 2020 13:58:42 +0000 (09:58 -0400)]
pan/bi: Add struct bifrost_fma_fma
So we can pack regular FMA ops.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
Alyssa Rosenzweig [Wed, 18 Mar 2020 13:57:32 +0000 (09:57 -0400)]
pan/bi: Model 3-bit Bifrost srcs in IR
We'll want to set these manually for schedule-time passthrough, as well
as use the enum for packing.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
Alyssa Rosenzweig [Wed, 18 Mar 2020 13:22:58 +0000 (09:22 -0400)]
pan/bi: Route through first_instruction field
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
Alyssa Rosenzweig [Wed, 18 Mar 2020 03:01:48 +0000 (23:01 -0400)]
pan/bi: Assign registers to ports
Now that we can pack registers given the assigned ports, and we can
assign registers from the indices, the missing link is assigning ports
from the registers, and now finally we get some real data showing up in
a disassembly exercising lots of different code paths.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
Alyssa Rosenzweig [Wed, 18 Mar 2020 02:42:54 +0000 (22:42 -0400)]
pan/bi: Add missing __attribute__((packed))
That this code worked before makes me rather nervous...
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
Alyssa Rosenzweig [Wed, 18 Mar 2020 02:17:39 +0000 (22:17 -0400)]
pan/bi: Pack register fields
Now that we have ctrl, the rest is natural... sorta.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
Alyssa Rosenzweig [Wed, 18 Mar 2020 01:35:44 +0000 (21:35 -0400)]
pan/bi: Add packing for register control field
Filling in some gaps based on intuition from the bit patterns but this
should be vaguely right. More investigation needed down the line.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
Alyssa Rosenzweig [Thu, 12 Mar 2020 18:33:32 +0000 (14:33 -0400)]
pan/bi: Sketch out instruction word packing
Instructions are 78-bits with some seriously suspicious packing
requirements but hey, gotta save 'em bits.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
Alyssa Rosenzweig [Thu, 12 Mar 2020 18:16:22 +0000 (14:16 -0400)]
pan/bi: Setup initial clause packing
At the moment, we just iterate the clauses in the post-RA, post-sched IR
and generate a dummy clause corresponding, passing the results to the
disassembler to verify.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4242>
Dylan Baker [Wed, 18 Mar 2020 21:48:40 +0000 (14:48 -0700)]
docs: update calendar, add news item, and link releases notes for 20.0.2
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4236>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4236>
Dylan Baker [Wed, 18 Mar 2020 21:40:36 +0000 (14:40 -0700)]
docs/relnotes: Add sha256 sums for 20.0.2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4236>
Dylan Baker [Wed, 18 Mar 2020 21:22:17 +0000 (14:22 -0700)]
Docs: Add release notes for 20.0.2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4236>
Eric Anholt [Wed, 18 Mar 2020 17:37:13 +0000 (10:37 -0700)]
ci: Disable tests that showed intermittent fails on a530 in day 1.
Link: https://gitlab.freedesktop.org/mesa/mesa/issues/2649
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4231>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4231>
Eric Anholt [Wed, 18 Mar 2020 17:35:17 +0000 (10:35 -0700)]
ci: Ban the recent popular freedreno a630 flakes.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4231>
Samuel Pitoiset [Wed, 18 Mar 2020 14:03:45 +0000 (15:03 +0100)]
radv: remove wrong assert that checks compute subgroup size
Ooops. For some reasons, I have been confused with Wave32 on GFX10,
but it's still possible to require a specific subgroup size if
only Wave64 is supported.
Fixes:
672d1061998 ("radv/gfx10: fix required subgroup size with VK_EXT_subgroup_size_control")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4227>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4227>
Jason Ekstrand [Tue, 17 Mar 2020 18:12:35 +0000 (13:12 -0500)]
anv: Swizzle fast-clear values
Starting with Gen12, we can fast-clear a lot more surface formats and we
are suddenly in the position of having to fast-clear surfaces with
formats with an implicit swizzle such as VK_FORMAT_R4G4B4A4_UNORM_PACK16
which is represented as ISL_FORMAT_A4B4G4R4 with a BGRA swizzle. In
order for blorp to do the fast-clear color conversion for us, it needs
a properly swizzled color.
This fixes the following Vulkan CTS groups on TGL:
- dEQP-VK.pipeline.blend.format.b4g4r4a4_unorm_pack16.*
- dEQP-VK.api.image_clearing.core.clear_color_image.*.b4g4r4a4*
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4218>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4218>
Jason Ekstrand [Tue, 17 Mar 2020 18:36:40 +0000 (13:36 -0500)]
intel/blorp: Add support for swizzling fast-clear colors
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4218>
Ian Romanick [Thu, 5 Mar 2020 07:00:24 +0000 (23:00 -0800)]
soft-fp64: Split a block that was missing a cast on a comparison
This function has code like:
if (0x7FD <= zExp) {
if ((0x7FD < zExp) ||
((zExp == 0x7FD) &&
(0x001FFFFFu == zFrac0 && 0xFFFFFFFFu == zFrac1) &&
increment)) {
...
return ...;
}
if (zExp < 0) {
I saw that, and I thought, "Uh... what? Dead code?" I thought it was a
bit fishy, so I grabbed the Berkeley SoftFloat Library 3e code, and
there is similar code in softfloat_roundPackToF64
(source/s_roundPackToF64.c), but it has an extra (uint16_t) cast in the
first comparison. This is basicially a shortcut for
if (zExp < 0 || zExp >= 0x7FD) {
So, having the nesting kind of makes sense. On a CPU, nesting the flow
control can be an optimization. On a GPU, it's just fail. Split the
block so that we don't need the uint16_t cast magic.
Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:
Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 683638 -> 658127 (-3.73%)
instructions in affected programs: 666839 -> 641328 (-3.83%)
helped: 92
HURT: 0
helped stats (abs) min: 26 max: 2456 x̄: 277.29 x̃: 144
helped stats (rel) min: 3.21% max: 4.22% x̄: 3.79% x̃: 3.90%
95% mean confidence interval for instructions value: -345.84 -208.75
95% mean confidence interval for instructions %-change: -3.86% -3.73%
Instructions are helped.
total cycles in shared programs: 5458858 -> 5344600 (-2.09%)
cycles in affected programs: 5360114 -> 5245856 (-2.13%)
helped: 92
HURT: 0
helped stats (abs) min: 126 max: 10300 x̄: 1241.93 x̃: 655
helped stats (rel) min: 1.71% max: 2.37% x̄: 2.12% x̃: 2.17%
95% mean confidence interval for cycles value: -1539.93 -943.94
95% mean confidence interval for cycles %-change: -2.16% -2.08%
Cycles are helped.
Fixes:
f111d72596c ("glsl: Add "built-in" functions to do add(fp64, fp64)")
Reviewed-by: Matt Turner <mattst88@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
Ian Romanick [Wed, 4 Mar 2020 21:00:44 +0000 (13:00 -0800)]
soft-fp64/fadd: Common code optimization for differing sign case
This is basically the same ideas from the previous 4 commits applied
to the aSign != bSign part... and all smashed into one commit.
The shader hurt for spill and / or fills is from
KHR-GL46.gpu_shader_fp64.builtin.inverse_dmat4.
Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:
Tiger Lake
total instructions in shared programs: 787258 -> 683638 (-13.16%)
instructions in affected programs: 725435 -> 621815 (-14.28%)
helped: 74
HURT: 0
helped stats (abs) min: 152 max: 10261 x̄: 1400.27 x̃: 975
helped stats (rel) min: 11.61% max: 20.92% x̄: 15.40% x̃: 14.86%
95% mean confidence interval for instructions value: -1740.11 -1060.43
95% mean confidence interval for instructions %-change: -16.01% -14.79%
Instructions are helped.
total cycles in shared programs: 6483227 -> 5458858 (-15.80%)
cycles in affected programs: 6051245 -> 5026876 (-16.93%)
helped: 74
HURT: 0
helped stats (abs) min: 1566 max: 95474 x̄: 13842.82 x̃: 9757
helped stats (rel) min: 13.94% max: 23.26% x̄: 17.98% x̃: 17.57%
95% mean confidence interval for cycles value: -17104.25 -10581.40
95% mean confidence interval for cycles %-change: -18.61% -17.35%
Cycles are helped.
total spills in shared programs: 553 -> 445 (-19.53%)
spills in affected programs: 553 -> 445 (-19.53%)
helped: 1
HURT: 0
total fills in shared programs: 1307 -> 1323 (1.22%)
fills in affected programs: 1307 -> 1323 (1.22%)
helped: 0
HURT: 1
Ice Lake
total instructions in shared programs: 781216 -> 678470 (-13.15%)
instructions in affected programs: 720088 -> 617342 (-14.27%)
helped: 74
HURT: 0
helped stats (abs) min: 153 max: 8863 x̄: 1388.46 x̃: 975
helped stats (rel) min: 11.24% max: 21.03% x̄: 15.47% x̃: 15.01%
95% mean confidence interval for instructions value: -1703.57 -1073.35
95% mean confidence interval for instructions %-change: -16.09% -14.85%
Instructions are helped.
total cycles in shared programs: 6464085 -> 5453997 (-15.63%)
cycles in affected programs: 6031771 -> 5021683 (-16.75%)
helped: 74
HURT: 0
helped stats (abs) min: 1552 max: 90317 x̄: 13649.84 x̃: 9650
helped stats (rel) min: 13.84% max: 23.11% x̄: 17.83% x̃: 17.41%
95% mean confidence interval for cycles value: -16802.89 -10496.79
95% mean confidence interval for cycles %-change: -18.46% -17.21%
Cycles are helped.
total spills in shared programs: 279 -> 368 (31.90%)
spills in affected programs: 279 -> 368 (31.90%)
helped: 0
HURT: 1
total fills in shared programs: 973 -> 1155 (18.71%)
fills in affected programs: 973 -> 1155 (18.71%)
helped: 0
HURT: 1
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
Ian Romanick [Wed, 4 Mar 2020 20:39:36 +0000 (12:39 -0800)]
soft-fp64/fadd: Move common code out of both branches of an if-statement
The previous two commits were just setting the scene for this change.
The mix(..., __propagateFloat64NaN(a, b), propagate) statements are not
identical in the two halves, but they are equivalent. The first clause
of the mix in the else-branch is trivally ±Inf. The first clause in the
then-branch __packFloat64(aSign, aExp, aFracHi, aFracLo). The
preceeding conditions prove that aExp=0x7ff, aFracHi=0, and aFracLo=0.
Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:
Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 819560 -> 787258 (-3.94%)
instructions in affected programs: 757737 -> 725435 (-4.26%)
helped: 74
HURT: 0
helped stats (abs) min: 43 max: 3545 x̄: 436.51 x̃: 296
helped stats (rel) min: 3.54% max: 6.16% x̄: 4.52% x̃: 4.36%
95% mean confidence interval for instructions value: -548.42 -324.61
95% mean confidence interval for instructions %-change: -4.68% -4.37%
Instructions are helped.
total cycles in shared programs: 6817254 -> 6483227 (-4.90%)
cycles in affected programs: 6385272 -> 6051245 (-5.23%)
helped: 74
HURT: 0
helped stats (abs) min: 430 max: 33271 x̄: 4513.88 x̃: 3047
helped stats (rel) min: 4.28% max: 7.45% x̄: 5.48% x̃: 5.31%
95% mean confidence interval for cycles value: -5610.46 -3417.30
95% mean confidence interval for cycles %-change: -5.65% -5.32%
Cycles are helped.
total spills in shared programs: 591 -> 553 (-6.43%)
spills in affected programs: 591 -> 553 (-6.43%)
helped: 1
HURT: 0
total fills in shared programs: 1353 -> 1307 (-3.40%)
fills in affected programs: 1353 -> 1307 (-3.40%)
helped: 1
HURT: 0
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
Ian Romanick [Wed, 4 Mar 2020 20:31:02 +0000 (12:31 -0800)]
soft-fp64/fadd: Use absolute value of expDiff
In one branch we know that expDiff is already positive.
In the other branch we know the expDiff is negative. Previously in that
branch the code was -(expDiff + 1). This is equvialent to (-expDiff) -
1, and since expDiff is negative, abs(expDiff) - 1.
The main purpose of this commit is to prepare for "soft-fp64/fadd: Move
common code out of both branches of an if-statement".
Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:
Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 818246 -> 819560 (0.16%)
instructions in affected programs: 756423 -> 757737 (0.17%)
helped: 1
HURT: 73
helped stats (abs) min: 1205 max: 1205 x̄: 1205.00 x̃: 1205
helped stats (rel) min: 1.36% max: 1.36% x̄: 1.36% x̃: 1.36%
HURT stats (abs) min: 2 max: 149 x̄: 34.51 x̃: 27
HURT stats (rel) min: 0.14% max: 1.09% x̄: 0.41% x̃: 0.30%
95% mean confidence interval for instructions value: -16.56 52.07
95% mean confidence interval for instructions %-change: 0.30% 0.47%
Inconclusive result (value mean confidence interval includes 0).
total cycles in shared programs: 6816686 -> 6817254 (<.01%)
cycles in affected programs: 6384704 -> 6385272 (<.01%)
helped: 37
HURT: 37
helped stats (abs) min: 30 max: 5790 x̄: 289.05 x̃: 102
helped stats (rel) min: 0.04% max: 0.86% x̄: 0.29% x̃: 0.31%
HURT stats (abs) min: 2 max: 1020 x̄: 304.41 x̃: 232
HURT stats (rel) min: <.01% max: 1.58% x̄: 0.55% x̃: 0.43%
95% mean confidence interval for cycles value: -165.37 180.72
95% mean confidence interval for cycles %-change: <.01% 0.27%
Inconclusive result (value mean confidence interval includes 0).
total spills in shared programs: 705 -> 591 (-16.17%)
spills in affected programs: 705 -> 591 (-16.17%)
helped: 1
HURT: 0
total fills in shared programs: 1501 -> 1353 (-9.86%)
fills in affected programs: 1501 -> 1353 (-9.86%)
helped: 1
HURT: 0
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
Ian Romanick [Wed, 4 Mar 2020 20:23:13 +0000 (12:23 -0800)]
soft-fp64/fadd: Rename aFrac and bFrac variables
Exchanging aFracHi / bFracHi and aFracLo / bFracLo should not affect the
result of the later call to __add64.
The main purpose of this commit is to prepare for "soft-fp64/fadd: Move
common code out of both branches of an if-statement".
v2: Fix a typo in a comment. Noticed by Matt.
Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:
Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 812094 -> 818246 (0.76%)
instructions in affected programs: 750271 -> 756423 (0.82%)
helped: 0
HURT: 74
HURT stats (abs) min: 7 max: 520 x̄: 83.14 x̃: 59
HURT stats (rel) min: 0.52% max: 1.48% x̄: 0.89% x̃: 0.84%
95% mean confidence interval for instructions value: 63.96 102.31
95% mean confidence interval for instructions %-change: 0.83% 0.95%
Instructions are HURT.
total cycles in shared programs: 6797157 -> 6816686 (0.29%)
cycles in affected programs: 6365175 -> 6384704 (0.31%)
helped: 0
HURT: 74
HURT stats (abs) min: 16 max: 1690 x̄: 263.91 x̃: 181
HURT stats (rel) min: 0.14% max: 0.68% x̄: 0.32% x̃: 0.27%
95% mean confidence interval for cycles value: 199.74 328.07
95% mean confidence interval for cycles %-change: 0.29% 0.36%
Cycles are HURT.
total spills in shared programs: 703 -> 705 (0.28%)
spills in affected programs: 703 -> 705 (0.28%)
helped: 0
HURT: 1
total fills in shared programs: 1499 -> 1501 (0.13%)
fills in affected programs: 1499 -> 1501 (0.13%)
helped: 0
HURT: 1
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
Ian Romanick [Wed, 4 Mar 2020 20:13:32 +0000 (12:13 -0800)]
soft-fp64/fadd: Combine an if-statement into the preceeding else-clause
The main purpose of this commit is to prepare for "soft-fp64/fadd: Move
common code out of both branches of an if-statement".
Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:
Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 812590 -> 812094 (-0.06%)
instructions in affected programs: 672135 -> 671639 (-0.07%)
helped: 57
HURT: 0
helped stats (abs) min: 1 max: 32 x̄: 8.70 x̃: 7
helped stats (rel) min: <.01% max: 0.49% x̄: 0.12% x̃: 0.09%
95% mean confidence interval for instructions value: -10.46 -6.94
95% mean confidence interval for instructions %-change: -0.15% -0.09%
Instructions are helped.
total cycles in shared programs: 6798039 -> 6797157 (-0.01%)
cycles in affected programs: 5810059 -> 5809177 (-0.02%)
helped: 54
HURT: 2
helped stats (abs) min: 2 max: 68 x̄: 16.44 x̃: 12
helped stats (rel) min: <.01% max: 0.12% x̄: 0.03% x̃: 0.02%
HURT stats (abs) min: 2 max: 4 x̄: 3.00 x̃: 3
HURT stats (rel) min: <.01% max: <.01% x̄: <.01% x̃: <.01%
95% mean confidence interval for cycles value: -19.50 -12.00
95% mean confidence interval for cycles %-change: -0.03% -0.02%
Cycles are helped.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
Ian Romanick [Wed, 4 Mar 2020 20:09:58 +0000 (12:09 -0800)]
soft-fp64/fadd: Reformat after previous commit
Convert
} else if (...) {
...
} else {
...
}
to
} else {
if (...) {
...
} else {
...
}
}
Not doing this reformatting in the previous commit makes the previous
commit easier to review, and doing it before the next commit makes the
next commit easier to review.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
Ian Romanick [Wed, 4 Mar 2020 20:05:06 +0000 (12:05 -0800)]
soft-fp64/fadd: Delete a redundant condition check
Previous condition checks already guaranteen that expDiff != 0 and
!(expDiff > 0), so expDiff < 0 is the only option left.
The main purpose of this commit is to prepare for "soft-fp64/fadd: Move
common code out of both branches of an if-statement".
Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:
Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 815491 -> 812590 (-0.36%)
instructions in affected programs: 753668 -> 750767 (-0.38%)
helped: 74
HURT: 0
helped stats (abs) min: 3 max: 281 x̄: 39.20 x̃: 25
helped stats (rel) min: 0.29% max: 0.73% x̄: 0.42% x̃: 0.40%
95% mean confidence interval for instructions value: -48.50 -29.91
95% mean confidence interval for instructions %-change: -0.45% -0.40%
Instructions are helped.
total cycles in shared programs: 6813681 -> 6798039 (-0.23%)
cycles in affected programs: 6381699 -> 6366057 (-0.25%)
helped: 74
HURT: 0
helped stats (abs) min: 24 max: 1488 x̄: 211.38 x̃: 149
helped stats (rel) min: 0.20% max: 0.44% x̄: 0.26% x̃: 0.25%
95% mean confidence interval for cycles value: -261.68 -161.08
95% mean confidence interval for cycles %-change: -0.28% -0.25%
Cycles are helped.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
Ian Romanick [Wed, 4 Mar 2020 03:51:16 +0000 (19:51 -0800)]
soft-fp64/fadd: Just let the subtraction happen when the result will be zero
The main purpose of this commit is to prepare for "soft-fp64/fadd: Move
common code out of both branches of an if-statement".
Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:
Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 815717 -> 815491 (-0.03%)
instructions in affected programs: 735489 -> 735263 (-0.03%)
helped: 39
HURT: 34
helped stats (abs) min: 2 max: 192 x̄: 20.79 x̃: 12
helped stats (rel) min: 0.01% max: 0.46% x̄: 0.26% x̃: 0.28%
HURT stats (abs) min: 1 max: 65 x̄: 17.21 x̃: 11
HURT stats (rel) min: <.01% max: 1.11% x̄: 0.35% x̃: 0.19%
95% mean confidence interval for instructions value: -10.40 4.21
95% mean confidence interval for instructions %-change: -0.07% 0.13%
Inconclusive result (value mean confidence interval includes 0).
total cycles in shared programs: 6820707 -> 6813681 (-0.10%)
cycles in affected programs: 6388725 -> 6381699 (-0.11%)
helped: 51
HURT: 23
helped stats (abs) min: 3 max: 1837 x̄: 184.76 x̃: 120
helped stats (rel) min: <.01% max: 0.48% x̄: 0.25% x̃: 0.25%
HURT stats (abs) min: 18 max: 216 x̄: 104.22 x̃: 98
HURT stats (rel) min: 0.06% max: 0.73% x̄: 0.31% x̃: 0.11%
95% mean confidence interval for cycles value: -154.67 -35.22
95% mean confidence interval for cycles %-change: -0.15% <.01%
Inconclusive result (%-change mean confidence interval includes 0).
total spills in shared programs: 702 -> 703 (0.14%)
spills in affected programs: 702 -> 703 (0.14%)
helped: 0
HURT: 1
total fills in shared programs: 1497 -> 1499 (0.13%)
fills in affected programs: 1497 -> 1499 (0.13%)
helped: 0
HURT: 1
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
Ian Romanick [Wed, 4 Mar 2020 03:49:13 +0000 (19:49 -0800)]
soft-fp64/fadd: Pick zero or non-zero result based on subtraction result
The main purpose of this commit is to prepare for "soft-fp64/fadd: Move
common code out of both branches of an if-statement".
Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:
Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 817327 -> 815717 (-0.20%)
instructions in affected programs: 755504 -> 753894 (-0.21%)
helped: 73
HURT: 1
helped stats (abs) min: 1 max: 159 x̄: 22.12 x̃: 14
helped stats (rel) min: 0.05% max: 0.40% x̄: 0.22% x̃: 0.23%
HURT stats (abs) min: 5 max: 5 x̄: 5.00 x̃: 5
HURT stats (rel) min: 0.07% max: 0.07% x̄: 0.07% x̃: 0.07%
95% mean confidence interval for instructions value: -27.27 -16.24
95% mean confidence interval for instructions %-change: -0.24% -0.20%
Instructions are helped.
total cycles in shared programs: 6822826 -> 6820707 (-0.03%)
cycles in affected programs: 6390844 -> 6388725 (-0.03%)
helped: 71
HURT: 3
helped stats (abs) min: 2 max: 537 x̄: 30.72 x̃: 18
helped stats (rel) min: <.01% max: 0.08% x̄: 0.03% x̃: 0.03%
HURT stats (abs) min: 10 max: 32 x̄: 20.67 x̃: 20
HURT stats (rel) min: 0.01% max: 0.02% x̄: 0.02% x̃: 0.02%
95% mean confidence interval for cycles value: -43.41 -13.86
95% mean confidence interval for cycles %-change: -0.04% -0.03%
Cycles are helped.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
Ian Romanick [Wed, 4 Mar 2020 03:44:13 +0000 (19:44 -0800)]
soft-fp64/fadd: Massively split the live range of zFrac0 and zFrac1
The main purpose of this commit is to prepare for "soft-fp64/fadd: Move
common code out of both branches of an if-statement".
Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:
Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 822766 -> 817327 (-0.66%)
instructions in affected programs: 760943 -> 755504 (-0.71%)
helped: 74
HURT: 0
helped stats (abs) min: 8 max: 515 x̄: 73.50 x̃: 51
helped stats (rel) min: 0.58% max: 1.10% x̄: 0.77% x̃: 0.73%
95% mean confidence interval for instructions value: -91.17 -55.83
95% mean confidence interval for instructions %-change: -0.81% -0.74%
Instructions are helped.
total cycles in shared programs: 6816791 -> 6822826 (0.09%)
cycles in affected programs: 6384809 -> 6390844 (0.09%)
helped: 0
HURT: 74
HURT stats (abs) min: 6 max: 1179 x̄: 81.55 x̃: 50
HURT stats (rel) min: 0.02% max: 0.17% x̄: 0.09% x̃: 0.09%
95% mean confidence interval for cycles value: 48.99 114.12
95% mean confidence interval for cycles %-change: 0.09% 0.10%
Cycles are HURT.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
Ian Romanick [Wed, 4 Mar 2020 03:38:13 +0000 (19:38 -0800)]
soft-fp64/fadd: Instead of tracking "b < a", track sign of the difference
Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:
Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 824403 -> 822766 (-0.20%)
instructions in affected programs: 756260 -> 754623 (-0.22%)
helped: 68
HURT: 1
helped stats (abs) min: 1 max: 118 x̄: 26.26 x̃: 18
helped stats (rel) min: 0.02% max: 0.97% x̄: 0.31% x̃: 0.23%
HURT stats (abs) min: 149 max: 149 x̄: 149.00 x̃: 149
HURT stats (rel) min: 0.17% max: 0.17% x̄: 0.17% x̃: 0.17%
95% mean confidence interval for instructions value: -31.94 -15.51
95% mean confidence interval for instructions %-change: -0.37% -0.23%
Instructions are helped.
total cycles in shared programs: 6828935 -> 6816791 (-0.18%)
cycles in affected programs: 6385191 -> 6373047 (-0.19%)
helped: 73
HURT: 0
helped stats (abs) min: 2 max: 852 x̄: 166.36 x̃: 120
helped stats (rel) min: <.01% max: 0.80% x̄: 0.22% x̃: 0.17%
95% mean confidence interval for cycles value: -210.80 -121.91
95% mean confidence interval for cycles %-change: -0.27% -0.17%
Cycles are helped.
total fills in shared programs: 1442 -> 1497 (3.81%)
fills in affected programs: 1442 -> 1497 (3.81%)
helped: 0
HURT: 1
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
Ian Romanick [Tue, 3 Mar 2020 18:21:18 +0000 (10:21 -0800)]
soft-fp64: Optimize __fmin64 and __fmax64 by using different evaluation order [v2]
v2: Go to extra effort to avoid flow control inserted to implement
short-circuit evaluation rules.
Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:
Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 797779 -> 796849 (-0.12%)
instructions in affected programs: 3499 -> 2569 (-26.58%)
helped: 21
HURT: 0
helped stats (abs) min: 8 max: 112 x̄: 44.29 x̃: 44
helped stats (rel) min: 16.09% max: 33.15% x̄: 25.72% x̃: 24.62%
95% mean confidence interval for instructions value: -55.94 -32.63
95% mean confidence interval for instructions %-change: -28.14% -23.30%
Instructions are helped.
total cycles in shared programs: 6601355 -> 6588351 (-0.20%)
cycles in affected programs: 25376 -> 12372 (-51.25%)
helped: 21
HURT: 0
helped stats (abs) min: 156 max: 1410 x̄: 619.24 x̃: 526
helped stats (rel) min: 42.39% max: 53.98% x̄: 50.12% x̃: 50.75%
95% mean confidence interval for cycles value: -776.58 -461.89
95% mean confidence interval for cycles %-change: -51.57% -48.67%
Cycles are helped.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> [v1]
Reviewed-by: Matt Turner <mattst88@gmail.com> [v1]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
Ian Romanick [Wed, 4 Mar 2020 22:21:02 +0000 (14:21 -0800)]
soft-fp64/ffloor: Simplify the >= 0 comparison
Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:
Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 797951 -> 797779 (-0.02%)
instructions in affected programs: 126482 -> 126310 (-0.14%)
helped: 15
HURT: 0
helped stats (abs) min: 1 max: 20 x̄: 11.47 x̃: 10
helped stats (rel) min: <.01% max: 0.60% x̄: 0.28% x̃: 0.29%
95% mean confidence interval for instructions value: -14.79 -8.14
95% mean confidence interval for instructions %-change: -0.40% -0.16%
Instructions are helped.
total cycles in shared programs: 6601437 -> 6601355 (<.01%)
cycles in affected programs: 1089336 -> 1089254 (<.01%)
helped: 15
HURT: 0
helped stats (abs) min: 2 max: 12 x̄: 5.47 x̃: 6
helped stats (rel) min: <.01% max: 0.04% x̄: 0.01% x̃: 0.01%
95% mean confidence interval for cycles value: -7.06 -3.87
95% mean confidence interval for cycles %-change: -0.02% <.01%
Cycles are helped.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
Ian Romanick [Tue, 3 Mar 2020 03:20:42 +0000 (19:20 -0800)]
soft-fp64: Relax the way NaN is propagated
Also reassociate a couple expressions to encourage some CSE.
Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:
Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 813599 -> 797951 (-1.92%)
instructions in affected programs: 796110 -> 780462 (-1.97%)
helped: 92
HURT: 0
helped stats (abs) min: 3 max: 5198 x̄: 170.09 x̃: 83
helped stats (rel) min: 0.36% max: 5.50% x̄: 1.57% x̃: 1.40%
95% mean confidence interval for instructions value: -282.42 -57.75
95% mean confidence interval for instructions %-change: -1.71% -1.42%
Instructions are helped.
total cycles in shared programs: 6687128 -> 6601437 (-1.28%)
cycles in affected programs: 6582246 -> 6496555 (-1.30%)
helped: 92
HURT: 0
helped stats (abs) min: 36 max: 14442 x̄: 931.42 x̃: 592
helped stats (rel) min: 0.45% max: 3.16% x̄: 1.44% x̃: 1.23%
95% mean confidence interval for cycles value: -1257.58 -605.27
95% mean confidence interval for cycles %-change: -1.58% -1.30%
Cycles are helped.
total spills in shared programs: 759 -> 702 (-7.51%)
spills in affected programs: 759 -> 702 (-7.51%)
helped: 3
HURT: 0
total fills in shared programs: 2412 -> 1442 (-40.22%)
fills in affected programs: 2412 -> 1442 (-40.22%)
helped: 3
HURT: 0
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
Ian Romanick [Tue, 3 Mar 2020 02:50:44 +0000 (18:50 -0800)]
soft-fp64/fsat: Micro-optimize x >= 1 test
Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:
Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 841590 -> 841332 (-0.03%)
instructions in affected programs: 121957 -> 121699 (-0.21%)
helped: 7
HURT: 0
helped stats (abs) min: 15 max: 54 x̄: 36.86 x̃: 41
helped stats (rel) min: 0.16% max: 0.33% x̄: 0.23% x̃: 0.18%
95% mean confidence interval for instructions value: -49.73 -23.98
95% mean confidence interval for instructions %-change: -0.29% -0.16%
Instructions are helped.
total cycles in shared programs: 6926828 -> 6923967 (-0.04%)
cycles in affected programs: 1038569 -> 1035708 (-0.28%)
helped: 7
HURT: 0
helped stats (abs) min: 128 max: 616 x̄: 408.71 x̃: 446
helped stats (rel) min: 0.18% max: 0.44% x̄: 0.29% x̃: 0.22%
95% mean confidence interval for cycles value: -571.72 -245.70
95% mean confidence interval for cycles %-change: -0.38% -0.19%
Cycles are helped.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
Ian Romanick [Tue, 3 Mar 2020 02:42:04 +0000 (18:42 -0800)]
soft-fp64/fsat: Micro-optimize x < 0 test
Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:
Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 841647 -> 841590 (<.01%)
instructions in affected programs: 122014 -> 121957 (-0.05%)
helped: 7
HURT: 0
helped stats (abs) min: 3 max: 12 x̄: 8.14 x̃: 9
helped stats (rel) min: 0.04% max: 0.07% x̄: 0.05% x̃: 0.04%
95% mean confidence interval for instructions value: -11.23 -5.06
95% mean confidence interval for instructions %-change: -0.06% -0.03%
Instructions are helped.
total cycles in shared programs: 6926904 -> 6926828 (<.01%)
cycles in affected programs: 1038645 -> 1038569 (<.01%)
helped: 7
HURT: 0
helped stats (abs) min: 4 max: 16 x̄: 10.86 x̃: 12
helped stats (rel) min: <.01% max: 0.01% x̄: <.01% x̃: <.01%
95% mean confidence interval for cycles value: -14.97 -6.74
95% mean confidence interval for cycles %-change: -0.01% <.01%
Cycles are helped.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
Ian Romanick [Tue, 3 Mar 2020 02:38:11 +0000 (18:38 -0800)]
soft-fp64/fsat: Correctly handle NaN
fsat is defined as min(max(a, 0.0), 1.0), and IEEE defines both min and
max to return the non-NaN value when one value is NaN. Based on this,
fsat should definitely return 0.0 for NaN.
Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:
Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 841666 -> 841647 (<.01%)
instructions in affected programs: 122033 -> 122014 (-0.02%)
helped: 7
HURT: 0
helped stats (abs) min: 1 max: 4 x̄: 2.71 x̃: 3
helped stats (rel) min: 0.01% max: 0.02% x̄: 0.02% x̃: 0.01%
95% mean confidence interval for instructions value: -3.74 -1.69
95% mean confidence interval for instructions %-change: -0.02% -0.01%
Instructions are helped.
total cycles in shared programs: 6927246 -> 6926904 (<.01%)
cycles in affected programs: 1038987 -> 1038645 (-0.03%)
helped: 7
HURT: 0
helped stats (abs) min: 18 max: 72 x̄: 48.86 x̃: 54
helped stats (rel) min: 0.03% max: 0.05% x̄: 0.03% x̃: 0.03%
95% mean confidence interval for cycles value: -67.38 -30.33
95% mean confidence interval for cycles %-change: -0.05% -0.02%
Cycles are helped.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Fixes:
a42163cbbc1 ("compiler: Add lowering support for 64-bit saturate operations to software")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2585
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
Ian Romanick [Tue, 3 Mar 2020 02:57:44 +0000 (18:57 -0800)]
soft-fp64/flt: Perform checks in a different order
The change to nir_opt_algebraic cleans up a pattern that was never
produced before the rest of this commit was added.
Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:
Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 843005 -> 841666 (-0.16%)
instructions in affected programs: 460655 -> 459316 (-0.29%)
helped: 64
HURT: 17
helped stats (abs) min: 1 max: 72 x̄: 21.72 x̃: 20
helped stats (rel) min: 0.01% max: 28.07% x̄: 12.67% x̃: 16.07%
HURT stats (abs) min: 1 max: 7 x̄: 3.00 x̃: 2
HURT stats (rel) min: 0.01% max: 0.04% x̄: 0.02% x̃: 0.02%
95% mean confidence interval for instructions value: -20.87 -12.19
95% mean confidence interval for instructions %-change: -12.35% -7.66%
Instructions are helped.
total cycles in shared programs: 6944998 -> 6927246 (-0.26%)
cycles in affected programs: 3891872 -> 3874120 (-0.46%)
helped: 71
HURT: 10
helped stats (abs) min: 2 max: 772 x̄: 254.21 x̃: 156
helped stats (rel) min: <.01% max: 66.44% x̄: 21.72% x̃: 18.40%
HURT stats (abs) min: 18 max: 69 x̄: 29.70 x̃: 20
HURT stats (rel) min: 0.02% max: 0.04% x̄: 0.03% x̃: 0.03%
95% mean confidence interval for cycles value: -270.82 -167.50
95% mean confidence interval for cycles %-change: -24.41% -13.65%
Cycles are helped.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
Ian Romanick [Tue, 3 Mar 2020 02:31:01 +0000 (18:31 -0800)]
soft-fp64/fneg: Don't treat NaN specially
__fabs64 doesn't do anything special, and the value is still NaN
regardless of the value of the MSB. In a strict sense, it's possible
that both functions should set the "signal" bit.
lts on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:
Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 844558 -> 843005 (-0.18%)
instructions in affected programs: 725975 -> 724422 (-0.21%)
helped: 53
HURT: 4
helped stats (abs) min: 1 max: 313 x̄: 29.87 x̃: 21
helped stats (rel) min: 0.01% max: 0.94% x̄: 0.30% x̃: 0.22%
HURT stats (abs) min: 4 max: 11 x̄: 7.50 x̃: 7
HURT stats (rel) min: 0.03% max: 0.09% x̄: 0.05% x̃: 0.04%
95% mean confidence interval for instructions value: -39.02 -15.47
95% mean confidence interval for instructions %-change: -0.34% -0.21%
Instructions are helped.
total cycles in shared programs: 6962024 -> 6944998 (-0.24%)
cycles in affected programs: 6185470 -> 6168444 (-0.28%)
helped: 59
HURT: 0
helped stats (abs) min: 64 max: 2863 x̄: 288.58 x̃: 208
helped stats (rel) min: 0.11% max: 0.87% x̄: 0.33% x̃: 0.27%
95% mean confidence interval for cycles value: -387.15 -190.00
95% mean confidence interval for cycles %-change: -0.38% -0.28%
Cycles are helped.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
Ian Romanick [Tue, 3 Mar 2020 00:37:58 +0000 (16:37 -0800)]
soft-fp64: Store sign value as 0 or 0x80000000
...instead of 0 or 1. Many places the sign bit is extracted, then later
put back in the same position. This saves some left-shift operations.
Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:
Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 848106 -> 844558 (-0.42%)
instructions in affected programs: 833480 -> 829932 (-0.43%)
helped: 106
HURT: 1
helped stats (abs) min: 1 max: 995 x̄: 33.48 x̃: 12
helped stats (rel) min: 0.15% max: 2.20% x̄: 0.60% x̃: 0.35%
HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel) min: <.01% max: <.01% x̄: <.01% x̃: <.01%
95% mean confidence interval for instructions value: -51.88 -14.43
95% mean confidence interval for instructions %-change: -0.71% -0.47%
Instructions are helped.
total cycles in shared programs: 6969125 -> 6962024 (-0.10%)
cycles in affected programs: 6717689 -> 6710588 (-0.11%)
helped: 78
HURT: 7
helped stats (abs) min: 2 max: 2083 x̄: 110.27 x̃: 56
helped stats (rel) min: <.01% max: 0.30% x̄: 0.11% x̃: 0.11%
HURT stats (abs) min: 2 max: 1340 x̄: 214.29 x̃: 4
HURT stats (rel) min: 0.01% max: 0.71% x̄: 0.13% x̃: 0.02%
95% mean confidence interval for cycles value: -144.02 -23.06
95% mean confidence interval for cycles %-change: -0.12% -0.07%
Cycles are helped.
total spills in shared programs: 814 -> 759 (-6.76%)
spills in affected programs: 814 -> 759 (-6.76%)
helped: 2
HURT: 1
total fills in shared programs: 2488 -> 2412 (-3.05%)
fills in affected programs: 2488 -> 2412 (-3.05%)
helped: 2
HURT: 1
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
Ian Romanick [Tue, 3 Mar 2020 00:33:16 +0000 (16:33 -0800)]
soft-fp64: Pick a single idiom for treating sign value as a Boolean
Replace all of the bool(qSign) with qSign != 0u. Remove unnecessary
parenthesis from around most of the existing qSign != 0u.
This dramatically simplifies the next commit.
Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:
Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 848109 -> 848106 (<.01%)
instructions in affected programs: 53 -> 50 (-5.66%)
helped: 1
HURT: 0
total cycles in shared programs: 6969145 -> 6969125 (<.01%)
cycles in affected programs: 396 -> 376 (-5.05%)
helped: 1
HURT: 0
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
Ian Romanick [Tue, 3 Mar 2020 00:43:11 +0000 (16:43 -0800)]
soft-fp64: Simplify __countLeadingZeros32 function
findMSB returns -1 for an input of zero, so 31 - findMSB(a) is
sufficient on its own.
There's only one user of findMSB in shader-db, and it does not match
this pattern.
TODO: Add a pattern in the backend code generator that emits 31 -
nir_op_ufind_msb(a) as if it were nir_op_uclz. That should save a couple
instructions.
Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:
Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 859509 -> 848109 (-1.33%)
instructions in affected programs: 841058 -> 829658 (-1.36%)
helped: 97
HURT: 0
helped stats (abs) min: 3 max: 1161 x̄: 117.53 x̃: 72
helped stats (rel) min: 0.98% max: 6.74% x̄: 1.70% x̃: 1.35%
95% mean confidence interval for instructions value: -147.21 -87.84
95% mean confidence interval for instructions %-change: -1.94% -1.46%
Instructions are helped.
total cycles in shared programs: 7072275 -> 6969145 (-1.46%)
cycles in affected programs: 6955767 -> 6852637 (-1.48%)
helped: 97
HURT: 0
helped stats (abs) min: 32 max: 10900 x̄: 1063.20 x̃: 560
helped stats (rel) min: 1.18% max: 7.58% x̄: 1.84% x̃: 1.45%
95% mean confidence interval for cycles value: -1339.43 -786.96
95% mean confidence interval for cycles %-change: -2.11% -1.57%
Cycles are helped.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
Ian Romanick [Tue, 3 Mar 2020 20:26:37 +0000 (12:26 -0800)]
soft-fp64: Don't open-code umulExtended
Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:
Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 928859 -> 859509 (-7.47%)
instructions in affected programs: 866293 -> 796943 (-8.01%)
helped: 76
HURT: 0
helped stats (abs) min: 75 max: 8042 x̄: 912.50 x̃: 688
helped stats (rel) min: 5.35% max: 21.02% x̄: 10.35% x̃: 7.58%
95% mean confidence interval for instructions value: -1138.37 -686.63
95% mean confidence interval for instructions %-change: -11.69% -9.00%
Instructions are helped.
total cycles in shared programs: 7272912 -> 7072275 (-2.76%)
cycles in affected programs: 6763486 -> 6562849 (-2.97%)
helped: 76
HURT: 0
helped stats (abs) min: 214 max: 30136 x̄: 2639.96 x̃: 1923
helped stats (rel) min: 1.75% max: 9.20% x̄: 4.04% x̃: 2.41%
95% mean confidence interval for cycles value: -3455.29 -1824.63
95% mean confidence interval for cycles %-change: -4.69% -3.39%
Cycles are helped.
total spills in shared programs: 817 -> 814 (-0.37%)
spills in affected programs: 791 -> 788 (-0.38%)
helped: 2
HURT: 0
total fills in shared programs: 2438 -> 2488 (2.05%)
fills in affected programs: 2392 -> 2442 (2.09%)
helped: 0
HURT: 2
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
Ian Romanick [Thu, 5 Mar 2020 00:53:36 +0000 (16:53 -0800)]
soft-fp64/b2f: Reimplement using bitwise logic ops
This doesn't help a lot of shaders, but it helps those few a LOT.
This could also be implemented using bcsel. That version is very
slightly worse because the generated SEL instruction wants to have two
immediate sources, so one of them usually needs an extra MOV instruction
to load.
Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:
Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 929619 -> 928859 (-0.08%)
instructions in affected programs: 1651 -> 891 (-46.03%)
helped: 8
HURT: 0
helped stats (abs) min: 38 max: 152 x̄: 95.00 x̃: 95
helped stats (rel) min: 42.70% max: 86.36% x̄: 49.88% x̃: 44.66%
95% mean confidence interval for instructions value: -132.97 -57.03
95% mean confidence interval for instructions %-change: -62.28% -37.49%
Instructions are helped.
total cycles in shared programs: 7280180 -> 7272912 (-0.10%)
cycles in affected programs: 12960 -> 5692 (-56.08%)
helped: 8
HURT: 0
helped stats (abs) min: 352 max: 1456 x̄: 908.50 x̃: 910
helped stats (rel) min: 52.45% max: 91.19% x̄: 59.24% x̃: 55.15%
95% mean confidence interval for cycles value: -1274.03 -542.97
95% mean confidence interval for cycles %-change: -70.06% -48.41%
Cycles are helped.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
Ian Romanick [Fri, 6 Mar 2020 02:03:35 +0000 (18:03 -0800)]
nir/algebraic: Simplify a contradiction that can occur in __flt64_nonnan
The pattern is added to opt_algebraic because, for example, comparisons
with constant 0.0 will produce (a1 < 0).
Even with a pass that optimized Boolean expressions, I think this would
be very difficult to automatically recognize and optimize.
Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:
Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 933054 -> 929619 (-0.37%)
instructions in affected programs: 784041 -> 780606 (-0.44%)
helped: 59
HURT: 0
helped stats (abs) min: 2 max: 213 x̄: 58.22 x̃: 44
helped stats (rel) min: 0.02% max: 2.51% x̄: 0.72% x̃: 0.46%
95% mean confidence interval for instructions value: -70.80 -45.64
95% mean confidence interval for instructions %-change: -0.92% -0.53%
Instructions are helped.
total cycles in shared programs: 7304712 -> 7280180 (-0.34%)
cycles in affected programs: 7176260 -> 7151728 (-0.34%)
helped: 92
HURT: 0
helped stats (abs) min: 8 max: 1414 x̄: 266.65 x̃: 166
helped stats (rel) min: 0.04% max: 2.34% x̄: 0.43% x̃: 0.22%
95% mean confidence interval for cycles value: -333.05 -200.26
95% mean confidence interval for cycles %-change: -0.54% -0.31%
Cycles are helped.
Regular shader-db changes:
No changes on any Intel platform.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
Ian Romanick [Sat, 7 Mar 2020 00:05:27 +0000 (16:05 -0800)]
nir/algebraic: Constant reassociation for bitwise operations too
Like
5886cd79a0e, but for iand, ior, and ixor.
Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:
Tiger Lake
total instructions in shared programs: 903108 -> 902830 (-0.03%)
instructions in affected programs: 654910 -> 654632 (-0.04%)
helped: 31
HURT: 5
helped stats (abs) min: 2 max: 31 x̄: 9.58 x̃: 7
helped stats (rel) min: 0.01% max: 0.23% x̄: 0.06% x̃: 0.04%
HURT stats (abs) min: 1 max: 10 x̄: 3.80 x̃: 3
HURT stats (rel) min: 0.01% max: 0.10% x̄: 0.03% x̃: 0.02%
95% mean confidence interval for instructions value: -10.55 -4.89
95% mean confidence interval for instructions %-change: -0.07% -0.03%
Instructions are helped.
total cycles in shared programs: 7059681 -> 7058006 (-0.02%)
cycles in affected programs: 5081309 -> 5079634 (-0.03%)
helped: 33
HURT: 12
helped stats (abs) min: 1 max: 444 x̄: 60.91 x̃: 18
helped stats (rel) min: <.01% max: 2.17% x̄: 0.25% x̃: 0.05%
HURT stats (abs) min: 1 max: 288 x̄: 27.92 x̃: 2
HURT stats (rel) min: <.01% max: 1.00% x̄: 0.23% x̃: 0.02%
95% mean confidence interval for cycles value: -68.32 -6.12
95% mean confidence interval for cycles %-change: -0.28% 0.03%
Inconclusive result (%-change mean confidence interval includes 0).
Ice Lake
total instructions in shared programs: 895384 -> 895159 (-0.03%)
instructions in affected programs: 658678 -> 658453 (-0.03%)
helped: 37
HURT: 0
helped stats (abs) min: 3 max: 16 x̄: 6.08 x̃: 4
helped stats (rel) min: <.01% max: 0.07% x̄: 0.04% x̃: 0.04%
95% mean confidence interval for instructions value: -7.46 -4.70
95% mean confidence interval for instructions %-change: -0.04% -0.03%
Instructions are helped.
total cycles in shared programs: 7092224 -> 7091195 (-0.01%)
cycles in affected programs: 5221666 -> 5220637 (-0.02%)
helped: 35
HURT: 11
helped stats (abs) min: 1 max: 247 x̄: 43.46 x̃: 12
helped stats (rel) min: <.01% max: 2.17% x̄: 0.23% x̃: 0.05%
HURT stats (abs) min: 2 max: 432 x̄: 44.73 x̃: 5
HURT stats (rel) min: <.01% max: 1.00% x̄: 0.25% x̃: 0.02%
95% mean confidence interval for cycles value: -49.00 4.26
95% mean confidence interval for cycles %-change: -0.27% 0.03%
Inconclusive result (value mean confidence interval includes 0).
Regular shader-db results:
All Haswell+ platforms had similar results. (Tiger Lake shown)
total instructions in shared programs:
17611408 ->
17611398 (<.01%)
instructions in affected programs: 1648 -> 1638 (-0.61%)
helped: 2
HURT: 0
total cycles in shared programs:
338366148 ->
338366124 (<.01%)
cycles in affected programs: 124048 -> 124024 (-0.02%)
helped: 2
HURT: 0
No changes on any earlier Intel platforms.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
Ian Romanick [Sat, 7 Mar 2020 00:23:29 +0000 (16:23 -0800)]
nir/algebraic: Generalize some and-of-shift-right patterns [v2]
Generalizes some of the patterns from
76289fbfa84a and
905ff8619824. In
particular, some of the soft-fp64 code generates (a & 0x7fffffff) << 1
when constant 0.0 is compared (flt or feq).
v2: Reduce the set of added patterns to those that actually help
something. This reduces the size of the state transition tables by
about 29k. Suggested by Jason. Remove the existing patterns that this
commit subsumes.
Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:
Tiger Lake
total instructions in shared programs: 903171 -> 903108 (<.01%)
instructions in affected programs: 635903 -> 635840 (<.01%)
helped: 25
HURT: 11
helped stats (abs) min: 1 max: 16 x̄: 5.04 x̃: 3
helped stats (rel) min: <.01% max: 0.15% x̄: 0.04% x̃: 0.03%
HURT stats (abs) min: 2 max: 14 x̄: 5.73 x̃: 5
HURT stats (rel) min: <.01% max: 0.11% x̄: 0.04% x̃: 0.02%
95% mean confidence interval for instructions value: -3.91 0.41
95% mean confidence interval for instructions %-change: -0.03% <.01%
Inconclusive result (value mean confidence interval includes 0).
total cycles in shared programs: 7059527 -> 7059681 (<.01%)
cycles in affected programs: 5249401 -> 5249555 (<.01%)
helped: 41
HURT: 9
helped stats (abs) min: 2 max: 76 x̄: 11.90 x̃: 10
helped stats (rel) min: <.01% max: 11.86% x̄: 0.99% x̃: 0.01%
HURT stats (abs) min: 2 max: 380 x̄: 71.33 x̃: 12
HURT stats (rel) min: <.01% max: 0.22% x̄: 0.04% x̃: 0.01%
95% mean confidence interval for cycles value: -14.93 21.09
95% mean confidence interval for cycles %-change: -1.40% -0.20%
Inconclusive result (value mean confidence interval includes 0).
Ice Lake
total instructions in shared programs: 895506 -> 895384 (-0.01%)
instructions in affected programs: 658800 -> 658678 (-0.02%)
helped: 37
HURT: 0
helped stats (abs) min: 2 max: 8 x̄: 3.30 x̃: 2
helped stats (rel) min: <.01% max: 0.03% x̄: 0.02% x̃: 0.02%
95% mean confidence interval for instructions value: -4.00 -2.59
95% mean confidence interval for instructions %-change: -0.02% -0.02%
Instructions are helped.
total cycles in shared programs: 7092748 -> 7092224 (<.01%)
cycles in affected programs: 5272008 -> 5271484 (<.01%)
helped: 36
HURT: 14
helped stats (abs) min: 2 max: 440 x̄: 21.67 x̃: 8
helped stats (rel) min: <.01% max: 11.86% x̄: 1.12% x̃: 0.02%
HURT stats (abs) min: 2 max: 122 x̄: 18.29 x̃: 6
HURT stats (rel) min: <.01% max: 0.07% x̄: 0.01% x̃: <.01%
95% mean confidence interval for cycles value: -29.24 8.28
95% mean confidence interval for cycles %-change: -1.40% -0.21%
Inconclusive result (value mean confidence interval includes 0).
Regular shader-db results:
All Haswell+ platforms had similar results. (Tiger Lake shown)
total instructions in shared programs:
17611489 ->
17611408 (<.01%)
instructions in affected programs: 21188 -> 21107 (-0.38%)
helped: 23
HURT: 1
helped stats (abs) min: 1 max: 16 x̄: 3.78 x̃: 3
helped stats (rel) min: 0.03% max: 5.82% x̄: 1.13% x̃: 0.85%
HURT stats (abs) min: 6 max: 6 x̄: 6.00 x̃: 6
HURT stats (rel) min: 0.60% max: 0.60% x̄: 0.60% x̃: 0.60%
95% mean confidence interval for instructions value: -5.27 -1.48
95% mean confidence interval for instructions %-change: -1.70% -0.42%
Instructions are helped.
total cycles in shared programs:
338418502 ->
338366148 (-0.02%)
cycles in affected programs: 2289052 -> 2236698 (-2.29%)
helped: 18
HURT: 3
helped stats (abs) min: 4 max: 18000 x̄: 2909.67 x̃: 38
helped stats (rel) min: 0.09% max: 4.07% x̄: 0.96% x̃: 0.43%
HURT stats (abs) min: 2 max: 14 x̄: 6.67 x̃: 4
HURT stats (rel) min: 0.22% max: 1.13% x̄: 0.66% x̃: 0.64%
95% mean confidence interval for cycles value: -5204.00 217.91
95% mean confidence interval for cycles %-change: -1.31% -0.14%
Inconclusive result (value mean confidence interval includes 0).
Ivy Bridge
total instructions in shared programs:
11875617 ->
11875615 (<.01%)
instructions in affected programs: 1339 -> 1337 (-0.15%)
helped: 2
HURT: 0
No changes on any earlier Intel platforms.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com> [v1]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
Ian Romanick [Thu, 31 Oct 2019 00:41:41 +0000 (17:41 -0700)]
nir/algebraic: optimize ior(ine(a, 0), ine(b, 0)) to ine(ior(a, b), 0)
Like
70f9e2589e6b. Also scrub the unnecessary size qualifier in both
replacement patterns.
This occurs in a handful of places in the soft-fp64 code, and that is
the primary reason for the change.
Perhaps the patterns that generate umin should be conditioned on
something, but I'm not sure what. lower_bitops might cover the cases
that matter, but it seems ugly.
Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:
Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 936505 -> 933388 (-0.33%)
instructions in affected programs: 925719 -> 922602 (-0.34%)
helped: 154
HURT: 1
helped stats (abs) min: 1 max: 211 x̄: 35.45 x̃: 16
helped stats (rel) min: 0.34% max: 9.30% x̄: 2.28% x̃: 0.96%
HURT stats (abs) min: 2342 max: 2342 x̄: 2342.00 x̃: 2342
HURT stats (rel) min: 2.28% max: 2.28% x̄: 2.28% x̃: 2.28%
95% mean confidence interval for instructions value: -51.21 10.99
95% mean confidence interval for instructions %-change: -2.61% -1.89%
Inconclusive result (value mean confidence interval includes 0).
total cycles in shared programs: 7323502 -> 7306184 (-0.24%)
cycles in affected programs: 7220376 -> 7203058 (-0.24%)
helped: 126
HURT: 1
helped stats (abs) min: 2 max: 946 x̄: 159.10 x̃: 95
helped stats (rel) min: 0.01% max: 9.62% x̄: 0.80% x̃: 0.37%
HURT stats (abs) min: 2728 max: 2728 x̄: 2728.00 x̃: 2728
HURT stats (rel) min: 0.37% max: 0.37% x̄: 0.37% x̃: 0.37%
95% mean confidence interval for cycles value: -192.07 -80.66
95% mean confidence interval for cycles %-change: -1.07% -0.51%
Cycles are helped.
total spills in shared programs: 635 -> 817 (28.66%)
spills in affected programs: 635 -> 817 (28.66%)
helped: 0
HURT: 3
total fills in shared programs: 2065 -> 2438 (18.06%)
fills in affected programs: 2019 -> 2392 (18.47%)
helped: 0
HURT: 2
Regular shader-db results:
All Haswell+ platforms had similar results. (Tiger Lake shown)
total instructions in shared programs:
17611506 ->
17611489 (<.01%)
instructions in affected programs: 33442 -> 33425 (-0.05%)
helped: 32
HURT: 6
helped stats (abs) min: 1 max: 6 x̄: 1.69 x̃: 1
helped stats (rel) min: 0.08% max: 1.90% x̄: 0.27% x̃: 0.11%
HURT stats (abs) min: 1 max: 15 x̄: 6.17 x̃: 5
HURT stats (rel) min: 0.09% max: 1.50% x̄: 0.65% x̃: 0.55%
95% mean confidence interval for instructions value: -1.70 0.80
95% mean confidence interval for instructions %-change: -0.30% 0.05%
Inconclusive result (value mean confidence interval includes 0).
total cycles in shared programs:
338419218 ->
338418502 (<.01%)
cycles in affected programs: 385795 -> 385079 (-0.19%)
helped: 42
HURT: 3
helped stats (abs) min: 2 max: 192 x̄: 24.57 x̃: 16
helped stats (rel) min: 0.04% max: 2.09% x̄: 0.33% x̃: 0.22%
HURT stats (abs) min: 64 max: 164 x̄: 105.33 x̃: 88
HURT stats (rel) min: 0.77% max: 1.58% x̄: 1.09% x̃: 0.93%
95% mean confidence interval for cycles value: -29.76 -2.06
95% mean confidence interval for cycles %-change: -0.40% -0.07%
Cycles are helped.
Ivy Bridge and Sandy Bridge had similar results. (Ivy Bridge shown)
total instructions in shared programs:
11875620 ->
11875617 (<.01%)
instructions in affected programs: 421 -> 418 (-0.71%)
helped: 2
HURT: 0
total cycles in shared programs:
178245336 ->
178245326 (<.01%)
cycles in affected programs: 3425 -> 3415 (-0.29%)
helped: 2
HURT: 0
No changes on Gen4 or Gen5.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
Ian Romanick [Tue, 3 Mar 2020 18:51:59 +0000 (10:51 -0800)]
nir/algebraic: Simplify logic to detect sign of an integer
This occurs in a handful of places in the soft-fp64 code, and that is
the primary reason for the change.
v2: Fix a typo in a comment. Noticed by Matt. Copy the correct fp64
shader-db results to the commit message. I realized that I used
accidentally used the results from the next commit.
Results on the 308 shaders extracted from the fp64 portion of the OpenGL
CTS:
Tiger Lake and Ice Lake had similar results. (Tiger Lake shown)
total instructions in shared programs: 906235 -> 906149 (<.01%)
instructions in affected programs: 353966 -> 353880 (-0.02%)
helped: 31
HURT: 2
helped stats (abs) min: 1 max: 8 x̄: 3.03 x̃: 3
helped stats (rel) min: 0.01% max: 1.59% x̄: 0.10% x̃: 0.04%
HURT stats (abs) min: 3 max: 5 x̄: 4.00 x̃: 4
HURT stats (rel) min: 0.02% max: 0.02% x̄: 0.02% x̃: 0.02%
95% mean confidence interval for instructions value: -3.51 -1.70
95% mean confidence interval for instructions %-change: -0.19% <.01%
Inconclusive result (%-change mean confidence interval includes 0).
total cycles in shared programs: 7076552 -> 7076173 (<.01%)
cycles in affected programs: 2878361 -> 2877982 (-0.01%)
helped: 37
HURT: 2
helped stats (abs) min: 2 max: 48 x̄: 10.81 x̃: 6
helped stats (rel) min: <.01% max: 2.17% x̄: 0.47% x̃: 0.01%
HURT stats (abs) min: 1 max: 20 x̄: 10.50 x̃: 10
HURT stats (rel) min: <.01% max: 0.01% x̄: <.01% x̃: <.01%
95% mean confidence interval for cycles value: -13.96 -5.48
95% mean confidence interval for cycles %-change: -0.72% -0.16%
Cycles are helped.
total fills in shared programs: 2064 -> 2065 (0.05%)
fills in affected programs: 45 -> 46 (2.22%)
helped: 0
HURT: 1
Regular shader-db results:
All Gen7+ platforms had similar results. (Tiger Lake shown)
total instructions in shared programs:
17611530 ->
17611506 (<.01%)
instructions in affected programs: 5934 -> 5910 (-0.40%)
helped: 10
HURT: 0
helped stats (abs) min: 1 max: 5 x̄: 2.40 x̃: 2
helped stats (rel) min: 0.14% max: 1.24% x̄: 0.47% x̃: 0.34%
95% mean confidence interval for instructions value: -3.53 -1.27
95% mean confidence interval for instructions %-change: -0.78% -0.17%
Instructions are helped.
total cycles in shared programs:
338419178 ->
338419218 (<.01%)
cycles in affected programs: 19244 -> 19284 (0.21%)
helped: 4
HURT: 2
helped stats (abs) min: 2 max: 4 x̄: 3.00 x̃: 3
helped stats (rel) min: 0.05% max: 0.11% x̄: 0.08% x̃: 0.08%
HURT stats (abs) min: 26 max: 26 x̄: 26.00 x̃: 26
HURT stats (rel) min: 1.20% max: 1.20% x̄: 1.20% x̃: 1.20%
95% mean confidence interval for cycles value: -9.08 22.41
95% mean confidence interval for cycles %-change: -0.35% 1.04%
Inconclusive result (value mean confidence interval includes 0).
No changes on any earlier Intel platform.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4142>
Pierre-Eric Pelloux-Prayer [Mon, 16 Mar 2020 14:10:23 +0000 (15:10 +0100)]
st/mesa: disallow deferred flush if there are multiple contexts
u_threaded can hang in these situation, with one context waiting on a
deferred fence from the other context.
But the other context isn't flushing its pending work (because it's waiting
for more work to pushed) so everything is stuck.
Fixes:
d17b35e671a ("gallium: add PIPE_FLUSH_DEFERRED")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1430
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4213>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4213>
Chad Versace [Thu, 6 Feb 2020 01:50:12 +0000 (17:50 -0800)]
anv: Use isl_drm_modifier_get_default_aux_state()
Use it in anv_layout_to_aux_state().
Refactor only. No change in behavior.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3881>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3881>
Jason Ekstrand [Wed, 4 Mar 2020 17:09:50 +0000 (11:09 -0600)]
intel/isl: Don't align linear images to 64K on Gen12+
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4048>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4048>
Samuel Pitoiset [Tue, 17 Mar 2020 14:32:45 +0000 (15:32 +0100)]
radv: fix random depth range unrestricted failures due to a cache issue
The shader module name is used to compute the pipeline key. The
driver used to load the wrong pipelines because the shader names
were similar.
This should fix random failures of
dEQP-VK.pipeline.depth_range_unrestricted.*
Fixes:
f11ea226664 ("radv: fix a performance regression with graphics depth/stencil clears")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4216>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4216>
Hyunjun Ko [Tue, 17 Mar 2020 03:57:03 +0000 (03:57 +0000)]
turnip: Do gathering xfb info after nir_remove_dead_variables
So we could align stream outputs correctly even if unused in/outs are
removed.
Fixes:
dEQP-VK.transform_feedback.fuzz.random_vertex.scalar_types.*
dEQP-VK.transform_feedback.fuzz.random_vertex.vector_types.*
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4207>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4207>
Hyunjun Ko [Tue, 17 Mar 2020 03:50:59 +0000 (03:50 +0000)]
turnip: Fix wrong assignment of xfb output's offset.
Should be divided by 4 so we could calculate the offset correctly in
tu6_setup_streamout.
Fixes:
2a1d6b81ed54971d33e83b7f5545da096b13b043
Related:
374406a7c420d266f920461f904864a94dc1b8c8
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4207>
Lionel Landwerlin [Tue, 10 Mar 2020 15:49:30 +0000 (17:49 +0200)]
intel/decoder: don't consider header fields past dword0
v2: use ULL
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4134>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4134>
Vasily Khoruzhick [Sun, 15 Mar 2020 19:09:30 +0000 (12:09 -0700)]
lima: decode depth/stencil write bits in RSW
Now that we know the bits that are responsible for enabling depth/stencil
writes in shader we can decode them properly.
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4197>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4197>
Icenowy Zheng [Thu, 6 Feb 2020 16:53:46 +0000 (00:53 +0800)]
lima: implement zsbuf reload
Fragment shader can write depth and stencil if we set necessary flags
in RSW. In addition to that we need to use special format for Z24S8.
Original format is apparently Z24X8 since we can't sample stencil in GLES2.
This new format also seems to use several components for storing depth
since we saw r != g != b when sampling with this format.
[vasily: - initialize clear->depth to 0xffffff if we reload depth, just
like blob does. Reloading doesn't work otherwise
- use single bitmap for reload type]
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4197>
Vasily Khoruzhick [Sat, 14 Mar 2020 23:33:00 +0000 (16:33 -0700)]
lima: disable Z16 format
Unfortunately we don't know how to reload Z16 buffers yet and blob
is using Z24 for dEQP tests that need depth reload.
Reviewed-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4197>
Eric Anholt [Thu, 27 Jun 2019 23:04:42 +0000 (16:04 -0700)]
gallium/util: Switch util_float_to_half to _mesa_float_to_half()'s impl.
The util_float_to_half() implementation was much smaller, but when trying
to switch _mesa_float_to_half to it, many testcases
(dEQP-VK.spirv_assembly.instruction.graphics.opquantize.*,
piglit.spec.arb_shading_language_packing.*packhalf2x16) start failing on
Intel. Replace the broken impl so that people don't have to debug it
later.
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3699>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3699>
Bas Nieuwenhuizen [Fri, 13 Mar 2020 19:48:27 +0000 (20:48 +0100)]
amd/llvm: Fix divergent descriptor regressions with radeonsi.
piglit/bin/arb_bindless_texture-limit -auto -fbo:
Needed to deal with non-NULL dynamic_index without deref in tex instructions.
piglit/bin/shader_runner tests/spec/arb_bindless_texture/execution/images/multiple-resident-images-reading.shader_test -auto:
Need to deal with non-deref images in enter_waterfall_imae.
Fixes:
b83c9aca4a5 "amd/llvm: Fix divergent descriptor indexing. (v3)"
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4191>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4191>
Dave Airlie [Tue, 17 Mar 2020 20:15:06 +0000 (06:15 +1000)]
gallium: fix build with latest meson and gcc10
In Fedora 32 build was failing with meson-0.53.2-1.git88e40c7.fc32
and gcc-10.0.1-0.9.fc32.x86_64.
Worked with meson-0.53.1-1 and same gcc.
/usr/bin/ld: src/gallium/state_trackers/dri/libdri.a(dri2.c.o): in function `dri2_interop_export_object':
/home/airlied/devel/mesa/mesa/build/../src/gallium/state_trackers/dri/dri2.c:1813: undefined reference to `st_finalize_texture'
/usr/bin/ld: src/gallium/state_trackers/dri/libdri.a(dri_screen.c.o): in function `dri_init_screen_helper':
/home/airlied/devel/mesa/mesa/build/../src/gallium/state_trackers/dri/dri_screen.c:580: undefined reference to `st_gl_api_create'
Moving this around seems to fix it.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4220>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4220>
Marek Olšák [Fri, 13 Mar 2020 23:49:59 +0000 (19:49 -0400)]
ac: don't set old denormals flags with LLVM >= 11
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4196>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4196>
Marek Olšák [Mon, 6 Jan 2020 20:27:15 +0000 (15:27 -0500)]
ac: set new LLVM denormal flags
See: https://reviews.llvm.org/D71358
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4196>
Marek Olšák [Thu, 23 Jan 2020 20:52:01 +0000 (15:52 -0500)]
ac: unify denorm setting enforcement
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4196>
Marek Olšák [Wed, 11 Mar 2020 23:28:44 +0000 (19:28 -0400)]
gallium/u_vbuf: simplify the first if statement in u_vbuf_upload_buffers
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4153>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4153>
Marek Olšák [Wed, 11 Mar 2020 21:27:29 +0000 (17:27 -0400)]
gallium/u_threaded: don't sync the thread for all unsychronized mappings
This was missing for the READ case. This improves glBegin/End performance.
(vbo maps with WRITE | READ | UNSYCHRONIZED)
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4153>
Eric Anholt [Wed, 11 Mar 2020 23:39:04 +0000 (16:39 -0700)]
freedreno/a5xx: Fix min-vs-mag filtering decisions on non-mipmap tex.
This a port of
3338d6e5f8b5 ("freedreno/a3xx: Mostly fix min-vs-mag
filtering decisions on non-mipmap tex.")
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4177>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4177>
Eric Anholt [Tue, 3 Mar 2020 22:38:09 +0000 (14:38 -0800)]
ci: Enable testing GLES2-3 on a530 (Dragonboard 820c).
Following on from the db410c conversion to baremetal testing, reuse the
same scripts in the same rack to run 7 db820c boards (#4/8 is failing in
the bootloader for unknown reasons).
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4177>
Eric Anholt [Wed, 11 Mar 2020 18:11:19 +0000 (11:11 -0700)]
ci: Enable ccaching of CMake builds as well.
They ignore $PATH for unknown reasons, so you have to force the ccache
wrapping yourself.
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4099>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4099>
Eric Anholt [Fri, 6 Mar 2020 21:23:20 +0000 (13:23 -0800)]
ci: Enable ccache in the container builds.
This should reduce our container rebuild times, particularly on the
40-minute ARM build (which is split across only 2 runners and thus likely
to have a hot cache) when working on updating containers.
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4099>
Eric Anholt [Fri, 6 Mar 2020 21:23:20 +0000 (13:23 -0800)]
ci: Update the ci-templates commit.
There has been a big rename of variables in the upstream repo to make it
clear what's being handed to ci-templates.
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4099>
Jason Ekstrand [Tue, 17 Mar 2020 03:58:53 +0000 (22:58 -0500)]
anv: Do an end-of-pipe sync before updating AUX table entries
We've found in GL that an actual end-of-pipe sync is required before
invalidating the aux tables and that a simple CS stall is insufficient.
If we're about to modify the actual AUX table entries from the GPU, we
should definitely make sure it's stopped dead before we do so.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4206>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4206>
Caio Marcelo de Oliveira Filho [Thu, 12 Mar 2020 21:27:13 +0000 (14:27 -0700)]
intel/blorp: Plumb the stage through blorp upload_shader
Vulkan uses that for its own upload function -- even though for BLORP
it doesn't really currently care. Neither Iris and i965 makes use of
it at the moment.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4170>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4170>
Duncan Hopkins [Thu, 12 Mar 2020 16:45:39 +0000 (16:45 +0000)]
zink: zero out zink_render_pass_state
Since zink_render_pass_state is used as a hash-key, the entire struct gets
compared. This means we don't want any uninitialized padding in there, or
else we risk getting false negatives. This has led to issues on macOS builds.
So let's zero out the struct before we start filling it out.
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4212>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4212>
Samuel Pitoiset [Mon, 16 Mar 2020 17:44:18 +0000 (18:44 +0100)]
radv/gfx10: fix required ballot size with VK_EXT_subgroup_size_control
If compute shaders require a specific subgroup size (ie. Wave32),
we have to use the correct ballot size.
Fixes dEQP-VK.subgroups.ballot_other.compute.*_requiredsubgroupSize.
Fixes:
fb07fd4e6cb ("radv: implement VK_EXT_subgroup_size_control")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4215>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4215>
Samuel Pitoiset [Mon, 16 Mar 2020 16:29:33 +0000 (17:29 +0100)]
radv/gfx10: fix required subgroup size with VK_EXT_subgroup_size_control
If compute shaders require a specific subgroup size (ie. Wave32),
we have to return the correct one.
Fixes dEQP-VK.subgroups.size_control.compute.required_subgroup_size_*.
Fixes:
fb07fd4e6cb ("radv: implement VK_EXT_subgroup_size_control")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4215>
Samuel Pitoiset [Tue, 17 Mar 2020 08:45:50 +0000 (09:45 +0100)]
radv: only inject implicit subpass dependencies if necessary
The Vulkan 1.2.134 spec update clarified when implicit subpass
dependencies should be injected by the driver. They only make
sense if automatic layout transitions are performed.
This should fix a performance regression with RPCS3 (although
they added a workaround for RADV since the regression has been found).
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2502
Fixes:
e60de085473 ("radv: handle missing implicit subpass dependencies")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4210>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4210>
Michel Dänzer [Thu, 12 Mar 2020 11:31:05 +0000 (12:31 +0100)]
gitlab-ci: Enable more Gallium drivers in meson-i386 job
These are the ones which can be enabled with the current x86_build
docker image and which build without warnings.
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4166>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4166>
Michel Dänzer [Thu, 12 Mar 2020 14:03:20 +0000 (15:03 +0100)]
llvmpipe: Use uintptr_t for pointer values
Instead of uint64_t. Fixes potentially writing beyond the end of the
handles pointer array on 32-bit architectures (and copying all 0s
instead of the computed pointer values to the array on big endian
ones).
Corresponding compiler warning:
../src/gallium/drivers/llvmpipe/lp_state_cs.c: In function ‘llvmpipe_set_global_binding’:
../src/gallium/drivers/llvmpipe/lp_state_cs.c:1312:12: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
1312 | va = (uint64_t)((char *)lp_res->data + offset);
| ^
Fixes:
264663d55d32 "gallivm/llvmpipe: add support for global
operations."
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4166>
Michel Dänzer [Thu, 12 Mar 2020 11:29:40 +0000 (12:29 +0100)]
gitlab-ci: Move classic driver testing to a new meson-classic job
The motivation is to allow llvmpipe to be enabled instead in the
meson-i386 job.
v2: (Eric Engestrom)
* Rename meson-main job to meson-gallium
* Remove stale comment above meson-i386 job
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4166>
Michel Dänzer [Thu, 12 Mar 2020 11:13:44 +0000 (12:13 +0100)]
gitlab-ci: Fold scons-swr job into scons job
Should be fast enough.
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4166>
Connor Abbott [Mon, 16 Mar 2020 14:23:44 +0000 (15:23 +0100)]
tu: Fix border color with compute shaders
I wasn't able to find any CTS tests that used compute shaders with
samplers and set a border color, so I hacked one of the tests included
with amber:
https://gist.github.com/cwabbott0/
e72f0ed8259b84ed6bf3920c68fefee6
The register was found via looking at dumps of the Vulkan blob, and
setting it fixes this test.
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4204>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4204>
Michel Dänzer [Tue, 17 Mar 2020 08:34:51 +0000 (09:34 +0100)]
gitlab-ci: Don't use buster-backports packages by default for x86_build
The backports repository can be temporarily inconsistent between
architectures, which can break the docker image build.
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4209>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4209>
Rohan Garg [Fri, 28 Feb 2020 12:48:53 +0000 (13:48 +0100)]
ci: Drop the git dependency in tracie
Instead of using git, use python and the Gitlab API
to fetch traces. This helps us slim down our ramdisks
in preparation for integrating trace replay on LAVA
devices.
Signed-off-by: Rohan Garg <rohan.garg@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4000>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4000>
Tomeu Vizoso [Fri, 6 Mar 2020 09:09:58 +0000 (10:09 +0100)]
gitlab-ci: Use surfaceless platform also for apitrace
In preparation for using apitrace to replay traces in LAVA jobs, build a
newer waffle so apitrace can use the surfaceless EGL platform.
As things were before this commit, Xvfb would have been needed in the
LAVA images.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4000>
Tomeu Vizoso [Wed, 11 Mar 2020 07:54:22 +0000 (08:54 +0100)]
gitlab-ci: Update renderdoc
Get closer to upstream to avoid accumulating changes.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4000>
Vasily Khoruzhick [Tue, 10 Mar 2020 08:53:57 +0000 (01:53 -0700)]
lima/gpir: fix crash in schedule_insert_ready_list()
Fix crash if node is already at position we want. Otherwise we remove
it from list (and list->prev becomes NULL) and then we dereference list->prev
in list_addtail()
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4126>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4126>
Vasily Khoruzhick [Tue, 10 Mar 2020 08:30:14 +0000 (01:30 -0700)]
lima/gpir: add better lowering for ftrunc
GP doesn't support ftrunc natively and unfortunately one in generic
opt_algebraic is not GP-friendly either. Introduce our own lowering
that utilizes fsign() that GP supports:
ftrunc(a) = fmul(fsign(a), ffloor(fmax(a, -a)))
Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4126>
Vasily Khoruzhick [Tue, 10 Mar 2020 02:34:43 +0000 (19:34 -0700)]
lima/gpir: kill dead writes to regs in DCE
Writes to regs that are never read will confuse regalloc since they
are never live and don't conflict with any regs. Kill them to prevent
overwriting another live reg.
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4125>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4125>
Connor Abbott [Fri, 4 Oct 2019 14:16:52 +0000 (10:16 -0400)]
lima/gpir: Optimize nots created from branch lowering
We also add a DCE pass to cleanup the result of this pass, which turns
out to also be necessary to cleanup the result of nir->gpir in some
cases that we didn't hit until the next commit.
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4125>
Connor Abbott [Thu, 3 Oct 2019 19:24:02 +0000 (15:24 -0400)]
lima/gpir: Optimize conditional break/continue
Optimize the result of a conditional break/continue. In NIR something
like:
loop {
...
if (cond)
continue;
would get lowered to:
block_0:
...
block_1:
branch_cond !cond block_3
block_2:
branch_uncond block_0
block_3:
...
We recognize the conditional branch skipping over the unconditional
branch, and turn it into:
block_0:
...
block_1:
branch_cond cond block_0
block_2:
block_3:
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4125>
Connor Abbott [Thu, 3 Oct 2019 19:19:40 +0000 (15:19 -0400)]
lima/gpir: Make lima_gpir_node_insert_child() useful
We weren't using this function before. The name is confusing, but it
changes the child while also fixing up the dependence link, if you don't
have access to it already. Or at least, I think that's what the
intention is, and what we'll need to change the branch condition in the
next commit. Adding a dependency between the new and old source doesn't
make any sense for this, and we also need to change the actual source.
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4125>
Vinson Lee [Sun, 15 Mar 2020 01:57:05 +0000 (18:57 -0700)]
panfrost: Fix gnu-empty-initializer error.
../src/gallium/drivers/panfrost/pan_cmdstream.c:1553:54: error: use of GNU empty initializer extension [-Werror,-Wgnu-empty-initializer]
union mali_attr varyings[PIPE_MAX_ATTRIBS] = { };
^
Fixes:
836686daf36c ("panfrost: Move panfrost_emit_varying_descriptor() to pan_cmdstream.c")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4198>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4198>
Rhys Perry [Mon, 16 Mar 2020 17:11:16 +0000 (17:11 +0000)]
aco: fix operand order for LS VGPR init bug workaround
Fixes:
a952bf3946 ('aco: Fix LS VGPR init bug on affected hardware.')
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4201>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4201>
Rhys Perry [Mon, 16 Mar 2020 13:47:55 +0000 (13:47 +0000)]
aco: fix instruction encoding for LS VGPR init bug workaround
Fixes:
a952bf3946 ('aco: Fix LS VGPR init bug on affected hardware.')
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4201>
Rhys Perry [Fri, 21 Feb 2020 18:53:19 +0000 (18:53 +0000)]
aco: set late kill for v_interp_p1_f32 for some APUs
Apparently needed for Stoney Ridge, Kabini and Mullins APUs.
gfx702 also has 16-bank LDS and https://llvm.org/docs/AMDGPUUsage.html
lists some dGPUs under there. Those GPUs seem to be Hawaii actually
(gfx701) and we don't seem to have gotten any interpolation related bugs
reported with them so far.
The late kill flag was tested by running pipeline-db with
ACO_DEBUG=validatera while setting late kill for SMEM buffer loads,
emit_vop2_instruction() and texture instructions. I also tested with
just setting the flag for v_interp_p1_f32.
As far as I know, the only other thing we have to consider for 16-bank LDS
is something to do with 16-bit interpolation. We don't do that yet.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3914>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3914>
Rhys Perry [Fri, 21 Feb 2020 15:46:39 +0000 (15:46 +0000)]
aco: add a late kill flag
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3914>
Rhys Perry [Fri, 21 Feb 2020 20:14:03 +0000 (20:14 +0000)]
aco: move some register demand helpers into aco_live_var_analysis.cpp
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3914>
Samuel Pitoiset [Fri, 13 Mar 2020 09:39:41 +0000 (10:39 +0100)]
radv/sqtt: handle thread trace capture in sqtt_QueuePresentKHR()
To avoid wasting CPU cycles when thread trace is not enabled.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4180>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4180>
Jason Ekstrand [Fri, 13 Mar 2020 20:30:41 +0000 (15:30 -0500)]
anv: Push UBO ranges relative to the start of the binding
There was a disconnect between anv_nir_compute_push_layout and the code
which sets up the push_ubo_sizes array. The NIR code we emit checks
relative to the start of the bound UBO range so that, if we end up with
a vector which straddles the start of the push range, we can perform the
bounds check without risking overflow issues. The code which sets up
the push_ubo_sizes, on the other hand, assumed it was relative to the
start of the push range. Somehow, this didn't get get caught by any of
the available tests.
Fixes:
e03f9652801 "anv: Bounds-check pushed UBOs when ..."
Closes: #2623
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4195>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4195>