Brian Paul [Tue, 1 May 2018 15:51:45 +0000 (09:51 -0600)]
gallium/i915: fix PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE typo
Fixes:
fffe5e2d14f807c ("gallium: add initial support for conservative
rasterization")
Trivial.
Rhys Perry [Sat, 7 Apr 2018 22:15:00 +0000 (16:15 -0600)]
nvc0: add conservative rasterization support
Subpixel precision bias, dilation and the post-snap mode are supported on
GM200 and newer. The pre-snap mode is supported for triangle primitives on
GP100.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Rhys Perry [Fri, 27 Apr 2018 14:43:00 +0000 (08:43 -0600)]
st/mesa: add support for nvidia conservative rasterization extensions
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Rhys Perry [Sat, 7 Apr 2018 22:15:00 +0000 (16:15 -0600)]
gallium: add initial support for conservative rasterization
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Rhys Perry [Fri, 27 Apr 2018 17:35:00 +0000 (11:35 -0600)]
mesa: add support for nvidia conservative rasterization extensions
Although the specs are written against compatibility GL 4.3 and allows core
profile and GLES2+, it is exposed for GL 1.0+ and GLES1 and GLES2+.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Brian Paul [Thu, 26 Apr 2018 17:55:46 +0000 (11:55 -0600)]
glsl/tests: add GLSL_TYPE_UINT8, GLSL_TYPE_INT8 cases to switch statements
To silence warnings about unhandled switch values.
Untested otherwise.
v2: move the INT/UINT8 cases after the INT/UINT16 cases, per Eric.
Reviewed-by: Eric Anholt <eric@anholt.net>
Brian Paul [Thu, 26 Apr 2018 17:55:16 +0000 (11:55 -0600)]
tgsi: use enums instead of unsigned in ureg code
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Timothy Arceri [Mon, 30 Apr 2018 10:39:43 +0000 (20:39 +1000)]
nir: move GL specific passes to src/compiler/glsl
With this we should have no passes in src/compiler/nir with any
dependencies on headers from core GL Mesa.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Andres Rodriguez [Mon, 30 Apr 2018 22:05:49 +0000 (18:05 -0400)]
radv/winsys: fix leaking resources from bo's imported by fd
A bo's ref_count was not being initialized when imported from an fd.
Therefore, we would fail to free the resource during VkFreeMemory().
This patch fixes applications like hifi VR in threaded mode, which
perform frequent imports/releases of IPC shared memory.
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
CC: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Scott D Phillips [Mon, 30 Apr 2018 17:25:47 +0000 (10:25 -0700)]
i965/tiled_memcpy: ytiled_to_linear a cache line at a time
Similar to the transformation applied to linear_to_ytiled, also align
each readback from the ytiled source to a cacheline (i.e. transfer a
whole cacheline from the source before moving on to the next column).
This will allow us to utilize movntqda (_mm_stream_si128) in a
subsequent patch to obtain near WB readback performance when accessing
the uncached ytiled memory, an order of magnitude improvement.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Chris Wilson [Mon, 30 Apr 2018 17:25:46 +0000 (10:25 -0700)]
i965: Record mipmap resolver for unmapping
When mapping a region of the mipmap_tree, record which complementary
method to use to unmap it afterwards. By doing so we can avoid
duplicating the decision tree used when mapping and thereby eliminate
trivial errors that can be introduced if the two if-chains become out of
sync.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Chris Wilson [Mon, 30 Apr 2018 17:25:45 +0000 (10:25 -0700)]
i965: Move unmap_depthstencil before map_depthstencil
Reorder code to avoid a forward declaration in the next patch.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Chris Wilson [Mon, 30 Apr 2018 17:25:44 +0000 (10:25 -0700)]
i965: Move unmap_etc before map_etc
Reorder code to avoid a forward declaration in the next patch.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Chris Wilson [Mon, 30 Apr 2018 17:25:43 +0000 (10:25 -0700)]
i965: Move unmap_s8 before map_s8
Reorder code to avoid a forward declaration in the next patch.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Chris Wilson [Mon, 30 Apr 2018 17:25:42 +0000 (10:25 -0700)]
i965: Move unmap_movntdqa before map_movntdqa
Reorder code to avoid a forward declaration in the next patch.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Chris Wilson [Mon, 30 Apr 2018 17:25:41 +0000 (10:25 -0700)]
i965: Move unmap_blit before map_blit
Reorder code to avoid a forward declaration in the next patch.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Chris Wilson [Mon, 30 Apr 2018 17:25:40 +0000 (10:25 -0700)]
i965: Move unmap_gtt before map_gtt
Reorder code to avoid a forward declaration in the next patch.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Dave Airlie [Mon, 30 Apr 2018 02:45:14 +0000 (12:45 +1000)]
ac/nir: expand 64-bit vec3 loads to fix shuffling.
If loading 64-bit vec3 values, a 4 component load would be followed
by a 2 component load and the resulting shuffle would fail as it
requires 2 4 components. This just expands the second results
vector out to 4 components.
This fixes 100 CTS tests:
dEQP-VK.spirv_assembly.type.vec3.*64*
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Kenneth Graunke [Tue, 10 Apr 2018 23:01:50 +0000 (16:01 -0700)]
i965: Don't stomp initial kflags for program cache.
We want to flag EXEC_OBJECT_CAPTURE, but we ought to preserve any
existing kflags. Today, there are none (as the program cache doesn't
support 48-bit addressing), but once we start using softpin, we'll
need to preserve EXEC_OBJECT_PINNED.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Kenneth Graunke [Tue, 10 Apr 2018 08:23:15 +0000 (01:23 -0700)]
i965: Let batchbuffers be placed anywhere in the 48-bit address space.
We were trying to mark batch buffers with EXEC_OBJECT_CAPTURE, and
accidentally stomped EXEC_OBJECT_SUPPORTS_48B_ADDRESS in the process.
There's no reason to restrict batch buffers to the lower 4GB.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Scott D Phillips [Thu, 19 Apr 2018 14:54:28 +0000 (07:54 -0700)]
intel: fix check for 48b ppgtt support
The previous logic of the supports_48b_addresses wasn't actually
checking if i915.ko was running with full_48bit_ppgtt. The ENOENT
it was checking for was actually coming from the invalid context
id provided in the test execbuffer. There is no path in the
kernel driver where the presence of
EXEC_OBJECT_SUPPORTS_48B_ADDRESS leads to an error.
Instead, check the default context's GTT_SIZE param for a value
greater than 4 GiB
v2 (Ken): Fix in i965 as well.
v3 Check GTT_SIZE instead of HAS_ALIASING_PPGTT (Chris Wilson)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Leo Liu [Fri, 27 Apr 2018 12:32:41 +0000 (08:32 -0400)]
st/omx/enc: fix blit setup for YUV LoadImage
The blit here involves scaling since it's copying from I8 format to R8G8 format.
Half of source will be filtered out with PIPE_TEX_FILTER_NEAREST instruction, it
looks that GPU always uses the second half as source. Currently we use "1" as
the start point of x for R, then causing 1 source pixel of U component shift to
right. So "-1" should be the start point for U component.
Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Juan A. Suarez Romero [Fri, 27 Apr 2018 08:38:09 +0000 (10:38 +0200)]
autotools, meson: bump up required VA version
Due using a new VP9 config we use, required VA API 0.39
Fixes:
413c5ca3727 ("travis: update libva required version")
CC: 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Juan A. Suarez Romero [Sat, 28 Apr 2018 17:01:48 +0000 (17:01 +0000)]
docs: update calendar, add news and link release notes to 18.0.2
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Juan A. Suarez Romero [Sat, 28 Apr 2018 16:57:30 +0000 (16:57 +0000)]
docs: add sha256 checksums for 18.0.2
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit
b3eed3ad03fd1eb61474cd0a8a173ad40fb8a876)
Juan A. Suarez Romero [Sat, 28 Apr 2018 16:22:11 +0000 (16:22 +0000)]
docs: add release notes for 18.0.2
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit
d38da7bd2d4387635fac8bc7f45e64f50dc43c43)
Marek Olšák [Fri, 13 Apr 2018 22:09:11 +0000 (18:09 -0400)]
radeonsi: increase the number of compiler threads depending on the CPU
The compiler queue was limited to 3 threads, so shader-db running
on a 16-thread CPU would have a bottleneck on the 3-thread queue.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Benedikt Schemmer <ben at besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 9 Apr 2018 23:55:10 +0000 (19:55 -0400)]
radeonsi: avoid a crash in gallivm_dispose_target_library_info
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Benedikt Schemmer <ben at besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 9 Apr 2018 23:23:55 +0000 (19:23 -0400)]
radeonsi: move data_layout into si_compiler
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Benedikt Schemmer <ben at besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 9 Apr 2018 23:13:37 +0000 (19:13 -0400)]
radeonsi: move passmgr into si_compiler
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Benedikt Schemmer <ben at besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 9 Apr 2018 22:43:54 +0000 (18:43 -0400)]
radeonsi: move target_library_info into si_compiler
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Benedikt Schemmer <ben at besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 9 Apr 2018 22:36:58 +0000 (18:36 -0400)]
radeonsi: use si_compiler::triple in si_llvm_optimize_module
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Benedikt Schemmer <ben at besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 9 Apr 2018 22:35:45 +0000 (18:35 -0400)]
radeonsi: add triple into si_compiler
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Benedikt Schemmer <ben at besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 9 Apr 2018 22:26:05 +0000 (18:26 -0400)]
radeonsi: add struct si_compiler containing LLVMTargetMachineRef
It will contain more variables.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Benedikt Schemmer <ben at besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 9 Apr 2018 01:53:25 +0000 (21:53 -0400)]
radeonsi: rename r600_texture::resource to buffer
r600_resource could be renamed to si_buffer.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 9 Apr 2018 01:52:05 +0000 (21:52 -0400)]
radeonsi: use r600_resource() typecast helper
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 9 Apr 2018 01:20:53 +0000 (21:20 -0400)]
radeonsi: remove unused atom parameter from si_atom::emit
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 9 Apr 2018 01:12:24 +0000 (21:12 -0400)]
radeonsi: inline 2 trivial state structures
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 9 Apr 2018 01:07:29 +0000 (21:07 -0400)]
radeonsi: remove function si_init_atom
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 9 Apr 2018 01:03:51 +0000 (21:03 -0400)]
radeonsi: remove si_atom::id
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 9 Apr 2018 00:54:02 +0000 (20:54 -0400)]
radeonsi: don't use an indirect table for state atoms
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 9 Apr 2018 00:26:14 +0000 (20:26 -0400)]
radeonsi: rename r600_atom -> si_atom
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 9 Apr 2018 00:20:39 +0000 (20:20 -0400)]
radeonsi: remove r600_pipe_common.h
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 13 Apr 2018 21:15:06 +0000 (17:15 -0400)]
radeonsi/gfx9: workaround for INTERP with indirect indexing
and clean up the conditions.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Marek Olšák [Thu, 12 Apr 2018 01:21:28 +0000 (21:21 -0400)]
radeonsi: rewrite DCC format compatibility checking code
It might be better to use a slow compressed clear when clearing to 1.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 5 Apr 2018 01:43:28 +0000 (21:43 -0400)]
radeonsi: implement DCC fast clear swizzle constraints more accurately
Reduce swizzle constraints to the ALPHA_IS_ON_MSB constraint and the clear
value of 1.
This significantly changes the DCC fast clear code, and fixes fast clear
for RGB formats without alpha.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 11 Apr 2018 15:30:58 +0000 (11:30 -0400)]
radeonsi: rename variables and document stuff around DCC fast clear
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 8 Apr 2018 03:40:26 +0000 (23:40 -0400)]
radeonsi: fully enable 2x DCC MSAA for array and non-array textures
The clear code is exactly the same as for 1 sample buffers -
just clear the whole thing.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 8 Apr 2018 04:19:50 +0000 (00:19 -0400)]
radeonsi: enable fast color clear for level 0 of mipmapped textures on <= VI
GFX9 is more complicated and needs a compute shader that we should just
copy from amdvlk.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 16 Apr 2018 20:34:56 +0000 (16:34 -0400)]
ac/surface: handle DCC subresource fast clear restriction on VI
v2: require the previous level to be clearable for determining whether
the last unaligned level is clearable
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
George Kyriazis [Tue, 24 Apr 2018 22:03:00 +0000 (17:03 -0500)]
swr/rast: No need to export GetSimdValidIndicesGfx
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Tue, 24 Apr 2018 21:44:19 +0000 (16:44 -0500)]
swr/rast: Small editorial changes
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Tue, 24 Apr 2018 16:13:54 +0000 (11:13 -0500)]
swr/rast: Use new processor detection mechanism
Use specific avx512 selection mechanism based on avx512er bit instead of
getHostCPUName(). LLVM 6.0.0 has a bug that reports wrong string for KNL
(fixed in 6.0.1).
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Mon, 23 Apr 2018 23:14:59 +0000 (18:14 -0500)]
swr/rast: Output rasterizer dir to console since it's process specific
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Mon, 23 Apr 2018 23:00:10 +0000 (18:00 -0500)]
swr/rast: Add TranslateGfxAddress for shader
Also add GFX_MEM_CLIENT_SHADER
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Mon, 23 Apr 2018 21:34:44 +0000 (16:34 -0500)]
swr/rast: jit PRINT improvements.
Sign-extend integer types to 32bit when specifying "%d" and add new %u
which zero-extends to 32bit. Improves printing of sub 32bit integer types
(i1 specifically).
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Mon, 23 Apr 2018 21:31:38 +0000 (16:31 -0500)]
swr/rast: Fix regressions.
Bump jit cache revision number to force recompile.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Mon, 23 Apr 2018 16:22:50 +0000 (11:22 -0500)]
swr/rast: Cleanup old cruft.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Fri, 20 Apr 2018 18:29:39 +0000 (13:29 -0500)]
swr/rast: Package events.proto with core output
However only if the file exists in DEBUG_OUTPUT_DIR. The expectation is
that AR rasterizerLauncher will start placing it there when launching
a workload (which is in a subsequent checkin)
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Thu, 19 Apr 2018 22:59:08 +0000 (17:59 -0500)]
swr/rast: Fix init in EventHandlerWorkerStats
Make sure we initialize variables.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Thu, 19 Apr 2018 18:15:31 +0000 (13:15 -0500)]
swr/rast: Fix return type of VCVTPS2PH.
expecting <8xi16> return.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Wed, 18 Apr 2018 20:17:04 +0000 (15:17 -0500)]
swr/rast: WIP Translation handling
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Tue, 17 Apr 2018 04:18:28 +0000 (23:18 -0500)]
swr/rast: Use different handing for stream masks
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Mon, 16 Apr 2018 23:54:45 +0000 (18:54 -0500)]
swr/rast: Silence warnings
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Sun, 15 Apr 2018 16:57:47 +0000 (11:57 -0500)]
swr/rast: Add support for TexelMask evaluation
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Sat, 14 Apr 2018 08:34:44 +0000 (03:34 -0500)]
swr/rast: Internal core change
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Fri, 13 Apr 2018 21:21:24 +0000 (16:21 -0500)]
swr/rast: Fix x86 lowering 64-bit float handling
- 64-bit cvt-to-float needs to be explicitly handled
- gathers need the right parameter types to work with doubles
Fixes draw-vertices piglit tests
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Fri, 13 Apr 2018 21:14:42 +0000 (16:14 -0500)]
swr/rast: Add some SIMD_T utility functors
VecEqual and VecHash
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Thu, 12 Apr 2018 18:10:05 +0000 (13:10 -0500)]
swr/rast: Fix wrong type allocation
ALLOCA pointer elements, not pointers.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Tue, 24 Apr 2018 18:29:41 +0000 (13:29 -0500)]
swr: touch generated files to update timestamp
previous change in generators necessitates this change
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
George Kyriazis [Tue, 10 Apr 2018 23:43:31 +0000 (18:43 -0500)]
swr/rast: Fix byte offset for non-indexed draws
for the case when USE_SIMD16_SHADERS == FALSE
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Marek Olšák [Tue, 24 Apr 2018 21:01:35 +0000 (17:01 -0400)]
util/u_queue: fix a deadlock in util_queue_finish
Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Dylan Baker [Thu, 26 Apr 2018 17:20:57 +0000 (10:20 -0700)]
meson: fix race condition revealed by using 0.44
Previously there was a special target that blocked for the generation of
anv_entrypoints.h, with meson 0.44 we don't need this, we can use a new
language feature instead. The problem is that previously that blocking
target would hide a race condition for the generation of another header,
anv_extensions.h. Now the build sometimes fails when anv_extensions.h is
not generated in time.
v2: - clarify the race condition in the commit message (Emil)
CC: Mark Janes <mark.a.janes@intel.com>
Fixes:
92550d9b16d2b295bdac087f31b1fd6d0f808e02
("meson: remove workaround for custom target creating .h and .c files")
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Dylan Baker [Thu, 26 Apr 2018 17:44:00 +0000 (10:44 -0700)]
bin: force git show to use default pretty setting
I have pretty default to short, which breaks this script.
v2: - Fix both places that don't define a --pretty (Emil)
cc: Juan A. Suarez <jasuarez@igalia.com>
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Andres Gomez <agomez@igalia.com> (v1)
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Tapani Pälli [Fri, 27 Apr 2018 06:52:33 +0000 (09:52 +0300)]
mesa: add TBO support for GL_EXT_texture_norm16
Earlier plumbing missed interaction with texture buffer objects.
Fixes:
7f467d4f73 "mesa: GL_EXT_texture_norm16 extension plumbing"
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Samuel Pitoiset [Wed, 25 Apr 2018 16:15:52 +0000 (18:15 +0200)]
ac: fix texture query LOD for 1D textures on GFX9
1D textures are allocated as 2D which means we only need
one coordinate for texture query LOD.
Fixes:
625dcbbc456 ("amd/common: pass address components individually to
ac_build_image_intrinsic")
Cc: 18.1 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Christian Gmeiner [Fri, 20 Apr 2018 12:55:53 +0000 (14:55 +0200)]
etnaviv: remove not needed includes
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Christian Gmeiner [Fri, 20 Apr 2018 12:55:52 +0000 (14:55 +0200)]
etnaviv: remove redundant include
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Timothy Arceri [Tue, 10 Apr 2018 04:34:26 +0000 (14:34 +1000)]
glsl: replace some asserts with unreachable when processing the ast
Reviewed-by: Matt Turner <mattst88@gmail.com>
Timothy Arceri [Fri, 27 Apr 2018 00:03:56 +0000 (10:03 +1000)]
mesa: drop the buffer mode param from the DrawBuffer driver function
No drivers used it.
Reviewed-by: Brian Paul <brianp@vmware.com>
Anuj Phogat [Mon, 16 Apr 2018 22:48:41 +0000 (15:48 -0700)]
anv/icl: Enable Vulkan on Ice Lake
This patch enables the Vulkan driver on Ice Lake h/w
with added warning about preliminary support.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Caio Marcelo de Oliveira Filho [Thu, 26 Apr 2018 19:11:20 +0000 (12:11 -0700)]
anv: enable VK_EXT_shader_viewport_index_layer
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jason Ekstrand [Sat, 21 Apr 2018 04:52:41 +0000 (21:52 -0700)]
anv/allocator: Don't shrink either end of the block pool
Previously, we only tried to ensure that we didn't shrink either end
below what was already handed out. However, due to the way we handle
relocations with block pools, we can't shrink the back end at all. It's
probably best to not shrink in either direction.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105374
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106147
Tested-by: Eero Tamminen <eero.t.tamminen@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Eric Anholt [Thu, 26 Apr 2018 16:24:32 +0000 (09:24 -0700)]
broadcom/vc5: Add support for centroid varyings.
It would be nice to share the flags packet emit logic with flat shade
flags, but I couldn't come up with a good way while still using our pack
macros. We need to refactor this to shader record setup at compile time,
anyway.
Fixes ext_framebuffer_multisample-interpolation * centroid-*
Eric Anholt [Wed, 25 Apr 2018 23:30:20 +0000 (16:30 -0700)]
broadcom/vc5: Add an assert about GFXH-1559.
Our TF outputs always start at 6 or 7 currently, so we don't hit the
broken 8 case. Let's make sure that doesn't change somehow.
Eric Anholt [Wed, 25 Apr 2018 23:24:15 +0000 (16:24 -0700)]
broadcom/vc5: Add validation that we don't violate GFXH-1633 requirements.
We don't use ldunifa yet, but we will eventually for UBOs.
Eric Anholt [Wed, 25 Apr 2018 23:16:27 +0000 (16:16 -0700)]
broadcom/vc5: Add validation that we don't violate GFXH-1625 requirements.
We don't use TMUWT yet, but we will once we do SSBOs.
Eric Anholt [Wed, 25 Apr 2018 21:18:52 +0000 (14:18 -0700)]
broadcom/vc5: Implement GFXH-1742 workaround (emit 2 dummy stores on 4.x).
This should fix help with intermittent GPU hangs in tests switching
formats while rendering small frames. Unfortunately, it didn't help with
the tests I'm having troubles with.
Eric Anholt [Wed, 25 Apr 2018 20:51:47 +0000 (13:51 -0700)]
broadcom/vc5: Add QPU validation for register writes after thrend.
The next shader gets to start writing the register file during these
slots, so make sure we don't stomp over them.
The only case of hitting this that I could imagine would be dead writes.
Eric Anholt [Wed, 25 Apr 2018 18:40:40 +0000 (11:40 -0700)]
st: Choose a 2101010 format for GL_RGB/GL_RGBA with a 2_10_10_10 type.
GLES's GL_EXT_texture_type_2_10_10_10_REV allows uploading this type to an
unsized internalformat, and it should be non-color-renderable.
fbobject.c's implementation of the check for color-renderable is checks
that the texture has a 2101010 mesa format, so make sure that we have
chosen a 2101010 format so that check can do what it meant to.
Fixes KHR-GLES3.packed_pixels.pbo_rectangle.rgb on vc5.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Charmaine Lee [Thu, 26 Apr 2018 16:21:52 +0000 (09:21 -0700)]
st/mesa: fix missing setting of _ElementSize in new_draw_rasterpos_stage
With this patch, _ElementSize is initialized along with the rest
of the vertex array attributes in new_draw_rasterpos_stage().
This fixes a crash in st_pipe_vertex_format() when running
topogun-1.06-orc-84k-resize trace file with VMware svga driver.
Reviewed-by: Brian Paul <brianp@vmware.com>
Drew Davenport [Wed, 25 Apr 2018 15:32:31 +0000 (09:32 -0600)]
st/va: Fix typos
s/attibute/attribute/
s/suface/surface/
v2: rebased(Leo)
Reviewed-by: Leo Liu <leo.liu@amd.com>
Drew Davenport [Tue, 24 Apr 2018 23:01:32 +0000 (17:01 -0600)]
st/va: Fix potential buffer overread
VASurfaceAttribExternalBuffers.pitches is indexed by
plane. Current implementation only supports single plane layout.
Reviewed-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Boyuan Zhang [Wed, 25 Apr 2018 15:49:52 +0000 (11:49 -0400)]
radeon/vcn: fix mpeg4 msg buffer settings
Previous bit-fields assignments are incorrect and will result certain mpeg4
decode failed due to wrong flag values. This patch fixes these assignments.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Ian Romanick [Fri, 18 Sep 2015 16:00:28 +0000 (12:00 -0400)]
radeon: Drop broken front_buffer_reading/drawing optimization
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Ian Romanick [Thu, 17 Sep 2015 14:56:15 +0000 (10:56 -0400)]
radeon: Use _mesa_is_front_buffer_drawing
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Samuel Pitoiset [Wed, 25 Apr 2018 09:22:17 +0000 (11:22 +0200)]
radv: set ac_surf_info::num_channels correctly
num_channels has been introduced since "ac/surface: don't set
the display flag for obviously unsupported cases".
Based on RadeonSI.
Fixes:
e29facff315 ("ac/surface: don't set the display flag for obviously unsupported cases (v2)")
Cc: 18.1 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 25 Apr 2018 08:56:15 +0000 (10:56 +0200)]
radv: fix DCC enablement since partial MSAA implementation
dcc_msaa_allowed is always false on GFX9+ and only true on VI
if RADV_PERFTEST=dccmsaa is set. This means DCC was disabled
in some situations where it should not.
This is likely going to fix a performance regression.
Fixes:
2f63b3dd09 ("radv: enable DCC for MSAA 2x textures on VI under an option")
Cc: 18.1 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Karol Herbst [Sun, 22 Apr 2018 01:29:07 +0000 (03:29 +0200)]
nir/opt_constant_folding: fix folding of 8 and 16 bit ints
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Karol Herbst [Sat, 21 Apr 2018 23:31:22 +0000 (01:31 +0200)]
nir: print 8 and 16 bit constants correctly
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>