Craig Topper [Tue, 5 Jul 2022 05:33:15 +0000 (22:33 -0700)]
[RISCV] Replace an explicit check with an assert.
Shift amounts should never be 0 or more than bitwidth - 1.
Craig Topper [Tue, 5 Jul 2022 05:28:08 +0000 (22:28 -0700)]
[RISCV] Rename some variables for clarity. NFC
Stephan Bergmann [Wed, 29 Jun 2022 06:17:58 +0000 (08:17 +0200)]
[test] Check for more -fsanitize=array-bounds behavior
...that had temporarily regressed with (since reverted)
<https://github.com/llvm/llvm-project/commit/
886715af962de2c92fac4bd37104450345711e4a>
"[clang] Introduce -fstrict-flex-arrays=<n> for stricter handling of flexible
arrays", and had then been seen to cause issues in the wild:
For one, the HarfBuzz project has various "fake" flexible array members of the
form
> Type arrayZ[HB_VAR_ARRAY];
in <https://github.com/harfbuzz/harfbuzz/blob/main/src/hb-open-type.hh>, where
HB_VAR_ARRAY is a macro defined as
> #ifndef HB_VAR_ARRAY
> #define HB_VAR_ARRAY 1
> #endif
in <https://github.com/harfbuzz/harfbuzz/blob/main/src/hb-machinery.hh>.
For another, the Firebird project in
<https://github.com/FirebirdSQL/firebird/blob/master/src/lock/lock_proto.h> uses
a trailing member
> srq lhb_hash[1]; // Hash table
as a "fake" flexible array, but declared in a
> struct lhb : public Firebird::MemoryHeader
that is not a standard-layout class (because the Firebird::MemoryHeader base
class also declares non-static data members).
(The second case is specific to C++. Extend the test setup so that all the
other tests are now run for both C and C++, just in case the behavior could ever
start to diverge for those two languages.)
A third case where -fsanitize=array-bounds differs from -Warray-bounds (and
which is also specific to C++, but which doesn't appear to have been encountered
in the wild) is when the "fake" flexible array member's size results from
template argument substitution.
Differential Revision: https://reviews.llvm.org/D128783
Daniel Bertalan [Sun, 3 Jul 2022 08:58:39 +0000 (10:58 +0200)]
[lld-macho] Handle LOH_ARM64_ADRP_LDR_GOT optimization hints
This hint instructs the linker to perform the AdrpLdr or AdrpAdd
transformation depending on whether the GOT load has been relaxed to
load a local symbol's address.
Differential Revision: https://reviews.llvm.org/D129059
Christian Sigg [Mon, 4 Jul 2022 06:11:30 +0000 (08:11 +0200)]
[mlir] Add InferIntRangeInterface to gpu.launch
Infers block/grid dimensions/indices or ranges of such dimensions/indices.
Reviewed By: krzysz00
Differential Revision: https://reviews.llvm.org/D129036
Fangrui Song [Tue, 5 Jul 2022 04:45:19 +0000 (21:45 -0700)]
[llvm-objcopy] -O binary: align sh_offset for section changed from SHT_NOBITS
For a SHT_NOBITS section like .bss, its sh_offset is typically not
aligned by sh_addralign. If it is converted to SHT_PROGBITS by
`--set-section-flags .bss=alloc,contents`, we should conceptually align
it when computing the output size for -O binary. Otherwise the output
size may be smaller than GNU objcopy produced output.
* binary-no-paddr.test has a case with non-sensical p_paddr=1 which has
a changed behavior. Update it.
Close https://github.com/llvm/llvm-project/issues/55246
Reviewed By: jhenderson
Differential Revision: https://reviews.llvm.org/D128961
wanglei [Tue, 5 Jul 2022 01:54:30 +0000 (09:54 +0800)]
[LoongArch] Add initial support for function calls
Note that this is just enough for simple function call examples to
generate working code.
A good portion of this patch is the extra functions that needed to be
implemented to support the test case. e.g. storeRegToStackSlot,
loadRegFromStackSlot, eliminateFrameIndex.
Differential Revision: https://reviews.llvm.org/D128429
wanglei [Tue, 5 Jul 2022 01:49:11 +0000 (09:49 +0800)]
[LoongArch] Add codegen support for conditional branches
Setting ISD::BR_CC to Expand makes it much easier to deal with
matching the expanded form.
Differential Revision: https://reviews.llvm.org/D128428
wanglei [Tue, 5 Jul 2022 01:46:19 +0000 (09:46 +0800)]
[LoongArch] Add codegen support for load/store operations
This patch also support lowering global addresses.
Differential Revision: https://reviews.llvm.org/D128427
Yeting Kuo [Sun, 3 Jul 2022 11:20:28 +0000 (19:20 +0800)]
[RISCV][Clang] Teach RISCVEmitter to generate BitCast for pointer operands.
RVV C intrinsics use pointers to scalar for base address and their corresponding
IR intrinsics but use pointers to vector. It makes some vector load intrinsics
need specific ManualCodegen and MaskedManualCodegen to just add bitcast for
transforming to IR.
For simplifying riscv_vector.td, the patch make RISCVEmitter detect pointer
operands and bitcast them.
Reviewed By: kito-cheng
Differential Revision: https://reviews.llvm.org/D129043
Chuanqi Xu [Tue, 5 Jul 2022 02:55:14 +0000 (10:55 +0800)]
[NFC] Remove unused test inputs
phyBrackets [Tue, 5 Jul 2022 02:41:00 +0000 (08:11 +0530)]
[NFC][ASTImporter] remove the unnecessary condition checks in ASTImporter.cpp
I think that these conditions are unnecessary because in VisitClassTemplateDecl we import the definition via the templated CXXRecordDecl and in VisitVarTemplateDecl via the templated VarDecl. These are named ToTemplted and DTemplated respectively.
Reviewed By: martong
Differential Revision: https://reviews.llvm.org/D128608
jacquesguan [Mon, 4 Jul 2022 09:15:32 +0000 (17:15 +0800)]
[RISCV][NFC] Merge the isolated decleration into foreach.
Reviewed By: benshi001
Differential Revision: https://reviews.llvm.org/D129063
zhongyunde [Tue, 5 Jul 2022 01:14:29 +0000 (09:14 +0800)]
[InstCombine] Make use of low zero bits to determine exact int->fp cast
According the comment https://reviews.llvm.org/D127854#inline-1226805,
We could also make use of these low zero bits, https://alive2.llvm.org/ce/z/GYxTRu
Reviewed By: spatel, nikic, xbolva00
Differential Revision: https://reviews.llvm.org/D128895
Sanjay Patel [Mon, 4 Jul 2022 22:55:24 +0000 (18:55 -0400)]
[InstCombine] fold sub of min/max of sub with common operand
x - max(x - y, 0) --> min(x, y)
x - min(x - y, 0) --> max(x, y)
https://alive2.llvm.org/ce/z/2YkqFe
issue #55470
Sanjay Patel [Mon, 4 Jul 2022 22:46:40 +0000 (18:46 -0400)]
[InstCombine] add tests for sub of smin/smax; NFC
issue #55470
Sanjay Patel [Mon, 4 Jul 2022 21:39:54 +0000 (17:39 -0400)]
[InstCombine] add helper function for sub-of-min/max folds; NFC
The test diffs are cosmetic -- but improvements -- because we
let instcombine handle replacement. Instead of dropping the
old value name, it propagates to the new instruction.
Joseph Huber [Mon, 4 Jul 2022 21:32:47 +0000 (17:32 -0400)]
[OffloadPackager] Use appropriate kind for LTO bitcode
Summary:
Currently we just check the extension to set the image kind. This
incorrectly labels the `.o` files created during LTO as object files.
This patch simply adds a check for the bitcode magic bytes instead.
Jonas Hahnfeld [Mon, 4 Jul 2022 17:27:49 +0000 (19:27 +0200)]
[Orc][LLJIT] Use JITLink on RISC-V
RuntimeDyld does not support RISC-V, so it makes sense to enable
JITLink by default. This also makes relocations work without support
for a large code model.
Differential Revision: https://reviews.llvm.org/D129092
Simon Pilgrim [Mon, 4 Jul 2022 20:43:40 +0000 (21:43 +0100)]
[X86] Regenerate fold-tied-op.ll test checks
Florian Hahn [Mon, 4 Jul 2022 20:37:16 +0000 (21:37 +0100)]
[LV] Consider runtime checks profitable if scalar cost is zero.
This fixes an UBSan failure after
644a965c1efef. When using
user-provided VFs/ICs (via the force-vector-width /
force-vector-interleave options) the scalar cost is zero, which would
cause divide-by-zero.
When forcing vectorization using the options, the cost of the runtime
checks should not block vectorization.
Nico Weber [Sun, 3 Jul 2022 20:14:48 +0000 (22:14 +0200)]
[clang-format] Update documentation
- Update `clang-format --help` output after
b1f0efc06acc.
- Update `clang-format-diff.py` help text, which apparently hasn't
been updated in a while. Since git and svn examples are now part
of the help text, remove them in the text following the help text.
Differential Revision: https://reviews.llvm.org/D129050
owenca [Sun, 3 Jul 2022 23:42:00 +0000 (16:42 -0700)]
[clang-format] Break on AfterColon only if not followed by comment
Break after a constructor initializer colon only if it's not followed by a
comment on the same line.
Fixes #41128.
Fixes #43246.
Differential Revision: https://reviews.llvm.org/D129057
Valentin Clement [Mon, 4 Jul 2022 19:16:13 +0000 (21:16 +0200)]
[flang] Make code more homogenous in CodeGen
This patch just make the code more similar
in each conversion.
This patch is part of the upstreaming effort from fir-dev branch.
Reviewed By: jeanPerier
Differential Revision: https://reviews.llvm.org/D129071
Sam McCall [Fri, 24 Jun 2022 01:01:45 +0000 (03:01 +0200)]
[pseudo] Store shift and goto actions in a compact structure with faster lookup.
The actions table is very compact but the binary search to find the
correct action is relatively expensive.
A hashtable is faster but pretty large (64 bits per value, plus empty
slots, and lookup is constant time but not trivial due to collisions).
The structure in this patch uses 1.25 bits per entry (whether present or absent)
plus the size of the values, and lookup is trivial.
The Shift table is 119KB = 27KB values + 92KB keys.
The Goto table is 86KB = 30KB values + 57KB keys.
(Goto has a smaller keyspace as #nonterminals < #terminals, and more entries).
This patch improves glrParse speed by 28%: 4.69 => 5.99 MB/s
Overall the table grows by 60%: 142 => 228KB.
By comparison, DenseMap<unsigned, StateID> is "only" 16% faster (5.43 MB/s),
and results in a 285% larger table (547 KB) vs the baseline.
Differential Revision: https://reviews.llvm.org/D128485
Jeff Bailey [Sun, 3 Jul 2022 03:42:58 +0000 (03:42 +0000)]
Use add_llvm_install_targets for install-llvmlibc
Using the LLVM rules for install ensures that DESTDIR and other expected
variables for an LLVM install work correctly.
Tested:
Manually with DESTDIR=/tmp/testinstall/ ninja install-llvmlibc
Reviewed By: lntue
Differential Revision: https://reviews.llvm.org/D129041
Benoit Jacob [Mon, 4 Jul 2022 15:33:50 +0000 (15:33 +0000)]
CombineContractBroadcast should not create dims unused in LHS+RHS
Differential Revision: https://reviews.llvm.org/D129087
Florian Hahn [Mon, 4 Jul 2022 16:23:47 +0000 (17:23 +0100)]
[LV] Add back CantReorderMemOps remark.
Add back remark unintentionally dropped by
644a965c1efef68f.
I will add a LV test separately, so we do not have to rely on a Clang
test to catch this.
Nicolas Vasilache [Mon, 4 Jul 2022 16:00:03 +0000 (09:00 -0700)]
[mlir][Linalg][NFC] Make getReassociationMapForFoldingUnitDims a visible helper function
Sander de Smalen [Mon, 4 Jul 2022 15:47:36 +0000 (15:47 +0000)]
[AArch64] Add support for insert/extract for nxv1i1 types.
This patch adds patterns and tests for subvector insert/extract
intrinsics to/from all legal predicate types.
Reviewed By: david-arm, kmclaughlin
Differential Revision: https://reviews.llvm.org/D128975
Craig Topper [Mon, 4 Jul 2022 15:33:21 +0000 (08:33 -0700)]
[X86] Disable combineVectorSizedSetCCEquality for soft float.
The vector types aren't legal with soft float.
Also disable under NoImplicitFloat for good measure.
Fixes PR56351.
Differential Revision: https://reviews.llvm.org/D129060
Shraiysh Vaishay [Mon, 4 Jul 2022 08:22:35 +0000 (13:52 +0530)]
[mlir][OpenMP] omp.task translation to LLVM IR
This patch adds translation for omp.task from OpenMPDialect to LLVM IR
Dialect and adds tests for the same.
Depends on D71989
Reviewed By: ftynse, kiranchandramohan, peixin, Meinersbur
Differential Revision: https://reviews.llvm.org/D123919
Sanjay Patel [Mon, 4 Jul 2022 14:54:16 +0000 (10:54 -0400)]
[SLP] add test for load combining + shuffling; NFC
issue #38821
Nikita Popov [Mon, 4 Jul 2022 14:45:13 +0000 (16:45 +0200)]
[InstCombine] Avoid ConstantExpr::get() in phi binop fold
Use ConstantFoldBinaryOpOperands() instead, in preparation for not
all binops having a supported constant expression.
Nikita Popov [Mon, 4 Jul 2022 14:40:07 +0000 (16:40 +0200)]
[Bitcode] Use bitcode input for test (NFC)
The constant expression used in the test will become invalid in
the future. Convert the input into bitcode, so we test that auto-
upgrade happens gracefully once this is the case.
Florian Hahn [Mon, 4 Jul 2022 14:20:52 +0000 (15:20 +0100)]
[LTO] Update remark test after
644a965c1efef6.
Peter Waller [Mon, 4 Jul 2022 14:06:38 +0000 (14:06 +0000)]
[LoopVectorize][NFC] Reinstate TTICapture workaround for gcc-6
Fixes #56374.
luxufan [Sun, 19 Jun 2022 12:01:25 +0000 (20:01 +0800)]
[RISCV] Add ADDI instr for computing FrameIndex address
RVV doesn't have immediate field for memory addressing. Currently
we build MachineInstructions in PEI to computing stack offset for
RVV load store instructions. These instructions were added too late to
can be optimized by CSE, LICM... passes.
This patch makes FrameIndex SDNodes can't be matched in RVV Load Store
instruction selection patterns. So that the FrameIndex SDNodes would be
selected as `ADDI GPR, targetframeindex`.
There are 2 advantages for such change:
1. Stack objects address computing can be optimized by machine function
passes.
2. Since the ADDI instruction's destination register can be used as a
temp register, we can save an emergency spill slot.
Differential Revision: https://reviews.llvm.org/D128187
Florian Hahn [Mon, 4 Jul 2022 14:10:48 +0000 (15:10 +0100)]
[LV] Vectorize cases with larger number of RT checks, execute only if profitable.
This patch replaces the tight hard cut-off for the number of runtime
checks with a more accurate cost-driven approach.
The new approach allows vectorization with a larger number of runtime
checks in general, but only executes the vector loop (and runtime checks) if
considered profitable at runtime. Profitable here means that the cost-model
indicates that the runtime check cost + vector loop cost < scalar loop cost.
To do that, LV computes the minimum trip count for which runtime check cost
+ vector-loop-cost < scalar loop cost.
Note that there is still a hard cut-off to avoid excessive compile-time/code-size
increases, but it is much larger than the original limit.
The performance impact on standard test-suites like SPEC2006/SPEC2006/MultiSource
is mostly neutral, but the new approach can give substantial gains in cases where
we failed to vectorize before due to the over-aggressive cut-offs.
On AArch64 with -O3, I didn't observe any regressions outside the noise level (<0.4%)
and there are the following execution time improvements. Both `IRSmk` and `srad` are relatively short running, but the changes are far above the noise level for them on my benchmark system.
```
CFP2006/447.dealII/447.dealII -1.9%
CINT2017rate/525.x264_r/525.x264_r -2.2%
ASC_Sequoia/IRSmk/IRSmk -9.2%
Rodinia/srad/srad -36.1%
```
`size` regressions on AArch64 with -O3 are
```
MultiSource/Applications/hbd/hbd 90256.00 106768.00 18.3%
MultiSourc...ks/ASCI_Purple/SMG2000/smg2000 240676.00 257268.00 6.9%
MultiSourc...enchmarks/mafft/pairlocalalign 472603.00 489131.00 3.5%
External/S...2017rate/525.x264_r/525.x264_r 613831.00 630343.00 2.7%
External/S...NT2006/464.h264ref/464.h264ref 818920.00 835448.00 2.0%
External/S...te/538.imagick_r/538.imagick_r 1994730.00 2027754.00 1.7%
MultiSourc...nchmarks/tramp3d-v4/tramp3d-v4 1236471.00 1253015.00 1.3%
MultiSource/Applications/oggenc/oggenc 2108147.00 2124675.00 0.8%
External/S.../CFP2006/447.dealII/447.dealII 4742999.00 4759559.00 0.3%
External/S...rate/510.parest_r/510.parest_r
14206377.00
14239433.00 0.2%
```
Reviewed By: lebedev.ri, ebrevnov, dmgreen
Differential Revision: https://reviews.llvm.org/D109368
Stella Laurenzo [Mon, 4 Jul 2022 14:06:16 +0000 (07:06 -0700)]
Fix MLIR Python CMake bug causing duplicate sources target.
The refactor in https://reviews.llvm.org/D128230 introduced a new target and the name is not scoped properly, leading to name collisions on larger projects. It is done properly on the target just below, so applying the same pattern here fixes the issue.
Nikita Popov [Mon, 4 Jul 2022 14:01:12 +0000 (16:01 +0200)]
[BPI] Avoid ConstantExpr::get()
Use ConstantFoldBinaryOpOperands() instead, to prepare for the case
where not all binary operators have a constant expression form.
I believe this code actually intended to set OnlyIfReduced=true,
however ConstantExpr::get() actually accepts a Flags argument at
that position (and OnlyIfReducedTy as the next argument), so this
ended up creating a constant expression with some random flag
(probably exact or nuw depending on which).
Valentin Clement [Mon, 4 Jul 2022 14:02:42 +0000 (16:02 +0200)]
[flang] Avoid segfault when defining op is not a fir::Convert
The previous code made the assumption that the defining
operation is a fir::ConvertOp without checking. This results in
segmentation fault in code like the added test.
Reviewed By: jeanPerier
Differential Revision: https://reviews.llvm.org/D129077
Tue Ly [Sat, 2 Jul 2022 08:50:31 +0000 (08:50 +0000)]
[libc] Add a separate algorithm_test.
Differential Revision: https://reviews.llvm.org/D128994
gbreynoo [Mon, 4 Jul 2022 13:21:45 +0000 (14:21 +0100)]
[llvm-ar][test] Add additional MRI script testing
This commit adds:
- Additional test coverage of the DELETE and END commands.
- File names to be read in the line endings test.
- A use of ADDLIB in the nonascii test.
Differential Revision: https://reviews.llvm.org/D128838
David Green [Mon, 4 Jul 2022 13:22:50 +0000 (14:22 +0100)]
[SLP] Peek into loads when hitting the RecursionMaxDepth
This patch slightly extends the limit on the RecursionMaxDepth inside
the SLP vectorizer. It does it only when it hits a load (or zext/sext of
a load), which allows it to peek through in the places where it will be
the most valuable, without ballooning out the O(..) by any 2^n factors.
Differential Revision: https://reviews.llvm.org/D122148
Nikita Popov [Mon, 4 Jul 2022 13:17:22 +0000 (15:17 +0200)]
[Reassociate] Avoid ConstantExpr::get()
Use ConstantFoldBinaryOpOperands() instead, to handle the case
where not all binary ops have a constant expression variant.
This is a bit awkward because we only want to pop the element from
Ops once we're sure that it has folded.
Nikita Popov [Mon, 4 Jul 2022 12:56:23 +0000 (14:56 +0200)]
[SCEVExpander] Avoid ConstantExpr::get() (NFCI)
Use ConstantFoldBinaryOpOperands() instead. This will be important
when not all binops have constant expression variants.
LLVM GN Syncbot [Mon, 4 Jul 2022 12:44:50 +0000 (12:44 +0000)]
[gn build] Port
25607d143d1d
Hui Xie [Sun, 26 Jun 2022 15:13:43 +0000 (16:13 +0100)]
[libc++] Implement `std::ranges::merge`
Implement `std::ranges::merge`. added unit tests
Differential Revision: https://reviews.llvm.org/D128611
David Green [Mon, 4 Jul 2022 12:38:43 +0000 (13:38 +0100)]
[VectorCombine] Improve shuffle select shuffle-of-shuffles
This in an extension to the code added in D123911 which added vector
combine folding of shuffle-select patterns, attempting to reduce the
total amount of shuffling required in patterns like:
%x = shuffle %i1, %i2
%y = shuffle %i1, %i2
%a = binop %x, %y
%b = binop %x, %y
shuffle %a, %b, selectmask
This patch extends the handing of shuffles that are dependent on one
another, which can arise from the SLP vectorizer, as-in:
%x = shuffle %i1, %i2
%y = shuffle %x
The input shuffles can also be emitted, in which case they are treated
like identity shuffles. This patch also attempts to calculate a better
ordering of input shuffles, which can help getting lower cost input
shuffles, pushing complex shuffles further down the tree.
Differential Revision: https://reviews.llvm.org/D128732
Nikita Popov [Mon, 4 Jul 2022 10:55:42 +0000 (12:55 +0200)]
[AMDGPUCodeGenPrepare] Check result of ConstantFoldBinaryOpOperands()
This function will become fallible once we don't support constant
expressions for all binops, so make sure to check the result.
Nikita Popov [Mon, 4 Jul 2022 10:49:52 +0000 (12:49 +0200)]
[ConstantFolding] Check return value of ConstantFoldInstOperandsImpl()
This operation is fallible, but ConstantFoldConstantImpl() is not.
If we fail to fold, we should simply return the original expression.
I don't think this can cause any issues right now, but it becomes
a problem if once make ConstantFoldInstOperandsImpl() not create a
constant expression for everything it possibly could.
Valentin Clement [Mon, 4 Jul 2022 10:56:47 +0000 (12:56 +0200)]
[flang] Add TODO for derived types with final procedure
Finalization is F2003 and although the runtime supports it already,
lowering is not ensuring all the derived type are finalized properly
when they should. This will require surveying the places where lowering
needs to call it. Add a hard TODO for now.
This patch is part of the upstreaming effort from fir-dev branch.
Reviewed By: jeanPerier
Differential Revision: https://reviews.llvm.org/D129069
Co-authored-by: Jean Perier <jperier@nvidia.com>
Sander de Smalen [Mon, 4 Jul 2022 09:36:13 +0000 (09:36 +0000)]
[AArch64] NFC: Move safe predicate casting to a separate function.
This patch puts the code to safely bitcast a predicate, and possibly zero
any undefined lanes when doing a widening cast, into one place and merges
the functionality with lowerConvertToSVBool.
This is some cleanup inspired by D128665.
Reviewed By: paulwalker-arm
Differential Revision: https://reviews.llvm.org/D128926
Dmitry Preobrazhensky [Mon, 27 Jun 2022 16:49:44 +0000 (19:49 +0300)]
[AMDGPU][GFX10][DOC][NFC] Update assembler syntax description
Summary of changes:
- Update MUBUF lds syntax (see https://reviews.llvm.org/D124485).
- Add v_cvt_pkrtz_f16_f32_dpp, v_cvt_pkrtz_f16_f32_sdwa.
- Update SMEM syntax (see https://reviews.llvm.org/D127314).
- Enable op_sel for v_add_nc_u16, v_sub_nc_u16 (see https://reviews.llvm.org/D123594).
- Minor bug fixing and improvements.
Simon Pilgrim [Mon, 4 Jul 2022 10:23:24 +0000 (11:23 +0100)]
[DAG] visitTRUNCATE - move GetDemandedBits AFTER SimplifyDemandedBits.
Another cleanup step before removing GetDemandedBits entirely.
Daniil Dudkin [Mon, 4 Jul 2022 10:22:12 +0000 (13:22 +0300)]
[mlir][NFC] Fix various warnings generated by GCC 9
Currently, there've been a lot of warnings while building MLIR.
This change fixes the warnings listed below.
.../SparseTensorUtils.cpp: In instantiation of ‘...::openSparseTensorCOO(...) [with ...]’:
.../SparseTensorUtils.cpp:1672:3: required from here
.../SparseTensorUtils.cpp:87:21: warning: format ‘%d’ expects argument of type ‘int’, but argument 3 has type ‘PrimaryType’ [-Wformat=]
.../OptUtils.cpp:36:5: warning: this statement may fall through [-Wimplicit-fallthrough=]
.../AffineOps.cpp:1741:32: warning: suggest parentheses around ‘&&’ within ‘||’ [-Wparentheses]
Reviewed By: aartbik, wrengr, aeubanks
Differential Revision: https://reviews.llvm.org/D128993
Chuanqi Xu [Mon, 4 Jul 2022 09:33:57 +0000 (17:33 +0800)]
[AST] Use canonical constraint declaration for ASTContext::getAutoType
When we do profiling in ASTContext::getAutoType, it wouldn't think about
the canonical declaration for the type constraint. It is bad since it
would cause a negative ODR mismatch while we already know the type
constraint declaration is a redeclaration for the previous one. Also it shouldn't be
bad to use the canonical declaration here.
Nicolas Vasilache [Fri, 1 Jul 2022 06:56:44 +0000 (23:56 -0700)]
[mlir][Tensor] Update ParallelInsertSlicOp semantics to match that of InsertSliceOp
This revision updates the op semantics to also allow rank-reducing behavior as well
as updates the implementation to reuse code between the sequential and the parallel
version of the op.
Depends on D128920
Differential Revision: https://reviews.llvm.org/D128985
Haojian Wu [Mon, 4 Jul 2022 09:30:11 +0000 (11:30 +0200)]
[pseudo] Remove duplicated code in ClangPseudo.cpp
The code was added accidently during the rebase when landing
fe66aebd.
Edd Barrett [Mon, 4 Jul 2022 06:02:25 +0000 (07:02 +0100)]
Revise outdated parts of the developer policy.
Specifically:
- Diffs are not passed around on mailing lists any more.
- Diffs should be `-U999999`.
- Clarify part about automated emails.
Differential review: https://reviews.llvm.org/D128645
Nikolas Klauser [Sun, 3 Jul 2022 23:21:44 +0000 (01:21 +0200)]
[libc++][NFC] Replace enable_if with __enable_if_t in a few places
Reviewed By: ldionne, #libc
Spies: jloser, libcxx-commits
Differential Revision: https://reviews.llvm.org/D128400
Nikita Popov [Mon, 4 Jul 2022 08:52:12 +0000 (10:52 +0200)]
[SimplifyCFG] Remove redundant checks for hoisting (NFCI)
These conditions are later checked in the HoistTerminator code
path. Checking them here is somewhat confusing, because this code
only checks the first instruction in the block, which is not
necessarily the terminator.
Nicolas Vasilache [Thu, 30 Jun 2022 11:27:41 +0000 (04:27 -0700)]
[mlir][Tensor] Move ParallelInsertSlice to the tensor dialect
This is moslty NFC and will allow tensor.parallel_insert_slice to gain
rank-reducing semantics by reusing the vast majority of the tensor.insert_slice impl.
Depends on D128857
Differential Revision: https://reviews.llvm.org/D128920
Florian Hahn [Mon, 4 Jul 2022 08:29:21 +0000 (09:29 +0100)]
[AArch64] Add additional tests for D120481.
Florian Hahn [Mon, 4 Jul 2022 08:25:26 +0000 (09:25 +0100)]
[LV] Simplify setDebugLocFromInst by using early exit (NFC).
Suggested as separate improvement in D128657.
Nikita Popov [Tue, 28 Jun 2022 09:25:54 +0000 (11:25 +0200)]
[IR] Remove support for insertvalue constant expression
This removes the insertvalue constant expression, as part of
https://discourse.llvm.org/t/rfc-remove-most-constant-expressions/63179.
This is very similar to the extractvalue removal from D125795.
insertvalue is also not supported in bitcode, so no auto-ugprade
is necessary.
ConstantExpr::getInsertValue() can be replaced with
IRBuilder::CreateInsertValue() or ConstantFoldInsertValueInstruction(),
depending on whether a constant result is required (with the latter
being fallible).
The ConstantExpr::hasIndices() and ConstantExpr::getIndices()
methods also go away here, because there are no longer any constant
expressions with indices.
Differential Revision: https://reviews.llvm.org/D128719
Shraiysh Vaishay [Mon, 4 Jul 2022 05:08:58 +0000 (10:38 +0530)]
[mlir][openmp] Added omp.taskloop
This patch adds omp.taskloop operation to OpenMP Dialect along with
tests.
Reviewed By: peixin
Differential Revision: https://reviews.llvm.org/D127380
Craig Topper [Mon, 4 Jul 2022 04:07:25 +0000 (21:07 -0700)]
[RISCV] Add more SHXADD patterns.
This handles the code we get for this.
int foo(unsigned x, int *y) {
return y[x >> 3];
}
The srl and shl implied by the array index will be combined to
form (srl (and X, C2), C1). We need to reverse this get to back
the shl to fold into SHXADD.
Craig Topper [Sun, 3 Jul 2022 21:41:36 +0000 (14:41 -0700)]
[RISCV] Move some SHXADD matching cases into a ComplexPattern. NFC
Some more complex cases require checking the relationship of
operands on different nodes of the match. They also require
additional instructions to be created. Using a ComplexPattern
gives us that flexibility.
I'll be adding another pattern in a future patch.
Argyrios Kyrtzidis [Sat, 2 Jul 2022 00:18:00 +0000 (17:18 -0700)]
[Driver] Ignore the clang modules validation-related flags if clang modules are not enabled
If clang modules are not enabled it becomes unnecessary to read the session timestamp file in order
to pass `-fbuild-session-timestamp` to the `cc1` invocation.
Differential Revision: https://reviews.llvm.org/D129030
esmeyi [Mon, 4 Jul 2022 03:16:16 +0000 (23:16 -0400)]
[AIX] Handling the label alignment of a global
variable with its multiple aliases.
This patch handles the case where a variable has
multiple aliases.
AIX's assembly directive .set is not usable for the
aliasing purpose, and using different labels allows
AIX to emulate symbol aliases. If a value is emitted
between any two labels, meaning they are not aligned,
XCOFF will automatically calculate the offset for them.
This patch implements:
1) Emits the label of the alias just before emitting
the value of the sub-element that the alias referred to.
2) A set of aliases that refers to the same offset
should be aligned.
3) We didn't emit aliasing labels for common and
zero-initialized local symbols in
PPCAIXAsmPrinter::emitGlobalVariableHelper, but
emitted linkage for them in
AsmPrinter::emitGlobalAlias, which caused a FAILURE.
This patch fixes the bug by blocking emitting linkage
for the alias without a label.
Reviewed By: shchenz
Differential Revision: https://reviews.llvm.org/D124654
jacquesguan [Fri, 1 Jul 2022 07:08:58 +0000 (15:08 +0800)]
[mlir][Vector] Fold ShuffleOp(SplatOp(X), SplatOp(X)) to SplatOp(X).
This patch folds ShuffleOp(SplatOp(X), SplatOp(X)) to SplatOp(X).
Differential Revision: https://reviews.llvm.org/D128969
Chen Zheng [Wed, 29 Jun 2022 09:21:04 +0000 (05:21 -0400)]
[SCEV] recognize llvm.annotation intrinsic
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D127835
Nicolas van Kempen [Sun, 3 Jul 2022 22:27:57 +0000 (16:27 -0600)]
[clang-tidy] Properly forward clang-tidy output when running tests
When running tests, the check_clang_tidy script encodes the output
string, making it hard to read when debugging checks. This removes the
.encode() call.
Test Plan:
Making a new default check for testing (as of right now, it includes a
failing test):
[~/llvm-project/clang-tools-extra] python3 clang-tidy/add_new_check.py
bugprone example
<...>
Pre-changes:
[~/llvm-project/build] ninja check-clang-tools
<...>
------------------------ clang-tidy output -----------------------
b"1 warning
generated.\n/data/users/nvankempen/llvm-project/build/Debug/tools/clang/tools/extra/test/clang-tidy/checkers/Output/bugprone-example.cpp.tmp.cpp:4:6:
warning: function 'f' is insufficiently awesome [bugprone-example]\nvoid
f();\n
^\n/data/users/nvankempen/llvm-project/build/Debug/tools/clang/tools/extra/test/clang-tidy/checkers/Output/bugprone-example.cpp.tmp.cpp:4:6:
note: insert 'awesome'\nvoid f();\n ^\n awesome_\n"
------------------------------------------------------------------
<...>
Post-changes:
[~/llvm-project/build] ninja check-clang-tools
<...>
------------------------ clang-tidy output -----------------------
1 warning generated.
/data/users/nvankempen/llvm-project/build/Debug/tools/clang/tools/extra/test/clang-tidy/checkers/Output/bugprone-example.cpp.tmp.cpp:4:6:
warning: function 'f' is insufficiently awesome [bugprone-example]
void f();
^
/data/users/nvankempen/llvm-project/build/Debug/tools/clang/tools/extra/test/clang-tidy/checkers/Output/bugprone-example.cpp.tmp.cpp:4:6:
note: insert 'awesome'
void f();
^
awesome_
------------------------------------------------------------------
<...>
Differential Revision: https://reviews.llvm.org/D127807
Ishaan Gandhi [Sun, 3 Jul 2022 20:42:31 +0000 (14:42 -0600)]
[clang-tidy] Don't treat invalid branches as identical
The clang-tidy check bugprone-branch-clone has a false positive if some
symbols are undefined. This patch silences the warning when the two
sides of a branch are invalid.
Fixes #56057
Differential Revision: https://reviews.llvm.org/D128402
Sunho Kim [Sun, 3 Jul 2022 20:30:56 +0000 (05:30 +0900)]
[clang] Fix gcc-6 compilation error. (NFC)
Fix https://github.com/llvm/llvm-project/issues/55626.
Differential Revision: https://reviews.llvm.org/D129049
Nico Weber [Fri, 1 Jul 2022 11:37:29 +0000 (13:37 +0200)]
[clang-format] Tweak help text a bit
In particular, make it clear that `--style=file` is the default,
since there's some confusion about this, e.g. here:
https://stackoverflow.com/questions/
61455148/
Differential Revision: https://reviews.llvm.org/D128984
Sanjay Patel [Sun, 3 Jul 2022 16:23:29 +0000 (12:23 -0400)]
[InstCombine] fold negated low-bit-mask to cmp+select
(-(X & 1)) & Y --> (X & 1) == 0 ? 0 : Y
https://alive2.llvm.org/ce/z/rhpH3i
This is noted as a missing IR canonicalization in issue #55618.
We already managed to fix codegen to the expected form.
Sanjay Patel [Sun, 3 Jul 2022 15:03:16 +0000 (11:03 -0400)]
[InstCombine] add tests for and-of-negated-lowbitmask; NFC
LLVM GN Syncbot [Sun, 3 Jul 2022 16:05:49 +0000 (16:05 +0000)]
[gn build] Port
2aea8af25136
Nikolas Klauser [Sun, 3 Jul 2022 14:52:22 +0000 (16:52 +0200)]
[libc++] Make _LIBCPP_DEBUG_RANDOMIZE_RANGE a function
Reviewed By: ldionne, Mordante, var-const, #libc
Spies: mgorny, libcxx-commits
Differential Revision: https://reviews.llvm.org/D128181
Craig Topper [Sun, 3 Jul 2022 15:57:51 +0000 (08:57 -0700)]
[RISCV] Replace call to APInt::countTrailingZeros with uint64_t verson. NFC
We know the number of bits is 64 or 32 so we can use the uint64_t
version directly. This saves the APInt needing to check for the
small vs large size.
Groverkss [Sun, 3 Jul 2022 15:22:35 +0000 (16:22 +0100)]
[MLIR][Affine] Allow affine-expr on RHS in IntegerSet
Currently, the parser for IntegerSet, only allows constraints like:
```
affine-constraint ::= affine-expr `>=` `0`
| affine-expr `==` `0`
```
This form is sometimes unreadable and painful to use when writing unittests
for Presburger library and tests in general.
This patch extends the parser to allow affine constraints with affine-expr on
the RHS:
```
affine-constraint ::= affine-expr `>=` `affine-expr`
| affine-expr `==` `affine-expr`
```
The internal storage and printing of IntegerSet is still in the original format.
Reviewed By: bondhugula
Differential Revision: https://reviews.llvm.org/D128915
David Green [Sun, 3 Jul 2022 14:49:16 +0000 (15:49 +0100)]
[AArch64] Regenerate more tests. NFC
Also includes some adjustments for asm.py to handle updating more cases
successfully.
Nuno Lopes [Sun, 3 Jul 2022 13:33:47 +0000 (14:33 +0100)]
[NFC] Switch a few uses of undef to poison as placeholders for unreachble code
luxufan [Sat, 18 Jun 2022 15:44:09 +0000 (23:44 +0800)]
[RISCV] Add a scavenge spill slot when use ADDI to compute scalable stack offset
Computing scalable offset needs up to two scrach registers. We add
scavenge spill slots according to the result of `RISCV::isRVVSpill`
and `RVVStackSize`. Since ADDI is not included in `RISCV::isRVVSpill`,
PEI doesn't add scavenge spill slots for scrach registers when using
ADDI to get scalable stack offsets.
The ADDI instruction has a destination register which can be used as
a scrach register. So one scavenge spil slot is sufficient for
computing scalable stack offsets.
Differential Revision: https://reviews.llvm.org/D128188
Jun Zhang [Sun, 3 Jul 2022 11:40:56 +0000 (19:40 +0800)]
Revert "Reland "[NFC] Add a missing test for for clang-repl""
This reverts commit
8679cbc29fb76195544956fe233060bb7a1a6453.
See https://lab.llvm.org/buildbot/#/builders/216/builds/6799
Nuno Lopes [Sun, 3 Jul 2022 10:56:29 +0000 (11:56 +0100)]
[LowerMatrixMultiplication] Switch dummy values from undef to poison [NFC]
Jun Zhang [Sun, 3 Jul 2022 10:04:52 +0000 (18:04 +0800)]
Reland "[NFC] Add a missing test for for clang-repl"
This reverts
3668d1264e2d246f7e222338b8a5cab18ce1bdab
As far as we know, `__attribute__((weak))` support has been really bad
in runtimeldyld, so we just disable it in Windows at this moment. This
should fix the angry Windows buildbot.
Differential Revision: https://reviews.llvm.org/D129042
Serge Pavlov [Fri, 1 Jul 2022 11:32:26 +0000 (18:32 +0700)]
[FPEnv] Allow CompoundStmt to keep FP options
This is a recommit of
b822efc7404bf09ccfdc1ab7657475026966c3b2,
reverted in
dc34d8df4c48b3a8f474360970cae8a58e6c84f0. The commit caused
fails because the test ast-print-fp-pragmas.c did not specify particular
target, and it failed on targets which do not support constrained
intrinsics. The original commit message is below.
AST does not have special nodes for pragmas. Instead a pragma modifies
some state variables of Sema, which in turn results in modified
attributes of AST nodes. This technique applies to floating point
operations as well. Every AST node that can depend on FP options keeps
current set of them.
This technique works well for options like exception behavior or fast
math options. They represent instructions to the compiler how to modify
code generation for the affected nodes. However treatment of FP control
modes has problems with this technique. Modifying FP control mode
(like rounding direction) usually requires operations on hardware, like
writing to control registers. It must be done prior to the first
operation that depends on the control mode. In particular, such
operations are required for implementation of `pragma STDC FENV_ROUND`,
compiler should set up necessary rounding direction at the beginning of
compound statement where the pragma occurs. As there is no representation
for pragmas in AST, the code generation becomes a complicated task in
this case.
To solve this issue FP options are kept inside CompoundStmt. Unlike to FP
options in expressions, these does not affect any operation on FP values,
but only inform the codegen about the FP options that act in the body of
the statement. As all pragmas that modify FP environment may occurs only
at the start of compound statement or at global level, such solution
works for all relevant pragmas. The options are kept as a difference
from the options in the enclosing compound statement or default options,
it helps codegen to set only changed control modes.
Differential Revision: https://reviews.llvm.org/D123952
NAKAMURA Takumi [Sun, 3 Jul 2022 06:23:10 +0000 (15:23 +0900)]
[Bazel] Make `builtin_headers_gen` as subset of CMake's `clang-resource-headers`
At the moment, two files are not installed by CMake.
- `lib/Headers/openmp_wrappers/time.h`
- `lib/Headers/ppc_wrappers/nmmintrin.h`
`builtin_headers_gen` is available as the source of rules_pkg.
The difference of the layout of installed headers makes cache hit harder.
Craig Topper [Sun, 3 Jul 2022 06:11:14 +0000 (23:11 -0700)]
[RISCV] Add more SHXADD isel patterns.
This handles the code we get for
int foo(int* x, unsigned y) {
return x[y >> 1];
}
The shift right and the shl will get DAG combined into
(shl (and X, 0xfffffffe), 1). We have custom isel to match the
shl+and, but with Zba the (add (shl X, 1), Y) part will get
matched and leave the and to be iseled by itself. This commit
adds a larger pattern that includes the and.
Vitaly Buka [Sun, 3 Jul 2022 03:14:51 +0000 (20:14 -0700)]
[lsan] malloc_usable_size returns 0 for nullptr
lewuathe [Sun, 3 Jul 2022 00:26:41 +0000 (09:26 +0900)]
[mlir][complex] Inverse canonicalization between exp and log
We can canonicalize consecutive complex.exp and complex.log which are inverse functions each other.
Reviewed By: bixia
Differential Revision: https://reviews.llvm.org/D128966
Craig Topper [Sat, 2 Jul 2022 16:51:00 +0000 (09:51 -0700)]
[RISCV] Match RISCVISD::ADD_LO in SelectAddrRegImm.
This allows us to fold global and constant pool addresses into
load/store during isel instead of in the post-isel peephole. I
did not copy the alignment check for ConsantPoolSDNode because it
wasn't tested.
This is a step towards being able to remove the post-isel
peephole.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D128738
Florian Hahn [Sat, 2 Jul 2022 14:18:16 +0000 (15:18 +0100)]
[VPlan] Move setDebugLocFromInst to VPTransformState (NFC).
The moved helpers are only used for codegen. It will allow moving the
remaining ::execute implementations out of LoopVectorize.cpp.
Reviewed By: Ayal
Differential Revision: https://reviews.llvm.org/D128657
Luo, Yuanke [Sat, 2 Jul 2022 08:49:02 +0000 (16:49 +0800)]
[globalisel] Add test case for regbank selection.
lorenzo chelini [Fri, 1 Jul 2022 18:21:09 +0000 (20:21 +0200)]
[MLIR] Rename FusePadOpWithLinalgConsumer -> FusePadOpWithLinalgProducer (NFC)
Follow up after D128978, where I mistakenly rename the file. The linalg op is
fused with its producer, not the consumer.
Craig Topper [Sat, 2 Jul 2022 07:57:35 +0000 (00:57 -0700)]
[RISCV] isel (shl (and X, C2), C) -> (slli (srliw X, C3), C3+C).
where C2 has 32 leading zeros and C3 trailing zeros.
When the shl is used by an add C is 1,2 or 3, we end up matching
(add (shl X, C), Y) first. This leaves an and with a constant that
is harder to materialize.