Dave Airlie [Fri, 21 Apr 2017 02:38:05 +0000 (03:38 +0100)]
radv/ac: eliminate unused vertex shader outputs. (v2)
This is ported from radeonsi, and I can see at least one
Talos shader drops an export due to this, and saves some
VGPR usage.
v2: use shared code.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 25 Apr 2017 22:33:29 +0000 (23:33 +0100)]
radeonsi/ac: move vertex export remove to common code.
This code can be shared by radv, we bump the max to
VARYING_SLOT_MAX here, but that shouldn't have too
much fallout.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 26 Apr 2017 23:31:29 +0000 (09:31 +1000)]
radv: fix regression in descriptor set freeing.
Since the host pool changes,
Fixes:
dEQP-VK.api.descriptor_pool.out_of_pool_memory
Fixes: 126d5ad "radv: Use host memory pool for non-freeable descriptors."
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Timothy Arceri [Wed, 26 Apr 2017 03:56:45 +0000 (13:56 +1000)]
glsl: remove duplicate validation
Varying types have already been validated in
apply_type_qualifier_to_variable() by this point.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Timothy Arceri [Wed, 26 Apr 2017 03:56:44 +0000 (13:56 +1000)]
glsl: use without_array() rather than get_scalar_type()
Here get_scalar_type() was just being use to remove the array
after that we converted it back to base_type anyway so just
use the without_array() helper.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Brian Paul [Tue, 25 Apr 2017 14:02:28 +0000 (08:02 -0600)]
svga: fix vertex buffer binding issue
When we ran Viewperf11's Maya-03 test 3 we saw warnings about flushing
the command buffer with mapped buffers. This happened when transitioning
from hardware rendering to a 'draw' fallback path.
The problem is the util_set_vertex_buffers_count() function doesn't do
exactly what we want in svga_hwtnl_vertex_buffers(). In a case such as
dst_count=2, dst={bufA, bufB}, count=1 and src={bufC}, when the function
returns we'll have dst_count=2 and dst={bufC, bufB}. What we really want
is dst_count=1 and dst={bufC, NULL}. As it was, we were telling the svga
device that there were two vertex buffers when in fact we really only
needed one for the subsequent drawing command.
In this particular case, we first did hardware drawing with {bufA, bufB}
then we transitioned to the 'draw' module, consuming vertex data from
bufA and bufB and writing the new vertex data to bufC. bufA and bufB are
mapped for reading when we flush the command buffer but should not be
referenced by the command buffer. The above change fixes that.
No Piglit regressions. Also tested with Viewperf, Google Earth, Heaven,
etc.
VMware bug 1842059
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Mon, 24 Apr 2017 18:58:22 +0000 (12:58 -0600)]
gallium/util: reduce util_snprintf() calls in debug_flush_might_flush_cb()
We only need to construct the debug message if the mapped_sync flag is set.
This should make the function faster since the flag is usually false.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Mon, 24 Apr 2017 18:57:14 +0000 (12:57 -0600)]
gallium/util: add some comments in u_debug_flush.c
Trivial.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Charmaine Lee [Thu, 20 Apr 2017 18:40:00 +0000 (11:40 -0700)]
svga: Removed the unused label 'done' in svga_validate_surface_view()
Trivial fix
Charmaine Lee [Thu, 20 Apr 2017 01:34:36 +0000 (18:34 -0700)]
svga: use the winsys interface to invalidate surface
Instead of directly sending the InvalidateGBSurface command,
this patch uses the invalidate_surface interface.
Fixes Linux VM piglit failures including
ext_texture_array-gen-mipmap, fbo-generatemipmap-array S3TC_DXT1
Reviewed-by: Brian Paul <brianp@vmware.com>
Charmaine Lee [Tue, 18 Apr 2017 22:55:59 +0000 (15:55 -0700)]
svga: fix format for screen target
This patch revises the fix in commit
606f13afa31c9f041a68eb22cc32112ce813f944
to properly translate the surface format for screen target.
Instead of changing the svga format for PIPE_FORMAT_B5G6R5_UNORM
to SVGA3D_R5G6B5 for all texture surfaces, this patch only restricts
SVGA3D_R5G6B5 for screen target surfaces. This avoids rendering
failures when specify a non-vgpu10 format in a vgpu10 context with
software renderer.
Fixes piglit failures spec@!opengl 1.1@draw-pixels,
spec@!opengl 1.1@teximage-colors gl_r3_g3_b2
spec@!opengl 1.1@texwrap formats
Tested Xorg with 16bits depth.
Also tested with MTT piglit, MTT glretrace.
Reviewed-by: Brian Paul <brianp@vmware.com>
Charmaine Lee [Tue, 25 Apr 2017 20:32:59 +0000 (14:32 -0600)]
svga: cache the backing surface handle in the texture object
CinebenchR15 not only binds the same texture for rendering and sampling,
it actually changes the framebuffer buffer attachment very often, causing
a lot of backed surface view to be created and a lot of surface copies
to be done. This patch caches the backed surface handle
in the texture resource and allows the backed surface view to
reuse the backed surface handle. With this patch, the number of
backed surface view reduces from 1312 to 3. Unfortunately, this
does not eliminate all the surface copies. There are still surface
copies involved when we switch from original to backed surface handle
for rendering.
Tested with CinebenchR15, NobelClinicianViewer, Turbine, Lightsmark2008,
MTT glretrace, MTT piglit.
Reviewed-by: Brian Paul <brianp@vmware.com>
Charmaine Lee [Tue, 25 Apr 2017 20:31:04 +0000 (14:31 -0600)]
svga: Update the backing resource only if needed
This patch adds a timestamp in svga_surface structure to keep track
of when the backing surface is last sync with the original resource.
This helps to avoid unnecessary surface copy from the original
resource to the backing surface if the original resource has not
since been modified.
This reduces the amount of surface copy with CinebenchR15.
Tested with CinebenchR15, mtt glretrace.
Reviewed-by: Brian Paul <brianp@vmware.com>
Charmaine Lee [Thu, 13 Apr 2017 22:12:25 +0000 (15:12 -0700)]
svga: Set the surface dirty bit for the right surface view
For VGPU10, we will render to a backed surface view when
the same resource is used for rendering and sampling.
In this case, we will mark the dirty bit for the backed surface view.
Reviewed-by: Brian Paul <brianp@vmware.com>
Charmaine Lee [Tue, 25 Apr 2017 20:27:51 +0000 (14:27 -0600)]
svga: Move rendertarget view related fields to hw_clear state
This patch moves the rendertarget view related fields from
svga_hw_draw_state to svga_hw_clear_state where all the hw
framebuffer related state resides.
Reviewed-by: Brian Paul <brianp@vmware.com>
Charmaine Lee [Wed, 12 Apr 2017 23:21:51 +0000 (16:21 -0700)]
svga: Move setting the rendered_to flags to framebuffer emit time
Instead of setting the rendered_to flags at set time, this patch
moves the setting of the flags to framebuffer emit time.
Reviewed-by: Brian Paul <brianp@vmware.com>
Brian Paul [Mon, 10 Apr 2017 21:02:05 +0000 (15:02 -0600)]
svga: add const qualifiers on svga_check_sampler_view_resource_collision()
We don't change any of the argument objects.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Mon, 10 Apr 2017 19:51:48 +0000 (13:51 -0600)]
svga: improve surface view debug messages
The old ones were somewhat cryptic.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Mon, 10 Apr 2017 19:48:21 +0000 (13:48 -0600)]
svga: add DEBUG_SAMPLERS
The debug output in svga_create_sampler_state() was controlled by
DEBUG_VIEWS but that's not consistent with the other debug output for
sampler views. Create/use a new debug flag just for this.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Thu, 6 Apr 2017 20:55:53 +0000 (14:55 -0600)]
svga: fail screen creation if HW version is too old
Tested by verifying 3D acceleration works with HWv8 but not earlier.
For HWv7 and older we get the GDI Generic renderer.
Reviewed-by: Neha Bhende<bhenden@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Deepak Rawat [Mon, 3 Apr 2017 15:12:43 +0000 (08:12 -0700)]
winsys/svga: fix error path when kernel is not able to create surface
If for some reason kernel is not able to create surface,
when no buffer was provided the function
vmw_svga_winsys_surface_create should return NULL.
This patch fixes the issue where the code was not following the
clean up path in case of error, which used to cause SIGSEGV.
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
Brian Paul [Tue, 25 Apr 2017 00:51:05 +0000 (18:51 -0600)]
draw: whitespace fixes in draw_pipe_vbuf.c
Remove trailing whitespace, fix formatting, etc. Trivial.
Brian Paul [Fri, 21 Apr 2017 19:46:28 +0000 (13:46 -0600)]
st/mesa: minor clean-ups in st_update_renderbuffer_surface()
Remove unneeded parens. Add const qualifiers. Move var decls closer
to where they're used.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Neha Bhende<bhenden@vmware.com>
Samuel Pitoiset [Mon, 24 Apr 2017 22:31:49 +0000 (00:31 +0200)]
nv50,nvc0: disable the TGSI merge registers pass
shader-db results on GK106 (Thanks Karol):
total instructions in shared programs : 3931608 -> 3929463 (-0.05%)
total gprs used in shared programs : 481255 -> 479014 (-0.47%)
total local used in shared programs : 27481 -> 27381 (-0.36%)
total bytes used in shared programs :
36031256 ->
36011120 (-0.06%)
local gpr inst bytes
helped 14 1471 1309 1309
hurt 1 88 384 384
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Mon, 24 Apr 2017 22:31:48 +0000 (00:31 +0200)]
radeonsi: disable the TGSI merge registers pass
47109 shaders in 29632 tests
Totals:
SGPRS: 1917364 -> 1916620 (-0.04 %)
VGPRS: 1165802 -> 1165202 (-0.05 %)
Spilled SGPRs: 1880 -> 1843 (-1.97 %)
Spilled VGPRs: 70 -> 65 (-7.14 %)
Private memory VGPRs: 1184 -> 1184 (0.00 %)
Scratch size: 1312 -> 1308 (-0.30 %) dwords per thread
Code Size:
60211356 ->
60192268 (-0.03 %) bytes
LDS: 1077 -> 1077 (0.00 %) blocks
Max Waves: 428597 -> 428674 (0.02 %)
Wait states: 0 -> 0 (0.00 %)
Totals from affected shaders:
SGPRS: 238173 -> 237429 (-0.31 %)
VGPRS: 149556 -> 148956 (-0.40 %)
Spilled SGPRs: 1263 -> 1226 (-2.93 %)
Spilled VGPRs: 25 -> 20 (-20.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 20 -> 16 (-20.00 %) dwords per thread
Code Size:
10457904 ->
10438816 (-0.18 %) bytes
LDS: 50 -> 50 (0.00 %) blocks
Max Waves: 41283 -> 41360 (0.19 %)
Wait states: 0 -> 0 (0.00 %)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Samuel Pitoiset [Mon, 24 Apr 2017 22:31:47 +0000 (00:31 +0200)]
st/glsl_to_tgsi: disable the merge registers pass conditionally
The main goal of this pass to merge temporary registers in order
to reduce the total number of registers and also to produce
optimal TGSI code.
In fact, compilers seem to be confused when temporary variables
are already merged, maybe because it's done too early in the
process.
Skipping the pass, reduce both the register pressure and the code
size, at least for Nouveau and RadeonSI because they have a real
backend compiler.
Found by luck while fixing an issue in the TGSI dead code elimination
pass which affects tex instructions with bindless samplers.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Samuel Pitoiset [Mon, 24 Apr 2017 22:31:46 +0000 (00:31 +0200)]
gallium: add PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Samuel Pitoiset [Tue, 25 Apr 2017 22:36:12 +0000 (00:36 +0200)]
radeonsi: use unsynchronized transfers for shader binary uploads
Because the buffer is new, it can't be referenced by any CS.
This can save few CPU cycles by skipping the whole
PIPE_TRANSFER_UNSYNCHRONIZED if in amdgpu_bo_map().
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Marek Olšák [Tue, 14 Feb 2017 21:23:04 +0000 (22:23 +0100)]
radeonsi: turn si_shader_key::mono into a non-union
A merged LS-HS shader needs both fix_fetch and inputs_to_copy
for compilation.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 22 Apr 2017 12:47:03 +0000 (14:47 +0200)]
radeonsi: adjust ESGS ring buffer size computation on VI
Cc: 17.0 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 23 Apr 2017 18:29:04 +0000 (20:29 +0200)]
radeonsi/gfx9: don't set deprecated field PARTIAL_ES_WAVE_ON
Cc: 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 23 Apr 2017 18:14:42 +0000 (20:14 +0200)]
radeonsi/gfx9: set MAX_PRIMGRP_IN_WAVE in the correct register
Cc: 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 23 Apr 2017 22:01:06 +0000 (00:01 +0200)]
radeonsi/gfx9: add a workaround for viewing a slice of 3D as a 2D image
Cc: 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 23 Apr 2017 21:29:20 +0000 (23:29 +0200)]
radeonsi/gfx9: fix 1D array shader images
Cc: 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 23 Apr 2017 21:06:38 +0000 (23:06 +0200)]
radeonsi/gfx9: fix most things wrong with shader images
There are 2 major hw changes:
- The address must always point to the address of level 0. GFX9 tiling
modes don't allow binding to a non-0 level.
- 3D must always be bound as 3D, because 2D and 3D use entirely different
tiling modes, and the texture target determines which set of modes is
used.
Cc: 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 23 Apr 2017 19:32:22 +0000 (21:32 +0200)]
radeonsi/gfx9: fix texture buffer objects and image buffers with IDXEN==0
Cc: 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Eric Engestrom [Tue, 25 Apr 2017 20:15:55 +0000 (21:15 +0100)]
configure: print LDFLAGS alongside CFLAGS & co.
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Sat, 22 Apr 2017 07:30:27 +0000 (17:30 +1000)]
mesa: tidy up left over APPLE_vertex_array_object semantics
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Sat, 22 Apr 2017 07:10:09 +0000 (17:10 +1000)]
mesa: inline bind_vertex_array() helper
The previous commit removed the only other user of this function.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Sat, 22 Apr 2017 07:01:15 +0000 (17:01 +1000)]
mesa: drop APPLE_vertex_array_object support
Shared context support for VAOs was dropped in
0b2750620b65.
From the ARB_vertex_array_object spec:
"This extension differs from GL_APPLE_vertex_array_object
in that client memory cannot be accessed through a
non-zero vertex array object. It also differs in that
vertex array objects are explicitly not sharable between
contexts."
Nobody should be using this extension over
ARB_vertex_array_object anymore so just drop it rather than
adding locking back just for VAOs created from these
functions.
For reference the Nvidia blob doesn't expose this extension.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Bas Nieuwenhuizen [Tue, 25 Apr 2017 22:04:46 +0000 (00:04 +0200)]
radv: Enable userspace fence checking.
v2: - Added some error handling.
- memset the buffer to 0.
v3: Added assert for buffer size.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Matt Turner [Tue, 25 Apr 2017 17:13:57 +0000 (10:13 -0700)]
i965: Remove unused variable 'options'
Should have been removed in commit
ad55b1a7701a
Matt Turner [Tue, 25 Apr 2017 17:12:03 +0000 (10:12 -0700)]
glsl: Initialize current_var
CID: 1324644 (Uninitialized pointer field)
Dave Airlie [Sun, 23 Apr 2017 18:52:34 +0000 (19:52 +0100)]
radv/ac: setup mrt exports then export them in one go. (v2)
Noticed while looking at Sascha Willems deferred shaders.
This is a bit of an llvm workaround, llvm was producing this:
v_cvt_pkrtz_f16_f32_e64 v4, v7, v8 ;
D2960004 00021107
v_cvt_pkrtz_f16_f32_e64 v6, v9, 1.0 ;
D2960006 0001E509
s_waitcnt vmcnt(0) ;
BF8C0F70
exp mrt0 v4, v4, v6, v6 compr ;
C400040F 00000604
s_waitcnt expcnt(0) ;
BF8C0F0F
v_cvt_pkrtz_f16_f32_e64 v4, v12, v5 ;
D2960004 00020B0C
v_cvt_pkrtz_f16_f32_e64 v5, v14, 1.0 ;
D2960005 0001E50E
exp mrt1 v4, v4, v5, v5 compr ;
C400041F 00000504
s_waitcnt expcnt(0) ;
BF8C0F0F
v_cvt_pkrtz_f16_f32_e64 v0, v0, v1 ;
D2960000 00020300
v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ;
D2960001 00020702
exp mrt2 v0, v0, v1, v1 done compr vm ;
C4001C2F 00000100
After this change:
v_cvt_pkrtz_f16_f32_e64 v4, v7, v8 ;
D2960004 00021107
s_waitcnt vmcnt(0) ;
BF8C0F70
v_cvt_pkrtz_f16_f32_e64 v0, v0, v1 ;
D2960000 00020300
v_cvt_pkrtz_f16_f32_e64 v6, v9, 1.0 ;
D2960006 0001E509
v_cvt_pkrtz_f16_f32_e64 v5, v12, v5 ;
D2960005 00020B0C
v_cvt_pkrtz_f16_f32_e64 v7, v14, 1.0 ;
D2960007 0001E50E
exp mrt0 v4, v4, v6, v6 compr ;
C400040F 00000604
v_cvt_pkrtz_f16_f32_e64 v1, v2, v3 ;
D2960001 00020702
exp mrt1 v5, v5, v7, v7 compr ;
C400041F 00000705
exp mrt2 v0, v0, v1, v1 done compr vm ;
C4001C2F 00000100
No waitcnt for exports are emitted.
v2: fixup index->mrt mapping (Bas).
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 21 Apr 2017 02:17:23 +0000 (03:17 +0100)]
radv/ac: overhaul vs output/ps input routing
In order to cleanly eliminate exports rewrite the
code first to mirror how radeonsi works for now.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 21 Apr 2017 02:02:46 +0000 (03:02 +0100)]
radv/ac: move point coord after layer/viewport.
These need to be ordered as per shader enum ordering, I'll
rewrite this soon, but this is a bug fix.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Samuel Pitoiset [Mon, 24 Apr 2017 23:10:50 +0000 (01:10 +0200)]
gallium: remove u_caps.c/h interface
No longer used.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 16 Apr 2017 20:04:57 +0000 (22:04 +0200)]
ddebug: implement get_query_result_resource
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 16 Apr 2017 18:09:03 +0000 (20:09 +0200)]
trace: don't trace resource_destroy
due to the lack of pipe_resource wrapping, we can get this call from inside
of driver calls, which would try to lock an already-locked mutex.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 22 Apr 2017 21:44:46 +0000 (23:44 +0200)]
gallium/util: add debugging helpers printing pipeline statistics
typically useful for hw bring-up
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Rob Herring [Mon, 24 Apr 2017 16:46:58 +0000 (11:46 -0500)]
Android: fix r300g only build
If r300g is the only radeon driver built, the Android build fails to
build:
ninja: error:
'out/target/product/linaro_x86_64/obj/STATIC_LIBRARIES/libmesa_pipe_radeon_intermediates/export_includes',
needed by
'out/target/product/linaro_x86_64/obj/SHARED_LIBRARIES/gallium_dri_intermediates/import_includes',
missing and no known rule to make it
This is because the path to build libmesa_pipe_radeon was only getting
added for r600g and radeonsi, but the library dependency was added for
all radeon drivers. As libmesa_pipe_radeon is not needed for r300g, drop
the library dependency.
Cc: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Emil Velikov <emil.velikov@collabora.com>
Timothy Arceri [Mon, 24 Apr 2017 05:59:24 +0000 (15:59 +1000)]
mesa: use locked version of HashWalk for xfb objects
From Chapter 5 'Shared Objects and Multiple Contexts' of
the OpenGL 4.5 spec:
"Objects which contain references to other objects include
framebuffer, program pipeline, query, transform feedback,
and vertex array objects. Such objects are called container
objects and are not shared"
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Mon, 24 Apr 2017 05:59:23 +0000 (15:59 +1000)]
mesa: create locked version of HashWalk
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Rafael Antognolli [Fri, 21 Apr 2017 22:11:17 +0000 (15:11 -0700)]
genxml: Fix gen_pack_header.py crash when field type is invalid.
Just return earlier in that case. Also set prefix to an empty string, so
we don't get to use it undefined.
Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rafael Antognolli [Thu, 30 Mar 2017 18:33:05 +0000 (11:33 -0700)]
genxml: Make BLEND_STATE command support variable length array.
We need to emit BLEND_STATE, which size is 1 + 2 * nr_draw_buffers
dwords (on gen8+), but the BLEND_STATE struct length is always 17. By
marking it size 1, which is actually the size of the struct minus the
BLEND_STATE_ENTRY's, we can emit a BLEND_STATE of variable number of
entries.
For gen6 and gen7 we set length to 0, since it only contains
BLEND_STATE_ENTRY's, and no other data.
With this change, we also change the code for blorp and anv to emit only
the needed BLEND_STATE_ENTRY's, instead of always emitting 16 dwords on
gen6-7 and 17 dwords on gen8+.
v2:
- Use designated initializers on blorp and remove 0 from
initialization (Jason)
- Default entries to disabled on Vulkan (Jason)
- Rebase code.
Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rafael Antognolli [Fri, 31 Mar 2017 16:57:22 +0000 (09:57 -0700)]
genxml: Fix python crash when no dwords are found.
If the 'dwords' dict is empty, max(dwords.keys()) throws an exception.
This case could happen when we have an instruction that is only an array
of other structs, with variable length.
v2:
- Add another clause for empty dwords and make it work with python 3
(Dylan)
- Set the length to 0 if dwords is empty, and do not declare dw
Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rafael Antognolli [Fri, 14 Apr 2017 15:36:45 +0000 (08:36 -0700)]
genxml: Remove unused parameter.
'start' parameter from Group.emit_pack_function() is useless.
Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rafael Antognolli [Tue, 18 Apr 2017 16:41:40 +0000 (09:41 -0700)]
intel/aubinator: Correctly read variable length structs.
Before this commit, when a group with count="0" is found, only one field
is added to the struct representing the instruction. This causes only
one entry to be printed by aubinator, for variable length groups.
With this commit we "detect" that there's a variable length group
(count="0") and store the offset of the last entry added to the struct
when reading the xml. When finally reading the aubdump file, we check
the size of the group and whether we have variable number of elements,
and in that case, reuse the last field to add the remaining elements.
Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Tested-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Nanley Chery [Mon, 6 Mar 2017 22:55:34 +0000 (14:55 -0800)]
isl/format: Update the R16G16B16X16_FLOAT entry
The section of the PRM mentioned in the code comment above this table
says that this format supports the render target write message. Internal
documentation says that this format also supports alpha blending. As a
side effect, this allows CCS_D buffers to be created for images with
this format.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Nanley Chery [Mon, 10 Apr 2017 18:47:10 +0000 (11:47 -0700)]
anv/pass: Delete anv_pass::subpass_attachments
This field has no users.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Francisco Jerez [Thu, 20 Apr 2017 18:42:27 +0000 (11:42 -0700)]
intel/fs: Take into account amount of data read in spilling cost heuristic.
Until now the spilling cost calculation was neglecting the amount of
data read from the register during the spilling cost calculation.
This caused it to make suboptimal decisions in some cases leading to
higher memory bandwidth usage than necessary.
Improves Unigine Heaven performance by ~4% on BDW, reversing an
unintended FPS regression from my previous commit
147e71242ce539ff28e282f009c332818c35f5ac with n=12 and statistical
significance 5%. In addition SynMark2 OglCSDof performance is
improved by an additional ~5% on SKL, and a Kerbal Space Program
apitrace around the Moho planet I can provide on request improves by
~20%.
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Francisco Jerez [Thu, 20 Apr 2017 18:44:01 +0000 (11:44 -0700)]
intel/fs: Use regs_written() in spilling cost heuristic for improved accuracy.
This is what we use later on to compute the number of registers that
will actually get spilled to memory, so it's more likely to match
reality than the current open-coded approximation.
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Sat, 22 Apr 2017 22:02:08 +0000 (15:02 -0700)]
i965/vec4: Use reads_accumulator_implicitly(), not MACH checks.
Curro pointed out that I should not just check for MACH, but use
the reads_accumulator_implicitly() helper, which would also prevent
the same bug with MAC and SADA2 (if we ever decide to use them).
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Mauro Rossi [Sat, 22 Apr 2017 10:13:37 +0000 (12:13 +0200)]
android: radv/ac: Fix nir.h include
Fixes following building errors due to missing include paths:
external/mesa/src/amd/common/ac_shader_info.c:23:10: fatal error: 'nir/nir.h' file not found
^
external/mesa/src/compiler/nir/nir.h:48:10: fatal error: 'nir_opcodes.h' file not found
^
Fixes: 224cf29 "radv/ac: add initial pre-pass for shader info gathering"
Acked-by: Dave Airlie <Airlied@redhat.com>
Acked-by: Emil Velikov <emil.velikov@collabora.com>
Vinson Lee [Thu, 20 Apr 2017 21:48:50 +0000 (14:48 -0700)]
configure.ac: Fix typos.
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Cc: <mesa-stable@lists.freedesktop.org>
Dave Airlie [Sun, 23 Apr 2017 19:21:29 +0000 (20:21 +0100)]
radv/ac: copy llvm machine feature flags from radeonsi.
This just updates this to use the same flags as radeonsi
for consistency.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Timothy Arceri [Mon, 17 Apr 2017 23:30:47 +0000 (09:30 +1000)]
i965: remove now unused GLSL IR optimisations
These are no longer used since the previous commit.
Acked-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Tue, 17 Jan 2017 23:28:22 +0000 (10:28 +1100)]
i965: remove GLSL IR optimisation loop
IVB is running into some spilling issues in piglit with the
loop removed. However those tests are not really reflective
of a real world use case, also fp64 is brand new to IVB
so we leave the spilling issues to be resolved at a later
time.
Run time for shader-db on my machine goes from ~795 seconds to
~665 seconds.
shader-db results BDW:
total instructions in shared programs:
12969459 ->
12968891 (-0.00%)
instructions in affected programs: 1463154 -> 1462586 (-0.04%)
helped: 3622
HURT: 3326
total cycles in shared programs:
246453572 ->
246504318 (0.02%)
cycles in affected programs:
208842622 ->
208893368 (0.02%)
helped: 24029
HURT: 35407
total loops in shared programs: 2931 -> 2931 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0
total spills in shared programs: 14560 -> 14498 (-0.43%)
spills in affected programs: 2270 -> 2208 (-2.73%)
helped: 17
HURT: 2
total fills in shared programs: 19671 -> 19632 (-0.20%)
fills in affected programs: 2060 -> 2021 (-1.89%)
helped: 17
HURT: 2
LOST: 17
GAINED: 40
Most of the hurt shaders are 1-2 instructions, with what looks like a max of 7.
I've looked at the worst cycles regressions and as far as I can tell its just
a scheduling difference.
Acked-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Sun, 31 Jul 2016 12:39:26 +0000 (22:39 +1000)]
glsl: use ARB_enhahnced_layouts for packing where possible
If packing doesn't cross locations we can easily make use of
ARB_enhanced_layouts to do packing rather than using the GLSL IR
lowering pass lower_packed_varyings().
Shader-db Broadwell results:
total instructions in shared programs:
12977822 ->
12977819 (-0.00%)
instructions in affected programs: 1871 -> 1868 (-0.16%)
helped: 4
HURT: 3
total cycles in shared programs:
246567288 ->
246567668 (0.00%)
cycles in affected programs: 1370386 -> 1370766 (0.03%)
helped: 592
HURT: 733
Acked-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Fri, 14 Apr 2017 06:25:58 +0000 (16:25 +1000)]
glsl: disable varying packing for varying used by interpolateAt*
Currently the NIR backends depend on GLSL IR copy propagation to
fix up the interpolateAt* function params after varying packing
changes the shader input to a global. It's possible copy propagation
might not always do what we need it too, and we also shouldn't
depend on optimisations to do this type of thing for us.
I'm not sure if the same is true for TGSI, but the following
commit should re-enable packing for most cases in a safer way,
so we just disable it everywhere.
No change in shader-db for i965 (BDW)
Acked-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Wed, 18 Jan 2017 23:41:57 +0000 (10:41 +1100)]
glsl_to_nir: skip ir_var_shader_shared variables
These should be lowered away in GLSL IR but if we don't get dead
code to clean them up it causes issues in glsl_to_nir.
We wan't to drop as many GLSL IR opts in future as we can so this
makes glsl_to_nir just ignore the vars if it sees them.
In future we will want to just use the nir lowering pass that
Vulkan currently uses.
Acked-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Fri, 13 Jan 2017 06:25:11 +0000 (17:25 +1100)]
nir/i965: add before ffma algebraic opts
This shuffles constants down in the reverse of what the previous
patch does and applies some simpilifications that may be made
possible from doing so.
Shader-db results BDW:
total instructions in shared programs:
12980814 ->
12977822 (-0.02%)
instructions in affected programs: 281889 -> 278897 (-1.06%)
helped: 1231
HURT: 128
total cycles in shared programs:
246562852 ->
246567288 (0.00%)
cycles in affected programs:
11271524 ->
11275960 (0.04%)
helped: 1630
HURT: 1378
V2: mark float opts as inexact
Reviewed-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Thu, 12 Jan 2017 02:10:55 +0000 (13:10 +1100)]
nir: shuffle constants to the top
V2: mark float opts as inexact
If one of the inputs to an mul/add is the result of another
mul/add there is a chance that we can reuse the result of that
mul/add in other calls if we do the multiplication in the right
order.
Also by attempting to move all constants to the top we increase
the chance of constant folding.
For example it is a fairly common pattern for shaders to do something
similar to this:
const float a = 0.5;
in vec4 b;
in float c;
...
b.x = b.x * c;
b.y = b.y * c;
...
b.x = b.x * a + a;
b.y = b.y * a + a;
So by simply detecting that constant a is part of the multiplication
in ffma and switching it with previous fmul that updates b we end up
with:
...
c = a * c;
...
b.x = b.x * c + a;
b.y = b.y * c + a;
Shader-db results BDW:
total instructions in shared programs:
13011050 ->
12967888 (-0.33%)
instructions in affected programs: 4118366 -> 4075204 (-1.05%)
helped: 17739
HURT: 1343
total cycles in shared programs:
246717952 ->
246410716 (-0.12%)
cycles in affected programs:
166870802 ->
166563566 (-0.18%)
helped: 18493
HURT: 7965
total spills in shared programs: 14937 -> 14560 (-2.52%)
spills in affected programs: 9331 -> 8954 (-4.04%)
helped: 284
HURT: 33
total fills in shared programs: 20211 -> 19671 (-2.67%)
fills in affected programs: 12586 -> 12046 (-4.29%)
helped: 286
HURT: 33
LOST: 39
GAINED: 33
Some of the hurt will go away when we shuffle things back down to the
bottom in the following patch. It's also noteworthy that almost all of the
spill changes are in Deus Ex both hurt and helped.
Reviewed-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Thu, 12 Jan 2017 06:01:03 +0000 (17:01 +1100)]
nir: add flt comparision simplification
Didn't turn out as useful as I'd hoped, but it will help alot more on
i965 by reducing regressions when we drop brw_do_channel_expressions()
and brw_do_vector_splitting().
I'm not sure how much sense 'is_not_used_by_conditional' makes on
platforms other than i965 but since this is a new opt it at least
won't do any harm.
shader-db BDW:
total instructions in shared programs:
13029581 ->
13029415 (-0.00%)
instructions in affected programs: 15268 -> 15102 (-1.09%)
helped: 86
HURT: 0
total cycles in shared programs:
247038346 ->
247036198 (-0.00%)
cycles in affected programs: 692634 -> 690486 (-0.31%)
helped: 183
HURT: 27
Reviewed-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Bas Nieuwenhuizen [Sat, 22 Apr 2017 23:31:05 +0000 (01:31 +0200)]
radv: Enable lowering fdiv in nir.
Results in faster code than the lowering by LLVM.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Rob Clark [Sun, 23 Apr 2017 16:40:15 +0000 (12:40 -0400)]
freedreno/a5xx: hack for r8g8b8a8_snorm
Blob won't render to this format, and sampling from it it uses the same
fmt value for r8g8b8_snorm and r8g8b8a8_snorm. But this is what is what
blocks us from jumping from gl30/gles20 to gl31/gles30. So a hack it
is!
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Sun, 23 Apr 2017 16:45:23 +0000 (12:45 -0400)]
freedreno/a5xx: rgtc formats
Signed-off-by: Rob Clark <robdclark@gmail.com>
Marek Olšák [Sun, 2 Apr 2017 17:07:49 +0000 (19:07 +0200)]
mesa: replace _mesa_index_buffer::type with index_size
This avoids repeated translations of the enum.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Bas Nieuwenhuizen [Sat, 22 Apr 2017 16:42:20 +0000 (18:42 +0200)]
radv: Use the correct pipeline for dispatches.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Fixes:
ec15e0d30 "radv: optimise compute shader grid size emission."
Tested-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Wladimir J. van der Laan [Tue, 18 Apr 2017 11:34:50 +0000 (13:34 +0200)]
etnaviv: Supertiled texture support on gc3000
Support supertiled textures on hardware that has the appropriate
feature flag SUPERTILED_TEXTURE.
Most of the scaffolding was already in place in etna_layout_multiple:
case ETNA_LAYOUT_SUPER_TILED:
*paddingX = 64;
*paddingY = 64;
*halign = TEXTURE_HALIGN_SUPER_TILED;
So this is just a matter of allowing it.
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Fabio Estevam [Mon, 17 Apr 2017 22:36:40 +0000 (19:36 -0300)]
etnaviv: etnaviv_fence: Simplify the return code logic
The return code can be simplified by using the logical not operator.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Rob Clark [Fri, 21 Apr 2017 21:48:42 +0000 (17:48 -0400)]
freedreno/a5xx: occlusion query
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Fri, 21 Apr 2017 20:26:49 +0000 (16:26 -0400)]
freedreno: drop ring arg from _set_stage()
It is always the draw ring. Except for a5xx queries like time-elapsed,
where we will eventually want to emit cmds into both binning and draw
rings.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Fri, 21 Apr 2017 20:08:58 +0000 (16:08 -0400)]
freedreno: update generated headers
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Fri, 21 Apr 2017 19:30:33 +0000 (15:30 -0400)]
freedreno: add support for hw accumulating queries
Some queries on a4xx and all queries on a5xx can do result accumulation
on CP so we don't need to track per-tile samples. We do still need to
handle pausing/resuming while switching batches (in case the query is
active over multiple draws which are executed out of order).
So introduce new accumulated-query helpers for these sorts of queries,
since it doesn't really fit in cleanly with the original query infra-
structure.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Fri, 21 Apr 2017 15:31:20 +0000 (11:31 -0400)]
freedreno: a bit of query refactor
Move a bit more of the logic shared by all query types (active tracking,
etc) into common code. This avoids introducing a 3rd copy of that logic
for a5xx.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Fri, 21 Apr 2017 13:50:30 +0000 (09:50 -0400)]
freedreno: make hw-query a helper
For a5xx (and actually some queries on a4xx) we can accumulate results
in the cmdstream, so we don't need this elaborate mechanism of tracking
per-tile query results. So make it into vfuncs so generation specific
backend can use it when it makes sense.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Kenneth Graunke [Fri, 21 Apr 2017 08:28:13 +0000 (01:28 -0700)]
i965/vec4: Avoid reswizzling MACH instructions in opt_register_coalesce().
opt_register_coalesce() was optimizing sequences such as:
mul(8) acc0:D, attr18.xyyy:D, attr19.xyyy:D
mach(8) vgrf5.xy:D, attr18.xyyy:D, attr19.xyyy:D
mov(8) m4.zw:F, vgrf5.xxxy:F
into:
mul(8) acc0:D, attr18.xyyy:D, attr19.xyyy:D
mach(8) m4.zw:D, attr18.xxxy:D, attr19.xxxy:D
This doesn't work - if we're going to reswizzle MACH, we'd need to
reswizzle the MUL as well. Here, the MUL fills the accumulator's .zw
components with attr18.yy * attr19.yy. But the MACH instruction expects
.z to contain attr18.x * attr19.x. Bogus results ensue.
No change in shader-db on Haswell. Prevents regressions in Timothy's
patches to use enhanced layouts for varying packing (which rearrange
code just enough to trigger this pre-existing bug, but were fine
themselves).
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Timothy Arceri [Fri, 21 Apr 2017 07:04:10 +0000 (17:04 +1000)]
mesa: validate sampler type across the whole program
Currently we were only making sure types were the same within a
single stage. This looks to have regressed with
953a0af8e3f73.
Fixes:
953a0af8e3f73 ("mesa: validate sampler uniforms during gluniform calls")
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
https://bugs.freedesktop.org/show_bug.cgi?id=97524
Timothy Arceri [Fri, 7 Apr 2017 01:40:40 +0000 (11:40 +1000)]
mesa: don't lock hashtables that are not shared across contexts
From Chapter 5 'Shared Objects and Multiple Contexts' of
the OpenGL 4.5 spec:
"Objects which contain references to other objects include
framebuffer, program pipeline, query, transform feedback,
and vertex array objects. Such objects are called container
objects and are not shared"
For we leave locking in place for framebuffer objects because
the EXT fbo extension allowed sharing.
We could maybe just replace the hash with an ordinary hash table
but for now this should remove most of the unnecessary locking.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Matt Turner [Wed, 5 Apr 2017 04:29:00 +0000 (14:29 +1000)]
mesa: Remove deleteFlag pattern from container objects.
This pattern was only useful when we used mutex locks, which the previous
commit removed.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Matt Turner [Fri, 21 Apr 2017 03:48:38 +0000 (13:48 +1000)]
mesa: Remove unnecessary locking from container objects.
From Chapter 5 'Shared Objects and Multiple Contexts' of
the OpenGL 4.5 spec:
"Objects which contain references to other objects include
framebuffer, program pipeline, query, transform feedback,
and vertex array objects. Such objects are called container
objects and are not shared"
For we leave locking in place for framebuffer objects because
the EXT fbo extension allowed sharing.
V2: (Timothy Arceri)
- rebased and dropped changes to framebuffer objects
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Timothy Arceri [Fri, 21 Apr 2017 03:29:46 +0000 (13:29 +1000)]
mesa: remove fallback RefCount == 0 pattern
We should never get here if this is 0 unless there is a
bug. Replace the check with an assert.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Elie TOURNIER [Fri, 21 Apr 2017 16:20:05 +0000 (17:20 +0100)]
egl: add gitignore
Since commit
ce562f9e3fa, two new files are generated.
We don't want to track them.
Signed-off-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Samuel Pitoiset [Fri, 21 Apr 2017 09:18:50 +0000 (11:18 +0200)]
glsl: make use of glsl_type::is_float()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Samuel Pitoiset [Fri, 21 Apr 2017 08:53:32 +0000 (10:53 +0200)]
glsl: make use of glsl_type::is_double()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Samuel Pitoiset [Fri, 21 Apr 2017 08:46:24 +0000 (10:46 +0200)]
glsl: make use of glsl_type::is_integer_64()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Samuel Pitoiset [Fri, 21 Apr 2017 08:42:12 +0000 (10:42 +0200)]
glsl: simplify glsl_type::is_integer_32_64()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Samuel Pitoiset [Fri, 21 Apr 2017 08:41:13 +0000 (10:41 +0200)]
glsl: add glsl_type::is_integer_64()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Samuel Pitoiset [Fri, 21 Apr 2017 08:36:05 +0000 (10:36 +0200)]
glsl: make use of glsl_type::is_boolean()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>