Simon Glass [Tue, 5 Jul 2016 23:10:16 +0000 (17:10 -0600)]
dm: socfpga: mmc: Support CONFIG_BLK
Update the driver to support using driver model for block devices.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 5 Jul 2016 23:10:15 +0000 (17:10 -0600)]
dm: mmc: zynq: Convert zynq to use driver model for MMC
Move zynq to the latest driver model support by enabling CONFIG_DM_MMC,
CONFIG_DM_MMC_OPS and CONFIG_BLK.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 5 Jul 2016 23:10:14 +0000 (17:10 -0600)]
dm: zynq: usb: Convert to CONFIG_DM_USB
Convert zynq USB to driver model. Note this is tested on zynq-zybo only.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 5 Jul 2016 23:10:13 +0000 (17:10 -0600)]
zynq: Increase the early malloc() size
This is needed to support driver-model conversion of USB and block devices.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 5 Jul 2016 23:10:12 +0000 (17:10 -0600)]
net: phy: marvell: Add a missing errno.h header
This corrects a build error on zynqmp.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 5 Jul 2016 23:10:11 +0000 (17:10 -0600)]
arm: Show early-malloc() usage in bdinfo
This is useful information to show how close we are to the limit. At present
it is only available by enabling DEBUG in board_r.c.
Make it available with the 'bdinfo' command also.
Note that this affects ARM only. The bdinfo command is different for each
architecture. Rather than duplicating the code it would be better to
refactor it (as was done with global_data).
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 5 Jul 2016 23:10:10 +0000 (17:10 -0600)]
dm: Use dm_scan_fdt_dev() directly where possible
Quite a few places have a bind() method which just calls dm_scan_fdt_dev().
We may as well call dm_scan_fdt_dev() directly. Update the code to do this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 5 Jul 2016 23:10:09 +0000 (17:10 -0600)]
dm: Convert users from dm_scan_fdt_node() to dm_scan_fdt_dev()
This new function is more convenient for callers, and handles pre-relocation
situations automatically.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 5 Jul 2016 23:10:08 +0000 (17:10 -0600)]
dm: core: Add a function to bind child devices
We currently use dm_scan_fdt_node() to bind devices. It is an internal
function and it requires the caller to know whether we are pre- or post-
relocation.
This requirement has become quite common in drivers, so the current function
is not ideal.
Add a new function with fewer arguments, that does not require internal
headers. This can be used directly as a post_bind() method if needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Jaehoon Chung [Tue, 28 Jun 2016 06:52:21 +0000 (15:52 +0900)]
dm: mmc: dwmmc: use the callback functions as static
There are no places to call these functions.
It should be used the callback function.
Then it can be used as static functions.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Jaehoon Chung [Tue, 28 Jun 2016 06:52:20 +0000 (15:52 +0900)]
dm: mmc: dwmmc: fix the wrong explanation for clock values
This e,g is wrong. Maximum/minimum e.g values are swapped each other.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Tue, 26 Jul 2016 22:33:04 +0000 (18:33 -0400)]
Merge branch 'master' of git.denx.de/u-boot-sunxi
Hans de Goede [Tue, 26 Jul 2016 20:26:39 +0000 (22:26 +0200)]
sunxi: Disable sun8i emac driver
Disable the sun8i emac driver for now, there are 2 issues with it:
1) It is causing issues with network connectivity under the kernel driver,
when booting the kernel with v2 of Corentin's sun8i-h3 emac driver, I get
the connection status bouncing between connected at 100mbps full-duplex
and being down every second.
The second issue is that when trying to use it from u-boot
I get a number of unaligned cache flush errors:
=> dhcp
BOOTP broadcast 1
BOOTP broadcast 2
CACHE: Misaligned operation at range [
7bf594a8,
7bf59628]
BOOTP broadcast 3
CACHE: Misaligned operation at range [
7bf59c90,
7bf59e10]
CACHE: Misaligned operation at range [
7bf5a478,
7bf5a5f8]
DHCP client bound to address 10.42.43.80 (1009 ms)
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Corentin LABBE <clabbe.montjoie@gmail.com>
Cc: Amit Singh Tomar <amittomer25@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Masahiro Yamada [Tue, 26 Jul 2016 18:47:58 +0000 (03:47 +0900)]
ARM: uniphier: move CONFIG_I2C_EEPROM to defconfig
We already have the entry for this option in Kconfig, so let's
migrate to it.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Tom Rini [Tue, 26 Jul 2016 21:34:51 +0000 (17:34 -0400)]
Merge git://git.denx.de/u-boot-mpc86xx
Tom Rini [Tue, 26 Jul 2016 21:34:28 +0000 (17:34 -0400)]
Merge git://git.denx.de/u-boot-fsl-qoriq
Chen-Yu Tsai [Fri, 22 Jul 2016 10:16:10 +0000 (18:16 +0800)]
net: sun8i_emac: Drop redundant and incorrect setting of syscon register
In sun8i_emac_board_setup, the driver partially configures the syscon
register for H3 EPHY. However, the settings are incomplete, and
completely unusable. The correct settings are later set in
sun8i_emac_set_syscon, but the incorrect CLK_SEL setting persists.
It is incorrect to use CLK_SEL to select 25 MHz, as the SoC does not
have a 25 MHz clock the EPHY can use.
This patch removes the setting of the syscon register in board_setup,
and also moves set_syscon above mdio_init. While mdio_init does not
access the PHY, it is better to have the PHY parameters setup before
the MDIO bus is registered.
Fixes:
a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Chen-Yu Tsai [Fri, 22 Jul 2016 10:16:09 +0000 (18:16 +0800)]
net: sun8i_emac: Do not configure AHB2 clock
The sun8i_emac driver erroneously configures the AHB2 clock when it
assumes it is configuring the AXI gates, which is not even documented
or ever appeared in either the WiP kernel driver or Allwinner's original
driver.
As a result, AHB2 clock mux is set to an invalid setting, making the
EPHY unusable.
Fixes:
a29710c525ff ("net: Add EMAC driver for H3/A83T/A64 SoCs.")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Chen-Yu Tsai [Fri, 22 Jul 2016 10:16:08 +0000 (18:16 +0800)]
sunxi: Add EMAC ethernet0 alias for H3 dtsi
The sunxi ethernet address generation code looks for ethernet[0-3]
aliases to find ethernet controllers to generate MAC addresses for.
Without a valid address, the driver fails to register.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Hans de Goede [Tue, 26 Jul 2016 15:47:16 +0000 (17:47 +0200)]
sunxi: Add defconfig and dts file for the Orange Pi PC Plus SBC
There is a new Orange Pi PC *Plus* version available now,
this is an extended version of the regular Orange Pi PC
with sdio wifi and an eMMC.
The upstream kernel devs have decided that they want a separate
dts for the PC Plus rather then sharing a single dts between the
regular PC and the PC Plus. So add a new orangepi_pc_plus_defconfig
to match.
The added dts file matches the one submitted to the upstream kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Qianyu Gong [Thu, 21 Jul 2016 04:39:27 +0000 (12:39 +0800)]
armv8: ls1043aqds: add IFC fixup in case QSPI is enabled
QSPI and IFC are pin-multiplexed on LS1043AQDS board. If QSPI is
enabled, IFC would not be initialized correctly. So disable the IFC
node for Linux.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Wenbin Song [Thu, 21 Jul 2016 10:55:16 +0000 (18:55 +0800)]
armv8/ls1043a: Add MTD partition scheme
Add and share the the MTD partition scheme with kernel by default
bootargs. And add the "mtdparts" env.
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Wenbin Song [Thu, 21 Jul 2016 10:31:23 +0000 (18:31 +0800)]
ARMv8/ls1046a: Cleanup the environment variables
Cleanup the variables: "kernel_addr","ramdisk_addr",
"ramdisk_size","console".
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
York Sun [Fri, 22 Jul 2016 17:52:23 +0000 (10:52 -0700)]
armv8: fsl-layerscape: mmu: Fix enabling MMU
MMU bit in SCTLR needs to be set explicitly after tables are
created. It isn't an issue for EL3 becuase this bit is already
set by early MMU setup. But for other exception levels this
bit was not set.
Signed-off-by: York Sun <york.sun@nxp.com>
Hongbo Zhang [Thu, 21 Jul 2016 10:09:39 +0000 (18:09 +0800)]
ARMv7: PSCI: ls102xa: move secure text section into OCRAM
LS1021 offers two secure OCRAM blocks for trustzone.
This patch moves all the secure text sections into the OCRAM.
Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Hongbo Zhang [Thu, 21 Jul 2016 10:09:38 +0000 (18:09 +0800)]
ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implemention
This patch implements PSCI functions for ls102xa SoC following PSCI v1.0,
they are as the list:
psci_version,
psci_features,
psci_cpu_suspend,
psci_affinity_info,
psci_system_reset,
psci_system_off.
Tested on LS1021aQDS, LS1021aTWR.
Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Hongbo Zhang [Thu, 21 Jul 2016 10:09:37 +0000 (18:09 +0800)]
ARMv7: PSCI: ls102xa: check target CPU ID before further operations
The input parameter CPU ID needs to be validated before furher oprations such
as CPU_ON, this patch introduces the function to do this.
Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Hongbo Zhang [Thu, 21 Jul 2016 10:09:36 +0000 (18:09 +0800)]
ARMv7: PSCI: add PSCI v1.0 functions skeleton
This patch adds all the PSCI v1.0 functions in to the common framework, with
all the functions returning "not implemented" by default, as a common framework
all the dummy functions are added here, it is up to every platform developer to
decide which version of PSCI and which functions to implement.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Mingkai Hu [Tue, 5 Jul 2016 08:01:56 +0000 (16:01 +0800)]
drivers: net/fm: Add Fman support for LS1046A
The Fman module on LS1046A is similiar with that on LS1043A but
LS1046A has one more XFI (10GbE) interface.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Mingkai Hu [Tue, 5 Jul 2016 08:01:55 +0000 (16:01 +0800)]
armv8: fsl_lsch2: Add LS1046A SoC support
The LS1046A processor is built on the QorIQ LS series architecture
combining four ARM A72 processor cores with DPAA 1.0 support.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Mihai Bantea <mihai.bantea@freescale.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Qianyu Gong [Tue, 5 Jul 2016 08:01:54 +0000 (16:01 +0800)]
armv8: fsl_lsch2: Add SerDes 2 support
New SoC LS1046A belongs to Freescale Chassis Generation 2 and
has two SerDes so we need to add this support in fsl_lsch2.
The SoC related SerDes 2 support will be added in SoC patch.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Qianyu Gong [Tue, 5 Jul 2016 08:01:53 +0000 (16:01 +0800)]
armv8: fsl-layerscape: Consolidate the LSCH2 common defines
Both LS1012A and LS1043A belong to FSL_LSCH2 and share some common
configurations. So put the common define under FSL_LSCH2 to increase
readability.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Alison Wang [Tue, 5 Jul 2016 08:01:52 +0000 (16:01 +0800)]
armv8: fsl-layerscape: Add A72 core detection
Add support to detect Cortex-A72 core for printing it out.
The Initiator Version of A72 core should be 0x4.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
York Sun [Fri, 1 Jul 2016 14:40:40 +0000 (07:40 -0700)]
armv8: ls1043aqds: Update MAINTAINERS
Add ls1043aqds_lpuart_defconfig to file list.
Signed-off-by: York Sun <york.sun@nxp.com>
York Sun [Fri, 1 Jul 2016 14:40:39 +0000 (07:40 -0700)]
armv8: ls2080aqds: Update MAINTAINERS
Add ls2080aqds_qspi_defconfig to file list.
Signed-off-by: York Sun <york.sun@nxp.com>
Sumit Garg [Tue, 14 Jun 2016 17:52:40 +0000 (13:52 -0400)]
arm: ls1021atwr: Add SD secure boot target
Add SD secure boot target for ls1021atwr.
Implement board specific spl_board_init() to setup CAAM stream ID and
corresponding stream ID in SMMU. Change the u-boot size defined by a
macro for copying the main U-Boot by SPL to also include the u-boot
Secure Boot header size as header is appended to u-boot image. So header
will also be copied from SD to DDR.
Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
Sumit Garg [Tue, 14 Jun 2016 17:52:39 +0000 (13:52 -0400)]
SECURE_BOOT: Enable SD as a source for bootscript
Add support for reading bootscript and bootscript header from SD. Also
renamed macros *_FLASH to *_DEVICE to represent SD alongwith NAND and
NOR flash.
Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
Sumit Garg [Tue, 14 Jun 2016 17:52:38 +0000 (13:52 -0400)]
SECURE_BOOT: Enable chain of trust in SPL framework
Override jump_to_image_no_args function to include validation of
u-boot image using spl_validate_uboot before jumping to u-boot image.
Also define macros in SPL framework to enable crypto operations.
Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
Sumit Garg [Tue, 14 Jun 2016 17:52:37 +0000 (13:52 -0400)]
DM: crypto/fsl: Enable rsa DM driver usage before relocation
Enable rsa signature verification in SPL framework before relocation for
verification of main u-boot.
Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
Rajesh Bhagat [Tue, 7 Jun 2016 13:29:34 +0000 (18:59 +0530)]
include: usb: Rename USB controller base address mapping
Remove Soc specific defines and use generic chasis specific defines
for USB controller base address mapping.
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
mario.six@gdsys.cc [Mon, 23 May 2016 08:12:11 +0000 (10:12 +0200)]
i2c: fsl: Fix driver initialization
Due to a oversight in testing, the initialization of the recently
introduced Freescale I2C DM driver works only for 36 bit mode of e.g.
the MPC85XX SoCs (specifically, if the physical addresses are 64 bit
wide and the DT addresses 32 bit wide).
This patch corrects the initialization so that it will work in a more
general setting.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: York Sun <york.sun@nxp.com>
Tom Rini [Tue, 26 Jul 2016 12:29:30 +0000 (08:29 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-i2c
mario.six@gdsys.cc [Thu, 21 Jul 2016 09:57:13 +0000 (11:57 +0200)]
i2c: mvtwsi: Add documentation
Add full documentation to all driver functions.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
mario.six@gdsys.cc [Thu, 21 Jul 2016 09:57:12 +0000 (11:57 +0200)]
i2c: mvtwsi: Make delay times frequency-dependent
Some devices using the MVTWSI driver have the option to run at speeds
faster than Standard Mode (100kHZ). On the Armada 38x controllers, this
is actually necessary, since due to erratum FE-8471889, a timing
violation concerning repeated starts prevents the controller from
working correctly in Standard Mode. One of the workarounds recommended
in the erratum is to set the bus to Fast Mode (400kHZ) operation and
ensure all connected devices are set to Fast Mode.
In the current version of the driver, however, the delay times are
hard-coded to 10ms, corresponding to Standard Mode operation. To take
full advantage of the faster modes, we would need to either keep the
currently configured I2C speed in a globally accessible variable, or
pass it to the necessary functions as a parameter. For DM, the first
option is not a problem, and we can simply keep the speed in the private
data of the driver. For the legacy interface, however, we would need to
introduce a static variable, which would cause problems with boots from
NOR flashes; see commit d6b7757 "i2c: mvtwsi: Eliminate
twsi_control_flags."
As to not clutter the interface with yet another parameter, we therefore
keep the default 10ms delays for the legacy functions.
In DM mode, we make the delay time dependant on the frequency to allow
taking full advantage of faster modes of operation (tested with up to
1MHZ frequency on Armada MV88F6820).
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
mario.six@gdsys.cc [Thu, 21 Jul 2016 09:57:11 +0000 (11:57 +0200)]
i2c: mvtwsi: Handle zero-length offsets properly
Zero-length offsets are not properly handled by the driver. When a read
operation with a zero-length offset is started, a START condition is
asserted, and since no offset bytes are transferred, a repeated START is
issued immediately after, which confuses the controller.
To fix this, we send the first START only if any address bytes need to
be sent, and keep track of the expected start status accordingly.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
mario.six@gdsys.cc [Thu, 21 Jul 2016 09:57:10 +0000 (11:57 +0200)]
i2c: mvtwsi: Add compatibility to DM
This patch adds the necessary functions and Kconfig entry to make the
MVTWSI I2C driver compatible with the driver model.
A possible device tree entry might look like this:
i2c@11100 {
compatible = "marvell,mv64xxx-i2c";
reg = <0x11000 0x20>;
clock-frequency = <100000>;
u-boot,i2c-slave-addr = <0x0>;
};
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
mario.six@gdsys.cc [Thu, 21 Jul 2016 09:57:09 +0000 (11:57 +0200)]
i2c: mvtwsi: Make address length variable
The length of the address parameter of the __twsi_i2c_read and
__twsi_i2c_write functions is fixed to four bytes.
As a final step in the preparation of the DM conversion, we make the
length of this parameter variable by turning it into an array of bytes,
and convert the 32 bit value that's passed to the legacy functions into
a four-byte-array on the fly.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
mario.six@gdsys.cc [Thu, 21 Jul 2016 09:57:08 +0000 (11:57 +0200)]
i2c: mvtwsi: Factor out adap parameter
To be able to use the compatibility layer from the DM functions, we
factor the adap parameter out of all functions, and pass the actual
register base instead.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
mario.six@gdsys.cc [Thu, 21 Jul 2016 09:57:07 +0000 (11:57 +0200)]
i2c: mvtwsi: Add compatibility functions
To prepare for the DM conversion, we add a layer of compatibility
functions to be used by both the legacy and the DM functions.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
mario.six@gdsys.cc [Thu, 21 Jul 2016 09:57:06 +0000 (11:57 +0200)]
i2c: mvtwsi: Use 'uint' instead of 'unsigned int'
Since some additional parameters will be added in the course of this
patch series (especially with the addition of DM support), we replace
the longer "unsigned int" declarations with "uint" declarations to keep
the parameter lists more readable.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
mario.six@gdsys.cc [Thu, 21 Jul 2016 09:57:05 +0000 (11:57 +0200)]
i2c: mvtwsi: Get rid of status parameter
The twsi_stop function contains a parameter "status," which is used to
pass in the current exit status of the function calling twsi_stop, and
either return this status unchanged if it indicates an error, or return
twsi_stop's exit status if it does not indicate an error.
While not massively complicated, this adds another purpose to the
twsi_stop function, which should have the sole purpose of asserting a
STOP condition on the bus (and not manage the exit status of its
caller).
Therefore, we move the exit status management into the caller functions
by introducing a "stop_status" variable and returning either the status
before the twsi_stop call (kept in the "status" variable), or the status
from the twsi_stop call, depending on which indicates an error.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
mario.six@gdsys.cc [Thu, 21 Jul 2016 09:57:04 +0000 (11:57 +0200)]
i2c: mvtwsi: Eliminate flags parameter
Due to breaking boots from NOR flashes, commit d6b7757 ("i2c: mvtwsi:
Eliminate twsi_control_flags") removed the static global
twsi_control_flags variable, which kept a set of default flags that were
always or'd to the control register when writing. It was replaced with a
flags parameter, which was passed around between the functions that
needed it.
Since the twsi_control_flags variable was used just for the purposes of
a) setting the MVTWSI_CONTROL_TWSIEN on every control register write,
and
b) setting the MVTWSI_CONTROL_ACK from twsi_i2c_read if needed,
anyway, the added overhead of another variable being passed around is no
longer justified, and we are better off implementing this flag setting
logic locally in the functions that actually write to the control
register.
Therefore, this patch sets MVTWSI_CONTROL_TWSIEN on every control
register write, replaces the twsi_i2c_read's flags parameter with a
ack_flag parameter, which tells the function whether to acknowledge the
read or not, and removes every other instance of the flags variable.
This has the added benefit that now every notion of "global default
flags" is gone, and it's much easier to see which control flags are
actually set at which point in time.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
mario.six@gdsys.cc [Thu, 21 Jul 2016 09:57:03 +0000 (11:57 +0200)]
i2c: mvtwsi: Improve and fix comments
This patch fixes only comments/documentation: Streamline capitalization
and improve grammar/punctuation.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
mario.six@gdsys.cc [Thu, 21 Jul 2016 09:57:02 +0000 (11:57 +0200)]
i2c: mvtwsi: Streamline code and add documentation
Convert groups of logically connected preprocessor defines into proper
enums, one macro into an inline function, and add documentation
to/extend existing documentation of these items.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
mario.six@gdsys.cc [Thu, 21 Jul 2016 09:57:01 +0000 (11:57 +0200)]
i2c: mvtwsi: Fix style violations
This patch fixes seven style violations: Six superfluous spaces after
casts, and one logical continuation violation.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
Mugunthan V N [Mon, 18 Jul 2016 09:41:09 +0000 (15:11 +0530)]
defconfig: am57xx_hs_evm: enable i2c driver model
Enable i2c driver model for am57xx_hs_evm as omap i2c
supports driver model.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Mugunthan V N [Mon, 18 Jul 2016 09:41:08 +0000 (15:11 +0530)]
defconfig: am57xx_evm: enable i2c driver model
Enable i2c driver model for am57xx_evm as omap i2c
supports driver model.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Mugunthan V N [Mon, 18 Jul 2016 09:41:07 +0000 (15:11 +0530)]
defconfig: dra7xx_hs_evm: enable i2c driver model
Enable i2c driver model for dra7xx_hs_evm as omap i2c
supports driver model.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Mugunthan V N [Mon, 18 Jul 2016 09:41:06 +0000 (15:11 +0530)]
defconfig: dra7xx_evm: enable i2c driver model
Enable i2c driver model for dra7xx_evm as omap i2c
supports driver model.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Mugunthan V N [Mon, 18 Jul 2016 09:41:05 +0000 (15:11 +0530)]
defconfig: am43xx_hs_evm: enable i2c driver model
Enable i2c driver model for am43xx_hs_evm as omap i2c
supports driver model.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Mugunthan V N [Mon, 18 Jul 2016 09:41:04 +0000 (15:11 +0530)]
defconfig: am43xx_evm: enable i2c driver model
Enable i2c driver model for am43xx_evm as omap i2c
supports driver model.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Mugunthan V N [Mon, 18 Jul 2016 09:41:03 +0000 (15:11 +0530)]
defconfig: am335x_evm: enable i2c driver model
Enable i2c driver model for am335x_evm as omap i2c
supports driver model.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Mugunthan V N [Mon, 18 Jul 2016 09:41:02 +0000 (15:11 +0530)]
defconfig: am335x_boneblack_vboot: enable i2c driver model
Enable i2c driver model for am335x_boneblack_vboot as omap i2c
supports driver model. Also enable CONFIG_DM_I2C_COMPAT for
legacy drivers of i2c devices.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Mugunthan V N [Mon, 18 Jul 2016 09:41:01 +0000 (15:11 +0530)]
drivers: i2c: omap24xx_i2c: adopt omap_i2c driver to driver model
Convert omap i2c driver to adopt i2c driver model
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Mugunthan V N [Mon, 18 Jul 2016 09:41:00 +0000 (15:11 +0530)]
drivers: i2c: omap24xx_i2c: prepare driver for DM conversion
Prepare the driver for DM conversion.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Mugunthan V N [Mon, 18 Jul 2016 09:40:59 +0000 (15:10 +0530)]
ti_armv7_common: i2c: do not define DM_I2C for spl
Since omap's spl doesn't support DM currently, do not define
DM_I2C for spl build.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Mugunthan V N [Mon, 18 Jul 2016 09:40:58 +0000 (15:10 +0530)]
drivers: i2c: uclass: parse dt parameters only when CONFIG_OF_CONTROL is enable
parse dt parameter of i2c devices only when CONFIG_OF_CONTROL
is enabled.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Mugunthan V N [Mon, 18 Jul 2016 09:40:57 +0000 (15:10 +0530)]
omap5/dra7: i2c: correct register offset for sync register
The register offset of i2c_sysc offset is not correct as per
omap5[1]/dra7[2] TRM, correct the offsets as per the
documentation.
[1] - http://www.ti.com/lit/pdf/swpu249
[2] - http://www.ti.com/lit/pdf/spruhz6
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Mugunthan V N [Mon, 18 Jul 2016 09:40:56 +0000 (15:10 +0530)]
omap4: i2c: correct register offset for sync register
The register offset of i2c_sysc offset is not correct as per
omap4 TRM [1], correct the offsets as per the documentation.
[1] - http://www.ti.com/lit/ug/swpu235ab/swpu235ab.pdf
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Marcin Niestroj [Fri, 6 May 2016 12:58:29 +0000 (14:58 +0200)]
tools: env: Fix format warnings in debug
Format warnings (-Wformat) were shown in printf() calls after defining
DEBUG macro.
Update format string and explicitly cast variables to suppress all
warnings.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
John Keeping [Fri, 15 Jul 2016 16:33:23 +0000 (17:33 +0100)]
rockchip: sdram: Fix register layout for Linux
The ChromeOS kernel reads the RAM settings from PMU_SYS_REG2 and expects
the bootloader to store the necessary information there. We're using
the same register to pass the same information between the SPL and
U-Boot but in a slightly different format.
Change this to use the format expected by the Linux DMC driver so that
the system doesn't hang in Linux by misconfiguring the RAM.
This is almost the same as commit b5788dc ("rockchip: rk3288: correct
sdram setting") which was reverted in commit b525556 ("Revert "rockchip:
rk3288: correct sdram setting"") but parenthese have been added to apply
the mask correctly when reading the "bw" setting and a couple of minor
style issues have been fixed to keep check_patch.pl happy.
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Mon, 18 Jul 2016 09:00:58 +0000 (17:00 +0800)]
mmc: rockchip: add SDHCI driver support for rockchip soc
Rockchip rk3399 using arasan sdhci-5.1 controller.
This patch add the controller support to enable mmc device
with full driver-model support, tested on rk3399 evb board.
According to my test result, this driver should be OK,
the command "part list mmc 0" can result in a right output,
but all the mmc command failed like this:
=> mmc info
No MMC device available
Command failed, result=1
The result of get_mmc_num in cmd/mmc.c is always 0?
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Tue, 19 Jul 2016 13:17:01 +0000 (21:17 +0800)]
ARM64: evb-rk3399: add a README for this board setup
Add a README to guide people flash the ATF and U-Boot
with Rockchip tools to bring up to board.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Tue, 19 Jul 2016 13:17:00 +0000 (21:17 +0800)]
config: add config file for evb-rk3399
This patch add basic config option for evb-rk3399 board.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Tue, 19 Jul 2016 13:16:59 +0000 (21:16 +0800)]
ARM64: rockchip: add support for rk3399 SoC based evb
RK3399 is a SoC from Rockchip with dual-core Cortex-A72
and quad-core Cortex-A53 CPU. It supports two USB3.0
type-C ports and two USB2.0 EHCI ports. Other interfaces
are very much like RK3288, the DRAM are 32bit width address
and support address from 0 to 4GB-128MB range.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Tue, 19 Jul 2016 13:16:58 +0000 (21:16 +0800)]
dts: add support for Rockchip rk3399 soc
These files are from kernel upstream:
"649a371 Add linux-next specific files for
20160616"
with some modification need by U-Boot:
- chosen with stdout-path to uart2.
- add clock-frequency for uart2
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Xu Ziyuan [Mon, 18 Jul 2016 01:56:46 +0000 (09:56 +0800)]
rockchip: update fastboot usage
Introduce how to use fastboot feature on rk3288.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Mon, 18 Jul 2016 01:35:26 +0000 (09:35 +0800)]
mkimage: rockchip: add suport for rk33 serial
Add support for rockchip rk33 series Soc like rk3368 and rk3399
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 17 Jul 2016 21:23:17 +0000 (15:23 -0600)]
rockchip: Use rockchip_get_clk() to obtain the SoC clock
The current code picks the first available clock. In U-Boot proper this is
the oscillator device, not the SoC clock device. As a result the HDMI display
does not work.
Fix this by calling rockchip_get_clk() instead.
Fixes:
135aa950 (clk: convert API to match reset/mailbox style)
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Simon Glass [Sun, 17 Jul 2016 21:23:16 +0000 (15:23 -0600)]
rockchip: Add a way to obtain the main clock device
On Rockchip SoCs we typically have a main clock device that uses the Soc
clock driver. There is also a fixed clock for the oscillator. Add a function
to obtain the core clock.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 17 Jul 2016 21:23:15 +0000 (15:23 -0600)]
dm: core: Add a way to find a device by its driver
Some SoCs have a single clock device. Provide a way to find it given its
driver name. This is handled by the linker so will fail if the name is not
found, avoiding strange errors when names change and do not match. It is
also faster than a string comparison.
Signed-off-by: Simon Glass <sjg@chromium.org>
Heiko Stübner [Fri, 15 Jul 2016 22:17:17 +0000 (00:17 +0200)]
rockchip: rk3288: fix FREF_MIN_HZ constant
According to the TRM the minimum FREF frequency is 269kHz not MHz.
Adapt the constant accordingly.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
Heiko Stübner [Fri, 15 Jul 2016 22:17:16 +0000 (00:17 +0200)]
cosmetic: rockchip: rk3288: rename rkclk_configure_cpu
The function is very specific to the rk3288 in its arguments
referencing the rk3288 cru and grf and every other rockchip soc
has differing cru and grf registers. So make that function naming
explicit.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
Heiko Stübner [Fri, 15 Jul 2016 22:17:15 +0000 (00:17 +0200)]
cosmetic: rockchip: sort socs according to numbers
Having some sort of ordering proofed helpful in a lot of other places
already. So for a larger number of rockchip socs it might be helpful
as well instead of an ever increasing unsorted list.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Acked-by: Simon Glass <sjg@chromium.org>
Heiko Stübner [Fri, 15 Jul 2016 22:17:14 +0000 (00:17 +0200)]
cosmetic: rockchip: rk3036: pinctrl: fix config symbol naming
Rockchip socs are always named rkxxxx in all places, as also shown
by the naming of the rk3036 pinctrl file itself.
Therefore also name the config symbol according to this scheme.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
Heiko Stübner [Fri, 15 Jul 2016 22:17:13 +0000 (00:17 +0200)]
cosmetic: rockchip: rk3288: pinctrl: fix config symbol naming
The rk3288 pinctrl is very specific to this soc, so should
not hog the generic rockchip naming.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
Xu Ziyuan [Thu, 14 Jul 2016 16:26:59 +0000 (00:26 +0800)]
rockchip: rk3288: add fastboot support
Enable fastboot feature on rk3288.
This path doesn't support the fastboot flash function command entirely.
We will hit "cannot find partition" assertion without specified
partition environment. Define gpt partition layout in specified board
such as firefly-rk3288, then enjoy it!
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Xu Ziyuan [Thu, 14 Jul 2016 06:52:35 +0000 (14:52 +0800)]
usb: dwc2 : invalidate dcache before starting DMA
Invalidate dcache before starting the DMA to ensure coherency. In case
there are any dirty lines from the DMA buffer in the cache, subsequent
cache-line replacements may corrupt the buffer in memory while the DMA
is still going on. Cache-line replacement can happen if the CPU tries to
bring some other memory locations into the cache while the DMA is going
on.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Xu Ziyuan [Thu, 14 Jul 2016 06:52:33 +0000 (14:52 +0800)]
usb: dwc2-otg: adjust fifo size via platform data
The total FIFO size of some SoCs may be different from the existen, this
patch supports fifo size setting from platform data.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Xu Ziyuan [Thu, 14 Jul 2016 06:52:32 +0000 (14:52 +0800)]
usb: rockchip-phy: implement USB2.0 phy control
So far, Rockchip SoCs have two kinds of USB2.0 phy, such as Synopsys and
Innosilicon. This patch applys dwc2 usb driver framework to implement
phy_init() and phy_off() methods for Synopsys phy on Rockchip platform.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Andreas Färber [Thu, 14 Jul 2016 04:22:09 +0000 (06:22 +0200)]
rockchip: Exclude rk_timer for ARM64
It conflicts with the generic_timer.
Cc: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Thu, 14 Jul 2016 03:51:05 +0000 (11:51 +0800)]
mkimage: rockchip: add suport for rk33 serial
Add support for rockchip rk33 series Soc like rk3368 and rk3399
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Andreas Färber [Thu, 14 Jul 2016 03:09:26 +0000 (05:09 +0200)]
rockchip: Clean up CPU selection
In preparation for RK3368 and RK3399, which need to select ARM64, don't
select CPU_V7 at the ARCH_ROCKCHIP level but at the SoC level instead.
Cc: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Fri, 8 Jul 2016 03:30:58 +0000 (11:30 +0800)]
board: move all the rockchip board in one folder
The 'evb_rk3036' and 'kylin' is not a vendor name, let's replace them
to 'rockchip' which is a real _vendor_ name, and meet the architecure
'board/<vendor>/<board-name>/'.
More boards from rockchip like evb_rk3288, evb_rk3399 will comes later.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Eddie Cai <eddie.cai.kernel@gmail.com>
Xu Ziyuan [Tue, 5 Jul 2016 10:06:30 +0000 (18:06 +0800)]
rockchip: add basic support for evb-rk3288 board
evb-3288 board RK3288-based development board with 2 USB ports, HDMI,
VGA, micro-SD card, audio, WiFi and Gigabit Ethernet. It also includes
on-board 8G eMMC and 2GB of SDRAM. Expansion connector provide access to
display pins, I2C, SPI, UART and GPIOs. This add some basic files
required to allow the board to output serial messaged and can run
command(mmc info etc).
evb-rk3288 also supports booting from eMMC or SD card, the default is eMMC.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Xu Ziyuan [Tue, 12 Jul 2016 11:09:49 +0000 (19:09 +0800)]
rockchip: add option to change method of loading u-boot
If we would like to boot from SD card, we have to implement mmc driver
in SPL stage, and get a slightly large SPL binary. Rockchip SoC's
bootrom code has the ability to load spl and u-boot, then boot.
If CONFIG_ROCKCHIP_SPL_BACK_TO_BROM is enabled, the spl will return to
bootrom in board_init_f(), then bootrom loads u-boot binary.
Loading sequence after rework:
bootrom ==> spl ==> bootrom ==> u-boot
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fixed up spelling of U-Boot, boorom, opinion->option, Rochchip:
Signed-off-by: Simon Glass <sjg@chromium.org>
Tom Rini [Tue, 26 Jul 2016 02:25:52 +0000 (22:25 -0400)]
Prepare v2016.09-rc1
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 25 Jul 2016 22:18:15 +0000 (18:18 -0400)]
sandbox: Migrate CONFIG_I2C_EEPROM
Most users of CONFIG_I2C_EEPROM were migrated to defconfig a while ago,
but sandbox was skipped. Leave it off for sandbox_spl where it does not
build, but does not need to be either.
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Scott Wood [Tue, 19 Jul 2016 21:26:21 +0000 (16:26 -0500)]
powerpc/86xx: Pass -mcpu=7400 to GCC
Without this, GCC uses the toolchain default, which may be incompatible
with -maltivec.
Signed-off-by: Scott Wood <oss@buserror.net>
Reviewed-by: York Sun <york.sun@nxp.com>
Tom Rini [Mon, 25 Jul 2016 18:49:54 +0000 (14:49 -0400)]
Merge git://git.denx.de/u-boot-nand-flash