Emma Anholt [Fri, 7 Jan 2022 01:09:11 +0000 (17:09 -0800)]
r600: Update the PS state when MSAA-ness changes, too.
Avoids a regression when enabling shader precompilation, where the
precompile would happen with MSAA disabled (so no sample mask export) but
we'd never catch up to the shader being rendered with MSAA.
Doesn't fix any current testcases, though.
Acked-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14427>
Emma Anholt [Fri, 7 Jan 2022 00:27:34 +0000 (16:27 -0800)]
r600: Update the PS state before checking for cb_misc update.
The update_ps_state updates ps_shader->current->ps_color_export_mask, so
we could miss statechanges.
Cc: mesa-stable
Acked-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14427>
Emma Anholt [Thu, 6 Jan 2022 18:53:15 +0000 (10:53 -0800)]
r600: Drop nr_ps_max_color_exports
Prior to
b6521801070d ("r600g: don't snoop context state while building
shaders"), it fed into the shader key, but nothing does any more.
Acked-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14427>
Connor Abbott [Thu, 24 Mar 2022 19:06:26 +0000 (20:06 +0100)]
freedreno/ci: Fix skip comment
This test was never supposed to be skipped, and the referenced commit
just exposed a bug in turnip fixed by the previous commit. It was
hanging due to a CTS bug making the submit take way too long, which will
be fixed once the CTS change lands.
Also, add it to the a630 skips.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15563>
Connor Abbott [Thu, 24 Mar 2022 16:31:29 +0000 (17:31 +0100)]
tu: Correctly handle VK_IMAGE_CREATE_EXTENDED_USAGE_BIT
In this case we should relax checks based on the format, since the user
will be responsible for them when creating an image view.
This gets dEQP-VK.image.sample_texture.*_bit_compressed_format_* not
skipping again after VK-GL-CTS
736eec57dc0c ("Fix checkSupport in
compressed texture sampling tests").
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15563>
Samuel Pitoiset [Mon, 28 Feb 2022 10:43:41 +0000 (11:43 +0100)]
radv: advertise VK_EXT_depth_clip_control
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6070
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15192>
Samuel Pitoiset [Mon, 28 Feb 2022 10:42:51 +0000 (11:42 +0100)]
radv: implement VK_EXT_depth_clip_control
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15192>
Danylo Piliaiev [Fri, 25 Mar 2022 13:26:52 +0000 (15:26 +0200)]
turnip: Fix the lack of WFM before indirect draws
We have to add WFM to pending bits when we are flushing into CP
for indirect draw to know when they should apply WFM workaround.
Fixes CTS tests:
dEQP-VK.draw.renderpass.indirect_draw.*_data_from_compute.indirect_draw_count*
Fixes:
abf0ae014a878d063132a4bf2f2515dc7052f069
("tu: Properly handle waiting on an earlier pipeline stage")
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15577>
Gert Wollny [Fri, 18 Mar 2022 08:04:47 +0000 (09:04 +0100)]
virgl: re-enable PIPE_CAP_TGSI_TEXCOORD with new host versions
Also upreaf the virglrenderer version used in the CI.
v2: Update checksums of trace result images (0 pixels were different)
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Corentin Noël <corentin.noel@collabora.com> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15446>
Samuel Pitoiset [Fri, 18 Mar 2022 09:15:41 +0000 (10:15 +0100)]
radv: lower adjusting gl_FragCoord.z for VRS in NIR
fossils-db (Sienna Cichlid):
Totals from 4432 (3.29% of 134913) affected shaders:
VGPRs: 231232 -> 231880 (+0.28%)
CodeSize:
24738224 ->
24718008 (-0.08%); split: -0.08%, +0.00%
MaxWaves: 93120 -> 93000 (-0.13%)
Instrs: 4540970 -> 4541062 (+0.00%); split: -0.01%, +0.01%
Latency:
49658353 ->
49641444 (-0.03%); split: -0.05%, +0.01%
InvThroughput: 9604328 -> 9603041 (-0.01%); split: -0.02%, +0.01%
VClause: 66497 -> 66498 (+0.00%)
SClause: 209530 -> 209532 (+0.00%); split: -0.01%, +0.01%
Copies: 276135 -> 276249 (+0.04%); split: -0.14%, +0.18%
PreSGPRs: 189409 -> 189415 (+0.00%)
PreVGPRs: 207368 -> 207458 (+0.04%)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15450>
Samuel Pitoiset [Thu, 10 Mar 2022 14:56:49 +0000 (15:56 +0100)]
radv: lower load_sample_mask_in in NIR
No fossils-db changes.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15450>
Mike Blumenkrantz [Tue, 22 Mar 2022 19:49:21 +0000 (15:49 -0400)]
radv: fix CmdSetColorWriteEnableEXT(attachmentCount==MAX_RTS)
cc: mesa-stable
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15508>
Samuel Pitoiset [Tue, 22 Feb 2022 15:39:29 +0000 (16:39 +0100)]
radv,aco: lower color exports in NIR
fossils-db (Sienna Cichlid):
Totals from 27108 (20.09% of 134913) affected shaders:
VGPRs: 1260608 -> 1261424 (+0.06%); split: -0.00%, +0.07%
CodeSize:
112795868 ->
112785892 (-0.01%); split: -0.05%, +0.04%
MaxWaves: 628608 -> 628448 (-0.03%); split: +0.00%, -0.03%
Instrs:
20750003 ->
20749314 (-0.00%); split: -0.01%, +0.00%
Latency:
288088081 ->
288015865 (-0.03%); split: -0.06%, +0.04%
InvThroughput:
53944847 ->
53961693 (+0.03%); split: -0.01%, +0.04%
VClause: 396463 -> 396467 (+0.00%); split: -0.02%, +0.02%
SClause: 842088 -> 842150 (+0.01%); split: -0.03%, +0.04%
Copies: 1244982 -> 1259026 (+1.13%); split: -0.01%, +1.14%
PreSGPRs: 1251949 -> 1251909 (-0.00%)
PreVGPRs: 1099647 -> 1100879 (+0.11%); split: -0.03%, +0.14%
fossils-db (Polaris10):
Totals from 23928 (17.60% of 135960) affected shaders:
SGPRs: 1751792 -> 1751024 (-0.04%); split: -0.05%, +0.01%
VGPRs: 1098964 -> 1098556 (-0.04%); split: -0.13%, +0.09%
CodeSize:
99893472 ->
99837940 (-0.06%); split: -0.06%, +0.00%
MaxWaves: 138322 -> 138306 (-0.01%); split: +0.03%, -0.04%
Instrs:
19213995 ->
19211980 (-0.01%); split: -0.02%, +0.01%
Latency:
273026926 ->
273109402 (+0.03%); split: -0.01%, +0.04%
InvThroughput:
111160907 ->
111195187 (+0.03%); split: -0.04%, +0.07%
VClause: 343058 -> 343097 (+0.01%); split: -0.02%, +0.03%
SClause: 802756 -> 802884 (+0.02%); split: -0.04%, +0.06%
Copies: 1729387 -> 1739208 (+0.57%); split: -0.04%, +0.61%
PreSGPRs: 1090264 -> 1090303 (+0.00%); split: -0.00%, +0.01%
PreVGPRs: 959490 -> 960600 (+0.12%); split: -0.04%, +0.15%
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15263>
Jakob Bornecrantz [Sun, 27 Mar 2022 15:00:22 +0000 (16:00 +0100)]
vulkan-device-select: Don't leak xcb_query_extension_reply_t
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15600>
Iago Toral Quiroga [Thu, 24 Mar 2022 09:45:50 +0000 (10:45 +0100)]
broadcom/compiler: allow ldunifa with indirect uniform loads
We handle uniforms by copying them into the uniform stream to be
consumed with ldunif when they have a constant offset. Otherwise
we fallback to general TMU access, which has more latency.
However, just like we did for UBOs and read-only SSBOs, we can
also try to use the unifa mechanism to handle indirect accesses
in certain cases instead of the TMU fallback.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15575>
Iago Toral Quiroga [Thu, 24 Mar 2022 09:05:17 +0000 (10:05 +0100)]
v3dv: implement VK_EXT_inline_uniform_block
Inline uniform blocks store their contents in pool memory rather
than a separate buffer, and are intended to provide a way in which
some platforms may provide more efficient access to the uniform
data, similar to push constants but with more flexible size
constraints.
We implement these in a similar way as push constants: for constant
access we copy the data in the uniform stream (using the new
QUNIFORM_UNIFORM_UBO_*) enums to identify the inline buffer from
which we need to copy and for indirect access we fallback to
regular UBO access.
Because at NIR level there is no distinction between inline and
regular UBOs and the compiler isn't aware of Vulkan descriptor
sets, we use the UBO index on UBO load intrinsics to identify
inline UBOs, just like we do for push constants. Particularly,
we reserve indices 1..MAX_INLINE_UNIFORM_BUFFERS for this,
however, unlike push constants, inline buffers are accessed
through descriptor sets, and therefore we need to make sure
they are located in the first slots of the UBO descriptor map.
This means we store them in the first MAX_INLINE_UNIFORM_BUFFERS
slots of the map, with regular UBOs always coming after these
slots.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15575>
Georg Lehmann [Fri, 25 Mar 2022 10:20:28 +0000 (11:20 +0100)]
radv: Add more RT pipeline stubs.
Entry points have to be provided even if the features are not supported.
Helps Doom Eternal.
Fixes:
f1095260a41 ("radv: Experimentally enable RT extensions.")
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15573>
Georg Lehmann [Fri, 25 Mar 2022 10:03:19 +0000 (11:03 +0100)]
radv: Add a vkCmdBuildAccelerationStructuresIndirectKHR stub.
Since this entry point is provided by VK_KHR_acceleration_structure, radv has
to implement it even if it doesn't support the indirect build feature.
Helps Doom Eternal.
Fixes:
82de184c3a2 ("radv: Enable VK_KHR_acceleration_structure with RADV_PERFTEST=rt.")
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15573>
Rhys Perry [Wed, 23 Mar 2022 18:32:06 +0000 (18:32 +0000)]
aco: fix RA validation of 16-bit fma_mix operands
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15562>
Pierre-Eric Pelloux-Prayer [Wed, 23 Mar 2022 14:37:49 +0000 (15:37 +0100)]
glsl/nir/linker: fix shader_storage_blocks_write_access
shader_storage_blocks_write_access was computed using the buffer indices
in the program but ShaderStorageBlocksWriteAccess is used with the shader
buffers.
So if a VS had 3 SSBOs and a FS had 4, the mask for VS was 0x3 (correct) but
the mask for the FS was 0x78 instead of 0x15.
Fix this by substracting the index of the first shader buffer in the program's
buffers.
Fixes:
79127f8d5be ("glsl: set ShaderStorageBlocksWriteAccess in the nir linker")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6184
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15552>
Pierre-Eric Pelloux-Prayer [Wed, 23 Mar 2022 12:35:14 +0000 (13:35 +0100)]
glsl/nir/linker: update shader_storage_blocks_write_access for SPIR-V
Most of the code inside the "!prog->data->spirv" blocks shouldn't be
executed for SPIR-V except the part updating the writable mask.
See https://gitlab.freedesktop.org/mesa/mesa/-/issues/6184
Cc: mesa-stable
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15552>
Daniel Schürmann [Fri, 18 Mar 2022 19:03:27 +0000 (20:03 +0100)]
aco: use branch definition as scratch register for SSA lowering
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15505>
Mike Blumenkrantz [Fri, 25 Mar 2022 13:48:27 +0000 (09:48 -0400)]
zink: use z24_in_z32f support and radv ci updates
This uses the new transfer helper codepath in zink and fixes a bunch of fail on radv.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15516>
Dave Airlie [Wed, 23 Mar 2022 04:59:42 +0000 (14:59 +1000)]
u_transfer_helper: add a new option for handling z24 stored in z32
It might be possible to combine this with the other merge to avoid
the overheads of making a temp copy.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15516>
Dave Airlie [Wed, 23 Mar 2022 06:24:32 +0000 (16:24 +1000)]
u_transfer: refactor out code to check interleave/deinterleave path.
The checks were reproduced making adding another one not so fun.
rework the deinterleave path code to match the interleave path code.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15516>
Dave Airlie [Wed, 23 Mar 2022 05:10:51 +0000 (15:10 +1000)]
util/format: add new z24/s8 packing helper to pack z32/s8.
If zink runs on top of a vulkan impl with no 24-bit float support
it needs support to pack into 24-bit for GL.
To avoid having to make a temp copy, add a new helper to convert
and pack.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15516>
Kenneth Graunke [Wed, 16 Mar 2022 10:06:22 +0000 (03:06 -0700)]
intel/compiler: Use nir_opt_uniform_atomics()
In general, an atomic intrinsic may perform separate atomics for every
enabled SIMD channel, as each channel may operate on different memory.
However, an extremely common case is for all channels to access the same
memory location. In this case, we can simply perform a reduction/scan
across the subgroup, and perform one atomic for the whole subgroup,
rather than one per channel. For example, if an intrinsic says to take
the minimum value of the existing memory and the value in each channel,
we can do a thread-local minimum of all enabled channels, then do a
single atomic to take the minimum of that and the existing memory.
Our hardware doesn't optimize the case where multiple channels ask for
atomics on the same memory location; it assumes the compiler will do so.
nir_opt_uniform_atomics() uses divergence analysis to detect this case,
adds the necessary subgroup operations, and moves the atomic inside a
conditional that disables all but a single invocation. It even detects
cases where the shader code already performs this kind of optimization,
and avoids doing it a second time.
This may not be the optimal solution for us. In the backend, we could
detect this case and emit send(1) instructions with NoMask, rather than
generating if...send(16)...endif, and a lot of unnecessary ALU ops. But
it's simple to do, reuses the same path as ACO, and still provides most
of the benefit by cutting up to 16x atomics down to a single atomic,
which is more merciful to the memory bus.
Improves performance of Shadow of the Tomb Raider by 5.5% on XeHP.
Improves performance of a customer-internal benchmark on XeHP at
3840x2160 and low settings by approximately 30%.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15484>
Kenneth Graunke [Tue, 15 Mar 2022 23:25:55 +0000 (16:25 -0700)]
intel/compiler: Convert to LCSSA and use divergence analysis.
We'll use this more shortly. For now, enable it to separately in case
anything bisects to this.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15484>
Kenneth Graunke [Fri, 16 Oct 2020 23:05:52 +0000 (16:05 -0700)]
intel/compiler: Set divergence analysis options
Although we don't use divergence analysis yet, we've had several
work-in-progress series that make use of it. We may as well set
our options so that those series can assume they're in place.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15484>
Kenneth Graunke [Thu, 17 Mar 2022 07:46:21 +0000 (00:46 -0700)]
intel/compiler: Implement nir_intrinsic_last_invocation
We haven't exposed this intrinsic as it doesn't directly correspond to
anything in SPIR-V. However, it's used internally by some NIR passes,
namely nir_opt_uniform_atomics().
We reuse most of the infrastructure in brw_find_live_channel, but with
LZD/ADD instead of FBL. A new SHADER_OPCODE_FIND_LAST_LIVE_CHANNEL is
like SHADER_OPCODE_FIND_LIVE_CHANNEL but from the other side.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15484>
Kenneth Graunke [Wed, 16 Mar 2022 09:14:52 +0000 (02:14 -0700)]
nir: Teach nir_divergence_analysis about Intel-specific intrinsics
- load_reloc_const is just an immediate constant load, it's convergent.
- nir_intrinsic_load_global_const_block_intel should be convergent,
it says the address must be uniform, and we uniformize the predicate
- Lowered image intrinsics: image_deref_load_param_intel just reads
information about an image, as long as the image variable is
convergent it should be too. load_raw_intel...if the address we
come up with is convergent, it ought to be as well.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15484>
Mike Blumenkrantz [Fri, 25 Mar 2022 22:41:16 +0000 (18:41 -0400)]
zink: add another radv flake
literally no idea
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15589>
Caio Oliveira [Tue, 15 Feb 2022 00:40:54 +0000 (16:40 -0800)]
intel/compiler: Inline TUE map computation into TUE Input lowering
Refactor since the TUE compute function is simpler now and the
comments make sense being near the lowering.
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15022>
Caio Oliveira [Tue, 15 Feb 2022 00:36:32 +0000 (16:36 -0800)]
intel/compiler: Use nir_var_mem_task_payload
Instead of reusing the in/out slot mechanism, use a separated NIR
variable mode. This will make easier later to implement staging the
output in shared memory (and storing all at the end to the URB).
Note to get 64-bit type support we currently rely on the
brw_nir_lower_mem_access_bit_sizes() pass.
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15022>
Daniel Schürmann [Wed, 23 Mar 2022 17:23:29 +0000 (18:23 +0100)]
aco: remove 'high' parameter from can_use_opsel()
No fossil-db changes.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15551>
Daniel Schürmann [Wed, 23 Mar 2022 14:12:09 +0000 (15:12 +0100)]
aco/optimizer: fix call to can_use_opsel() in apply_insert()
The definition index is -1.
Fixes:
54292e99c7844500314bfd623469c65adef954c5 ('aco: optimize 32-bit extracts and inserts using SDWA ')
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15551>
Adam Jackson [Thu, 24 Mar 2022 14:49:16 +0000 (10:49 -0400)]
wsi/x11: xcb_wait_for_special_event failure is an error
The only ways that function can return NULL are:
- the xcb connection was closed
- the window for the swapchain was destroyed
- the special event listener was unregistered from another thread
- malloc failure
All of these are permanent errors, the swapchain is no longer in a
usable state, so we should treat this as VK_ERROR_SURFACE_LOST_KHR.
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15558>
Alyssa Rosenzweig [Thu, 17 Mar 2022 15:47:47 +0000 (11:47 -0400)]
pan/va: Lower BLEND to call blend shaders
Do this as late as possible.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Fri, 19 Nov 2021 20:38:04 +0000 (15:38 -0500)]
pan/va: Add packing unit tests
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Mon, 2 Aug 2021 16:30:54 +0000 (12:30 -0400)]
pan/va: Add shader-db support
Reports the common subset from Bifrost, as well as Mali offline compiler
style normalized cycle counts.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Mon, 2 Aug 2021 21:11:03 +0000 (17:11 -0400)]
pan/va: Implement the cycle model
Will feed into shader-db reporting, and maybe other things eventually.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Fri, 23 Jul 2021 20:36:04 +0000 (16:36 -0400)]
pan/va: Test instruction selection lowerings
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Mon, 26 Jul 2021 22:05:39 +0000 (18:05 -0400)]
pan/va: Lower branch offsets
Logic is lifted from bi_layout.c, adapted to work on instructions (not
clauses) and for Valhall's off-by-one semantic which is annoyingly
different than Bifrost. (But the same as Midgard -- Bifrost was
annoyingly different than Midgard!)
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Fri, 23 Jul 2021 20:35:06 +0000 (16:35 -0400)]
pan/va: Add instruction selection lowering pass
Valhall removes certain instructions from Bifrost, requiring a canonical
lowering.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Tue, 27 Jul 2021 18:17:14 +0000 (14:17 -0400)]
pan/va: Add constant lowering pass
Valhall has a lookup table for common constants. Add a pass to take
advantage of it, lowering away immediate indices.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Fri, 23 Jul 2021 15:21:35 +0000 (11:21 -0400)]
pan/va: Validate FAU before packing
These are pre-conditions required for packing.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Fri, 23 Jul 2021 15:21:29 +0000 (11:21 -0400)]
pan/va: Add FAU validation
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Thu, 22 Jul 2021 15:59:09 +0000 (11:59 -0400)]
pan/va: Add unit tests for ADD_IMM optimizations
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Thu, 22 Jul 2021 00:29:54 +0000 (20:29 -0400)]
pan/va: Optimize add with imm to ADD_IMM
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Mon, 19 Jul 2021 19:51:52 +0000 (15:51 -0400)]
pan/va: Add packing routines
Mostly manual since Valhall is regular.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Tue, 27 Jul 2021 17:24:22 +0000 (13:24 -0400)]
pan/va: Add helpers for swapping bitwise sources
Annoyingly different from Bifrost.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Thu, 24 Mar 2022 21:13:24 +0000 (17:13 -0400)]
pan/va: Generate header containing enums
We already collect enums in the ISA description XML. Export them for use in the
compiler backend, particularly the packing code.
Usually we'd use Mako for templating. In this case, the script is so trivial a
template engine didn't seem worth it. (The obvious version with Mako was about
10 lines longer than just prints and f-strings used here.)
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Suggested-by: Icecream95 <ixn@disroot.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Fri, 23 Jul 2021 16:04:13 +0000 (12:04 -0400)]
pan/va: Build opcode info structures
Filled out the new structures from XML.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Fri, 25 Feb 2022 16:52:41 +0000 (11:52 -0500)]
pan/va: Permit encoding more flags
Missed the first time around.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Thu, 24 Mar 2022 22:08:27 +0000 (18:08 -0400)]
pan/va: Unify flow control
Group together dependency waits and flow control into a single enum. This
simplifies the code, clarifies some detail, and ensures consistency moving
forward.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Thu, 24 Mar 2022 00:29:08 +0000 (20:29 -0400)]
pan/va: Add Bifrost-style LD_VAR instructions
For use in the legacy non-MALLOC_IDVS flow. Especially useful in blit shaders.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Wed, 23 Mar 2022 15:57:52 +0000 (11:57 -0400)]
pan/va: Add LD_VAR_BUF instructions
Like LD_VAR_BUF_IMM but indirect.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Wed, 23 Mar 2022 20:45:35 +0000 (16:45 -0400)]
pan/va: Add ST_TILE instruction
Encoded like LD_TILE, required for some MSAA blend shaders.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Thu, 24 Mar 2022 22:10:23 +0000 (18:10 -0400)]
pan/bi: Rename I->action to I->flow
For consistency with the Valhall ISA.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Wed, 23 Mar 2022 15:57:11 +0000 (11:57 -0400)]
pan/bi: Model LD_VAR_BUF instructions
These are indirect versions of LD_VAR_BUF_IMM, taking their index in bytes. Used
for indirect varying loads (the NIR lowering is inefficient).
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Wed, 23 Mar 2022 21:20:33 +0000 (17:20 -0400)]
pan/bi: Augment ST_TILE with register format
To model its Valhall incarnation.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Thu, 17 Mar 2022 16:31:28 +0000 (12:31 -0400)]
pan/bi: Check return addresses in blend shaders
Required on Valhall, where jumping to 0x0 doesn't automatically terminate the
program. Luckily the check is free there too.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Thu, 17 Mar 2022 16:15:37 +0000 (12:15 -0400)]
pan/bi: Allow branch_offset on BLEND
Required to model BLEND accurately on Valhall, where it encodes a special
relative branch... Midgard style!
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Wed, 23 Mar 2022 02:30:11 +0000 (22:30 -0400)]
pan/bi: Model Valhall-style A(CMP)XCHG
Handled consistently with computational atomics.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Wed, 23 Mar 2022 01:53:04 +0000 (21:53 -0400)]
pan/bi: Add ATOM_RETURN pseudo-instruction
Allows modeling Valhall's atomics better.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Wed, 23 Mar 2022 01:47:27 +0000 (21:47 -0400)]
pan/bi: Rename PATOM_C to ATOM
This is basically what's native on Valhall. Use the Valhall naming for the
pseudo-instruction on Bifrost for consistency.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Wed, 23 Mar 2022 13:22:40 +0000 (09:22 -0400)]
pan/bi: Gate late DCE/CSE on "optimize"
Otherwise we can end up with unlowered ATOM.i32 on Valhall.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Alyssa Rosenzweig [Wed, 23 Mar 2022 22:12:31 +0000 (18:12 -0400)]
pan/bi: Use consistent modifier lists in packing
If there are modifiers only used by pseudo instructions, not the real
instructions, bi_packer can get out-of-sync with bi_opcodes, causing
hard-to-debug issues. Do the stupid-simple thing to ensure this doesn't happen.
This may be a temporary issue, depending whether ISA.xml and the IR get split
out for better Valhall support.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15223>
Emma Anholt [Thu, 24 Mar 2022 05:13:20 +0000 (22:13 -0700)]
nouveau/nir: Enable nir_opt_move/sink.
NIR load_consts/inputs tend to happen together at the top of the program.
In the TGSI backend the loads got emitted at use time, while the NIR
backend was emitting the loads at load intrinsic time. By sinking the
intrinsics, we can greatly reduce register pressure.
nv92 NIR results:
total local in shared programs: 2024 -> 2020 (-0.20%)
local in affected programs: 4 -> 0
total gpr in shared programs: 790424 -> 735455 (-6.95%)
gpr in affected programs: 215968 -> 160999 (-25.45%)
total instructions in shared programs: 6058339 -> 6051208 (-0.12%)
instructions in affected programs: 410795 -> 403664 (-1.74%)
total bytes in shared programs:
41820104 ->
41660304 (-0.38%)
bytes in affected programs: 7147296 -> 6987496 (-2.24%)
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15542>
Rajnesh Kanwal [Thu, 10 Mar 2022 13:01:27 +0000 (13:01 +0000)]
pvr: Use vk_common_GetDeviceQueue API.
Removes pvr_GetDeviceQueue implementation. As we are now
using the common vk_queue structure as a base for pvr_queue,
we can use vk_common_GetDeviceQueue implementation instead.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15574>
Boris Brezillon [Fri, 28 Jan 2022 12:32:46 +0000 (04:32 -0800)]
dzn: Compile-test the driver
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14766>
Erik Faye-Lund [Thu, 24 Jun 2021 11:09:35 +0000 (13:09 +0200)]
microsoft: Initial vulkan-on-12 driver
This is Dozen, the Vulkan on DirectX 12 driver. Not to be confused with
DirectEggs.
This is an early prototype, and not meant to be upstreamed as-is.
Co-Authored-by: Boris Brezillon <boris.brezillon@collabora.com>
Co-Authored-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Co-Authored-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Co-Authored-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14766>
Enrico Galli [Tue, 8 Feb 2022 23:08:01 +0000 (15:08 -0800)]
microsoft/spirv_to_dxil: Add missing ralloc_free
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14766>
Boris Brezillon [Wed, 16 Mar 2022 09:21:39 +0000 (02:21 -0700)]
vulkan/util: Make STACK_ARRAY() work for arrays of pointers
And add an explicit cast on the pointer returned by malloc() to
make C++ happy.
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14766>
Boris Brezillon [Fri, 25 Mar 2022 12:17:21 +0000 (05:17 -0700)]
vulkan/image: Make MSVC C++ compiler happy
Fix 'error C4576: a parenthesized type followed by an initializer
list is a non-standard explicit type conversion syntax' errors by
declaring an actual variable and returning it in
vk_image_view_subresource_range().
All those MSVC/c++ related-constraints are quite annoying to be honest,
but it looks like the D3D12 headers have been updated to plain C
recently, which will allow us to write the driver in C, and hopefully
get all this sort of issues behind us.
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14766>
Mike Blumenkrantz [Fri, 25 Mar 2022 14:15:48 +0000 (10:15 -0400)]
zink: add anv cts skips from waiver
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15578>
Mike Blumenkrantz [Fri, 25 Mar 2022 12:58:15 +0000 (08:58 -0400)]
zink: update radv fails
this should be the exact current baseline
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15576>
Rajnesh Kanwal [Thu, 17 Feb 2022 09:45:18 +0000 (09:45 +0000)]
pvr: Implement vkCreateSampler and vkDestroySampler APIs.
Implements vkCreateSampler and vkDestroySampler APIs.
Also fixes maxSamplerLodBias value from 15.0f to 16.0f
as it's the max supported by our hardware.
Also changing maxSamplerAnisotropy from 16.0f to 1.0f to
temporarily disable anisotropy as we are missing software
support for it.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15557>
Boris Brezillon [Wed, 23 Mar 2022 13:09:50 +0000 (14:09 +0100)]
vulkan/util: Get rid of VK_OUTARRAY_MAKE()
Get rid of VK_OUTARRAY_MAKE() so people don't get tempted to
use it and produce code that doesn't compile with MSVC, which
doesn't support typeof().
Suggested-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15522>
Boris Brezillon [Wed, 23 Mar 2022 13:06:00 +0000 (14:06 +0100)]
vulkan/wsi: Stop using VK_OUTARRAY_MAKE()
We're trying to replace VK_OUTARRAY_MAKE() by VK_OUTARRAY_MAKE_TYPED()
so people don't get tempted to use it and make things incompatible with
MSVC (which doesn't support typeof()).
Suggested-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15522>
Boris Brezillon [Wed, 23 Mar 2022 12:59:40 +0000 (13:59 +0100)]
vulkan/device_select: Stop using VK_OUTARRAY_MAKE()
We're trying to replace VK_OUTARRAY_MAKE() by VK_OUTARRAY_MAKE_TYPED()
so people don't get tempted to use it and make things incompatible with
MSVC (which doesn't support typeof()).
Suggested-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15522>
Boris Brezillon [Wed, 23 Mar 2022 12:57:41 +0000 (13:57 +0100)]
venus: Stop using VK_OUTARRAY_MAKE()
We're trying to replace VK_OUTARRAY_MAKE() by VK_OUTARRAY_MAKE_TYPED()
so people don't get tempted to use it and make things incompatible with
MSVC (which doesn't support typeof()).
Suggested-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15522>
Boris Brezillon [Wed, 23 Mar 2022 12:54:26 +0000 (13:54 +0100)]
panvk: Stop using VK_OUTARRAY_MAKE()
We're trying to replace VK_OUTARRAY_MAKE() by VK_OUTARRAY_MAKE_TYPED()
so people don't get tempted to use it and make things incompatible with
MSVC (which doesn't support typeof()).
Suggested-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15522>
Boris Brezillon [Wed, 23 Mar 2022 12:50:34 +0000 (13:50 +0100)]
anv: Stop using VK_OUTARRAY_MAKE()
We're trying to replace VK_OUTARRAY_MAKE() by VK_OUTARRAY_MAKE_TYPED()
so people don't get tempted to use it and make things incompatible with
MSVC (which doesn't support typeof()).
Suggested-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15522>
Boris Brezillon [Wed, 23 Mar 2022 12:40:46 +0000 (13:40 +0100)]
pvr: Stop using VK_OUTARRAY_MAKE()
We're trying to replace VK_OUTARRAY_MAKE() by VK_OUTARRAY_MAKE_TYPED()
so people don't get tempted to use it and make things incompatible with
MSVC (which doesn't support typeof()).
Suggested-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15522>
Boris Brezillon [Wed, 23 Mar 2022 12:37:47 +0000 (13:37 +0100)]
turnip: Stop using VK_OUTARRAY_MAKE()
We're trying to replace VK_OUTARRAY_MAKE() by VK_OUTARRAY_MAKE_TYPED()
so people don't get tempted to use it and make things incompatible with
MSVC (which doesn't support typeof()).
Suggested-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15522>
Boris Brezillon [Wed, 23 Mar 2022 12:28:36 +0000 (13:28 +0100)]
v3dv: Stop using VK_OUTARRAY_MAKE()
We're trying to replace VK_OUTARRAY_MAKE() by VK_OUTARRAY_MAKE_TYPED()
so people don't get tempted to use it and make things incompatible with
MSVC (which doesn't support typeof()).
Suggested-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15522>
Caio Oliveira [Wed, 16 Mar 2022 00:04:04 +0000 (17:04 -0700)]
intel/fs: Fix IsHelperInvocation for the case no discard/demote are used
Use emit_predicate_on_sample_mask() helper that does check where to
get the correct mask depending on whether discard/demote was used or
not.
Fixes:
45f5db5a84a ("intel/fs: Implement "demote to helper invocation"")
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15400>
Caio Oliveira [Wed, 16 Mar 2022 00:15:17 +0000 (17:15 -0700)]
intel/fs: Initialize the sample mask in flags register when using demote
Without this change, a check for "is helper invocation" could read
uninitialized values.
Fixes:
45f5db5a84a ("intel/fs: Implement "demote to helper invocation"")
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15400>
Christian Gmeiner [Sun, 13 Mar 2022 11:40:24 +0000 (12:40 +0100)]
nir: Use const for nir_shader_get_entrypoint(..)
nir_shader_get_entrypoint(..) should not modify the passed nir_shader
object. Enforce this by marking shader paramenter as const.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15362>
Mike Blumenkrantz [Fri, 25 Mar 2022 01:45:32 +0000 (21:45 -0400)]
mesa/st: add special casing for pointsize constant updating during validate
the previous method of using affected_states to trigger constant updates
was ineffectual in the scenario where a ubo pointsize was needed on
the first time a non-precompiled shader was used after being the not-last
vertex stage:
* have vs+gs -> gs precompiles with pointsize lowering -> gs constants get updated
* remove gs -> vs was precompiled without pointsize lowering -> vs constants broken
now just do a quick check as in st_atom_shader.c and set the flag manually to
ensure the update is done correctly every time
cc: mesa-stable
fixes #6207
fixes (radv):
KHR-GL46.texture_cube_map_array.image_op_fragment_sh
KHR-GL46.texture_cube_map_array.sampling
KHR-GL46.texture_cube_map_array.texture_size_fragment_sh
KHR-GL46.constant_expressions*
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15570>
Mike Blumenkrantz [Fri, 25 Mar 2022 01:22:09 +0000 (21:22 -0400)]
zink: update anv icl ci list
praise be to dynamic state fixes!
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15569>
Mike Blumenkrantz [Thu, 24 Mar 2022 21:31:36 +0000 (17:31 -0400)]
zink: flush clears before toggling color write
ensure these sync up onto the expected buffers
Fixes:
3892c133811 ("zink: add an alternate path for EXT_color_write_enable usage")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15568>
Mike Blumenkrantz [Thu, 24 Mar 2022 19:44:02 +0000 (15:44 -0400)]
zink: fix up color_write_enable workaround
this needs to only swizzle to dummy surfaces if it's the workaround,
not just if color_write_enable is active
Fixes:
3892c133811 ("zink: add an alternate path for EXT_color_write_enable usage")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15568>
Rob Clark [Fri, 25 Mar 2022 00:11:44 +0000 (17:11 -0700)]
freedreno/ci: Update a306 expectations
These have started to flakey UnexpectedPass somewhere along the way.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14900>
Rob Clark [Wed, 2 Feb 2022 19:53:36 +0000 (11:53 -0800)]
pipe-loader: Try loading freedreno for virtgpu device
Freedreno will check if the virtgpu supports the pass-thru context, and
if not will bail, falling back to virgl.
TODO this requires that virgl is also enabled in the mesa build, even if
it is not needed.. maybe there is a better way to handle this?
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14900>
Rob Clark [Wed, 2 Feb 2022 18:56:26 +0000 (10:56 -0800)]
freedreno/drm: Add virtio backend
Add a new backend to enable using native driver in a VM guest, via a new
virtgpu context type which (indirectly) makes host kernel interface
available in guest and handles the details of mapping buffers to guest,
etc.
Note that fence-fd's are currently a bit awkward, in that they get
signaled by the guest kernel driver (drm/virtio) once virglrenderer in
the host has processed the execbuf, not when host kernel has signaled
the submit fence. For passing buffers to the host (virtio-wl) the egl
context in virglrenderer is used to create a fence on the host side.
But use of out-fence-fd's in guest could have slightly unexpected
results. For this reason we limit all submitqueues to default priority
(so they cannot be preepmted by host egl context). AFAICT virgl and
venus have a similar problem, which will eventually be solveable once we
have RESOURCE_CREATE_SYNC.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14900>
Rob Clark [Fri, 18 Mar 2022 21:34:21 +0000 (14:34 -0700)]
freedreno/drm: Reorder device destroy
Call backend specific cleanup fxn earlier. This is needed if the
backend has things like bo's to delete, otherwise the handle_table
will already be destroyed causing problems in bo_del()
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14900>
Rob Clark [Tue, 15 Mar 2022 00:14:59 +0000 (17:14 -0700)]
freedreno/drm: Extract out "softpin" submit/ringbuffer base class
We are going to want basically the identical thing, other than
flush_submit_list, for virtio backend. Now that we've moved various
other dependencies into the base classes, extract out an abstract base
class for submit/ringbuffer.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14900>
Rob Clark [Mon, 14 Mar 2022 23:56:55 +0000 (16:56 -0700)]
freedreno/drm: Move ring_pool slab parent to base
Prep to move most of sp submit/ringbuffer to something that can be
re-used by virtio backend.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14900>