Kostya Kortchinsky [Mon, 9 Nov 2020 23:14:49 +0000 (15:14 -0800)]
[scudo][standalone] Correct min/max region indices
The original code to keep track of the minimum and maximum indices
of allocated 32-bit primary regions was sketchy at best.
`MinRegionIndex` & `MaxRegionIndex` were shared between all size
classes, and could (theoretically) have been updated concurrently. This
didn't materialize anywhere I could see, but still it's not proper.
This changes those min/max indices by making them class specific rather
than global: classes are locked when growing, so there is no
concurrency there. This also allows to simplify some of the 32-bit
release code, that now doesn't have to go through all the regions to
get the proper min/max. Iterate and unmap will no longer have access to
the global min/max, but they aren't used as much so this is fine.
Differential Revision: https://reviews.llvm.org/D91106
Sean Silva [Fri, 6 Nov 2020 03:35:15 +0000 (19:35 -0800)]
[mlir] Add DecomposeCallGraphTypes pass.
This replaces the old type decomposition logic that was previously mixed
into bufferization, and makes it easily accessible.
This also deletes TestFinalizingBufferize, because after we remove the type
decomposition, it doesn't do anything that is not already provided by
func-bufferize.
Differential Revision: https://reviews.llvm.org/D90899
Nico Weber [Mon, 16 Nov 2020 20:23:02 +0000 (15:23 -0500)]
lld/mach-o: Infer darwinnew from filename ld64.lld.darwinnew too
`-flavor` is difficult to use through the clang driver since it
must be the first argument.
clang's `-fuse-ld=foo` looks for `ld64.foo` when targeting darwin,
so it's easiest if darwinnew accepts some `ld64.foo`. Let's go with
`ld64.lld.darwinnew`, so that `clang -fuse-ld=lld.darwinnew` does
the right thing (assuming a symlink with the name `ld64.ld.darwinnew
exists in the right place).
This is temporary until darwinnew replaces ld64.lld, and it only
exists to make testing the new lld port easier.
Philip Reames [Mon, 16 Nov 2020 18:51:31 +0000 (10:51 -0800)]
[SCEV] Factor out part of wrap flag detection logic [NFC](try 2)
This is a cut down version of 1ec6e1 which was reverted due to a compile time issue. The key changes made from that patch: 1) only infer the flags needed along each path, 2) be careful to preserve order of checks, and 3) avoid computing NW flags at all since we need to prove the stronger property (does not cross 0) in the caller anyways.
Assuming this doesn't trip regressions, I'm going to try weakening (1). My end objective is to move flag inference into addrec construction. If I can't weaken (1) without compile time impact, I'll have a problem.
Arnold Schwaighofer [Mon, 16 Nov 2020 15:51:20 +0000 (07:51 -0800)]
[coro] Async coroutines: Make sure we can handle control flow in suspend point dispatch function
Create a valid basic block with a terminator before we call
InlineFunction.
Differential Revision: https://reviews.llvm.org/D91547
Florian Hahn [Mon, 16 Nov 2020 16:03:05 +0000 (16:03 +0000)]
[ConstraintElimination] Add complex test cases.
Sanjay Patel [Mon, 16 Nov 2020 19:20:46 +0000 (14:20 -0500)]
Revert "[InstCombine] add multi-use demanded bits fold for add with low-bit mask"
This reverts commit
e56103d25016c9ce4e98f652ac1a09379793ccf5.
There is a stage2 msan failure blamed on this commit:
http://lab.llvm.org:8011/#/builders/74/builds/888/steps/9/logs/stdio
Aaron Ballman [Mon, 16 Nov 2020 19:39:34 +0000 (14:39 -0500)]
Another speculative fix for lldb related to ConstexprSpecKind
Aaron Ballman [Mon, 16 Nov 2020 19:23:04 +0000 (14:23 -0500)]
Speculatively fix the lldb build
Pick up the changes from
41b65f166b51760f77d0f9e465b3858f46e101f0.
Thorsten [Mon, 16 Nov 2020 19:08:33 +0000 (14:08 -0500)]
Convert ConstexprKind from Specifiers.h to a scoped enum; NFC
Jonas Devlieghere [Mon, 16 Nov 2020 19:02:40 +0000 (11:02 -0800)]
[dsymutil] Generalize handling of aliases external symbols
In
f9fb9da36c34d2745b74dc30e6c26f7d3f48466c we fixed spurious warnings
caused by aliases to private extern symbols. This patch generalizes that
to regular external symbols as well.
Amara Emerson [Sat, 14 Nov 2020 07:08:47 +0000 (23:08 -0800)]
[AArch64][GlobalISel] Look through a G_ZEXT when trying to match shift-extended register offsets.
The G_ZEXT in these cases seems to actually come from a combine that we do but
SelectionDAG doesn't. Looking through it allows us to match "uxtw #2" addressing
modes.
Differential Revision: https://reviews.llvm.org/D91475
Scott Linder [Mon, 16 Nov 2020 18:41:25 +0000 (18:41 +0000)]
[YAMLIO] Correctly diagnose empty alias/anchor
The `Range` of an alias/anchor token includes the leading `&` or `*`,
but it is skipped while parsing the name. The check for an empty name
fails to account for the skipped leading character and so the error is
never hit.
Fix the off-by-one and add a couple regression tests.
Reviewed By: dexonsmith
Differential Revision: https://reviews.llvm.org/D91462
Craig Topper [Mon, 16 Nov 2020 18:12:45 +0000 (10:12 -0800)]
[RISCV] Add MC tests for the User Vector CSRs
Make sure we can parse and print the user CSR names
Differential Revision: https://reviews.llvm.org/D91469
Louis Dionne [Mon, 16 Nov 2020 18:35:14 +0000 (13:35 -0500)]
[libc++] Remove transitional #error message
It's been more than 4 years now, so anyone that was defining
_LIBCPP_TRIVIAL_PAIR_COPY_CTOR has had ample time to see that
error and fix their code.
Jameson Nash [Mon, 16 Nov 2020 17:34:43 +0000 (12:34 -0500)]
Reland "[AsmPrinter] fix -disable-debug-info option"
This reverts commit
105ed27ed80dd47a9d32e72bbdd2a776a3318f38, and
removes the offending line from the tests.
Praveen G [Mon, 16 Nov 2020 17:56:04 +0000 (12:56 -0500)]
[Flang][OpenMP] Add semantic checks for OpenMP Depend clause.
Add the semantic checks for the OpenMP 4.5 - 2.13.9 Depend clause.
1. List items in depend clause should not be zero length array sections.
2. A variable that is part of another variable like structure component
should not be specified on a depend clause.
Test cases : omp-depend01.f90, omp-depend02.f90, omp-depend03.f90
Reviewed By: kiranchandramohan
Differential Revision: https://reviews.llvm.org/D89934
Craig Topper [Mon, 16 Nov 2020 17:22:42 +0000 (09:22 -0800)]
[RISCV] When matching SROIW, check all 64 bits of the OR mask
We need to make sure the upper 32 bits are all ones to ensure the result is properly sign extended. Previously we only checked the lower 32 bits of the mask. I've also added a check that the shift amount is less than 32. Without that the original code asserts inside maskLeadingOnes if the SROI check is removed or the SROIW pattern is checked first. I've refactored the code to use early outs to reduce nesting.
I've also updated SLOIW matching with the same changes, but I couldn't find a broken test case with the existing code.
Differential Revision: https://reviews.llvm.org/D90961
Arthur Eubanks [Sat, 14 Nov 2020 02:34:34 +0000 (18:34 -0800)]
[SimplifyCFG] Respect optforfuzzing in NPM pass
Regression caused by refactoring in
cdd006eec9409923f9a56b9026ce2cb72e7b71dc.
See discussion in https://reviews.llvm.org/D89917.
Reviewed By: arsenm, morehouse
Differential Revision: https://reviews.llvm.org/D91473
Raphael Isemann [Mon, 16 Nov 2020 17:41:00 +0000 (18:41 +0100)]
[lldb] Skip TestCppKeywordsAsCIdentifiers on Windows
Somehow static_assert is a keyword with C on Windows (maybe the Windows
default is C11?). Skipping the test for now.
peter klausler [Fri, 13 Nov 2020 17:40:59 +0000 (09:40 -0800)]
[flang] Unsplit COMPLEX operations
COMPLEX negation, addition, subtraction, conversions of kind, and
equality/inequality were represented as component-wise REAL
operations. It turns out to be easier for lowering if we
do not split and recombine these COMPLEX operations, and it
avoids a potential problem with COMPLEX valued function calls
in these contexts. So add this suite of operations to the
typed expression representation in place of the component-wise
transformations, and support them in folding.
Differential revision: https://reviews.llvm.org/D91443
Jonathan Metzman [Mon, 16 Nov 2020 17:35:35 +0000 (09:35 -0800)]
[fuzzer] Disable uncaught-exception on non-Win+undo bad fix
Test is failing on non-Windows platforms. Also undo speculative
fix since it causes failures on Windows.
Xun Li [Mon, 16 Nov 2020 17:14:44 +0000 (09:14 -0800)]
[Coroutine] Allocas used by StoreInst does not always escape
In the existing logic, for a given alloca, as long as its pointer value is stored into another location, it's considered as escaped.
This is a bit too conservative. Specifically, in non-optimized build mode, it's often to have patterns of code that first store an alloca somewhere and then load it right away.
These used should be handled without conservatively marking them escaped.
This patch tracks how the memory location where an alloca pointer is stored into is being used. As long as we only try to load from that location and nothing else, we can still
consider the original alloca not escaping and keep it on the stack instead of putting it on the frame.
Differential Revision: https://reviews.llvm.org/D91305
Jonathan Metzman [Mon, 16 Nov 2020 17:04:54 +0000 (09:04 -0800)]
[fuzzer] Add allocator_may_return_null to uncaught-exception.test.
Speculative fix for failing unittest.
Matt Arsenault [Tue, 10 Nov 2020 16:06:59 +0000 (11:06 -0500)]
AMDGPU: Select global saddr mode from SGPR pointer
Use the 64-bit SGPR base with a 0 offset, since it's 1 fewer
instruction to materialize the 0 vs. the 64-bit copy.
Mirko Brkusanin [Mon, 16 Nov 2020 16:43:15 +0000 (17:43 +0100)]
[AMDGPU][GlobalISel] Fix lowerShlSat
RegBankSelect would crash on G_SELECT when type is not s1.
Differential Revision: https://reviews.llvm.org/D91437
Matt Arsenault [Mon, 9 Nov 2020 23:01:29 +0000 (18:01 -0500)]
AMDGPU: Split large offsets when selecting global saddr mode
When the offset doesn't fit in the immediate field, move some to
voffset.
Victor Huang [Mon, 16 Nov 2020 16:33:06 +0000 (10:33 -0600)]
Fix the compilation assertion due to unreachable BB pruning not deleting the associated BB from the jump tables
This patch is added to remove the unreachable MBBs reference in the jump table.
Differential Revisien: https://reviews.llvm.org/D90498
Reviewed by: amyk, bsaleil
Jay Foad [Mon, 16 Nov 2020 15:52:18 +0000 (15:52 +0000)]
[AMDGPU] Add comments. NFC.
Christian Sigg [Mon, 16 Nov 2020 10:41:59 +0000 (11:41 +0100)]
[mlir] Require std.alloc() ops to have canonical layout during LLVM lowering.
The current code allows strided layouts, but the number of elements allocated is ambiguous. It could be either the number of elements in the shape (the current implementation), or the amount of elements required to not index out-of-bounds with the given maps (which would require evaluating the layout map).
If we require the canonical layouts, the two will be the same.
Reviewed By: nicolasvasilache, ftynse
Differential Revision: https://reviews.llvm.org/D91523
Andrzej Warzynski [Mon, 16 Nov 2020 10:58:04 +0000 (10:58 +0000)]
[flang][f18] Remove "-fdebug-resolve-names"
This option doesn't enable any unique feature/code-patch. Also, it is
neither tested nor documented.
Differential Revision: https://reviews.llvm.org/D91537
Kazushi (Jam) Marukawa [Sun, 15 Nov 2020 01:08:10 +0000 (10:08 +0900)]
[VE] Optimize leaf functions
Optimize leaf functions by not generating save/restore for callee saved
registers. Update regression tests also.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D91539
David Truby [Mon, 16 Nov 2020 13:39:11 +0000 (13:39 +0000)]
[MLIR][OpenMP] Add omp.wsloop operation
This adds a simple definition of a "workshare loop" operation for
the OpenMP MLIR dialect, excluding the "reduction" and "allocate"
clauses and without a custom parser and pretty printer.
The schedule clause also does not yet accept the modifiers that are
permitted in OpenMP 5.0.
Co-authored-by: Kiran Chandramohan <kiran.chandramohan@arm.com>
Reviewed By: ftynse, clementval
Differential Revision: https://reviews.llvm.org/D86071
Simon Moll [Mon, 16 Nov 2020 15:24:05 +0000 (16:24 +0100)]
[VE] fastcc and vreg-to-vreg copy
This defines a 'fastcc' for the VE target and implements vreg-to-vreg
copy for parameter passing. The 'fastcc' extends the standard CC for
SX-Aurora with register passing of vector-typed parameters and return
values.
Reviewed By: kaz7
Differential Revision: https://reviews.llvm.org/D90842
Yonghong Song [Sat, 14 Nov 2020 19:06:23 +0000 (11:06 -0800)]
BPF: make __builtin_btf_type_id() return 64bit int
Linux kernel recently added support for kernel modules
https://lore.kernel.org/bpf/
20201110011932.3201430-5-andrii@kernel.org/
In such cases, a type id in the kernel needs to be presented
as (btf id for modules, btf type id for this module).
Change __builtin_btf_type_id() to return 64bit value
so libbpf can do the above encoding.
Differential Revision: https://reviews.llvm.org/D91489
Xiangling Liao [Mon, 16 Nov 2020 14:42:39 +0000 (09:42 -0500)]
[AIX][driver] Include crti[_64].o and -bcdtors also for C language link invocations by default
In order to support attribute((constructor)) and attribute((destructor)),
which is used by various LLVM non-C++ runtime components, AIX will include
crti[_64].o and -bcdtors for C language link invocations by default.
Differential Revision: https://reviews.llvm.org/D91361
Raphael Isemann [Mon, 16 Nov 2020 07:15:42 +0000 (08:15 +0100)]
[lldb] Add support for using variables with C++ keywords names in non-C++ expressions
LLDB is currently always activating C++ when parsing expressions as LLDB itself
is using C++ features when creating the final AST that will be codegen'd
(specifically, references to variables, namespaces and using declarations are
used).
This is causing problems for users that have variables in non-C++ programs (e.g.
plain C or Objective-C) that have names which are keywords in C++. Expressions
referencing those variables fail to parse as LLDB's Clang parser thinks those
identifiers are C++ keywords and not identifiers that may belong to a
declaration.
We can't just disable C++ in the expression parser for those situations as
replacing the functionality of the injected C++ code isn't trivial. So this
patch is just disabling most keywords that are exclusive to C++ in LLDB's Clang
parser when we are in a non-C++ expression. There are a few keywords we can't
disable for now:
* `using` as that's currently used in some situations to inject variables into the expression function.
* `__null` as that's used by LLDB to define `NULL`/`Nil`/`nil`.
Getting rid of these last two keywords is possible but is a large enough change
that this will be handled in follow up patches.
Note that this only changes the keyword status of those tokens but this patch
does not remove any C++ functionality from the expression parser. The type
system still follows C++ rules and so does the rest of the expression parser.
There is another small change that gives the hardcoded macro definitions in LLDB
a higher precedence than the macros imported from the Objective-C modules. The
reason for this is that the Objective-C modules in LLDB are actually parsed in
Objective-C++ mode and they end up providing the C++ definitions of certain
system macros (like `NULL` being defined as `nullptr`). So we have to move the
LLDB definition forward and surround the definition from the module with an
`#ifdef` to make sure that we use the correct LLDB definition that doesn't
reference C++ keywords. Or to give an example, this is how the expression source
code changes:
Before:
```
#define NULL (nullptr) // injected module definition
#ifndef NULL
#define NULL (__null) // hardcoded LLDB definition
#endif
```
After:
```
#ifndef NULL
#define NULL (__null) // hardcoded LLDB definition
#endif
#ifndef NULL
#define NULL (nullptr) // injected module definition
#endif
```
Fixes rdar://
10356912
Reviewed By: shafik
Differential Revision: https://reviews.llvm.org/D82770
LLVM GN Syncbot [Mon, 16 Nov 2020 14:58:16 +0000 (14:58 +0000)]
[gn build] Port
8dbe44cb293
Florian Hahn [Mon, 16 Nov 2020 09:49:04 +0000 (09:49 +0000)]
Add pass to add !annotate metadata from @llvm.global.annotations.
This patch adds a new pass to add !annotation metadata for entries in
@llvm.global.anotations, which is generated using
__attribute__((annotate("_name"))) on functions in Clang.
This has been discussed on llvm-dev as part of
RFC: Combining Annotation Metadata and Remarks
http://lists.llvm.org/pipermail/llvm-dev/2020-November/146393.html
Reviewed By: thegameg
Differential Revision: https://reviews.llvm.org/D91195
Hanhan Wang [Mon, 16 Nov 2020 14:50:45 +0000 (06:50 -0800)]
[mlir][StandardToSPIRV] Extend support for lowering cmpi to SPIRV.
The logic of vector on boolean was missed. This patch adds the logic and test on
it.
Reviewed By: mravishankar
Differential Revision: https://reviews.llvm.org/D91403
Francesco Petrogalli [Mon, 16 Nov 2020 14:49:28 +0000 (14:49 +0000)]
[clang][SveEmitter] Fix enum declarations. [NFCI]
Adapt the declarations of `svpattern` and `svprfop` to the most recent
one defined in section "5. Enum declarations" of the SVE ACLE
specifications [1].
The signature of the intrinsics using these enums have been changed
accordingly.
A test has been added to make sure that `svpattern` and `svprfop` are
not typedefs.
[1] https://developer.arm.com/documentation/100987/latest, version
00bet6
Reviewed By: joechrisellis
Differential Revision: https://reviews.llvm.org/D91333
Kazushi (Jam) Marukawa [Sat, 14 Nov 2020 12:16:33 +0000 (21:16 +0900)]
[VE] Add lsv/lvs intrinsic instructions
Add lsv/lvs intrinsic instructions and a regression test.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D91526
Aaron Ballman [Mon, 16 Nov 2020 14:23:10 +0000 (09:23 -0500)]
Fix bots that are running with assertions enabled; NFC.
Aaron Ballman [Mon, 16 Nov 2020 14:13:24 +0000 (09:13 -0500)]
Adding some explicit casts to appease build bots; NFC
Thorsten [Mon, 16 Nov 2020 14:08:08 +0000 (09:08 -0500)]
Convert TypeSpecifierSign from Specifiers.h to a scoped enum; NFC
Thorsten [Mon, 16 Nov 2020 13:28:21 +0000 (08:28 -0500)]
Convert TypeSpecifiersPipe from Specifiers.h to a scoped enum; NFC
Vassil Vassilev [Mon, 16 Nov 2020 12:56:11 +0000 (12:56 +0000)]
Reland "Move the test compiler setup in a common place. NFCI"
Original commit message: "
Move the test compiler setup in a common place. NFCI
This patch reduces the copy paste in the unittest/CodeGen folder by moving the
common compiler setup phase in a header file.
Differential revision: https://reviews.llvm.org/D91061
"
This patch includes a fix for the memory leaks pointed out by @vitalybuka
Dmitry Preobrazhensky [Mon, 16 Nov 2020 13:02:32 +0000 (16:02 +0300)]
[AMDGPU][MC] Corrected error position for some operands and modifiers
Partially fixes bug 47518 (https://bugs.llvm.org/show_bug.cgi?id=47518)
Reviewers: rampitec
Differential Revision: https://reviews.llvm.org/D91412
Max Kazantsev [Mon, 16 Nov 2020 13:09:20 +0000 (20:09 +0700)]
[Test] More tests on range checks
Caroline Concatto [Wed, 11 Nov 2020 14:41:01 +0000 (14:41 +0000)]
[AArch64] Add check for widening instruction for SVE.
This patch fixes the function isWideningInstruction for scalable vectors.
Now the cost model can check the widening pattern for SVE.
Differential Revision: https://reviews.llvm.org/D91260
Matthew Malcomson [Thu, 12 Nov 2020 12:37:36 +0000 (12:37 +0000)]
Hwasan reporting check for dladdr failing
In `GetGlobalSizeFromDescriptor` we use `dladdr` to get info on the the
current address. `dladdr` returns 0 if it failed.
During testing on Linux this returned 0 to indicate failure, and
populated the `info` structure with a NULL pointer which was
dereferenced later.
This patch checks for `dladdr` returning 0, and in that case returns 0
from `GetGlobalSizeFromDescriptor` to indicate failure of identifying
the address.
This occurs when `GetModuleNameAndOffsetForPC` succeeds for some address
not in a dynamically loaded library. One example is when the found
"module" is '[stack]' having come from parsing /proc/self/maps.
Differential Revision: https://reviews.llvm.org/D91344
Vitaly Buka [Mon, 16 Nov 2020 12:19:29 +0000 (04:19 -0800)]
Revert "Move the test compiler setup in a common place. NFCI"
There is memory leaks
This reverts commit
23cc838099e10b13a32e54105f4db0f1b7e3a842.
This reverts commit
888d06dfb8b55c4fd41fa4febe22c6fc4111c118.
Vitaly Buka [Mon, 16 Nov 2020 11:00:30 +0000 (03:00 -0800)]
[NFC][tsan] Simplify call_pthread_cancel_with_cleanup
Max Kazantsev [Mon, 16 Nov 2020 12:18:01 +0000 (19:18 +0700)]
[Test] More tests on range check elimination
Michał Górny [Fri, 13 Nov 2020 09:48:29 +0000 (10:48 +0100)]
[lldb] [Process/FreeBSDRemote] Optimize regset pointer logic
Create a helper GetOffsetRegSetData() method to get pointer
to the regset data accounting for the necessary offset. Establish
the offsets in the constructor and store them in the structure. This
avoids having to add new Get*Offset() methods and combines some common
code.
Differential Revision: https://reviews.llvm.org/D91411
Michał Górny [Wed, 11 Nov 2020 20:20:50 +0000 (21:20 +0100)]
[lldb] [Process/FreeBSDRemote] Modernize and simplify YMM logic
Eliminate the remaining swith-case code for register getters,
and migrate YMM registers to regset-oriented model. Since these
registers are recombined from XMM and YMM_Hi128 XSAVE blocks, while LLDB
gdb-server protocol transmits YMM registers whole, the offset-based
model will not work here. Nevertheless, some improvement was possible.
Replace generic 'XSaveRegSet' along with sub-sets for XSAVE components
with 'YMMRegSet' (and more regsets in the future as further components
are implemented). Create a helper GetYMMSplitReg() method that obtains
pointers to the appropriate XMM and YMM_Hi128 blocks to reduce code
duplication.
Differential Revision: https://reviews.llvm.org/D91293
Michał Górny [Wed, 11 Nov 2020 14:20:59 +0000 (15:20 +0100)]
[lldb] [Process/FreeBSDRemote] Access debug registers via offsets
Use offset-based method to access x86 debug registers. This also
involves adding a test for the correctness of these offsets, and making
GetDR() method of NativeRegisterContextWatchpoint_x86 public to avoid
duplicate code.
Differential Revision: https://reviews.llvm.org/D91268
Michał Górny [Wed, 11 Nov 2020 11:43:04 +0000 (12:43 +0100)]
[lldb] [Process/FreeBSDRemote] Access FPR via RegisterInfo offsets
Use offset-based method to access base x87 FPU registers, using offsets
relative to the position of 'struct FPR', as determined by the location
of first register in it (fctrl). Change m_fpr to use a fixed-size array
matching FXSAVE size (512 bytes). Add unit tests for verifying
RegisterInfo offsets and sizes against the FXSAVE layout.
Differential Revision: https://reviews.llvm.org/D91248
Dmitry Preobrazhensky [Mon, 16 Nov 2020 11:37:57 +0000 (14:37 +0300)]
[AMDGPU][MC] Corrected error position for swizzle()
Partially fixes bug 47518 (https://bugs.llvm.org/show_bug.cgi?id=47518)
Reviewers: rampitec
Differential Revision: https://reviews.llvm.org/D91408
Dmitry Preobrazhensky [Mon, 16 Nov 2020 11:23:29 +0000 (14:23 +0300)]
[AMDGPU][MC] Corrected error position for hwreg() and sendmsg()
Partially fixes bug 47518 (https://bugs.llvm.org/show_bug.cgi?id=47518)
Reviewers: rampitec
Differential Revision: https://reviews.llvm.org/D91407
Michał Górny [Tue, 10 Nov 2020 22:58:36 +0000 (23:58 +0100)]
[lldb] [Process/FreeBSDRemote] Access GPR via reginfo offsets
Read and write registers from m_gpr using offsets from RegisterInfo
rather than explicit switch-case. This eliminates a lot of redundant
code, and avoids mistakes such as type mismatches seen recently (wrt
segment registers). The same logic will be extended to other register
sets in the future.
Make m_gpr an uint8_t std::array to ease accesses. Ideally, we could
avoid including <machine/reg.h> entirely in the future and instead
get the correct GPR size from Utility/RegisterContextFreeBSD_* somehow.
While at it, modify register set logic to use an explicit enum with
llvm::Optional<>, making the code cleaner and at the same time enabling
compiler warnings for unhandled sets.
Since now we're fully relying on 'struct GPR' defined
in Utility/RegisterContextFreeBSD_* being entirely in sync with
the system structure, add unit tests to verify the field offsets
and sizes.
Differential Revision: https://reviews.llvm.org/D91216
Nicolas Vasilache [Mon, 16 Nov 2020 10:40:24 +0000 (10:40 +0000)]
[mlir][Linalg] Add support for tileAndDistribute on tensors.
scf.parallel is currently not a good fit for tiling on tensors.
Instead provide a path to parallelism directly through scf.for.
For now, this transformation ignores the distribution scheme and always does a block-cyclic mapping (where block is the tile size).
Differential revision: https://reviews.llvm.org/D90475
Kazushi (Jam) Marukawa [Fri, 13 Nov 2020 09:57:53 +0000 (18:57 +0900)]
[VE] Add pfchv intrinsic instructions
Add pfchv intrinsic instructions and a regression test.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D91522
Vitaly Buka [Mon, 16 Nov 2020 11:05:50 +0000 (03:05 -0800)]
[sanitizer] Fix StackDepotPrint testing
Make test order agnostic as it can change with platform.
Benjamin Kramer [Mon, 16 Nov 2020 10:51:39 +0000 (11:51 +0100)]
[LoopFlatten] Fold variable into assert. NFC.
Florian Hahn [Mon, 16 Nov 2020 10:25:49 +0000 (10:25 +0000)]
[IRGen] Add !annotation metadata for auto-init stores.
This patch updates Clang's IRGen to add !annotation nodes with an
"auto-init" annotation to all stores for auto-initialization.
As discussed in 'RFC: Combining Annotation Metadata and Remarks'
(http://lists.llvm.org/pipermail/llvm-dev/2020-November/146393.html)
this allows using optimization remarks to track down where auto-init
code was inserted (and not removed by optimizations).
There are a few cases in the tests where !annotation gets dropped by
optimizations. Those optimizations will be updated in subsequent
patches.
This patch is based on a patch by Francis Visoiu Mistrih.
Reviewed By: thegameg, paquette
Differential Revision: https://reviews.llvm.org/D91417
Sjoerd Meijer [Mon, 9 Nov 2020 17:32:25 +0000 (17:32 +0000)]
[LoopFlatten] Widen the IV
Widen the IV to the widest available and legal integer type, which makes this
transformations always safe so that we can skip overflow checks.
Motivation is to let this pass trigger on 64-bit targets too, and this is the
last patch in a serie to achieve this: D90402 moves pass LoopFlatten to just
before IndVarSimplify so that IVs are not already widened, D90421 factors out
widening from IndVarSimplify into Utils/SimplifyIndVar so that we can also use
it in LoopFlatten.
Differential Revision: https://reviews.llvm.org/D90640
David Penry [Mon, 16 Nov 2020 10:16:07 +0000 (10:16 +0000)]
[ARM] Cortex-M7 schedule
This patch adds the SchedMachineModel for Cortex-M7. It
also adds test cases for the scheduling information.
Details of the pipeline and descriptions are in comments
in file ARMScheduleM7.td included in this patch.
Differential Revision: https://reviews.llvm.org/D91355
Mikhail Goncharov [Mon, 16 Nov 2020 09:37:55 +0000 (10:37 +0100)]
[lld] Use %t file in test
Otherwise it fails in some setups when creation of "out.wasm" is not possible.
Differential Revision: https://reviews.llvm.org/D91521
Joachim Protze [Mon, 2 Nov 2020 15:34:46 +0000 (16:34 +0100)]
[OpenMP][Tool] Add Archer option to disable data race analysis for sequential part
This introduces the new `ARCHER_OPTIONS` flag `ignore_serial=0|1` to disable
analysis and logging of memory accesses in the sequential part of the OpenMP
application.
In the sequential part of an OpenMP program no data race is possible, unless
there is non-OpenMP concurrency (such as pthreads, MPI, ...). For the latter
reason, this is not active by default.
Besides reducing the runtime overhead for the sequential part of the program,
this reduces the memory overhead for sequential initialization. In combination
with `flush_shadow=1` this can allow analysis of applications, which run close
to the limit of available memory, but only access smaller parts of shared
memory during each OpenMP parallel region.
A problem for this approach is that Archer only gets active, when the OpenMP
runtime gets initialized, which might be after serial initialization of the
application. In such case, it helps to call for example `omp_get_max_threads()`
at the beginning of main.
Differential Revision: https://reviews.llvm.org/D90473
Fraser Cormack [Fri, 13 Nov 2020 12:24:13 +0000 (12:24 +0000)]
[RISCV] Use a macro to simplify getTargetNodeName
Similar to the X86 and AMDGPU targets, this uses a macro to cut down on
repetitive and error-prone code when converting RISCVISD node names to
strings in getTargetNodeName.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D91414
Kazushi (Jam) Marukawa [Mon, 16 Nov 2020 09:24:52 +0000 (18:24 +0900)]
[VE] Change variable capitalization
Change dl to DL in VEFrameLowering.cpp. And clean some comments.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D91490
Simon Moll [Mon, 16 Nov 2020 08:47:18 +0000 (09:47 +0100)]
[VP][NFC] Rename to HANDLE_VP_TO_OPC
Use the less surprising shorthand OPC instead of OC.
Jan Svoboda [Fri, 13 Nov 2020 13:17:54 +0000 (14:17 +0100)]
[clang][cli] Add support for options with two flags for controlling the same field.
This enables automatically parsing and generating CC1 arguments for options where two flags control the same field, e.g. -fexperimental-new-pass-manager and -fno-experimental new pass manager.
Reviewed By: Bigcheese, dexonsmith
Original patch by Daniel Grumberg.
Differential Revision: https://reviews.llvm.org/D83071
Lang Hames [Mon, 16 Nov 2020 08:22:20 +0000 (19:22 +1100)]
[MCJIT] Profile the code generated by MCJIT engine using Intel VTune profiler
Patch by Elena Kovanova. Thanks Elena!
Problem:
LLVM already has a feature to profile the JIT-compiled code with VTune. This is
done using Intel JIT Profiling API (https://github.com/intel/ittapi). Function
information is captured by VTune as soon as the function is JIT-compiled. We
tried to use the same approach to report the function information generated by
the MCJIT engine – read parsing the debug information for in-memory ELF module
and report it using JIT API. As the results, we figured out that it did not work
properly for the following cases: inline functions, the functions located in
multiple source files, the functions having several bodies (address ranges).
Solution:
To overcome limitations described above, we have introduced new APIs as a part
of Intel ITT APIs to report the entire in-memory ELF module to be further
processed as regular ELF binaries with debug information.
This patch
1. Switches LLVM to open source version of Intel ITT/JIT APIs
(https://github.com/intel/ittapi) to keep it always up to date.
2. Adds support of profiling the code generated by MCJIT engine using Intel
VTune profiler
Another separate patch will get rid of obsolete Intel ITT APIs stuff, having
LLVM already switched to https://github.com/intel/ittapi.
Differential Revision: https://reviews.llvm.org/D86435
Simon Moll [Mon, 16 Nov 2020 08:19:14 +0000 (09:19 +0100)]
[VE] LVLGen sets VL before vector insts
The VE backend represents vector instructions with an explicit 'i32'
vector length operand. In the VE ISA, the vector length is always read
from the VL hardware register. The LVLGen pass inserts 'lvl'
instructions as necessary to set VL to the right value before each
vector instruction.
Reviewed By: kaz7
Differential Revision: https://reviews.llvm.org/D91416
Max Kazantsev [Mon, 16 Nov 2020 06:41:13 +0000 (13:41 +0700)]
Recommit "[NFC] Move code between functions as a preparation step for further improvement"
The bug should be fixed now.
Kazu Hirata [Mon, 16 Nov 2020 06:29:30 +0000 (22:29 -0800)]
[JumpThreading] Call eraseBlock when folding a conditional branch
This patch teaches the jump threading pass to call BPI->eraseBlock
when it folds a conditional branch.
Without this patch, BranchProbabilityInfo could end up with stale edge
probabilities for the basic block containing the conditional branch --
one edge probability with less than 1.0 and the other for a removed
edge.
This patch is one of the steps before we can safely re-apply D91017.
Differential Revision: https://reviews.llvm.org/D91511
Kazu Hirata [Mon, 16 Nov 2020 05:15:31 +0000 (21:15 -0800)]
[IR] Use llvm::is_contained in BasicBlock::removePredecessor (NFC)
Kazu Hirata [Mon, 16 Nov 2020 04:32:57 +0000 (20:32 -0800)]
[Loop Fusion] Use pred_empty and succ_empty (NFC)
Kazu Hirata [Mon, 16 Nov 2020 03:52:59 +0000 (19:52 -0800)]
[ADCE] Use succ_empty (NFC)
QingShan Zhang [Mon, 16 Nov 2020 03:44:36 +0000 (03:44 +0000)]
[NFC][Test] Add test coverage for IEEE Long Double on Power8
Kazu Hirata [Mon, 16 Nov 2020 03:26:38 +0000 (19:26 -0800)]
[BranchProbabilityInfo] Use predecessors(BB) and successors(BB) (NFC)
Kazu Hirata [Mon, 16 Nov 2020 03:12:49 +0000 (19:12 -0800)]
[TRE] Use successors(BB) (NFC)
Craig Topper [Mon, 16 Nov 2020 02:16:34 +0000 (18:16 -0800)]
[X86] Fix crash with i64 bitreverse on 32-bit targets with XOP.
We unconditionally marked i64 as Custom, but did not install a
handler in ReplaceNodeResults when i64 isn't legal type. This
leads to ReplaceNodeResults asserting.
We have two options to fix this. Only mark i64 as Custom on
64-bit targets and let it expand to two i32 bitreverses which
each need a VPPERM. Or the other option is to add the Custom
handling to ReplaceNodeResults. This is what I went with.
Kazu Hirata [Mon, 16 Nov 2020 03:01:20 +0000 (19:01 -0800)]
[SanitizerCoverage] Use llvm::all_of (NFC)
Serguei Katkov [Tue, 10 Nov 2020 04:30:56 +0000 (11:30 +0700)]
[IRCE] Use the same min runtime iteration threshold for BPI and BFI checks
In the last change to IRCE the BPI is ignored if BFI is present, however
BFI and BPI have a different thresholds. Specifically BPI approach checks only
latch exit probability so it is expected if the loop has only one exit block (latch)
the behavior with BFI and BPI should be the same,
BPI approach by default uses threshold 10, so it considers the loop with estimated
number of iterations less then 10 should not be considered for IRCE optimization.
BFI approach uses the default value 3 and this is inconsistent.
The CL modifies the code to use the same threshold for both approaches..
The test is updated due to it has two side-exits (except latch) and each of them has a
probability 1/16, so BFI estimates the number of runtime iteration is about to 7
(1/16 + 1/16 + some for latch) and test fails.
Reviewers: mkazantsev, ebrevnov
Reviewed By: mkazantsev
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D91230
Wang, Pengfei [Mon, 16 Nov 2020 01:44:06 +0000 (09:44 +0800)]
[CodeGen][X86] Remove unused trivial check-prefixes from all CodeGen/X86 directory.
I had manually removed unused prefixes from CodeGen/X86 directory for more than 100 tests.
I checked the change history for each of them at the beginning, and then I mainly focused on the format since I found all of the unused prefixes were result from either insensible copy or residuum after functional update.
I think it's OK to remove the remaining X86 tests by script now. I wrote a rough script which works for me in most tests. I put it in llvm/utils temporarily for review and hope it may help other components owners.
The tests in this patch are all generated by the tool and checked by update tool for the autogenerated tests. I skimmed them and checked about 30 tests and didn't find any unexpected changes.
Reviewed By: mtrofin, MaskRay
Differential Revision: https://reviews.llvm.org/D91496
Richard Smith [Mon, 16 Nov 2020 01:40:57 +0000 (17:40 -0800)]
PR48169: Fix crash generating debug info for class non-type template
parameters.
It appears that LLVM isn't able to generate a DW_AT_const_value for a
constant of class type, but if it could, we'd match GCC's debug info in
this case, and in the interim we no longer crash.
Sanjay Patel [Sun, 15 Nov 2020 20:43:34 +0000 (15:43 -0500)]
[InstCombine] reduce code for flip of masked bit; NFC
There are 1-2 potential follow-up NFC commits to reduce
this further on the way to generalizing this for vectors.
The operand replacing path should be dead code because demanded
bits handles that more generally (D91415).
Sanjay Patel [Sun, 15 Nov 2020 20:08:41 +0000 (15:08 -0500)]
[InstCombine] add multi-use demanded bits fold for add with low-bit mask
I noticed an add example like the one from D91343, so here's a similar patch.
The logic is based on existing code for the single-use demanded bits fold.
But I only matched a constant instead of using compute known bits on the
operands because that was the motivating patterni that I noticed.
I think this will allow removing a special-case (but incomplete) dedicated
fold within visitAnd(), but I need to untangle the existing code to be sure.
https://rise4fun.com/Alive/V6fP
Name: add with low mask
Pre: (C1 & (-1 u>> countLeadingZeros(C2))) == 0
%a = add i8 %x, C1
%r = and i8 %a, C2
=>
%r = and i8 %x, C2
Differential Revision: https://reviews.llvm.org/D91415
Sanjay Patel [Sun, 15 Nov 2020 19:57:01 +0000 (14:57 -0500)]
[InstCombine] add vector tests for multi-use demanded bits; NFC
See D91415.
Martin Storsjö [Sat, 14 Nov 2020 07:33:36 +0000 (09:33 +0200)]
[OpenMP] Fix building for windows after adding omp_calloc
Differential Revision: https://reviews.llvm.org/D91478
Nikita Popov [Sun, 15 Nov 2020 19:29:53 +0000 (20:29 +0100)]
[AA] Add missing AAQI parameter
This alias() call did not pass on the AAQueryInfo.
Florian Hahn [Sun, 15 Nov 2020 17:59:02 +0000 (17:59 +0000)]
[MemorySSA] Add pointer decrement loop clobber test case.
faisalv [Sun, 15 Nov 2020 17:13:57 +0000 (11:13 -0600)]
[NFC, Refactor] Modernize the TypeSpecifierWidth enum (Specifiers.h) to a scoped enum
Reviewed here: https://reviews.llvm.org/D91409 by Aaron.
Highlights of the review:
- avoid an underlying type for enums
- avoid enum bit fields (MSVC packing anomalies) and favor static_casts to unsigned bit-fields
Patch by Thorsten Schuett <schuett@gmail.com> w some minor fixes in SemaType.cpp where a couple asserts had to be repaired to deal with lack of implicit coversion to int.
Thanks Thorsten!
Aaron Puchert [Sun, 15 Nov 2020 17:02:09 +0000 (18:02 +0100)]
Consistent spelling in diagnostics: {l,r}value instead of {l,r}-value
As Richard Smith pointed out in the review of D90123, both the C and C++
standard call it lvalue and rvalue, so let's stick to the same spelling
in Clang.
Aaron Puchert [Sun, 15 Nov 2020 15:11:23 +0000 (16:11 +0100)]
[Sema] Improve notes for value category mismatch in overloading
When an overloaded member function has a ref-qualifier, like:
class X {
void f() &&;
void f(int) &;
};
we would print strange notes when the ref-qualifier doesn't fit the value
category:
X x;
x.f();
X().f(0);
would both print a note "no known conversion from 'X' to 'X' for object
argument" on their relevant overload instead of pointing out the
mismatch in value category.
At first I thought the solution is easy: just use the FailureKind member
of the BadConversionSequence struct. But it turns out that we weren't
properly setting this for function arguments. So I went through
TryReferenceInit to make sure we're doing that right, and found a number
of notes in the existing tests that improved as well.
Fixes PR47791.
Reviewed By: rsmith
Differential Revision: https://reviews.llvm.org/D90123
Marek Kurdej [Sun, 15 Nov 2020 15:17:52 +0000 (16:17 +0100)]
[gcc] Fix -Wempty-body warning. NFC.
Florian Hahn [Sun, 15 Nov 2020 14:57:47 +0000 (14:57 +0000)]
[VPlan] Use VPValue def for VPWidenGEPRecipe.
This patch turns VPWidenGEPRecipe into a VPValue and uses it
during VPlan construction and codegeneration instead of the plain IR
reference where possible.
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D84683