Jesse Natalie [Tue, 1 Feb 2022 22:36:32 +0000 (14:36 -0800)]
microsoft/compiler: Process signatures before the shader code
This lets us set up some metadata based on I/O vars without having
to do multiple passes over them.
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14837>
Jesse Natalie [Tue, 1 Feb 2022 20:50:08 +0000 (12:50 -0800)]
microsoft/compiler: Handle I/O vars larger than a vec4
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14837>
Jesse Natalie [Tue, 1 Feb 2022 20:44:38 +0000 (12:44 -0800)]
microsoft/compiler: Lower 64bit I/O to 32 and then run lower_pack
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14837>
Jesse Natalie [Fri, 28 Jan 2022 23:11:42 +0000 (15:11 -0800)]
microsoft/compiler: Handle b2f64
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14837>
Jesse Natalie [Fri, 28 Jan 2022 21:46:58 +0000 (13:46 -0800)]
microsoft/compiler: Set dx11_1_double_extensions flag for dfma/ddiv
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14837>
Jesse Natalie [Fri, 28 Jan 2022 21:46:41 +0000 (13:46 -0800)]
microsoft/compiler: Fix dxil_nir_lower_double_math_instr pass for vectors
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14837>
Jesse Natalie [Tue, 1 Feb 2022 19:39:43 +0000 (11:39 -0800)]
microsoft/compiler: Fix make_double and split_double to respect swizzles
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14837>
Jesse Natalie [Fri, 28 Jan 2022 21:45:36 +0000 (13:45 -0800)]
microsoft/compiler: Fix splitdouble struct name
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14837>
Jesse Natalie [Fri, 28 Jan 2022 20:54:17 +0000 (12:54 -0800)]
microsoft/compiler: It's possible to have doubles without int64
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14837>
Jesse Natalie [Fri, 28 Jan 2022 20:24:28 +0000 (12:24 -0800)]
microsoft/compiler: Add never-supported double ops to lower_doubles bitmask
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14837>
Jesse Natalie [Wed, 2 Feb 2022 20:39:14 +0000 (12:39 -0800)]
microsoft/compiler: Only treat tess level location as special if it's a patch constant
Fixes:
a550c059 ("microsoft/compiler: For load_input from DS, use loadPatchConstant")
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14837>
Jesse Natalie [Wed, 2 Feb 2022 14:57:02 +0000 (06:57 -0800)]
microsoft/compiler: Only prep phis for the current function
Fixes:
41af9620 ("microsoft/compiler: Emit all NIR functions into the DXIL module")
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14837>
Jesse Natalie [Tue, 1 Feb 2022 16:23:38 +0000 (08:23 -0800)]
microsoft/compiler: Lower mul_2x32_64
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14837>
Emma Anholt [Fri, 12 Nov 2021 18:08:20 +0000 (10:08 -0800)]
ci: Uprev vulkan-cts to 1.2.8.0
This brings in some interesting new vulkan tests and fixes for the
spurious KHR-GL TF failures. Also, reduces the runtime of
dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.36 so that it
should stop timing out.
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13779>
Emma Anholt [Wed, 17 Nov 2021 00:17:25 +0000 (16:17 -0800)]
llvmpipe: Disable an assertion that may not be quite right.
It triggered on uprevving VK-GL-CTS, and @airlied says it's tripped
apparently spuriously before. There seems to be some interesting logic
behind it, so leave the big comment for whoever can revisit the issue some
day.
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13779>
Emma Anholt [Wed, 2 Feb 2022 05:22:52 +0000 (21:22 -0800)]
ci/i915: Update rendering hash for plot3d trace.
Its rendering changed slightly at some point, but it's fine.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13779>
Emma Anholt [Thu, 3 Feb 2022 04:15:28 +0000 (20:15 -0800)]
ci/freedreno: Reduce concurrency for a618 vk_full.
This ran into OOM-kills with the CTS uprev. Looking at caselists at the
time of fail, some had 500MB of system memory used by the CTS (mostly
spirv string codegen), plus whatever BOs were allocated, and the lazors
are only 4GB it looks like.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13779>
Emma Anholt [Wed, 2 Feb 2022 18:56:34 +0000 (10:56 -0800)]
ci/turnip: Extend the full-vk-run job timeouts.
Between adding features and increased test coverage, we're hitting the
1-hour job limit. !13441 tried to increase the full run timeout for LAVA,
but by having not bumped the gitlab-ci timeout value it ended up just
letting the job keep running in LAVA after gitlab had given up on it.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13779>
Emma Anholt [Wed, 2 Feb 2022 17:51:30 +0000 (09:51 -0800)]
ci/freereno: Reduce run-by-default a630-vk coverage.
In the autotune merge, we added another 1/15th run of a configuration
knob, thinking that was small enough to be in the noise. But actually the
main run is only 1/9th, so another 1/15th took us from nearly hitting the
job runtime target, to totally missing it. Crank things back down to keep
MRs flowing.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13779>
Emma Anholt [Mon, 31 Jan 2022 19:45:36 +0000 (11:45 -0800)]
r300: Simplify DCE by assuming all output writes are used.
No change on shader-db.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14847>
Emma Anholt [Thu, 3 Feb 2022 05:08:13 +0000 (21:08 -0800)]
r300: Set up shadow sampler lowering in precompiles.
Otherwise you end up lowering all shadow samples to a MOV dst
temp[0].0000, which is pretty silly.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14847>
Emma Anholt [Mon, 31 Jan 2022 19:31:31 +0000 (11:31 -0800)]
r300: Fix missing \n in an error message.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14847>
Mike Blumenkrantz [Thu, 27 Jan 2022 15:44:34 +0000 (10:44 -0500)]
zink: add synchronization for conditional render buffer
doesn't seem to do anything on any drivers I've tested, but maybe it's
needed somewhere
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14853>
Mike Blumenkrantz [Thu, 27 Jan 2022 15:43:33 +0000 (10:43 -0500)]
zink: add VK_BUFFER_USAGE_CONDITIONAL_RENDERING_BIT_EXT for query binds
required by spec
cc: mesa-stable
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14853>
Rhys Perry [Wed, 2 Feb 2022 16:42:24 +0000 (16:42 +0000)]
aco: don't encode src2 for v_writelane_b32_e64
Encoding src2 doesn't cause issues for print_asm() because we have a
workaround there, but it does for RGP and it seems the developers are not
interested in fixing it.
https://github.com/GPUOpen-Tools/radeon_gpu_profiler/issues/61
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Tested-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14832>
Rhys Perry [Mon, 31 Jan 2022 18:13:07 +0000 (18:13 +0000)]
aco: add test for optimizations with casts
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14810>
Rhys Perry [Mon, 31 Jan 2022 18:28:59 +0000 (18:28 +0000)]
aco: fix neg(mul)/abs(mul) optimization with different bit-size
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14810>
Rhys Perry [Mon, 31 Jan 2022 18:22:58 +0000 (18:22 +0000)]
aco: don't combine add/mul of different bit-size
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14810>
Rhys Perry [Mon, 31 Jan 2022 18:12:59 +0000 (18:12 +0000)]
aco: don't apply omod/clamp of different bit-size
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14810>
Rhys Perry [Mon, 31 Jan 2022 18:01:45 +0000 (18:01 +0000)]
aco: don't combine fneg/fabs of different bit-size
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14810>
Rhys Perry [Thu, 27 Jan 2022 14:18:04 +0000 (14:18 +0000)]
aco/tests: implement sub-dword program inputs
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14810>
Rhys Perry [Thu, 27 Jan 2022 14:17:23 +0000 (14:17 +0000)]
aco/tests: add a bunch more building helpers
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14810>
Alyssa Rosenzweig [Wed, 2 Feb 2022 22:20:16 +0000 (17:20 -0500)]
panfrost: Fix texel interleave flag on Valhall
Interleave mode specified per-plane on Valhall. The texture descriptor proper
merely has a flag specifying whether planes are somehow interleaved
(u-interleaved, AFBC, or block compressed formats) or whether they are all
linear (and uncompressed).
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14851>
Alyssa Rosenzweig [Wed, 2 Feb 2022 22:15:10 +0000 (17:15 -0500)]
panfrost: Add remaining ZS/CRC XML
Flesh out the ZS/CRC XML, adding fields required for AFBC. Valhall allows AFBC
compressing stencil buffers independent of depth buffers, which is a new feature
since Bifrost. That results in a shuffling of the descriptor.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14851>
Alyssa Rosenzweig [Wed, 2 Feb 2022 22:13:20 +0000 (17:13 -0500)]
panfrost: Add Valhall Plane Descriptor XML
This looks superficially like the Bifrost "Surface" descriptor, but it
additionally specifies the in-memory representation of blocks (clumps). If I
understand correctly, decompression is controlled by the plane descriptor,
rather than the texture descriptor level. This is a bit more flexible than
Bifrost.
Once the new fields here are wired up to Mesa, my
dEQP-GLES2.functional.texture.* failures should go away... I hope!
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14851>
Alyssa Rosenzweig [Sun, 9 Jan 2022 18:38:23 +0000 (13:38 -0500)]
panfrost: Fix alignments on Valhall
Otherwise we get DATA_INVALID_FAULT trying to run even trivial null jobs. For
each descriptor, set the correct alignment.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14851>
Alyssa Rosenzweig [Fri, 28 Jan 2022 18:47:53 +0000 (13:47 -0500)]
panfrost: Remove blend shader return value on v9
Removed since there's a new ABI for blend shaders. Even if we always write 0,
it's better not to pack this at all, and to denoise the dumps.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14851>
Alejandro Piñeiro [Mon, 24 Jan 2022 13:13:00 +0000 (14:13 +0100)]
v3d/drm-shim: remove drm-shim driver
After starting to use a new version of the simulator, it got
outdated.
We made some initial effort to update it, but it was not
working. Taking into account that no one is using it, it is better to
just remove it.
We keep the noop drm drivers, as they could have some value for
developers that doesn't have access to the v3dv3 simulator.
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14682>
Shirish S [Mon, 31 Jan 2022 11:00:37 +0000 (16:30 +0530)]
radeonsi: allocate protected buffer only if required
protected buffer allocations need to be made if the context is secure
Signed-off-by: Shirish S <shirish.s@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14848>
Pierre-Eric Pelloux-Prayer [Thu, 3 Feb 2022 08:35:07 +0000 (09:35 +0100)]
radeonsi: limit loop unrolling for LLVM < 13
Without this change LLVM 12 hits this error:
"""
LLVM ERROR: Error while trying to spill SGPR0_SGPR1 from class SReg_64:
Cannot scavenge register without an emergency spill slot!
"""
when running glcts KHR-GL46.arrays_of_arrays_gl.AtomicUsage test.
Fixes:
9ff086052ab ("radeonsi: unroll loops of up to 128 iterations")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14848>
Samuel Pitoiset [Wed, 19 Jan 2022 09:08:43 +0000 (10:08 +0100)]
radv: stop setting streamout state when a new pipeline is bound
It's required to have a valid graphics bound pipeline with XFB when
vkCmdBeginTransformFeedbackKHR() is called. This removes extra work
when binding a pipeline.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14610>
Iago Toral Quiroga [Wed, 2 Feb 2022 10:23:11 +0000 (11:23 +0100)]
broadcom/compiler: allow ldunifa with read-only SSBOs
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14830>
Iago Toral Quiroga [Wed, 2 Feb 2022 10:39:53 +0000 (11:39 +0100)]
broadcom/compiler: fix offset alignment for ldunifa when skipping
The intention was to align the address to 4 bytes (32-bit), not
16 bytes.
Fixes:
bdb6201ea1 ("broadcom/compiler: use ldunifa with unaligned constant offset")
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14830>
Dylan Baker [Wed, 2 Feb 2022 23:49:12 +0000 (15:49 -0800)]
docs: update calendar for 22.0.0-rc1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14845>
Dylan Baker [Wed, 2 Feb 2022 23:09:58 +0000 (15:09 -0800)]
docs: reset new_features.txt
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14843>
Mike Blumenkrantz [Wed, 2 Feb 2022 23:00:20 +0000 (18:00 -0500)]
llvmpipe: ci updates
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14835>
Mike Blumenkrantz [Wed, 2 Feb 2022 20:54:45 +0000 (15:54 -0500)]
llvmpipe: disable PIPE_SHADER_CAP_FP16_CONST_BUFFERS
this cap is broken
cc: mesa-stable
fixes:
GTF-GL46.gtf21.GL2Tests.glGetUniform.glGetUnifor
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14835>
Mike Blumenkrantz [Wed, 2 Feb 2022 19:53:45 +0000 (14:53 -0500)]
zink: disable PIPE_SHADER_CAP_FP16_CONST_BUFFERS
this cap is broken
cc: mesa-stable
fixes:
GTF-GL46.gtf21.GL2Tests.glGetUniform.glGetUniform
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14835>
Dylan Baker [Wed, 2 Feb 2022 22:43:00 +0000 (14:43 -0800)]
VERSION: bump version for 22.0 release
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14840>
Bas Nieuwenhuizen [Fri, 28 Jan 2022 20:04:07 +0000 (21:04 +0100)]
radv: Handle SDMA for padding.
Also assert that nobody actually needs to chain an SDMA IB because we have
not implemented non-PKT3 chaining.
Fixes:
ef40f2ccc29 ("radv/amdgpu: Fix handling of IB alignment > 4 words.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5923
Tested-by: Mike Lothian <mike@fireburn.co.uk>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14781>
Emma Anholt [Wed, 26 Jan 2022 00:00:59 +0000 (16:00 -0800)]
intel: Add missing dep of gen_*_header.py on utils.py.
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14725>
Emma Anholt [Tue, 25 Jan 2022 23:50:53 +0000 (15:50 -0800)]
freedreno/isaspec: Add missing dep of encode.py/decode.py calls on isa.py
Fixes: #5921
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14725>
Caio Oliveira [Wed, 19 May 2021 16:35:22 +0000 (09:35 -0700)]
anv: Add experimental support for VK_NV_mesh_shader
Enable setting ANV_EXPERIMENTAL_NV_MESH_SHADER=1 environment variable.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
Caio Oliveira [Wed, 7 Jul 2021 19:47:15 +0000 (12:47 -0700)]
intel/dev: Enable Mesh Shading for DG2
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
Marcin Ślusarz [Mon, 13 Dec 2021 13:14:04 +0000 (14:14 +0100)]
anv: Put first few push constants directly into Task/Mesh InlineData
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
Marcin Ślusarz [Thu, 9 Dec 2021 15:50:24 +0000 (16:50 +0100)]
anv: include ClipDistance array in mesh shader per-vertex output
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
Marcin Ślusarz [Thu, 9 Dec 2021 15:48:03 +0000 (16:48 +0100)]
anv: tell the hardware about gl_[Clip|Cull]Distance in mesh shaders
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
Marcin Ślusarz [Fri, 16 Jul 2021 13:06:44 +0000 (15:06 +0200)]
anv: Implement indirect dispatch for Mesh pipeline
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
Marcin Ślusarz [Mon, 12 Jul 2021 11:46:31 +0000 (13:46 +0200)]
anv: Add support for UBOs, SSBOs and push constants in Mesh pipeline
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
Marcin Ślusarz [Mon, 5 Jul 2021 13:48:03 +0000 (15:48 +0200)]
anv: Add support for non-zero firstTask in vkCmdDrawMeshTasksNV
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
Marcin Ślusarz [Fri, 16 Jul 2021 12:21:51 +0000 (14:21 +0200)]
anv: Enable conditional rendering in vkCmdDrawMeshTasksNV
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
Caio Oliveira [Thu, 20 May 2021 19:07:34 +0000 (12:07 -0700)]
anv: Implement Mesh Shading pipeline
The Mesh pipeline is implemented as a variant of the
regular (primitive) Graphics Pipeline.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
Caio Oliveira [Tue, 18 May 2021 19:13:52 +0000 (12:13 -0700)]
anv: Add boilerplate for VK_NV_mesh_shader
Use minimum values for the properties.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
Caio Oliveira [Fri, 17 Dec 2021 00:47:14 +0000 (16:47 -0800)]
intel/common: Add helper for URB allocation in Mesh pipeline
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
Caio Marcelo de Oliveira Filho [Thu, 8 Jul 2021 19:20:38 +0000 (12:20 -0700)]
intel: Add INTEL_URB_DEREF_BLOCK_SIZE_MESH
And corresponding value in XML.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
Alyssa Rosenzweig [Sat, 29 Jan 2022 17:53:43 +0000 (12:53 -0500)]
pan/va: Add ARM_shader_framebuffer_fetch asm test
This is a nontrivial chunk of code that makes for a nice dis/assembler test
case (and caught a bug already...). Add it to the observatory.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
Alyssa Rosenzweig [Sat, 29 Jan 2022 17:53:05 +0000 (12:53 -0500)]
pan/va: Handle shift lanes in assembler
Noticed in a program using ARM_shader_framebuffer_fetch.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
Alyssa Rosenzweig [Sat, 29 Jan 2022 15:38:39 +0000 (10:38 -0500)]
pan/va: Add lots of swizzle assembler tests
The swizzle handling in ISA.xml was broken in a bunch of place. Now that
we've fixed these issues, let's add tons of tests to validate.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
Alyssa Rosenzweig [Sat, 29 Jan 2022 16:52:02 +0000 (11:52 -0500)]
pan/va: Add 2-channel 8-bit swizzles for conversions
Instructions like V2S8_TO_V2S16 need a special 4-bit special selecting any two
bytes. The definition is the same as Bifrost. Let's call this a half-swizzle
since we need a name, and it is indeed half a swizzle...
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
Alyssa Rosenzweig [Sat, 29 Jan 2022 16:20:49 +0000 (11:20 -0500)]
pan/va: Vectorize 8->16-bit conversions
Matches Bifrost, too.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
Alyssa Rosenzweig [Sat, 29 Jan 2022 16:08:25 +0000 (11:08 -0500)]
pan/va: Fix lane select for [US]_TO_[USF]32
The lane select is in bit 28, this is covered by the "16-bit swizzle" mode.
However, the source type isn't inferred from the name in valhall.py, so
explicitly annotate the source as 16-bit.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
Alyssa Rosenzweig [Sat, 29 Jan 2022 15:51:06 +0000 (10:51 -0500)]
pan/va: Fix MKVEC.v2i16 lane select
The lanes are at bit 28 and bit 26 respectively. This matches the 16-bit "swizzle" encoding. In general the handling of widens/swizzles/lane/lanes on Valhall is rather confused but... one problem at a time.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
Alyssa Rosenzweig [Fri, 28 Jan 2022 23:02:22 +0000 (18:02 -0500)]
pan/va: Test LD_TILE assembly
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
Alyssa Rosenzweig [Fri, 28 Jan 2022 23:02:06 +0000 (18:02 -0500)]
pan/va: Add missing fields to LD_TILE
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
Alyssa Rosenzweig [Fri, 28 Jan 2022 22:17:25 +0000 (17:17 -0500)]
pan/va: Add missing <clamp/> to V2F32_TO_V2F16
For parity with Bifrost.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
Alyssa Rosenzweig [Wed, 2 Feb 2022 17:20:19 +0000 (12:20 -0500)]
pan/va: Add .absolute bit to BRANCHZI
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
Lionel Landwerlin [Fri, 5 Feb 2021 19:16:38 +0000 (21:16 +0200)]
anv: Update VK_KHR_fragment_shading_rate for newer HW
Per primitive & attachment shading rate support added.
v2: Rebase on KHR_dynamic_rendering
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
Lionel Landwerlin [Tue, 1 Feb 2022 19:57:19 +0000 (21:57 +0200)]
anv/pass: rely on precomputed dynamic rendering pass/subpass more
For instance, the current code in genX_cmd_buffer.c assumes that the
depth/stencil attachments & resolves will be at the end of all
attachments, but that won't be the case anymore with fragment rate
shading.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
Lionel Landwerlin [Wed, 17 Feb 2021 12:39:08 +0000 (14:39 +0200)]
anv: force primitive shading rate write in last geometry stage
v2: Use new helper to check if stage supports variable shading rate
setting
v3: Update comment & iterate backward (Caio)
Apply only to relevant platforms (Lionel)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
Lionel Landwerlin [Tue, 10 Nov 2020 16:08:31 +0000 (18:08 +0200)]
intel/compiler: add primitive rate output support
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
Lionel Landwerlin [Wed, 17 Feb 2021 11:47:36 +0000 (13:47 +0200)]
intel/compiler: add a new pass to lower shading rate into HW format
Rework:
* Jason: Modernize brw_nir_lower_shading_rate_output:
1. Use nir_shader_instructions_pass()
2. Use *_imm builder helpers.
3. Use nir_intrinsic_base() instead of ->const_index[0]
v2: Also lower loads (Caio)
v3: Update stage check to trigger lowering (Caio)
v4: Assert on != MESH (Caio)
v5: Fixup instruction insertion (Caio)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
Lionel Landwerlin [Tue, 23 Nov 2021 08:13:42 +0000 (10:13 +0200)]
nir/builder: add ishl_imm helper
v2: add (y >= x->bit_size) condition (Caio)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
Lionel Landwerlin [Thu, 27 Jan 2022 08:26:58 +0000 (10:26 +0200)]
isl: disable CPB surface compression
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
Lionel Landwerlin [Fri, 6 Nov 2020 15:03:33 +0000 (17:03 +0200)]
isl: add support for coarse pixel control surfaces
Those surfaces are used as attachment to rendering passes and describe
the rate of coarse pixel shading for the pass.
v2: Move CPB_BIT tile filtering to isl_gfx125_filter_tiling() (Nanley)
v3: Drop unused macro (Nanley)
s/isl_to_gen/isl_encode/ (Nanley)
Remove pitch alignment 128B constraint already covered by tiling (Nanley)
Move some asserts together (Nanley)
v4: Disable miptail for now (Nanley)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
Lionel Landwerlin [Fri, 6 Nov 2020 14:17:16 +0000 (16:17 +0200)]
intel/dev: details CPS feature support
DG2 introduces per primitive coarse pixel settings (in stages
preceding the PS shader) and also a control surface specifying the
rate at through the resulting surface.
v2: update comment (Caio)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
Lionel Landwerlin [Fri, 5 Feb 2021 12:39:33 +0000 (14:39 +0200)]
genxml: add new 3DSTATE_PS_EXTRA bit
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
Lionel Landwerlin [Thu, 5 Nov 2020 14:20:41 +0000 (16:20 +0200)]
genxml: gen12.5 changes for CPS
v2: Make genxml look more like BSpec (Caio)
Fixup X_Focal/Y_Focal entries (Caio)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
Lionel Landwerlin [Mon, 8 Feb 2021 16:29:26 +0000 (18:29 +0200)]
compiler: add VARYING bit for primitive shading rate
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
Filip Gawin [Wed, 6 Oct 2021 14:50:21 +0000 (16:50 +0200)]
r300: replace recursive calls with loops
Recursive "loops" tend to be more difficult to follow
and understand. Additionally iterative approach should be
nicer for compiler. (Less to allocate on stack and easier to optimize)
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13226>
Nanley Chery [Tue, 1 Feb 2022 19:02:16 +0000 (14:02 -0500)]
intel/isl: Add more PRM text for HiZ/STC requirement
Add text describing why HierarchicalDepthBufferEnable must be set along
with SeparateStencilBufferEnable.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14825>
Nanley Chery [Mon, 31 Jan 2022 21:07:34 +0000 (16:07 -0500)]
intel/isl: Fix depth buffer TiledSurface programming
The assert for the TiledSurface field caught a programming error, but
with a segfault instead of the usual route of assert-failing. We only
set this field when we have a depth surface, but we also need to set it
when one isn't provided. Fix this issue and drop the assert.
Fixes:
b77d694223a ("intel/isl: Allow HiZ with Tile4/64 surfaces")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5950
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14825>
Nanley Chery [Tue, 1 Feb 2022 18:51:06 +0000 (13:51 -0500)]
intel/isl: Simplify Z-buffer tiling config during emit
For SNB and prior, assert that the surface is Y-tiled and use constants
when configuring the tiling parameters. This makes a follow-on commit
clearer.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14825>
Shmerl [Sun, 30 Jan 2022 02:08:09 +0000 (21:08 -0500)]
docs/features: Add VK_KHR_acceleration_structure, VK_KHR_pipeline_library, VK_KHR_ray_query, VK_KHR_ray_tracing_pipeline.
Closes: #5901
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14796>
Chia-I Wu [Fri, 28 Jan 2022 05:26:28 +0000 (21:26 -0800)]
venus: update venus-protocol to 1.3.204
There should be no visible functional change. Although an unrelated
change in the codegen replaced vn_info_extension_spec_version by
vn_info_extension_get. We have to adapt to that.
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14782>
Emma Anholt [Sun, 30 Jan 2022 04:27:01 +0000 (20:27 -0800)]
r300/r600: Add drm-shim support.
I was tired of swapping gpus around just to check shader-db results of MRs
for these. I put it in src/amd since it doesn't make sense in either of
r300 or r600.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14809>
Emma Anholt [Mon, 31 Jan 2022 18:11:15 +0000 (10:11 -0800)]
r300: Disable fp16 and int16 in swtcl vertex shaders.
We already had them disabled for hwtcl, but in the swtcl case gallivm's
param query would return (nir) support even though nir-to-tgsi couldn't
handle it because TGSI doesn't do fp16/int16.
Fixes:
7d2ea9b0edef ("r300: Request NIR shaders from mesa/st and use NIR-to-TGSI.")
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14809>
Iván Briano [Tue, 1 Feb 2022 21:44:25 +0000 (13:44 -0800)]
anv: Report the right conformance version
Fixes:
df8ac77af80 ("anv: Advertise Vulkan 1.3")
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14827>
Iván Briano [Sat, 29 Jan 2022 01:17:09 +0000 (17:17 -0800)]
anv: Handle resolveImageLayout on dynamic rendering
Fixes:
5d9e8bc9be6 ("anv: implement the meat of VK_KHR_dynamic_rendering")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5942
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14812>
Mike Blumenkrantz [Tue, 1 Feb 2022 17:20:51 +0000 (12:20 -0500)]
docs: update features/relnotes for zink sparse texture clamp
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14813>
Mike Blumenkrantz [Fri, 14 Jan 2022 15:43:44 +0000 (10:43 -0500)]
zink: ARB_sparse_texture_clamp
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14813>