platform/kernel/u-boot.git
3 years agobuild_bug.h: add wrapper for _Static_assert
Rasmus Villemoes [Tue, 18 May 2021 09:19:46 +0000 (11:19 +0200)]
build_bug.h: add wrapper for _Static_assert

[Linux commit 6bab69c65013bed5fce9f101a64a84d0385b3946]

BUILD_BUG_ON() is a little annoying, since it cannot be used outside
function scope.  So one cannot put assertions about the sizeof() a
struct next to the struct definition, but has to hide that in some more
or less arbitrary function.

Since gcc 4.6 (which is now also the required minimum), there is support
for the C11 _Static_assert in all C modes, including gnu89.  So add a
simple wrapper for that.

_Static_assert() requires a message argument, which is usually quite
redundant (and I believe that bug got fixed at least in newer C++
standards), but we can easily work around that with a little macro
magic, making it optional.

For example, adding

  static_assert(sizeof(struct printf_spec) == 8);

in vsprintf.c and modifying that struct to violate it, one gets

./include/linux/build_bug.h:78:41: error: static assertion failed: "sizeof(struct printf_spec) == 8"
 #define __static_assert(expr, msg, ...) _Static_assert(expr, "" msg "")

godbolt.org suggests that _Static_assert() has been support by clang
since at least 3.0.0.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agoMerge tag 'xilinx-for-v2021.10' of https://source.denx.de/u-boot/custodians/u-boot...
Tom Rini [Thu, 1 Jul 2021 12:57:23 +0000 (08:57 -0400)]
Merge tag 'xilinx-for-v2021.10' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2021.10

clk:
- Add driver for Xilinx Clocking Wizard IP

fdt:
- Also record architecture in /fit-images

net:
- Fix plat/priv data handling in axi emac
- Add support for 10G/25G speeds

pca953x:
- Add missing dependency on i2c

serial:
- Fix dependencies for DEBUG uart for pl010/pl011
- Add setconfig option for cadence serial driver

watchdog:
- Add cadence wdt expire now function

zynq:
- Update DT bindings to reflect the latest state and descriptions

zynqmp:
- Update DT bindings to reflect the latest state and descriptions
- SPL: Add support for ECC DRAM initialization
- Fix R5 core 1 handling logic
- Enable firmware driver for mini configurations
- Enable secure boot, regulators, wdt
- Add support xck devices and 67dr
- Add psu init for sm/smk-k26 SOMs
- Add handling for MMC seq number via mmc_get_env_dev()
- Handle reserved memory locations
- Add support for u-boot.itb generation for secure OS
- Handle BL32 handoffs for secure OS
- Add support for 64bit addresses for u-boot.its generation
- Change eeprom handling via nvmem aliases

3 years agoxilinx: zynqmp: Add support for 67dr silicon
T Karthik Reddy [Thu, 13 May 2021 13:13:25 +0000 (07:13 -0600)]
xilinx: zynqmp: Add support for 67dr silicon

Add zynqmp 67dr silicon to zynqmp device id table.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agowatchdog: cadence: Add expire_now method
Michal Simek [Mon, 28 Jun 2021 11:44:16 +0000 (13:44 +0200)]
watchdog: cadence: Add expire_now method

It is working in a way that only minimal timeout is setup to reach
expiration just right after it is setup.
Please make sure that PMUFW is compiled with ENABLE_EM flag.

On U-Boot prompt you can test it like:
ZynqMP> wdt dev watchdog@fd4d0000
ZynqMP> wdt list
watchdog@fd4d0000 (cdns_wdt)
ZynqMP> wdt dev
dev: watchdog@fd4d0000
ZynqMP> wdt expire
(And reset should happen here)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoarm64: zynqmp: Enable WDT command
Michal Simek [Mon, 28 Jun 2021 09:18:43 +0000 (11:18 +0200)]
arm64: zynqmp: Enable WDT command

Enable watchdog command to be able to work with watchdogs.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoMerge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-spi into next
Tom Rini [Wed, 30 Jun 2021 19:48:09 +0000 (15:48 -0400)]
Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-spi into next

- Cypress s25hl-t/s25hs-t support (Takahiro Kuwano)

3 years agomtd: spi-nor-tiny: Add fixups for Cypress s25hl-t/s25hs-t
Takahiro Kuwano [Tue, 29 Jun 2021 06:01:04 +0000 (15:01 +0900)]
mtd: spi-nor-tiny: Add fixups for Cypress s25hl-t/s25hs-t

Fixes mode clocks for SPINOR_OP_READ_FAST_4B in tiny.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agomtd: spi-nor-core: Add fixups for Cypress s25hl-t/s25hs-t
Takahiro Kuwano [Tue, 29 Jun 2021 06:01:03 +0000 (15:01 +0900)]
mtd: spi-nor-core: Add fixups for Cypress s25hl-t/s25hs-t

The nor->ready() and spansion_sr_ready() introduced earlier in this
series are used for multi-die package parts.

The nor->quad_enable() sets the volatile QE bit on each die.

The nor->erase() is hooked if the device is not configured to uniform
sectors, assuming it has 32 x 4KB sectors overlaid on bottom address.
Other configurations, top and split, are not supported at this point.
Will submit additional patches to support it as needed.

The post_bfpt/sfdp() fixes the params wrongly advertised in SFDP.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agomtd: spi-nor-core: Add Cypress manufacturer ID in set_4byte
Takahiro Kuwano [Tue, 29 Jun 2021 06:01:02 +0000 (15:01 +0900)]
mtd: spi-nor-core: Add Cypress manufacturer ID in set_4byte

Cypress chips support SPINOR_OP_EN4B(B7h) to enable 4-byte addressing mode.

Cypress chips support B8h to disable 4-byte addressing mode instead of
SPINOR_OP_EX4B(E9h).

This patch defines new opcode and updates set_4byte() to support
enable/disable 4-byte addressing mode for Cypress chips.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agomtd: spi-nor-core: Read status by Read Any Register
Takahiro Kuwano [Tue, 29 Jun 2021 06:01:01 +0000 (15:01 +0900)]
mtd: spi-nor-core: Read status by Read Any Register

The spansion_sr_ready() reads status register 1 by Read Any Register
commnad. This function is called from Flash specific hook with die address
and dummy cycles to support multi-die package parts from Spansion/Cypress.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agomtd: spi-nor-core: Add the ->ready() hook
Takahiro Kuwano [Tue, 29 Jun 2021 06:01:00 +0000 (15:01 +0900)]
mtd: spi-nor-core: Add the ->ready() hook

For dual/quad die package devices from Spansion/Cypress, the device's
status needs to be checked by reading status registers in all dies, by
using Read Any Register command. To support this, a Flash specific hook
that can overwrite the legacy status check is needed.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agomtd: spi-nor-core: Add support for volatile QE bit
Takahiro Kuwano [Tue, 29 Jun 2021 06:00:59 +0000 (15:00 +0900)]
mtd: spi-nor-core: Add support for volatile QE bit

Some of Spansion/Cypress chips support volatile version of configuration
registers and it is recommended to update volatile registers in the field
application due to a risk of the non-volatile registers corruption by
power interrupt. This patch adds a function to set Quad Enable bit in CFR1
volatile.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agomtd: spi-nor-core: Add support for Read/Write Any Register
Takahiro Kuwano [Tue, 29 Jun 2021 06:00:58 +0000 (15:00 +0900)]
mtd: spi-nor-core: Add support for Read/Write Any Register

Some of Spansion/Cypress chips support Read/Write Any Register commands.
These commands are mainly used to write volatile registers and access to
the registers in second and subsequent die for multi-die package parts.

The Read Any Register instruction (65h) is followed by register address
and dummy cycles, then the selected register byte is returned.

The Write Any Register instruction (71h) is followed by register address
and register byte to write.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agomtd: spi-nor-ids: Add Cypress s25hl-t/s25hs-t
Takahiro Kuwano [Tue, 29 Jun 2021 06:00:57 +0000 (15:00 +0900)]
mtd: spi-nor-ids: Add Cypress s25hl-t/s25hs-t

The S25HL-T/S25HS-T family is the Cypress Semper Flash with Quad SPI.

https://www.cypress.com/file/424146/download (256Mb/512Mb/1Gb, single die)
https://www.cypress.com/file/499246/download (2Gb/4Gb, dual/quad die)

The full version can be found in the following links (registration
required).
https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-Semper-Flash-with-Quad-SPI/ta-p/260789?attachment-id=19522
https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-2Gb-MCP-Semper-Flash-with-Quad-SPI/ta-p/260823?attachment-id=29503

S25HL/HS-T (Semper Flash with Quad SPI) Family has user-configurable
sector architecture. By default, the 512Mb and 1Gb, single-die package
parts are configured to non-uniform that 4KB sectors overlaid on bottom
address. To support this, an erase hook makes overlaid sectors appear as
uniform sectors. The 2Gb, dual-die package parts are configured to uniform
by default.

Tested on Xilinx Zynq-7000 FPGA board.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agomtd: spi-nor: Add Cypress manufacturer ID
Takahiro Kuwano [Tue, 29 Jun 2021 06:00:56 +0000 (15:00 +0900)]
mtd: spi-nor: Add Cypress manufacturer ID

This patch adds Cypress manufacturer ID (34h) definition.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agoMerge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-sh into next
Tom Rini [Mon, 28 Jun 2021 22:32:07 +0000 (18:32 -0400)]
Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-sh into next

- V3U Falcon board support

3 years agoMerge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-spi into next
Tom Rini [Mon, 28 Jun 2021 22:31:53 +0000 (18:31 -0400)]
Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-spi into next

- xSPI Octal DTR support (Pratyush Yadav)
- MXIC SPI driver (Zhengxun)

3 years agoMerge tag 'v2021.07-rc5' into next
Tom Rini [Mon, 28 Jun 2021 20:22:13 +0000 (16:22 -0400)]
Merge tag 'v2021.07-rc5' into next

Prepare v2021.07-rc5

# gpg: Signature made Mon 28 Jun 2021 03:39:36 PM EDT
# gpg:                using RSA key 1A3C7F70E08FAB1707809BBF147C39FF9634B72C
# gpg: Good signature from "Thomas Rini <trini@konsulko.com>" [ultimate]

# Conflicts:
# configs/am64x_evm_r5_defconfig

3 years agoPrepare v2021.07-rc5
Tom Rini [Mon, 28 Jun 2021 19:38:55 +0000 (15:38 -0400)]
Prepare v2021.07-rc5

Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agoarm64: Fix relocation of env_addr if POSITION_INDEPENDENT=y
Kunihiko Hayashi [Tue, 15 Jun 2021 06:33:02 +0000 (15:33 +0900)]
arm64: Fix relocation of env_addr if POSITION_INDEPENDENT=y

If both POSITION_INDEPENDENT and SYS_RELOC_GD_ENV_ADDR are enabled,
wherever original env is placed anywhere, it should be relocated to
the right address.

Relocation offset gd->reloc_off is calculated with SYS_TEXT_BASE in
setup_reloc() and env address gd->env_addr is relocated by the offset in
initr_reloc_global_data().

gd->env_addr
  = (orig env) + gd->reloc_off
  = (orig env) + (gd->relocaddr - SYS_TEXT_BASE)

However, SYS_TEXT_BASE isn't always runtime base address when
POSITION_INDEPENDENT is enabled. So the relocated env_addr might point to
wrong address. For example, if SYS_TEXT_BASE is zero, gd->env_addr is
out of memory location and memory exception will occur.

There is a difference between linked address such as SYS_TEXT_BASE and
runtime base address. In _main, the difference is calculated as
"run-vs-link" offset. The env_addr should also be added to the offset
to fix the address.

gd->env_addr
  = (orig env) + ("run-vs-link" offset)   + gd->reloc_off
  = (orig env) + (SYS_TEXT_BASE - _start) + (gd->relocaddr - SYS_TEXT_BASE)
  = (orig env) + (gd->relocaddr - _start)

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Marek Vasut <marex@denx.de>
3 years agoconfigs: Resync with savedefconfig
Tom Rini [Mon, 28 Jun 2021 14:17:29 +0000 (10:17 -0400)]
configs: Resync with savedefconfig

Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agoarm64: dts: zynqmp: Add psgtr and phy entry for USB and SATA node
Piyush Mehta [Mon, 21 Jun 2021 04:41:27 +0000 (10:11 +0530)]
arm64: dts: zynqmp: Add psgtr and phy entry for USB and SATA node

This patch adds psgtr clocks and phy entry for USB0, USB1 and SATA node for
zc1751-xm017-dc3 board.

Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agonet: xilinx: axi_emac: Add support for 10G/25G AXI ethernet
Ashok Reddy Soma [Thu, 24 Jun 2021 06:34:41 +0000 (00:34 -0600)]
net: xilinx: axi_emac: Add support for 10G/25G AXI ethernet

Add support for 10G/25G (XXV) high speed ethernet. This Makes use of
the exiting AXI DMA, similar to 1G.

Signed-off-by: Alessandro Temil <atemil@waymo.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agonet: xilinx: axi_emac: Cleanup of of_to_plat()
Ashok Reddy Soma [Thu, 24 Jun 2021 06:34:40 +0000 (00:34 -0600)]
net: xilinx: axi_emac: Cleanup of of_to_plat()

There are lot of accesses to priv data in of_to_plat(), which is incorrect.
Create a platform data structure and use it in of_to_plat(), then copy all
platform data to priv data in probe.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoserial: zynq: Add support for serial parameters
Kunihiko Hayashi [Fri, 25 Jun 2021 11:19:11 +0000 (20:19 +0900)]
serial: zynq: Add support for serial parameters

This adds serial parameters that include stop bit mode, parity mode,
and character length. Mark parity and space parity modes are not
supported.

At the moment, the only path to call setconfig directly is DM testing,
however, this affects the size of SPL for DM testing, so it doesn't
apply to SPL.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
3 years agoserial: Add additional depencies for PL010 and PL011 drivers
Michal Simek [Thu, 24 Jun 2021 11:36:23 +0000 (13:36 +0200)]
serial: Add additional depencies for PL010 and PL011 drivers

Both of these drivers are implemented with and without DM that's why more
symbols should be handled.
The most problematic one is enabling DEBUG_UART_PL011 based on
PL01X_SERIAL(DM based) because debug console has type selection based on
it.
enum pl01x_type type = CONFIG_IS_ENABLED(DEBUG_UART_PL011) ?
TYPE_PL011 : TYPE_PL010;

Without it pl01x_generic_setbrg() is configuring different registers.

Fixes: 4cc24aeaf420 ("serial: Add missing Kconfig dependencies for debug consoles")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agomtd: spi-nor-core: Allow using Micron mt35xu512aba in Octal DTR mode
Pratyush Yadav [Fri, 25 Jun 2021 19:17:29 +0000 (00:47 +0530)]
mtd: spi-nor-core: Allow using Micron mt35xu512aba in Octal DTR mode

Since this flash doesn't have a Profile 1.0 table, the Octal DTR
capabilities are enabled in the post SFDP fixup, along with the 8D-8D-8D
fast read settings.

Enable Octal DTR mode with 20 dummy cycles to allow running at the
maximum supported frequency of 200Mhz.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agomtd: spi-nor-core: Add support for Cypress Semper flash
Pratyush Yadav [Fri, 25 Jun 2021 19:17:28 +0000 (00:47 +0530)]
mtd: spi-nor-core: Add support for Cypress Semper flash

The Cypress Semper flash is an xSPI compliant octal DTR flash. Add
support for using it in octal DTR mode.

The flash by default boots in a hybrid sector mode. Switch to uniform
sector mode on boot. Use the default 20 dummy cycles for a read fast
command.

The SFDP programming on some older versions of the flash was incorrect.
Fixes for that are included in the fixup hooks.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agomtd: spi-nor-core: Add non-uniform erase for Spansion/Cypress
Takahiro Kuwano [Fri, 25 Jun 2021 19:17:27 +0000 (00:47 +0530)]
mtd: spi-nor-core: Add non-uniform erase for Spansion/Cypress

Some of Spansion/Cypress chips have overlaid 4KB sectors at top and/or
bottom, depending on the device configuration, while U-Boot supports
uniform sector layout only.

The spansion_erase_non_uniform()  erases overlaid 4KB sectors,
non-overlaid portion of normal sector, and remaining normal sectors, by
selecting correct erase command and size based on the address to erase
and size of overlaid portion in parameters. Since different Spansion
flashes can use different opcode for erasing the 4K sectors, the opcode
must be passed in as a parameter based on the flash being used.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
[p.yadav@ti.com: Refactor the function to be compatible with nor->erase,
make 4K opcode customizable, call spi_nor_setup_op() before executing
the op.]
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agomtd: spi-nor-core: allow truncated erases
Pratyush Yadav [Fri, 25 Jun 2021 19:17:26 +0000 (00:47 +0530)]
mtd: spi-nor-core: allow truncated erases

On devices with non-uniform sector sizes like Spansion S25 or S28 family
of flashes the sector under erase does not necessarily have to be
mtd->erasesize bytes long. For example, on S28 flashes the first 128 KiB
region is composed of 32 4 KiB sectors, then a 128 KiB sector, and then
256 KiB sectors till the end.

Let the flash-specific erase functions erase less than the requested
length in case of the 4 or 128 KiB sectors and report the number of
bytes erased back to the calling function.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agomtd: spi-nor-core: Perform a Soft Reset on boot
Pratyush Yadav [Fri, 25 Jun 2021 19:17:25 +0000 (00:47 +0530)]
mtd: spi-nor-core: Perform a Soft Reset on boot

When the flash is handed to us in a stateful mode like 8D-8D-8D, it is

difficult to detect the mode the flash is in. One option is to read SFDP
in all modes and see which one gives the correct "SFDP" signature, but
not all flashes support SFDP in 8D-8D-8D mode.

Further, even if you detect the mode of the flash via SFDP, you still
have the problem of actually reading the ID. The Read ID command is not
standardized across flash vendors. Flashes can have different dummy
cycles needed for reading the ID. Some flashes even expect a 4-byte
dummy address with the Read ID command. All this information cannot be
obtained from the SFDP table.

So, perform a Software Reset sequence before reading the ID and
initializing the flash. A Soft Reset will bring back the flash in its
default protocol mode assuming no non-volatile configuration was set.
This will let us detect the flash even if ROM hands it to us in Octal
DTR mode.

To accommodate cases where there is more than one flash on a board, and
only one of them needs a soft reset, failure to reset is not made fatal,
and we still try to read ID if possible.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agomtd: spi-nor-core: Perform a Soft Reset on shutdown
Pratyush Yadav [Fri, 25 Jun 2021 19:17:24 +0000 (00:47 +0530)]
mtd: spi-nor-core: Perform a Soft Reset on shutdown

On probe, the SPI NOR core will put a flash in 8D-8D-8D mode if it
supports it. But Linux as of now expects to get the flash in 1S-1S-1S
mode. Handing the flash to Linux in Octal DTR mode means the kernel will
fail to detect the flash.

So, we need to reset to Power-on-Reset (POR) state before handing off
the flash. A Software Reset command can be used to do this.

One limitation of the soft reset is that it will restore state from
non-volatile registers in some flashes. This means that if the flash was
set to 8D mode in a non-volatile configuration, a soft reset won't help.
This commit assumes that we don't set any non-volatile bits anywhere,
and the flash doesn't have any non-volatile Octal DTR mode
configuration.

Since spi-nor-tiny doesn't (and likely shouldn't) have
spi_nor_soft_reset(), add a dummy spi_nor_remove() for it that does
nothing.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agomtd: spi-nor-core: Detect Soft Reset sequence support from BFPT
Pratyush Yadav [Fri, 25 Jun 2021 19:17:23 +0000 (00:47 +0530)]
mtd: spi-nor-core: Detect Soft Reset sequence support from BFPT

A Soft Reset sequence will return the flash to Power-on-Reset (POR)
state. It consists of two commands: Soft Reset Enable and Soft Reset.
Find out if the sequence is supported from BFPT DWORD 16.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agomtd: spi-nor-core: Do not make invalid quad enable fatal
Pratyush Yadav [Fri, 25 Jun 2021 19:17:22 +0000 (00:47 +0530)]
mtd: spi-nor-core: Do not make invalid quad enable fatal

The Micron MT35XU512ABA flash does not support the quad enable bit. But
instead of programming the Quad Enable Require field to 000b ("Device
does not have a QE bit"), it is programmed to 111b ("Reserved").

While this is technically incorrect, it is not reason enough to abort
BFPT parsing. Instead, continue BFPT parsing assuming there is no quad
enable bit present.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agomtd: spi-nor-core: Enable octal DTR mode when possible
Pratyush Yadav [Fri, 25 Jun 2021 19:17:21 +0000 (00:47 +0530)]
mtd: spi-nor-core: Enable octal DTR mode when possible

Allow flashes to specify a hook to enable octal DTR mode. Use this hook
whenever possible to get optimal transfer speeds.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agomtd: spi-nor-core: Prepare Read SR and FSR for Octal DTR mode
Pratyush Yadav [Fri, 25 Jun 2021 19:17:20 +0000 (00:47 +0530)]
mtd: spi-nor-core: Prepare Read SR and FSR for Octal DTR mode

The xSPI Profile 1.0 table specifies how many dummy cycles and address
bytes are needed for the Read Status Register command in Octal DTR mode.
Use that information to send the correct Read SR command.

Some controllers might have trouble reading just 1 byte in DTR mode. So,
when we are in DTR mode read 2 bytes and discard the second. This shows
no side effects with the two flashes I tested: Micron mt35xu512aba and
Cypress s28hs512t.

Update Read FSR to mimic Read SR because they share the same
characteristics.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agomtd: spi-nor-core: Parse xSPI Profile 1.0 table
Pratyush Yadav [Fri, 25 Jun 2021 19:17:19 +0000 (00:47 +0530)]
mtd: spi-nor-core: Parse xSPI Profile 1.0 table

This table is indication that the flash is xSPI compliant and hence
supports octal DTR mode. Extract information like the fast read opcode,
the number of dummy cycles needed for a Read Status Register command,
and the number of address bytes needed for a Read Status Register
command.

The default dummy cycles for a fast octal DTR read are set to 20. Since
there is no simple way of determining the dummy cycles needed for the
fast read command, flashes that use a different value should update it
in their flash-specific hooks.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agomtd: spi-nor-core: Get command opcode extension type from BFPT
Pratyush Yadav [Fri, 25 Jun 2021 19:17:18 +0000 (00:47 +0530)]
mtd: spi-nor-core: Get command opcode extension type from BFPT

Some devices in DTR mode expect an extra command byte called the
extension. The extension can either be same as the opcode, bitwise
inverse of the opcode, or another additional byte forming a 16-byte
opcode. Get the extension type from the BFPT. For now, only flashes with
"repeat" and "inverse" extensions are supported.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agomtd: spi-nor-core: prepare BFPT parsing for JESD216 rev D
Pratyush Yadav [Fri, 25 Jun 2021 19:17:17 +0000 (00:47 +0530)]
mtd: spi-nor-core: prepare BFPT parsing for JESD216 rev D

JESD216 rev D makes BFPT 20 DWORDs. Update the BFPT size define to
reflect that.

The check for rev A or later compared the BFPT header length with the
maximum BFPT length, BFPT_DWORD_MAX. Since BFPT_DWORD_MAX was 16, and so
was the BFPT length for both rev A and B, this check worked fine. But
now, since BFPT_DWORD_MAX is 20, it means this check will also stop BFPT
parsing for rev A or B, since their length is 16.

So, instead check for BFPT_DWORD_MAX_JESD216 to stop BFPT parsing for
the first JESD216 version, and check for BFPT_DWORD_MAX_JESD216B for the
next two versions.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agomtd: spi-nor-core: Add support for DTR protocol
Pratyush Yadav [Fri, 25 Jun 2021 19:17:16 +0000 (00:47 +0530)]
mtd: spi-nor-core: Add support for DTR protocol

Double Transfer Rate (DTR) is SPI protocol in which data is transferred
on each clock edge as opposed to on each clock cycle. Make
framework-level changes to allow supporting flashes in DTR mode.

Right now, mixed DTR modes are not supported. So, for example a mode
like 4S-4D-4D will not work. All phases need to be either DTR or STR.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agomtd: spi-nor-core: Do not set data direction when there is no data
Pratyush Yadav [Fri, 25 Jun 2021 19:17:15 +0000 (00:47 +0530)]
mtd: spi-nor-core: Do not set data direction when there is no data

Even when spi_nor_write_reg() has no data to write, like when executing
a write enable operation, it sets the data direction to
SPI_MEM_DATA_OUT. This trips up spi_mem_check_buswidth() because it
expects a data phase when there is none. Make sure the data direction is
set to SPI_MEM_NO_DATA when there is no data to write.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agomtd: spi-nor-core: Rework hwcaps selection
Pratyush Yadav [Fri, 25 Jun 2021 19:17:14 +0000 (00:47 +0530)]
mtd: spi-nor-core: Rework hwcaps selection

The spi-mem layer provides a spi_mem_supports_op() function to check
whether a specific operation is supported by the controller or not.
This is much more accurate than the hwcaps selection logic based on
SPI_{RX,TX}_ flags.

Rework the hwcaps selection logic to use spi_mem_supports_op().

To make sure the build doesn't break for boards not using CONFIG_DM_SPI,
add a simple SPI_{RX,TX}_ based hwcaps selection logic in spi-mem-nodm
similar to spi_mem_default_supports_op(). This change is only
compile-tested.

To avoid SPL size problems on the x530 board, the old hwcaps selection
is still kept around. Leaving the code in-place was getting difficult to
read and understand, so the code is restructured to have it all in one
isolated function. As a result of this, the parameter hwcaps to
spi_nor_setup() is no longer needed. Remove it.

Based on the Linux commit c76f5089796a (mtd: spi-nor: Rework hwcaps
selection for the spi-mem case, 2019-08-06)

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agomtd: spi-nor-core: Introduce flash-specific fixup hooks
Pratyush Yadav [Fri, 25 Jun 2021 19:17:13 +0000 (00:47 +0530)]
mtd: spi-nor-core: Introduce flash-specific fixup hooks

Sometimes the information in a flash's SFDP tables is wrong. Sometimes
some information just can't be expressed in the SFDP table. So,
introduce the fixup hooks to allow tailoring settings for a specific
flash.

Three hooks are added: default_init, post_sfdp, and post_bfpt. These
allow tweaking the flash settings at different point in the probe
sequence. Since the hooks reside in nor->info, set that value just
before the call to spi_nor_init_params().

The hooks and at what points they are executed mimics Linux's spi-nor
framework. One major difference is that Linux puts the struct
spi_nor_fixups in nor->info. This is not possible in U-Boot because the
spi-nor-ids list is shared between spi-nor-core.c and spi-nor-tiny.c.
Since spi-nor-tiny shouldn't have those fixup hooks populated, add a
separate function that lets flashes populate their fixup hooks.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agomtd: spi-nor-core: Move SFDP related declarations to top
Pratyush Yadav [Fri, 25 Jun 2021 19:17:12 +0000 (00:47 +0530)]
mtd: spi-nor-core: Move SFDP related declarations to top

These structures will be used in a later commit inside another structure
definition. Also take the declarations out of the ifdef since they won't
affect the final binary anyway and will be used in a later commit.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agomtd: spi-nor-core: Add a ->setup() hook
Pratyush Yadav [Fri, 25 Jun 2021 19:17:11 +0000 (00:47 +0530)]
mtd: spi-nor-core: Add a ->setup() hook

nor->setup() can be used by flashes to configure settings in case they
have any peculiarities that can't be easily expressed by the generic
spi-nor framework. This includes things like different opcodes, dummy
cycles, page size, uniform/non-uniform sector sizes, etc.

Move related declarations to avoid forward declarations.

Inspired by the Linux kernel's setup() hook.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agomtd: spi-nor-core: Fix address width on flash chips > 16MB
Pratyush Yadav [Fri, 25 Jun 2021 19:17:10 +0000 (00:47 +0530)]
mtd: spi-nor-core: Fix address width on flash chips > 16MB

If a flash chip has more than 16MB capacity but its BFPT reports
BFPT_DWORD1_ADDRESS_BYTES_3_OR_4, the spi-nor framework defaults to 3.

The check in spi_nor_scan() doesn't catch it because addr_width did get
set. This fixes that check.

Ported from Kernel commit 324f78dfb442b82365548b657ec4e6974c677502.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agospi: cadence-qspi: Add support for octal DTR flashes
Pratyush Yadav [Fri, 25 Jun 2021 19:17:09 +0000 (00:47 +0530)]
spi: cadence-qspi: Add support for octal DTR flashes

Set up opcode extension and enable/disable DTR mode based on whether the
command is DTR or not.

xSPI flashes can have a 4-byte dummy address associated with some
commands like the Read Status Register command in octal DTR mode. Since
the flash does not support sending the dummy address, we can not use
automatic write completion polling in DTR mode. Further, no write
completion polling makes it impossible to use DAC mode for DTR writes.
In that mode, the controller does not know beforehand how long a write
will be and so it can de-assert Chip Select (CS#) at any time. Once CS#
is de-assert, the flash will go into burning phase. But since the
controller does not do write completion polling, it does not know when
the flash is busy and might send in writes while the flash is not ready.

So, disable write completion polling and make writes go through indirect
mode for DTR writes and let spi-mem take care of polling the SR.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agospi: cadence-qspi: Add a small delay before indirect writes
Pratyush Yadav [Fri, 25 Jun 2021 19:17:08 +0000 (00:47 +0530)]
spi: cadence-qspi: Add a small delay before indirect writes

Once the start bit is toggled it takes a small amount of time before it
is internally synchronized. This means we can't start writing during
that part. So add a small delay to allow the bit to be synchronized.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agospi: cadence-qspi: Do not calibrate when device tree sets read delay
Pratyush Yadav [Fri, 25 Jun 2021 19:17:07 +0000 (00:47 +0530)]
spi: cadence-qspi: Do not calibrate when device tree sets read delay

If the device tree provides a read delay value, use that directly and do
not perform the calibration procedure.

This allows the device tree to over-ride the read delay value in cases
where the read delay value obtained via calibration is incorrect. One
such example is the Cypress Semper flash. It needs a read delay of 4 in
octal DTR mode. But since the calibration procedure is run before the
flash is switched in octal DTR mode, it yields a read delay of 2. A
value of 4 works for both octal DTR and legacy modes.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agospi: spi-mem: add spi_mem_dtr_supports_op()
Pratyush Yadav [Fri, 25 Jun 2021 19:17:06 +0000 (00:47 +0530)]
spi: spi-mem: add spi_mem_dtr_supports_op()

spi_mem_default_supports_op() rejects DTR ops by default to ensure that
the controller drivers that haven't been updated with DTR support
continue to reject them. It also makes sure that controllers that don't
support DTR mode at all (which is most of them at the moment) also
reject them.

This means that controller drivers that want to support DTR mode can't
use spi_mem_default_supports_op(). Driver authors have to roll their own
supports_op() function and mimic the buswidth checks. Or even worse,
driver authors might skip it completely or get it wrong.

Add spi_mem_dtr_supports_op(). It provides a basic sanity check for DTR
ops and performs the buswidth requirement check. Move the logic for
checking buswidth in spi_mem_default_supports_op() to a separate
function so the logic is not repeated twice.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agospi: spi-mem: export spi_mem_default_supports_op()
Pratyush Yadav [Fri, 25 Jun 2021 19:17:05 +0000 (00:47 +0530)]
spi: spi-mem: export spi_mem_default_supports_op()

Controllers can use this function to perform basic sanity checking on
the spi-mem op.

Reviewed-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agospi: spi-mem: allow specifying a command's extension
Pratyush Yadav [Fri, 25 Jun 2021 19:17:04 +0000 (00:47 +0530)]
spi: spi-mem: allow specifying a command's extension

In xSPI mode, flashes expect 2-byte opcodes. The second byte is called
the "command extension". There can be 3 types of extensions in xSPI:
repeat, invert, and hex. When the extension type is "repeat", the same
opcode is sent twice. When it is "invert", the second byte is the
inverse of the opcode. When it is "hex" an additional opcode byte based
is sent with the command whose value can be anything.

So, make opcode a 16-bit value and add a 'nbytes', similar to how
multiple address widths are handled.

All usages of sizeof(op->cmd.opcode) also need to be changed to be
op->cmd.nbytes because that is the actual indicator of opcode size.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agospi: spi-mem: allow specifying whether an op is DTR or not
Pratyush Yadav [Fri, 25 Jun 2021 19:17:03 +0000 (00:47 +0530)]
spi: spi-mem: allow specifying whether an op is DTR or not

Each phase is given a separate 'dtr' field so mixed protocols like
4S-4D-4D can be supported.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agoMerge tag 'u-boot-imx-20210625' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
Tom Rini [Fri, 25 Jun 2021 17:33:47 +0000 (13:33 -0400)]
Merge tag 'u-boot-imx-20210625' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

Fixes for 2021.07
-----------------

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/7903

3 years agospi: Add MXIC controller driver
Zhengxun [Wed, 23 Jun 2021 17:15:15 +0000 (17:15 +0000)]
spi: Add MXIC controller driver

Add a driver for Macronix SPI controller IP.

This patch referred from linux spi-mxic.c. The difference from the
linux version is described here.

1. To adapt uboot spi framework, modify some functions naming.

2. Remove the incompatible functions of Uboot.

3. Add dummy byte recalculattion function to support dummy buswidth
   not align data buswidth operation.(ex: 1-1-4, 1-1-8)

4. Add Octal mode support.

Signed-off-by: Zhengxun <zhengxunli.mxic@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
[jagan: fixed file permission, comment line, kconfig]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agoMerge https://source.denx.de/u-boot/custodians/u-boot-sh
Tom Rini [Fri, 25 Jun 2021 01:18:22 +0000 (21:18 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-sh

- Beacon board fix, for this release.

3 years agoMerge https://source.denx.de/u-boot/custodians/u-boot-usb
Tom Rini [Fri, 25 Jun 2021 01:17:49 +0000 (21:17 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-usb

- A few easy MX7 EHCI USB fixes, for this release.

3 years agousb: ehci-mx6: Do not fail when 'reg' is not found
Fabio Estevam [Sun, 20 Jun 2021 15:00:52 +0000 (12:00 -0300)]
usb: ehci-mx6: Do not fail when 'reg' is not found

Unlike imx6, on imx7 the USB PHY is described as:

usbphynop1: usbphynop1 {
compatible = "usb-nop-xceiv";
clocks = <&clks IMX7D_USB_PHY1_CLK>;
clock-names = "main_clk";
#phy-cells = <0>;
};

which does not have the 'reg' property.

Do not return an error when the 'reg' property is not found
for the USB PHY.

This fixes USB gadget regression on a imx7s-warp board.

Successfully tested the "ums 0 mmc 0" command on two boards:
imx7s-warp and imx6dl-pico-pi.

Signed-off-by: Fabio Estevam <festevam@denx.de>
3 years agousb: ehci-mx6: Move fdtdec_get_alias_seq() inside the CONFIG_MX6
Fabio Estevam [Sun, 20 Jun 2021 15:00:51 +0000 (12:00 -0300)]
usb: ehci-mx6: Move fdtdec_get_alias_seq() inside the CONFIG_MX6

On a imx7s-warp board the fdtdec_get_alias_seq() function
always fails.

As priv->portnr is only used on i.MX6, move fdtdec_get_alias_seq()
inside the CONFIG_MX6 block.

Signed-off-by: Fabio Estevam <festevam@denx.de>
3 years agoARM: rmobile: beacon: Set CONFIG_RZ_G2 on Beacon boards
Adam Ford [Thu, 24 Jun 2021 17:52:11 +0000 (12:52 -0500)]
ARM: rmobile: beacon: Set CONFIG_RZ_G2 on Beacon boards

The board detection is incorrectly stating it's an rcar3 variant
instead of an RZ/G2 variant on all the r8a774*1_beacon boards.
Set the flag to correctly display as RZ/G2[M/N/H]

Signed-off-by: Adam Ford <aford173@gmail.com>
3 years agoARM: rmobile: Add basic PSCI support for R8A779A0 V3U Falcon
Hai Pham [Tue, 27 Oct 2020 12:06:51 +0000 (19:06 +0700)]
ARM: rmobile: Add basic PSCI support for R8A779A0 V3U Falcon

Enable basic PSCI support for R8A779A0 V3U Falcon

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
3 years agoARM: renesas: Add GICv3 initialization for V3U Falcon
Koji Matsuoka [Thu, 16 Jul 2020 03:11:16 +0000 (12:11 +0900)]
ARM: renesas: Add GICv3 initialization for V3U Falcon

Init GICv3 for V3U Falcon in early phase

Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
3 years agoARM: renesas: Add generic timer initialization for V3U Falcon
Koji Matsuoka [Tue, 21 Jul 2020 06:21:53 +0000 (15:21 +0900)]
ARM: renesas: Add generic timer initialization for V3U Falcon

Init the Generic Timer for V3U Falcon in early phase

Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
3 years agoARM: renesas: Add R8A779A0 V3U Falcon board code
Hai Pham [Thu, 21 May 2020 13:14:05 +0000 (20:14 +0700)]
ARM: renesas: Add R8A779A0 V3U Falcon board code

Add board code for the R8A779A0 V3U Falcon board.

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
--
Marek: - various small rebase fixes and clean ups

3 years agoARM: renesas: Add R8A779A0 V3U platform code
Hai Pham [Thu, 21 May 2020 07:11:13 +0000 (14:11 +0700)]
ARM: renesas: Add R8A779A0 V3U platform code

Add platform code to support R8A779A0 V3U SoC.

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
3 years agoARM: dts: renesas: Add RPC node to R8A779A0 V3U
Marek Vasut [Sun, 25 Apr 2021 21:00:21 +0000 (23:00 +0200)]
ARM: dts: renesas: Add RPC node to R8A779A0 V3U

The R-Car V3U does support RPC interface, however the support for it is
missing in upstream Linux DTs as of commit 9f4ad9e425a1 ("Linux 5.12"),
add the node into u-boot.dtsi to let U-Boot access the SPI NOR or HF.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
3 years agoARM: dts: renesas: Add R8A779A0 V3U DT extras
Hai Pham [Thu, 21 May 2020 10:37:33 +0000 (17:37 +0700)]
ARM: dts: renesas: Add R8A779A0 V3U DT extras

Add R8A779A0 V3U DT extras for U-Boot.

Based on "ARM: dts: renesas: Add R8A779A0 V3U DTs"
by Hai Pham <hai.pham.ud@renesas.com>

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
3 years agoARM: dts: renesas: Add R8A779A0 V3U Falcon DTs
Marek Vasut [Sun, 25 Apr 2021 20:28:00 +0000 (22:28 +0200)]
ARM: dts: renesas: Add R8A779A0 V3U Falcon DTs

Import R8A779A0 V3U Falcon DTs from Linux 5.12,
commit 9f4ad9e425a1 ("Linux 5.12") .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
3 years agoARM: dts: renesas: Add R8A779A0 V3U DTs and headers
Marek Vasut [Sun, 25 Apr 2021 20:28:00 +0000 (22:28 +0200)]
ARM: dts: renesas: Add R8A779A0 V3U DTs and headers

Import R8A779A0 V3U DTs and headers from Linux 5.12,
commit 9f4ad9e425a1 ("Linux 5.12") .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
3 years agopinctrl: renesas: Import R8A779A0 V3U PFC tables
Marek Vasut [Mon, 26 Apr 2021 23:55:54 +0000 (01:55 +0200)]
pinctrl: renesas: Import R8A779A0 V3U PFC tables

Import R8A779A0 V3U PFC tables from Linux 5.12, commit 9f4ad9e425a1
("Linux 5.12") . Add parts of PFC table integration from
pinctrl: renesas: Add R8A779A0 V3U PFC tables
by Hai Pham <hai.pham.ud@renesas.com>" .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
3 years agogpio: renesas: Handle R8A779A0 V3U INEN register
Marek Vasut [Tue, 27 Apr 2021 19:29:50 +0000 (21:29 +0200)]
gpio: renesas: Handle R8A779A0 V3U INEN register

The R8A779A0 V3U GPIO block has additional "General Input Enable" INEN
register. Add new R8A779A0 compatible string with a new quirk and also
a handler for this quirk which toggles the INEN register in the right
place. INEN register handling is based on "gpio: renesas: Add R8A779A0
V3U support" by Hai Pham <hai.pham.ud@renesas.com>

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
3 years agoclk: renesas: Add R8A779A0 clock tables
Hai Pham [Tue, 11 Aug 2020 03:46:34 +0000 (10:46 +0700)]
clk: renesas: Add R8A779A0 clock tables

Add clock tables for R8A779A0 V3U SoC from Linux 5.12,
commit 9f4ad9e425a1 ("Linux 5.12")

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
--
Marek: - Add .reset_modemr_offset
       - Sync tables from Linux 5.12
       - Rebase on latest u-boot

3 years agoclk: renesas: Handle R8A779A0 V3U clock types in Gen3 clock code
Marek Vasut [Tue, 27 Apr 2021 17:52:53 +0000 (19:52 +0200)]
clk: renesas: Handle R8A779A0 V3U clock types in Gen3 clock code

On R8A779A0 V3U SoC, PLL1 and PLL5 use a divider value
from cpg_pll_configs table while PLL{20,21,30,31,4} use
different control offset. Introduce new types to handle
this and handle those types in the Gen3 clock code.

Based on "clk: renesas: Add support for R8A779A0 V3U PLLn"
by Hai Pham <hai.pham.ud@renesas.com>

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
3 years agoMerge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-spi into...
Tom Rini [Thu, 24 Jun 2021 15:11:13 +0000 (11:11 -0400)]
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-spi into next

- SPI NOT OF partitions (Marek Behún)
- Macronic SPI NAND (Jaime Liao)
- Macronix MX66UW2G345G SPI NOR (zhengxun)

3 years agocmd: mtd: expand <name> argument definition in command help
Marek Behún [Wed, 26 May 2021 12:08:26 +0000 (14:08 +0200)]
cmd: mtd: expand <name> argument definition in command help

The <name> argument can now also be MTD's DM device name or OF path.
Mention this is command help.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
3 years agomtd: compare also with OF path and device name in get_mtd_device_nm()
Marek Behún [Wed, 26 May 2021 12:08:25 +0000 (14:08 +0200)]
mtd: compare also with OF path and device name in get_mtd_device_nm()

The get_mtd_device_nm() function (code imported from Linux) simply
iterates all registered MTD devices and compares the given name with
all MTDs' names.

With SPI_FLASH_MTD enabled U-Boot registers a SPI-NOR as a MTD device
with name identical to the SPI flash chip name (from SPI ID table). Thus
for a board with multiple same SPI-NORs it registers multiple MTDs, but
all with the same name (such as "s25fl164k"). We do not want to change
this behaviour, since such a change could break existing boot scripts,
which can rely on a hardcoded name.

In order to allow somehow to uniqely select a MTD device, change
get_mtd_device_nm() function as such:
- if first character of name is '/', try interpreting it as OF path
- otherwise compare the name with MTDs name and MTDs device name.

In the following example a board has two "s25fl164k" SPI-NORs. They both
have name "s25fl164k", thus cannot be uniquely selected via this name.
With this change, the user can select the second SPI-NOR either with
"spi-nor@1" or "/soc/spi@10600/spi-nor@1".

Example:
  => mtd list
  List of MTD devices:
  * s25fl164k
    - device: spi-nor@0
    - parent: spi@10600
    - driver: jedec_spi_nor
    - path: /soc/spi@10600/spi-nor@0
    - type: NOR flash
    - block size: 0x1000 bytes
    - min I/O: 0x1 bytes
    - 0x000000000000-0x000000800000 : "s25fl164k"
  * s25fl164k
    - device: spi-nor@1
    - parent: spi@10600
    - driver: jedec_spi_nor
    - path: /soc/spi@10600/spi-nor@1
    - type: NOR flash
    - block size: 0x1000 bytes
    - min I/O: 0x1 bytes
    - 0x000000000000-0x000000800000 : "s25fl164k"

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
3 years agocmd: mtd: print device OF path in listing
Marek Behún [Wed, 26 May 2021 12:08:24 +0000 (14:08 +0200)]
cmd: mtd: print device OF path in listing

Print MTD's device OF path in the output of `mtd list` command.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
3 years agomtd: probe SPI NOR devices in mtd_probe_devices()
Marek Behún [Wed, 26 May 2021 12:08:23 +0000 (14:08 +0200)]
mtd: probe SPI NOR devices in mtd_probe_devices()

In order for `mtd list` U-Boot command to list SPI NOR devices without
the need to run `sf probe` before, we have to probe SPI NOR devices in
mtd_probe_devices().

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
3 years agomtd: remove mtd_probe() function
Marek Behún [Wed, 26 May 2021 12:08:22 +0000 (14:08 +0200)]
mtd: remove mtd_probe() function

The device_probe() function does the same thing as mtd_probe() and
mtd_probe() is only used in mtd_probe_uclass_mtd_devs(), where the
probing can be made simpler by using uclass_foreach_dev_probe macro.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
3 years agomtd: spi-nor: fill-in mtd->dev member
Marek Behún [Wed, 26 May 2021 12:08:21 +0000 (14:08 +0200)]
mtd: spi-nor: fill-in mtd->dev member

Fill in mtd->dev member with nor->dev.

This can be used by MTD OF partition parser.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
3 years agomtd: spi-nor: allow registering multiple MTDs when DM is enabled
Marek Behún [Wed, 26 May 2021 12:08:20 +0000 (14:08 +0200)]
mtd: spi-nor: allow registering multiple MTDs when DM is enabled

Currently when the SPI_FLASH_MTD config option is enabled, only one SPI
can be registered as MTD at any time - it is the last one probed (since
with old non-DM model only one SPI NOR could be probed at any time).

When DM is enabled, allow for registering multiple SPI NORs as MTDs by
utilizing the nor->mtd structure, which is filled in by spi_nor_scan
anyway, instead of filling a separate struct mtd_info.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
3 years agomtd: add support for parsing partitions defined in OF
Marek Behún [Wed, 26 May 2021 12:08:19 +0000 (14:08 +0200)]
mtd: add support for parsing partitions defined in OF

Add support for parsing partitions defined in device-trees via the
`partitions` node with `fixed-partitions` compatible.

The `mtdparts`/`mtdids` mechanism takes precedence. If some partitions
are defined for a MTD device via this mechanism, the code won't register
partitions for that MTD device from OF, even if they are defined.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
3 years agodm: core: add ofnode_get_path()
Marek Behún [Wed, 26 May 2021 12:08:18 +0000 (14:08 +0200)]
dm: core: add ofnode_get_path()

Add function for retrieving full node path of a given ofnode.
This uses np->full_name if OF is live, otherwise a call to
fdt_get_path() is made.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agodm: core: add non-translating version of ofnode_get_addr_size_index()
Marek Behún [Wed, 26 May 2021 12:08:17 +0000 (14:08 +0200)]
dm: core: add non-translating version of ofnode_get_addr_size_index()

Add functions ofnode_get_addr_size_index_notrans(), which is a
non-translating version of ofnode_get_addr_size_index().

Some addresses are not meant to be translated, for example those of MTD
fixed-partitions.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agomtd: spinand: macronix: Add support for serial NAND flash
Jaime Liao [Mon, 7 Jun 2021 08:19:15 +0000 (16:19 +0800)]
mtd: spinand: macronix: Add support for serial NAND flash

Macronix NAND Flash devices are available in different configurations
and densities.

MX"35" means SPI NAND
MX35"UF" , UF meands 1.8V
MX35LF"2G" , 2G means 2Gbits
MX35LF2G"E4" , E4 means internal ECC and Quad I/O(x4)

MX35UF4GE4AD/MX35UF2GE4AD/MX35UF1GE4AD are 1.8V 4G/2Gbit serial
NAND flash device with 8-bit on-die ECC
https://www.mxic.com.tw/Lists/Datasheet/Attachments/7983/MX35UF4GE4AD,%201.8V,%204Gb,%20v0.00.pdf

MX35UF2GE4AC/MX35UF1GE4AC are 1.8V 2G/1Gbit serial
NAND flash device with 8-bit on-die ECC
https://www.mxic.com.tw/Lists/Datasheet/Attachments/7974/MX35UF2GE4AC,%201.8V,%202Gb,%20v1.0.pdf

Validated via normal(default) and QUAD mode by read, erase, read back,
on Xilinx Zynq PicoZed FPGA board which included Macronix
SPI Host(drivers/spi/spi-mxic.c).

Signed-off-by: Jaime Liao <jaimeliao@mxic.com.tw>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agoMerge https://source.denx.de/u-boot/custodians/u-boot-x86
Tom Rini [Wed, 23 Jun 2021 12:46:26 +0000 (08:46 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-x86

- x86: Discard .note.gnu.property sections
- nvme: Skip block device creation for inactive namespaces
- nvme: Convert NVMe doc to reST, and various minor fixes

3 years agoMerge tag 'mmc-2021-6-22' of https://source.denx.de/u-boot/custodians/u-boot-mmc
Tom Rini [Wed, 23 Jun 2021 12:45:29 +0000 (08:45 -0400)]
Merge tag 'mmc-2021-6-22' of https://source.denx.de/u-boot/custodians/u-boot-mmc

- Revert fsl_esdhc_imx using VENDORSPEC_FRC_SDCLK_ON
- Fix data read for dw_mmc
- Increase minimum bus freq for mtk-sd
- Minor cleanup

3 years agoMerge branch '2021-06-22-assorted-fixes'
Tom Rini [Wed, 23 Jun 2021 12:45:09 +0000 (08:45 -0400)]
Merge branch '2021-06-22-assorted-fixes'

- Assorted minor bugfixes

3 years agotest: Include /sbin to the PATH when creating file system
Andy Shevchenko [Thu, 10 Jun 2021 15:08:42 +0000 (18:08 +0300)]
test: Include /sbin to the PATH when creating file system

On some distributions the mkfs is under /sbin and /sbin is not set
for mere users. Include /sbin to the PATH when creating file system,
so that users won't get a scary traceback from Python.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
3 years agoMAINTAINER, git-mailrc: Update the mmc maintainer
Jaehoon Chung [Mon, 14 Jun 2021 22:16:36 +0000 (07:16 +0900)]
MAINTAINER, git-mailrc: Update the mmc maintainer

Update to me as co-maintainer with Peng.
Additionally, update the mmc alias in git-mailrc.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
3 years agoglobal_data: Ensure we have <config.h> when symbols are not in Kconfig yet
Tom Rini [Thu, 3 Jun 2021 13:39:02 +0000 (09:39 -0400)]
global_data: Ensure we have <config.h> when symbols are not in Kconfig yet

All symbols that are defined in Kconfig will always be defined (or not)
prior to preprocessing due to the -include directive while building.
However, symbols which are not yet migrated will only be defined (or
not) once the board config.h is included, via <config.h>.  While the end
goal must be to migrate all symbols, today we have cases where the size
of gd will get mismatched within the build, based on include order.
Mitigate this by making sure that any <asm/global_data.h> that uses
symbols not in Kconfig does start with <config.h>.  Remove this when not
needed.

Cc: Alexey Brodkin <alexey.brodkin@synopsys.com>
Cc: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Cc: Huan Wang <alison.wang@nxp.com>
Cc: Angelo Dureghello <angelo@sysam.it>
Cc: Rick Chen <rick@andestech.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agosocfpga64: Do not define CONFIG_SYS_MEM_RESERVE_SECURE to 0
Tom Rini [Thu, 3 Jun 2021 13:39:01 +0000 (09:39 -0400)]
socfpga64: Do not define CONFIG_SYS_MEM_RESERVE_SECURE to 0

Based on the comment in socfpga_soc64_common.h, the intention is for
CONFIG_SYS_MEM_RESERVE_SECURE to be unused.  However, in the code we do:
...

and that will evaluate to true.  This leads to unwanted code being
compiled.  Further, as CONFIG_SYS_MEM_RESERVE_SECURE has not been
migrated to Kconfig, this leads to a mismatch in the size of gd
depending on if we have or have not also had <configs/BOARD.h> also
included yet.

Remove the define as it's not needed.

Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Chee Hong Ang <chee.hong.ang@intel.com>
Cc: Dalon Westergreen <dalon.westergreen@intel.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agoRevert "powerpc: fix regression in arch_initr_trap()"
Tom Rini [Thu, 3 Jun 2021 13:39:00 +0000 (09:39 -0400)]
Revert "powerpc: fix regression in arch_initr_trap()"

With the changes in commit 588efcdd72fc ("powerpc: Don't use relative
include for config.h in global_data.h") fixing the root of the problem,
we no longer need this re-inclusion.

This reverts commit f6c0d365d3e8ee8e4fd3ebe2ed957c2bca9d3328.

Cc: Matt Merhar <mattmerhar@protonmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agopowerpc: Don't use relative include for config.h in global_data.h
Tom Rini [Thu, 3 Jun 2021 13:38:59 +0000 (09:38 -0400)]
powerpc: Don't use relative include for config.h in global_data.h

As there is an arch/powerpc/include/asm/config.h file using "" to get
config.h here can lead to using that rather than include/config.h.  This
in turn can lead to a mismatch in the size of gd.

Cc: Matt Merhar <mattmerhar@protonmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tested-by: Matt Merhar <mattmerhar@protonmail.com>
3 years agomalloc: add SPDX license identifiers
Heinrich Schuchardt [Sat, 29 May 2021 11:18:00 +0000 (13:18 +0200)]
malloc: add SPDX license identifiers

The original code is in the public domain. Licenses/README states that the
general license for U-Boot is GPL 2.0+. So we can mark the malloc code as
GPL 2.0+ too.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
3 years agoMAINTAINERS: Add an entry for NVMe
Bin Meng [Tue, 22 Jun 2021 13:16:23 +0000 (21:16 +0800)]
MAINTAINERS: Add an entry for NVMe

This was missed when NVMe support was initially brought to U-Boot
back in 2017. Add an entry for it and list myself as the maintainer.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
3 years agodoc: develop: Convert README.nvme to reST
Bin Meng [Tue, 22 Jun 2021 13:16:22 +0000 (21:16 +0800)]
doc: develop: Convert README.nvme to reST

This converts the existing README.nvme to reST, and puts it under
the develop/driver-model/ directory.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
3 years agonvme: Don't clear nvme blk device's priv space
Bin Meng [Tue, 22 Jun 2021 13:16:21 +0000 (21:16 +0800)]
nvme: Don't clear nvme blk device's priv space

A udevice's priv space is cleared in alloc_priv() in the DM core.
Don't do it again in its probe() routine.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
3 years agonvme: Drop useless members of 'struct nvme_ns'
Bin Meng [Tue, 22 Jun 2021 13:16:20 +0000 (21:16 +0800)]
nvme: Drop useless members of 'struct nvme_ns'

mode_select_num_blocks and mode_select_block_len in 'struct nvme_ns'
are not useful. Drop them.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
3 years agonvme: Eliminate the offset of one during block dev creation
Bin Meng [Tue, 22 Jun 2021 13:16:19 +0000 (21:16 +0800)]
nvme: Eliminate the offset of one during block dev creation

At present there is an offset of one added during the creation of
block device. This can be very confusing as we wanted to encode the
namespace id in the block device name but namespae id cannot be zero.

This changes to use the namespace id directly in the block device
name, eliminating the offset of one effectively.

Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>