Bas Nieuwenhuizen [Sun, 2 Jul 2017 00:48:41 +0000 (02:48 +0200)]
ac/nir: Make shader key a struct.
Some bits can be passed to almost every shader, and I don't like
adding 5 variables.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Thu, 17 Aug 2017 22:32:41 +0000 (00:32 +0200)]
radv: Use 0 for the layer id if the vertex shader does not export it.
To use when we have e.g. input attachments, but there is no layer
export in the previous shader and hence no layered rendering.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Thu, 17 Aug 2017 22:29:20 +0000 (00:29 +0200)]
ac/nir: Implement input attachments with layered rendering.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Wed, 16 Aug 2017 19:57:29 +0000 (21:57 +0200)]
ac/nir: Determine if input attachments are used in the info pass.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Wed, 23 Aug 2017 20:28:06 +0000 (22:28 +0200)]
ac/nir: Cast sources of integer ops to int.
The int32->float semantic conversion got dropped in a testcase,
because the src was already float. On closer inspection I decided
to add a few more casts for integer op operands to be safe too.
Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Adam Jackson [Thu, 24 Aug 2017 17:15:15 +0000 (13:15 -0400)]
Revert "include: Sync Khronos headers for OpenGL 4.6"
Broke the BUILDING_MESA bit, oops.
This reverts commit
ef1e87e6cdbd80e74a8bc6d48b0b174a0812fe69.
Adam Jackson [Tue, 8 Aug 2017 15:52:42 +0000 (11:52 -0400)]
include: Sync Khronos headers for OpenGL 4.6
Taken from
c21e602b9fda1d3bbaecb08194592f67e6a0649b from
OpenGL-Registry.
Signed-off-by: Adam Jackson <ajax@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Eric Engestrom [Thu, 17 Aug 2017 09:09:21 +0000 (10:09 +0100)]
dri: fix typo
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Eric Engestrom [Fri, 18 Aug 2017 10:25:13 +0000 (11:25 +0100)]
i965: add missing `const` in function signature
Gets rid of a few warnings of the form:
src/mesa/drivers/dri/i965/intel_screen.c:918:49: warning: passing argument 2 of ‘modifier_is_supported’ discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers]
!modifier_is_supported(&screen->devinfo, f, 0, modifier))
^
src/mesa/drivers/dri/i965/intel_screen.c:301:1: note: expected ‘struct intel_image_format *’ but argument is of type ‘const struct intel_image_format *’
Fixes:
1efd73df39b39589d26f "i965: Advertise the CCS modifier"
Cc: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Eric Engestrom [Thu, 24 Aug 2017 14:14:16 +0000 (15:14 +0100)]
egl/android: add missing include
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Brian Paul [Sat, 19 Aug 2017 03:03:16 +0000 (21:03 -0600)]
vbo: fix glVertexAttrib(index=0)
Depending on which extension or GL spec you read the behavior of
glVertexAttrib(index=0) either sets the current value for generic
attribute 0, or it emits a vertex just like glVertex(). I believe
it should do either, depending on context (see below).
The piglit gl-2.0-vertex-const-attr test declares two vertex attributes:
attribute vec2 vertex;
attribute vec4 attr;
and the GLSL linker assigns "vertex" to location 0 and "attr" to location 1.
The test passes.
But if the declarations were reversed such that "attr" was location 0 and
"vertex" was location 1, the test would fail to draw properly.
The problem is the call to glVertexAttrib(index=0) to set attr's value
was interpreted as glVertex() and did not set generic attribute[0]'s value.
Interesting, calling glVertex() outside glBegin/End (which is effectively
what the piglit test does) does not generate a GL error.
I believe the behavior of glVertexAttrib(index=0) should depend on
whether it's called inside or outside of glBegin/glEnd(). If inside
glBegin/End(), it should act like glVertex(). Else, it should behave
like glVertexAttrib(index > 0). This seems to be what NVIDIA does.
This patch makes two changes:
1. Check if we're inside glBegin/End for glVertexAttrib()
2. Fix the vertex array binding for recalculate_input_bindings(). As it was,
we were using &vbo->currval[VBO_ATTRIB_POS], but that's interpreted
as a zero-stride attribute and doesn't make sense for array drawing.
No Piglit regressions. Fixes updated gl-2.0-vertex-const-attr test and
passes new gl-2.0-vertex-attrib-0 test.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101941
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Thu, 24 Aug 2017 13:35:49 +0000 (07:35 -0600)]
gallivm: remove unused variable
Trivial.
Brian Paul [Tue, 22 Aug 2017 03:44:22 +0000 (21:44 -0600)]
st/mesa: add const qualifiers in st_extensions.c
Trivial.
Brian Paul [Tue, 22 Aug 2017 17:42:38 +0000 (11:42 -0600)]
st/mesa: whitespace/indentation fixes in st_init_extensions()
Brian Paul [Tue, 22 Aug 2017 17:10:20 +0000 (11:10 -0600)]
pipe-loader: use MAYBE_UNUSED to silence warning
Trivial.
Ilia Mirkin [Thu, 24 Aug 2017 03:15:48 +0000 (23:15 -0400)]
nv50/ir: properly set sType for TXF ops to U32
All of the coordinates and LOD args are integers for TXF. This mostly
doesn't matter, except for converting into a levelZero=true operation by
removing an explicit zero LOD. For the comparison against zero to work
properly, the sType of the instruction has to be set correctly.
Fixes: KHR-GL45.robust_buffer_access_behavior.texel_fetch
Reported-by: Karol Herbst <karolherbst@gmail.com>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
Samuel Pitoiset [Wed, 23 Aug 2017 14:43:33 +0000 (16:43 +0200)]
mesa: remove duplicate assignments in bind_xfb_buffers()
Useless to do that before checking errors. It's now similar to
the other bind_XXX_buffers() helpers.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Samuel Pitoiset [Wed, 23 Aug 2017 14:43:32 +0000 (16:43 +0200)]
mesa: fix debug/error messages in glColorMaski()
Trivial. While we are at it, adjust indentation.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Timothy Arceri [Sun, 13 Aug 2017 23:23:41 +0000 (09:23 +1000)]
glsl: stop adding pointers from bindless structs to the cache
This is so we always create reproducible cache entries. Consistency
is required for verification of any third party distributed shaders.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Timothy Arceri [Fri, 11 Aug 2017 05:13:38 +0000 (15:13 +1000)]
glsl: stop adding pointers from shader_info to the cache
This is so we always create reproducible cache entries. Consistency
is required for verification of any third party distributed shaders.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Timothy Arceri [Tue, 22 Aug 2017 23:10:27 +0000 (09:10 +1000)]
compiler: move pointers to the start of shader_info
This will allow us to easily skip them when writting the struct
to disk cache.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Timothy Arceri [Fri, 11 Aug 2017 04:59:02 +0000 (14:59 +1000)]
glsl: always write a name/label string to the cache
In the following patch we will stop writing the pointer to cache.
Unfortunately adding empty strings to that cache seems to be the
only thing we can do here once we no longer have the pointers.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Timothy Arceri [Fri, 11 Aug 2017 04:22:07 +0000 (14:22 +1000)]
glsl: don't write uniform storage offset if there isn't one
This is so we always create reproducible cache entries. Consistency
is required for verification of any third party distributed shaders.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Timothy Arceri [Fri, 11 Aug 2017 04:17:24 +0000 (14:17 +1000)]
glsl: add has_uniform_storage() helper to shader cache
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Timothy Arceri [Fri, 11 Aug 2017 04:01:34 +0000 (14:01 +1000)]
glsl: stop adding pointers from glsl_struct_field to the cache
This is so we always create reproducible cache entries. Consistency
is required for verification of any third party distributed shaders.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Timothy Arceri [Fri, 11 Aug 2017 03:55:13 +0000 (13:55 +1000)]
glsl: stop adding pointers from gl_shader_variable to the cache
This is so we always create reproducible cache entries. Consistency
is required for verification of any third party distributed shaders.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Timothy Arceri [Fri, 11 Aug 2017 03:53:18 +0000 (13:53 +1000)]
glsl: allow NULL to be passed to encode_type_to_blob()
This will be used by the following commit.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Dave Airlie [Mon, 21 Aug 2017 04:11:04 +0000 (14:11 +1000)]
radv/gfx9: don't expose linear depth on vega.
This just zeros out the linear flags for gfx9 + depth formats.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 21 Aug 2017 04:10:21 +0000 (14:10 +1000)]
radv: don't degrade tiling mode for small compressed or depth texture.
This is what radeonsi does, so we should do the same, also vega
doesn't support linear depth textures anyways.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 21 Aug 2017 04:04:02 +0000 (14:04 +1000)]
radv/gfx9: only minify image view width/height/depth before gfx9.
For gfx9 the addressing for images has changed, so we need to
provide the hw with the level0, however we still need to scale
for format block differences (so our compressed upload paths still
work).
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 21 Aug 2017 03:58:27 +0000 (13:58 +1000)]
radv/image: don't rescale width/height if the format isn't changing
If the image view has the same format, we don't need to rescale
the w/h.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 21 Aug 2017 03:56:33 +0000 (13:56 +1000)]
radv: cleanup some image view descriptor setup.
Avoid passing the vulkan image creation into the image view descriptor
setup. This cleans up the usage of range inside the init, instead
using the properly inited values in the image view.
This is just a cleanup but some future vega changes will depend on it.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 21 Aug 2017 06:17:27 +0000 (07:17 +0100)]
radv/gfx9: emit sx_mrt_blend registers
GFX9 needs the SX MRT blend registers programmed, port over
the code from radeonsi to workout the values from the blend
state, and program the registers on rbplus systems.
This fixes lots of:
dEQP-VK.pipeline.blend.*
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 21 Aug 2017 06:28:14 +0000 (07:28 +0100)]
radv: bump space check for indexed draw.
For the GFX9 packet we need one more dword.
Fixes an assert in:
dEQP-VK.draw.shader_draw_parameters.base_vertex.draw_indexed
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 21 Aug 2017 05:00:49 +0000 (06:00 +0100)]
radv/gfx9: fixup db/stencil disable.
This fixes disabled Z/stencil.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 21 Aug 2017 07:28:27 +0000 (08:28 +0100)]
radv/gfx9: fix level count in color register setup.
There was an off by one here.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 21 Aug 2017 07:27:25 +0000 (08:27 +0100)]
radv/gfx9: use total levels in texture descriptor
We need to use all the levels when filling out the gfx9
descriptor.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Tue, 15 Aug 2017 16:09:21 +0000 (18:09 +0200)]
radv: Implement bc optimize.
Seems like we actually enabled it already, but did not implement
the shader part. With this patch we do.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Tue, 15 Aug 2017 14:31:20 +0000 (16:31 +0200)]
ac/nir: refactor input variable iteration.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Kenneth Graunke [Thu, 17 Aug 2017 19:09:41 +0000 (12:09 -0700)]
i965: Stop using wm_prog_data->binding_table.render_target_start.
Render target surfaces always start at binding table index 0.
This is required for us to use headerless FB writes, which we
really want to do. So, we'll never change that.
Given that, it's not necessary to look up a wm_prog_data field
which we already know contains 0. We can drop the dependency in
brw_renderbuffer_surfaces (Gen4-5)...which was already confusingly
missing from gen6_renderbuffer_surfaces.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Kenneth Graunke [Wed, 16 Aug 2017 23:47:07 +0000 (16:47 -0700)]
i965: Add a brw_wm_prog_data::has_render_target_reads field.
State upload code should use prog_data rather than poking at shader_info
directly.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Kenneth Graunke [Thu, 17 Aug 2017 08:28:56 +0000 (01:28 -0700)]
i965: Inline brw_update_renderbuffer_surfaces().
Less baklava layers.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Kenneth Graunke [Thu, 17 Aug 2017 08:17:02 +0000 (01:17 -0700)]
i965: Pass fb into emit_null_surface instead of dimensions.
We either want the framebuffer dimensions or 1x1x1. Passing fb and
falling back to 1x1x1 lets us shorten some calls.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Kenneth Graunke [Thu, 17 Aug 2017 08:05:31 +0000 (01:05 -0700)]
i965: Devirtualize update_renderbuffer_surface.
Replace piles of my own boilerplate with 1-2 lines of code.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Kenneth Graunke [Thu, 17 Aug 2017 07:58:43 +0000 (00:58 -0700)]
i965: Delete update_renderbuffer_surface flags.
We don't need yet another set of flags. The function already has access
to both brw and the unit, so it can check brw->draw_aux_buffer_disabled
itself in one line of code. The layered flag was only used to assert
that Gen4-5 doesn't do layered rendering, which isn't that useful.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Kenneth Graunke [Thu, 17 Aug 2017 07:57:33 +0000 (00:57 -0700)]
i965: Make brw_update_renderbuffer_surface static.
Also rename it to gen6_update_renderbuffer_surface, as this is the
function for Gen6+. Having functions named "brw_*" and "gen4_*"
is confusing...if we're using gens, let's stick with those.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Kenneth Graunke [Wed, 16 Aug 2017 20:18:26 +0000 (13:18 -0700)]
i965: Drop BRW_NEW_BLORP from SURFACE_STATE setup code.
BLORP invalidates the binding tables, but it doesn't destroy any of the
existing SURFACE_STATE entries in the statebuffer. We can reuse those.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Wed, 16 Aug 2017 23:04:22 +0000 (16:04 -0700)]
i965: Make a BRW_NEW_FAST_CLEAR_COLOR dirty bit.
When changing fast clear colors, we need to emit new SURFACE_STATE
with the updated color at the next draw call.
Most things work today because the atoms that handle SURFACE_STATE
for images (mutable images, textures, render targets) also listen to
BRW_NEW_BLORP, causing us to re-emit these on every BLORP operation.
However, this is overkill - most BLORP operations don't require us
to re-emit SURFACE_STATE.
One case where this is broken today is a fast clear to a different
color followed by a non-coherent framebuffer fetch. The renderbuffer
read atom doesn't listen to BRW_NEW_BLORP, and would not get the new
fast clear color.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Tue, 22 Aug 2017 21:56:36 +0000 (14:56 -0700)]
i965: Drop Gen7+ nonsense from brw_ff_gs.c.
brw_ff_gs.c is about using the geometry shader to implement things
that the fixed function ought to do, but doesn't on old hardware.
Gen7+ does not need this. We should drop the misleading comment
about Gen7 not using geometry shaders.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Kenneth Graunke [Tue, 22 Aug 2017 21:23:17 +0000 (14:23 -0700)]
i965: Only set key->flat_shade if COL0/COL1 are written.
This may reduce some recompiles.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Kenneth Graunke [Fri, 18 Aug 2017 06:48:07 +0000 (23:48 -0700)]
i965: Clean up brwNewProgram().
All shader stages do the exact same thing, so we don't need the switch
statement, or the redundant FS case. I believe these used to be
different before Tim eliminated the (e.g.) brw_vertex_program
subclasses.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Leo Liu [Wed, 23 Aug 2017 17:18:21 +0000 (13:18 -0400)]
st/va: exclude the buffer reallocation for encode case
Since encoder only support de-interlaced buffers.
v2: move to parameter call to tell dec/enc
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Tim Rowley [Tue, 22 Aug 2017 15:39:57 +0000 (10:39 -0500)]
swr: limit pipe_draw_info->restart_index usage
Only copy this value when in restart drawing mode.
Eliminates valgrind errors when running trivial programs.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Samuel Pitoiset [Wed, 23 Aug 2017 15:10:56 +0000 (17:10 +0200)]
radeonsi: fix wrong assertion in si_init_bindless_descriptors()
Bad mistake, sorry.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Leo Liu [Wed, 23 Aug 2017 13:53:10 +0000 (09:53 -0400)]
radeon/video: Return false explicitly for HEVC if not the case
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Gwan-gyeong Mun [Tue, 22 Aug 2017 15:57:18 +0000 (00:57 +0900)]
gallium/docs: Fix the math formula of U2I64
before:
dst.xy = (uint64_t) src0.x
dst.zw = (uint64_t) src0.y
after:
dst.xy = (int64_t) src0.x
dst.zw = (int64_t) src0.y
Signed-off-by: Mun Gwan-gyeong <elongbug@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Gwan-gyeong Mun [Tue, 22 Aug 2017 15:29:44 +0000 (00:29 +0900)]
gallium/docs: Add missing word "Not"
Signed-off-by: Mun Gwan-gyeong <elongbug@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Nicolai Hähnle [Tue, 1 Aug 2017 21:09:48 +0000 (23:09 +0200)]
tgsi: store opcode mnemonics in a separate table
They are only used for debug info.
Together with making tgsi_opcode_info::opcode a bitfield, this reduces
the size of tgsi_opcode_info on 64-bit systems from 24 bytes to 4 bytes,
and makes the whole data structure a bit more linker friendly.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 2 Aug 2017 10:05:34 +0000 (12:05 +0200)]
gallium: use tgsi_get_opcode_name instead of tgsi_opcode_info::mnemonic
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 1 Aug 2017 21:05:10 +0000 (23:05 +0200)]
tgsi: macro-ify the opcodes table
So we can easily re-arrange members of tgsi_opcode_info, and readers of
the code don't have to guess what all the 0s mean.
Mostly done with regex search&replace.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 1 Aug 2017 20:58:18 +0000 (22:58 +0200)]
tgsi: remove post_indent from some 64-bit opcodes
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 1 Aug 2017 20:48:08 +0000 (22:48 +0200)]
tgsi: reduce tgsi_opcode_info::pre_dedent and post_indent to 1 bit
It's not clear why they were ever 2 bits to begin with. Perhaps
the original intent was to use signed values, but that doesn't
seem to have ever been the case in master.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 18 Aug 2017 18:28:02 +0000 (20:28 +0200)]
gallium/radeon: fix saving multi-part command streams
Use the correct type to fix pointer arithmetic.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 18 Aug 2017 18:17:29 +0000 (20:17 +0200)]
ac/debug: invoke valgrind checks while parsing IBs
Help catch garbage data written into IBs.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 22 Aug 2017 15:33:54 +0000 (17:33 +0200)]
ac/debug: annotate IB dumps with the raw values
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 18 Aug 2017 16:06:20 +0000 (18:06 +0200)]
ac/debug: use an explicit getter for fetching words from the IB
Guard against out-of-bounds accesses, and prepare for upcoming changes.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Thu, 17 Aug 2017 19:36:40 +0000 (21:36 +0200)]
radeonsi: update comment describing indices into sctx->descriptors
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 18 Aug 2017 17:29:49 +0000 (19:29 +0200)]
util: fix valgrind errors when dumping pipe_draw_info
Various index-related fields are only initialized when required, so
they should only be dumped in those cases.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Samuel Pitoiset [Wed, 23 Aug 2017 07:42:58 +0000 (09:42 +0200)]
radeonsi: do not assert when reserving bindless slot 0
When assertions were disabled, the compiler removed
the call to util_idalloc_alloc() and the first allocated
bindless slot was 0 which is invalid per the spec.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Samuel Pitoiset [Wed, 23 Aug 2017 08:59:07 +0000 (10:59 +0200)]
radeonsi: rename some bindless-related helper functions
I think it makes more sense.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Samuel Pitoiset [Wed, 23 Aug 2017 08:59:06 +0000 (10:59 +0200)]
radeonsi: minor cleanups in si_make_{texture,image}_handle_resident()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Rob Herring [Mon, 21 Aug 2017 19:27:42 +0000 (14:27 -0500)]
Android: gallium_dri: pass dri.sym to linker
Pass the dri.sym version script to the linker. This ensures only
explicitly exported symbols are exported and shrinks the library by up
to 60KB.
HAVE_DLADDR also needs to be set so that __driDriverExtensions is defined.
We need to pass "--undefined-version" because the Android build system
sets --no-undefined-version by default and we get an error on
driver specific symbols if those drivers are disabled without the option.
Suggested-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Leo Liu [Mon, 21 Aug 2017 18:03:40 +0000 (14:03 -0400)]
st/va: enable P016 format i.e. reallocate buffer if format changed
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Mon, 21 Aug 2017 15:51:35 +0000 (11:51 -0400)]
radeon/vcn: enable P016 mode support
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Mon, 21 Aug 2017 15:50:38 +0000 (11:50 -0400)]
radeon/vcn: correct target buffer pitch calculation
since the way should be as same as UVD
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Francisco Jerez [Fri, 18 Aug 2017 19:04:55 +0000 (12:04 -0700)]
anv: Check that in_fence fd is valid before closing it.
Probably harmless, but will overwrite errno with a failure status
code. Reported by coverity.
CID 1416600: Argument cannot be negative (NEGATIVE_RETURNS)
Fixes:
5c4e4932e02 (anv: Implement support for exporting semaphores as FENCE_FD)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Francisco Jerez [Fri, 18 Aug 2017 18:00:42 +0000 (11:00 -0700)]
anv: Add error handling to setup_empty_execbuf().
The anv_execbuf_add_bo() call can actually fail in practice, which
should cause the QueueSubmit operation to fail. Reported by Coverity.
CID: 1416606: Unchecked return value (CHECKED_RETURN)
Fixes:
017cdb10cf (anv: Submit a dummy batch when only semaphores are provided.)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Marek Olšák [Tue, 22 Aug 2017 14:58:40 +0000 (16:58 +0200)]
tgsi/scan: fix uses_double
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 19 Aug 2017 18:25:08 +0000 (20:25 +0200)]
gallium: remove TGSI opcode SCS
use COS+SIN instead.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Acked-by: Jose Fonseca <jfonseca@vmware.com>
Marek Olšák [Thu, 17 Aug 2017 13:36:20 +0000 (15:36 +0200)]
gallium/u_blitter: don't use boolean, TRUE, FALSE
v2: cherry-picked from the bigger patch series
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)
Tested-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Thu, 17 Aug 2017 11:42:06 +0000 (13:42 +0200)]
gallium/u_simple_shaders: do util_make_layered_clear_vertex_shader differently
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Thu, 17 Aug 2017 01:35:13 +0000 (03:35 +0200)]
gallium/u_blitter: remove get_next_surface_layer callback
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Brian Paul <brianp@vmware.com>
Samuel Pitoiset [Tue, 22 Aug 2017 10:34:48 +0000 (12:34 +0200)]
st/glsl_to_tgsi: fix getting the image type for array of structs (again)
We want the type of the field, not of the struct.
This fixes a regression in the following piglit test:
arb_bindless_texture/compiler/images/arrays-of-struct.frag
Fixes:
49d9286a3f ("glsl: stop copying struct and interface member names")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Sun, 20 Aug 2017 10:41:13 +0000 (12:41 +0200)]
gallium: remove TGSI opcode BREAKC
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 19 Aug 2017 20:23:08 +0000 (22:23 +0200)]
gallium: remove TGSI opcode XPD
use MUL+MAD+MOV instead.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Marek Olšák [Sat, 19 Aug 2017 20:00:02 +0000 (22:00 +0200)]
gallium: remove TGSI opcode DPH
use DP4 or DP3 + ADD.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Marek Olšák [Sat, 19 Aug 2017 19:41:57 +0000 (21:41 +0200)]
gallium: remove TGSI opcode DP2A
use DP3 instead.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Marek Olšák [Sat, 19 Aug 2017 19:18:53 +0000 (21:18 +0200)]
gallium: remove TGSI_OPCODE_CALLNZ
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Marek Olšák [Sat, 19 Aug 2017 19:09:52 +0000 (21:09 +0200)]
gallium: remove TGSI FENCE opcodes
use MEMBAR instead
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Marek Olšák [Sat, 19 Aug 2017 18:24:34 +0000 (20:24 +0200)]
gallium: remove TGSI opcodes PUSHA, POPA, SAD, TXQ_LZ
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Marek Olšák [Mon, 21 Aug 2017 21:16:42 +0000 (23:16 +0200)]
radeonsi: emit VGT_REUSE_OFF in the right place
clip_regs aren't marked dirty when writes_viewport_index is changed.
Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 19 Aug 2017 21:37:29 +0000 (23:37 +0200)]
radeonsi: add support for TGSI opcodes DCEIL, DFLR, DROUND, DSSG, DTRUNC
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 19 Aug 2017 20:51:51 +0000 (22:51 +0200)]
radeonsi: use a faster version of PK2H
+ 4 piglit regressions, but it's correct accorcing to the GL spec and
performance is more important than piglit.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 19 Aug 2017 13:51:30 +0000 (15:51 +0200)]
radeonsi: don't decompress Z/S if there is no HTILE
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 19 Aug 2017 13:28:14 +0000 (15:28 +0200)]
gallium/radeon: add helpers for whether HTILE is enabled
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 19 Aug 2017 13:06:22 +0000 (15:06 +0200)]
radeonsi/gfx9: don't flush L2 metadata for DB if not needed
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 19 Aug 2017 13:06:22 +0000 (15:06 +0200)]
radeonsi/gfx9: don't flush L2 metadata for CB if not needed
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 18 Aug 2017 13:51:59 +0000 (15:51 +0200)]
radeonsi/gfx9: don't flush TC L2 between rendering and texturing if not needed
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 18 Aug 2017 22:34:12 +0000 (00:34 +0200)]
radeonsi/gfx9: use correct TC flush flags when invalidating CB & DB
Now we can finally stop flushing L2 data.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 17 Aug 2017 21:35:36 +0000 (23:35 +0200)]
ac/surface/gfx9: don't allow DCC for the smallest mipmap levels
This fixes garbage there if we don't flush TC L2 after rendering.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>