Yonggang Luo [Tue, 6 Sep 2022 15:59:50 +0000 (23:59 +0800)]
c11: Update the values of enum mtx_plain, mtx_recursive, mtx_timed to make sure mtx_recursive != mtx_plain | mtx_recursive
According to c11 standards, there is 4 variant of mtx_init parameter,
mtx_plain
mtx_timed
mtx_plain|mtx_recursive
mtx_timed|mtx_recursive
Directly use mtx_recursive is not a thing, so we need make sure mtx_plain and mtx_plain|mtx_recursive are not equal,
So now we choose the values from Android c11 threads.h for enum mtx_plain, mtx_recursive, mtx_timed, to make sure
c11/threads.h be more c11 conformance, and can raise error when the type parameter of mtx_init are not one of
mtx_plain
mtx_timed
mtx_plain|mtx_recursive
mtx_timed|mtx_recursive
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18445>
Yonggang Luo [Tue, 6 Sep 2022 15:51:41 +0000 (23:51 +0800)]
svga: direct use of mtx_recursive is not c11 conformance
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18445>
Yonggang Luo [Tue, 6 Sep 2022 15:50:43 +0000 (23:50 +0800)]
radeonsi: direct use of mtx_recursive is not c11 conformance
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18445>
Yonggang Luo [Tue, 23 Aug 2022 19:46:57 +0000 (03:46 +0800)]
mesa: direct use of mtx_recursive is not c11 conformance
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18445>
Rob Clark [Tue, 13 Sep 2022 18:14:46 +0000 (11:14 -0700)]
freedreno: Remap high/norm/low priorities
At the gallium level, we only have three priorities. But if kernel
supports preemption we'll have 3*nr_rings priority levels. We'd prefer
to have the priorities that userspace picks be distributed over the
entire range of priorities so that preemption can work.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18584>
Rob Clark [Tue, 13 Sep 2022 16:37:28 +0000 (09:37 -0700)]
freedreno: nr_rings -> nr_priorities
This was renamed in the UABI header over a year ago, see
fc40e5e10c3b ("drm/msm: Utilize gpu scheduler priorities")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18584>
Rob Clark [Tue, 13 Sep 2022 16:33:11 +0000 (09:33 -0700)]
freedreno: Misc indent fix
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18584>
Chia-I Wu [Wed, 7 Sep 2022 23:26:25 +0000 (16:26 -0700)]
turnip: add support for VK_KHR_global_priority
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18510>
Chia-I Wu [Thu, 8 Sep 2022 00:14:44 +0000 (17:14 -0700)]
turnip: add tu_physical_device::submitqueue_priority_count
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18510>
Chia-I Wu [Thu, 8 Sep 2022 01:41:48 +0000 (18:41 -0700)]
turnip: fix error handling for tu_queue_init
tu_queue_finish can only be called on initialized queues.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18510>
Ruijing Dong [Sat, 10 Sep 2022 20:52:12 +0000 (16:52 -0400)]
frontends/va: add HRD, filler data enable and etc
HRD parameters and filler data enable and skip frame
enable data are needed even though some application
doesn't use them.
Also for per picture rate control, max_qp and min_qp
are added.
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18534>
Ruijing Dong [Sat, 10 Sep 2022 20:42:40 +0000 (16:42 -0400)]
frontends/va: add max_frame_size into rate control
why:
max au size and per picture rate control data structure
need to follow the input
how:
have max_frame_size as the input to rate control
also re-calculate other rate control related params
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18534>
Ruijing Dong [Sat, 10 Sep 2022 20:28:19 +0000 (16:28 -0400)]
frontends/va: change getEncParamPreset location
why:
getEncParamPreset functions overwrite the incoming
messages.
how:
To change a location after the decoder is created,
so that if no incoming message the default ones
will be used otherwise the new messages will
overwrite the default values.
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18534>
Ruijing Dong [Sat, 10 Sep 2022 20:19:09 +0000 (16:19 -0400)]
frontend/va: remove some unnecessary code
clean up some code related to h264 encoding.
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18534>
Chia-I Wu [Thu, 8 Sep 2022 17:59:56 +0000 (10:59 -0700)]
subprojects: uprev perfetto to v29.0
This is mainly to get perfetto's commit
3e7228376 ("tracing: Clean up
platform TLS state on shutdown").
Acked-by: Rob Clark <robdclark@chromium.org>
Acked-by: Sami Kyöstilä <skyostil@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18502>
Chia-I Wu [Tue, 6 Sep 2022 19:40:21 +0000 (12:40 -0700)]
vulkan: update ALLOWED_ANDROID_VERSION for api level 33
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18476>
Yiwei Zhang [Tue, 13 Sep 2022 22:19:28 +0000 (22:19 +0000)]
venus: ignore pInheritanceInfo if not secondary command buffer
TEST: no segfault in dEQP-VK.api.command_buffers.bad_inheritance_info_random
Fixes:
6f5289df533 ("venus: refactor VkCommandBufferBeginInfo fixups to function")
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18583>
Emma Anholt [Tue, 13 Sep 2022 04:11:14 +0000 (21:11 -0700)]
turnip: Only emit descriptor loads for active stages in the pipeline.
zink has a push descriptor template layout that has every possible stage,
which gets used regardless of what stages are in the pipeline. By
skipping over the unused stages, we cut the CP overhead.
Improves TU_DEBUG=sysmem gfxbench gl_driver2 on zink by 6.57% +/-
0.331143% (n=5).
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18562>
Emma Anholt [Tue, 13 Sep 2022 21:32:20 +0000 (14:32 -0700)]
ci/turnip: Add missing a618 full-run bypass fails.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18562>
Adam Jackson [Thu, 1 Sep 2022 21:48:34 +0000 (17:48 -0400)]
wsi/x11: Fix the is-visual-supported check
This was sort of well intentioned, but wrong. bits_per_rgb_value is the
number of significant bits in the color (channel) specification, not the
number of bits used to name that color within the pixel. If you have a
depth 24 visual but the colormap is 11 bits deep then each of those
channels selects one of 256 11-bit color values in the output ramp.
The open source drivers mostly don't expose anything like that, but
nvidia does, and we refuse to work. That's silly. Practically speaking
we can probably render to any TrueColor or DirectColor visual that your
X server exposes, since it is probably not going to have visuals for
non-color-renderable formats. Just check the visual class instead.
Likewise when matching formats to visuals, count the bits in the rgb
masks in the visual.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6995
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18381>
Rhys Perry [Wed, 6 Oct 2021 14:06:51 +0000 (15:06 +0100)]
nir/algebraic: optimize bits=umin(bits, 32-(offset&0x1f))
Optimizes patterns which are created by recent versions of vkd3d-proton,
when constant folding doesn't eliminate it entirely:
- ubitfield_extract(value, offset, umin(bits, 32-(offset&0x1f)))
- ibitfield_extract(value, offset, umin(bits, 32-(offset&0x1f)))
- bitfield_insert(base, insert, offset, umin(bits, 32-(offset&0x1f)))
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13225>
Pierre-Eric Pelloux-Prayer [Thu, 8 Sep 2022 13:43:05 +0000 (15:43 +0200)]
radeonsi: invalidate L2 when using dcc stores
This is only needed on chips with tcc_rb_non_coherent=1.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7084
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18494>
Pierre-Eric Pelloux-Prayer [Thu, 8 Sep 2022 08:21:32 +0000 (10:21 +0200)]
mesa: remove fallback for GL_DEPTH_STENCIL
st_TexSubImage has this "default to fallback for depth-stencil" since
2013. I think it's time to remove this limitation - hopefully all
drivers will be happy with the change to avoid adding yet another CAP.
This helps CS:GO startup a lot, because the fallback path is very very
slow.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18484>
Pierre-Eric Pelloux-Prayer [Mon, 12 Sep 2022 09:00:04 +0000 (11:00 +0200)]
mesa: simplify _mesa_texstore_z24_s8 and s8_z24
The spec says:
If the base internal format is DEPTH_STENCIL and format
is not DEPTH_STENCIL, then the values of the stencil
index texture components are undefined.
Which can be translated as: we don't need to bother preserving
the original stencil values.
Suggested by Emma Anholt.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18484>
Pierre-Eric Pelloux-Prayer [Thu, 8 Sep 2022 07:47:59 +0000 (09:47 +0200)]
mesa: avoid reading back textures from VRAM
This can be very slow on dGPU.
I tried a different version that would allocate a full row
and then do a single memcpy per row but the performance
was similar so I kept the simple version.
Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18484>
Juston Li [Tue, 23 Aug 2022 20:22:10 +0000 (13:22 -0700)]
venus: add support for VK_EXT_multi_draw
Test:
./deqp-vk -n dEQP-VK.draw.*multi_draw*
Test run totals:
Passed: 11520/11520 (100.0%)
Failed: 0/11520 (0.0%)
Not supported: 0/11520 (0.0%)
Warnings: 0/11520 (0.0%)
Waived: 0/11520 (0.0%)
Signed-off-by: Juston Li <justonli@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18304>
Juston Li [Tue, 23 Aug 2022 20:28:22 +0000 (13:28 -0700)]
venus: sync to latest venus protocol headers
- v1.3.227 update
- added VK_EXT_multi_draw
Signed-off-by: Juston Li <justonli@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18304>
Emma Anholt [Sun, 11 Sep 2022 05:45:48 +0000 (22:45 -0700)]
nouveau: Fix compiler warnings about silly address checks in ir_print.
in/out/sv are arrays, so &array[i] is a non-null pointer. Presumably
numSysVals/Inputs/Outputs are only incremented when there's data in the
arrays, anyway.
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18536>
Chia-I Wu [Tue, 30 Aug 2022 07:10:54 +0000 (00:10 -0700)]
turnip: reduce MAX_STORAGE_BUFFER_RANGE
Reduce MAX_STORAGE_BUFFER_RANGE from (1<<29) to (1<<27). While (1<<28)
is fine based on my tests, let's match what the latest version of the
blob does.
Tested on a618 and a635.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18322>
Karol Herbst [Tue, 13 Sep 2022 15:48:45 +0000 (17:48 +0200)]
rusticl/device: print error when libclc fails to load
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18580>
Alyssa Rosenzweig [Sun, 11 Sep 2022 15:07:50 +0000 (11:07 -0400)]
asahi: Handle blending with MRT
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18525>
Alyssa Rosenzweig [Sat, 10 Sep 2022 21:56:10 +0000 (17:56 -0400)]
asahi: Don't crash on <4 channel render targets
It doesn't matter what we put in the swizzle for the unused components,
but if we try to stuff out-of-bounds PIPE_SWIZZLE_0/1/NONE values,
we'll crash in GenXML. Fixes failing tests in
dEQP-GLES3.functional.fragment_out.basic.fixed.*
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18525>
Alyssa Rosenzweig [Sun, 11 Sep 2022 15:17:15 +0000 (11:17 -0400)]
agx: Don't use nir_find_variable_with_driver_location
io_semantics is the preferred alternative.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18525>
Alyssa Rosenzweig [Fri, 9 Sep 2022 21:01:10 +0000 (17:01 -0400)]
agx: Lower txs to a descriptor crawl
There's no native txs instruction... but we can emulate one :-) This is
heavy on shader ALU, but in the production driver, it'll all be hoisted
up to the preamble shader and so it shouldn't matter much. This
keeps the driver itself simple and low overhead, with a completely
obvious generalization to bindless.
Passes dEQP-GLES3.functional.shaders.texture_functions.texturesize.*
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18525>
Alyssa Rosenzweig [Fri, 9 Sep 2022 20:59:23 +0000 (16:59 -0400)]
agx: Implement load_global(_constant)
Found in compute shaders, maps to a subset of device_load, and will be
used for some lowerings soon.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18525>
Alyssa Rosenzweig [Fri, 9 Sep 2022 18:32:32 +0000 (14:32 -0400)]
agx: Implement txd
Handles all cases except for cube maps, which don't seem to work
properly, so those are lowered.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18525>
Alyssa Rosenzweig [Thu, 8 Sep 2022 22:59:35 +0000 (18:59 -0400)]
agx: Implement texture offsets and comparators
Texture offsets and shadow comparison values get grouped into a vector
passed by register. Comparison values are provided as-is (fp32). Texture
offsets are packed into nibbles, but we can do this on the CPU, as
nonconstant offsets are forbidden in GLSL at least. They're also
forbidden in Vulkan/SPIR-V without ImageGatherExtended/
shaderImageGatherExtended. I'm happy kicking the NIR lowering can down
the line, this commit is complicated enough already.
Passes dEQP-GLES3.functional.shaders.texture_functions.texture.* and
dEQP-GLES3.functional.shaders.texture_functions.textureoffset.*
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18525>
Alyssa Rosenzweig [Fri, 9 Sep 2022 18:32:01 +0000 (14:32 -0400)]
agx: Make p_combine take a dynamic src count
For larger vectors.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18525>
Alyssa Rosenzweig [Fri, 9 Sep 2022 21:00:47 +0000 (17:00 -0400)]
agx,asahi: Implement nir_intrinsic_load_texture_base_agx
Save off what we pass to BIND_TEXTURE.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18525>
Alyssa Rosenzweig [Fri, 9 Sep 2022 20:59:56 +0000 (16:59 -0400)]
nir: Add nir_intrinsic_texture_base_agx sysval
For non-bindless textures, get the base address of the texture
descriptor array, so we can crawl descriptors in the shader. For
bindless, this isn't needed (since the bindless handle will be the
address itself).
jekstrand suggested the idea of the descriptor crawl. It worked out
pretty well, all considered.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18525>
Alyssa Rosenzweig [Mon, 27 Jun 2022 14:19:47 +0000 (10:19 -0400)]
panfrost: Honour cso->req_local_mem
Fixes api.min_max_local_mem_size.
nir->info.shared_size can't be trusted in OpenCL.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18559>
Alyssa Rosenzweig [Tue, 5 Jul 2022 19:11:59 +0000 (15:11 -0400)]
panfrost: Respect buffer offset for OpenCL
This is so dumb. Panfrost port of
d98b82a1039 ("iris/cs: take buffer offsets
into account for CL")
Fixes buffer.sub_buffers_read_write
Fixes:
80b90a0f2b8 ("panfrost: Implement panfrost_set_global_binding")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Suggested-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18560>
Sarah Walker [Thu, 28 Jul 2022 09:05:57 +0000 (10:05 +0100)]
pvr: Update FWIF 3d and compute register structures
This matches changes made in FW 1.17.OS@6285007.
Signed-off-by: Sarah Walker <sarah.walker@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18440>
Karmjit Mahil [Thu, 11 Aug 2022 14:33:45 +0000 (15:33 +0100)]
pvr: Emit cs words for load op on vkCmdBeginRenderPass().
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18569>
Sarah Walker [Fri, 27 May 2022 13:51:39 +0000 (14:51 +0100)]
pvr: Remove STRIP_RENDERING members from FWIF
This matches changes made in FW 1.17.OS@6256262.
Signed-off-by: Sarah Walker <sarah.walker@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18490>
Rajnesh Kanwal [Thu, 11 Aug 2022 09:59:17 +0000 (10:59 +0100)]
pvr: Implement vkCmdDrawIndexedIndirect API.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18486>
Rajnesh Kanwal [Fri, 5 Aug 2022 09:45:10 +0000 (10:45 +0100)]
pvr: Implement vkCmdDrawIndirect API.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18486>
Eric Engestrom [Tue, 13 Sep 2022 08:16:19 +0000 (09:16 +0100)]
docs: move rusticl readme into docs/
And convert it from Markdown to rST.
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18568>
Rajnesh Kanwal [Fri, 12 Aug 2022 15:23:05 +0000 (16:23 +0100)]
pvr: Implement vkGetPhysicalDeviceImageFormatProperties2 API.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18487>
Georg Lehmann [Mon, 12 Sep 2022 09:50:21 +0000 (11:50 +0200)]
radv: Enable VK_EXT_load_store_op_none.
VK_ATTACHMENT_STORE_OP_NONE_EXT is already supported through
VK_KHR_dynamic_rendering.
It doesn't seem like we need to do anything special for
VK_ATTACHMENT_LOAD_OP_NONE_EXT.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7246
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18545>
David Heidelberg [Tue, 30 Aug 2022 16:03:21 +0000 (18:03 +0200)]
ci: uprev piglit 2022-09-08
Main change is new traces YAML format!
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18329>
David Heidelberg [Thu, 1 Sep 2022 20:50:38 +0000 (22:50 +0200)]
ci: introduce update_traces_checksum.py
Invoking this script takes checksums from all failed jobs and update
them in $driver-traces.yml files.
```
.gitlab-ci/bin/update_traces_checksum.py --rev $(git rev-parse HEAD)
```
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18329>
David Heidelberg [Wed, 7 Sep 2022 21:32:19 +0000 (23:32 +0200)]
ci: split ci_run_n_monitor into script and shared parts
These parts will be shared with the update checksum script.
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18329>
David Heidelberg [Sat, 3 Sep 2022 22:35:01 +0000 (00:35 +0200)]
ci: export whole results/ directory for all traces jobs
We use `results/results.json.bz2` in `update_traces_checksum.py`.
Just few extra KiB.
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18329>
David Heidelberg [Sat, 3 Sep 2022 18:54:40 +0000 (20:54 +0200)]
ci: performance traces: make use of no-perf label
Traces with label `no-perf` will be skipped in performance testing.
This commit adds the yq tool, which preprocesses the traces.yml file
before sending it to the piglit.
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18329>
David Heidelberg [Sat, 3 Sep 2022 19:06:09 +0000 (21:06 +0200)]
ci: check traces.yml files with yamllint
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18329>
David Heidelberg [Tue, 30 Aug 2022 20:23:07 +0000 (22:23 +0200)]
ci/crocus: convert traces to new YAML format
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18329>
David Heidelberg [Tue, 30 Aug 2022 20:10:32 +0000 (22:10 +0200)]
ci/i915: convert traces to new YAML format
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18329>
David Heidelberg [Tue, 30 Aug 2022 20:03:05 +0000 (22:03 +0200)]
ci/intel: convert traces to new YAML format
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18329>
David Heidelberg [Tue, 30 Aug 2022 19:43:33 +0000 (21:43 +0200)]
ci/radeonsi: convert traces to new YAML format
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18329>
David Heidelberg [Tue, 30 Aug 2022 19:25:49 +0000 (21:25 +0200)]
ci/panfrost: convert traces to new YAML format
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18329>
David Heidelberg [Tue, 30 Aug 2022 19:14:07 +0000 (21:14 +0200)]
ci/broadcom: convert traces to new YAML format
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18329>
David Heidelberg [Tue, 30 Aug 2022 19:01:25 +0000 (21:01 +0200)]
ci/lavapipe: convert traces to new YAML format
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18329>
David Heidelberg [Tue, 30 Aug 2022 18:59:05 +0000 (20:59 +0200)]
ci/llvmpipe: convert traces to new YAML format
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18329>
David Heidelberg [Tue, 30 Aug 2022 18:43:44 +0000 (20:43 +0200)]
ci/virgl: convert traces to new YAML format
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18329>
David Heidelberg [Sat, 20 Aug 2022 21:59:46 +0000 (23:59 +0200)]
ci/freedreno: convert traces to new YAML format
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18329>
Karmjit Mahil [Fri, 26 Aug 2022 15:15:21 +0000 (16:15 +0100)]
pvr: Handle VK_CULL_MODE_FRONT_AND_BACK.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18550>
Samuel Pitoiset [Mon, 29 Aug 2022 16:38:01 +0000 (18:38 +0200)]
radv: advertise extendedDynamicState2PatchControlPoints
For less stuttering with Zink, also required by Zink for full GPL.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6584
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18344>
Samuel Pitoiset [Tue, 30 Aug 2022 15:11:57 +0000 (17:11 +0200)]
radv: implement dynamic patch control points
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18344>
Samuel Pitoiset [Mon, 29 Aug 2022 16:35:52 +0000 (18:35 +0200)]
radv: move emitting GE_CNTL for non-NGG pipelines from the cmdbuf
GE_CNTL is the equivalent of IA_MULTI_VGT_PARAM on GFX9 and older.
Calling this function for every draw shouldn't really hurt in practice
because only non-NGG pipelines need this.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18344>
Samuel Pitoiset [Mon, 29 Aug 2022 16:27:52 +0000 (18:27 +0200)]
radv: move emitting PRIMGROUP_SIZE for <= GFX9 from the cmdbuf
The number of tessellation patches that is computed from the number
of patch control points might change dynamically too.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18344>
Samuel Pitoiset [Mon, 29 Aug 2022 16:12:23 +0000 (18:12 +0200)]
radv: pass the number of patch control points to si_get_ia_multi_vgt_param()
To prepare for dynamic patch control points.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18344>
Samuel Pitoiset [Tue, 30 Aug 2022 14:39:22 +0000 (16:39 +0200)]
radv: add ABI lowering support for dynamic patch control points
The number of patch control points (TCS) and the number of patches
(TCS/TES) is read from user SGPRs.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18344>
Samuel Pitoiset [Tue, 30 Aug 2022 15:05:11 +0000 (17:05 +0200)]
radv: add shader arguments for dynamic patch control points
This introduces two new user SGPRS:
- tcs_offchip_layout: input patch size and number of patches in TCS
- tes_num_patches: number of patches in TES
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18344>
Samuel Pitoiset [Tue, 30 Aug 2022 15:49:34 +0000 (17:49 +0200)]
aco: prevent a division by zero when patch control points is dynamic
tess_input_vertices is zero if the state is dynamic.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18344>
Samuel Pitoiset [Wed, 31 Aug 2022 13:01:02 +0000 (15:01 +0200)]
radv: set workgroup_size to 256 when patch control points is dynamic
It's the maximum possible value. This is to ensure that compilers
don't optimize away barriers, like in ACO when workgroup_size is less
than or equal to wave_size, s_barrier is considered a no-op.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18344>
Samuel Pitoiset [Wed, 31 Aug 2022 13:00:43 +0000 (15:00 +0200)]
radv: skip computing some tess info when patch control points is dynamic
We don't know the value.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18344>
Samuel Pitoiset [Tue, 30 Aug 2022 14:34:14 +0000 (16:34 +0200)]
radv: add radv_pipeline_key::dynamic_patch_control_points
This will be used to compile different tessellation shaders when
patch control points is dynamic.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18344>
Samuel Pitoiset [Wed, 31 Aug 2022 09:16:05 +0000 (11:16 +0200)]
radv: emit the LDS size for TCS directly from the pipeline on GFX9+
To be consistent with the LDS shader config for LS, and this will
be emitted from the cmdbuf for dynamic patch control points.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18344>
Samuel Pitoiset [Wed, 31 Aug 2022 09:00:10 +0000 (11:00 +0200)]
radv: reword a comment about dynamic states when rasterization is disabled
Make it more generic instead of listing all states.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18344>
Erik Faye-Lund [Mon, 12 Sep 2022 12:12:29 +0000 (14:12 +0200)]
docs/zink: document rgtc requirement
OpenGL 3.0 requires RGTC support, and until we have emulation in place,
we should document that requirement.
Fixes:
d50e8554b99 ("zink: add feature-documentation")
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18549>
Samuel Pitoiset [Thu, 1 Sep 2022 10:18:54 +0000 (12:18 +0200)]
radv: upload the PS epilog in the existing pipeline BO
This reduces the number of BOs needed.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18363>
Samuel Pitoiset [Thu, 1 Sep 2022 10:14:11 +0000 (12:14 +0200)]
radv: store the binary to radv_shader_part
This is currently always freed after the upload but this will allow
to upload the PS epilog later.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18363>
Samuel Pitoiset [Thu, 1 Sep 2022 09:33:40 +0000 (11:33 +0200)]
radv: split upload_shader_part() in two parts
One that creates the radv_shader_part object and one that uploads it.
This will be used to upload the PS epilogs as part of the existing
pipeline BO.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18363>
Samuel Pitoiset [Thu, 1 Sep 2022 09:55:49 +0000 (11:55 +0200)]
radv: store the VS prologs/PS epilogs VA at upload time
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18363>
Samuel Pitoiset [Mon, 12 Sep 2022 06:18:37 +0000 (08:18 +0200)]
radv/ci: re-enable dEQP-VK.renderpass2.depth_stencil_resolve.*_samplemask
Since RADV switched to 100% dynamic rendering, image transitions for
attachments not used in a subpass are correctly performed.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18542>
Samuel Pitoiset [Thu, 1 Sep 2022 11:56:34 +0000 (13:56 +0200)]
radv: add a pointer to radv_shader_binary in radv_shader
With GPL, we will have to keep the shader binary in the library for
uploading it later, so it's easier to have a pointer in radv_shader.
The shader binary will be freed when the library is destroyed.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18515>
Caio Oliveira [Sat, 10 Sep 2022 18:09:15 +0000 (11:09 -0700)]
intel/compiler: Use brw_ud* helpers in thread payload code
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
Caio Oliveira [Fri, 9 Sep 2022 23:52:10 +0000 (16:52 -0700)]
intel/compiler: Add a few more brw_ud* helpers
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
Caio Oliveira [Tue, 30 Aug 2022 00:13:00 +0000 (17:13 -0700)]
intel/compiler: Make thread_payload struct abstract
Each shader stage has its own struct and will instantiate it, so the
base class doesn't need to be instantiated anymore.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
Caio Oliveira [Tue, 23 Aug 2022 04:47:02 +0000 (21:47 -0700)]
intel/compiler: Create and use struct for CS thread payload
Move subgroup_id, that's only used by CS for verx10 < 125, as part of
the payload too -- even though is not, strictly speaking.
Note the thread execution of Task/Mesh is similar enough, so we make
their common struct inherit from cs_thread_payload.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
Caio Oliveira [Tue, 30 Aug 2022 07:47:32 +0000 (00:47 -0700)]
intel/compiler: Export brw_get_subgroup_id_param_index()
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
Caio Oliveira [Fri, 26 Aug 2022 00:00:15 +0000 (17:00 -0700)]
intel/compiler: Create and use struct for Bindless thread payload
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
Caio Oliveira [Tue, 23 Aug 2022 06:02:34 +0000 (23:02 -0700)]
intel/compiler: Store start of ICP handles in GS thread payload struct
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
Caio Oliveira [Tue, 23 Aug 2022 05:23:17 +0000 (22:23 -0700)]
intel/compiler: Create and use struct for GS thread payload
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
Caio Oliveira [Mon, 22 Aug 2022 06:05:08 +0000 (23:05 -0700)]
intel/compiler: Create and use struct for TASK and MESH thread payloads
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
Caio Oliveira [Mon, 22 Aug 2022 04:22:12 +0000 (21:22 -0700)]
intel/compiler: Create and use struct for VS thread payload
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
Caio Oliveira [Mon, 22 Aug 2022 03:51:58 +0000 (20:51 -0700)]
intel/compiler: Create and use struct for TES thread payload
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
Caio Oliveira [Sat, 20 Aug 2022 00:31:37 +0000 (17:31 -0700)]
intel/compiler: Store start of ICP handles in TCS thread payload struct
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
Caio Oliveira [Fri, 19 Aug 2022 22:04:15 +0000 (15:04 -0700)]
intel/compiler: Store Primitive ID in TCS thread payload struct
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
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