Lukasz Majewski [Thu, 26 Apr 2018 13:07:18 +0000 (15:07 +0200)]
arm: imx53: Add support for imx53 boards from K+P
This commit adds support for DDC and HSC boards from
K+P in u-boot.
Console output:
U-Boot 2018.05-rc2-00090-g752b7ed6f9 (Apr 26 2018 - 14:24:24 +0200)
CPU: Freescale i.MX53 rev2.1 at 800 MHz
Reset cause: WDOG
Model: K+P iMX53
DRAM: 512 MiB
MMC: FSL_SDHC: 0
Loading Environment from MMC... OK
In: serial
Out: serial
Err: serial
Module EEPROM:
ID: TQMa53-CB.0401
SN:
63152762
MAC: 00:0b:64:03:14:2a
BBoard:40x0 Rev:10
Net: eth0: ethernet@
63fec000
Hit any key to stop autoboot: 0
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Lukasz Majewski [Tue, 15 May 2018 14:26:43 +0000 (16:26 +0200)]
sandbox: tests: Add tests for mc34708 PMIC device
Following tests has been added for mc34708 device:
- get_test for mc34708 PMIC
- Check if proper number of registers is read
- Check if default (emulated via i2c device) value is properly read
- Check if value write/read operation is correct
- Perform tests to check if pmic_clrsetbits() is working correctly
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Lukasz Majewski [Tue, 15 May 2018 14:26:42 +0000 (16:26 +0200)]
sandbox: tests: Exclude common test code (pmic_get) in test/dm/pmic.c
The common code can be excluded to be reused by tests for other PMIC.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Lukasz Majewski [Tue, 15 May 2018 14:26:41 +0000 (16:26 +0200)]
sandbox: Enable MC34708 PMIC support
This MC34708 PMIC is somewhat special - it used single transfers (R/W) with
3 bytes size - up till now U-Boot's PMICs only used 1 byte.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Lukasz Majewski [Tue, 15 May 2018 14:26:40 +0000 (16:26 +0200)]
sandbox: Enable support for MC34708 PMIC in DTS
This commit also provides the default values of the emulated MC34708 PMIC
internal registers content.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Lukasz Majewski [Tue, 15 May 2018 14:26:39 +0000 (16:26 +0200)]
sandbox: Rewrite i2c_pmic_emul.c to support PMIC with 3 bytes transmission
This change enables support for MC34708 PMIC in sandbox. Now we can
emulate the I2C transfers larger than 1 byte.
Notable changes for this driver:
- From now on the register number is not equal to index in the buffer,
which emulates the PMIC registers
- The PMIC register's pool is now dynamically allocated up till
64 regs * 3 bytes each = 192 B
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Lukasz Majewski [Tue, 15 May 2018 14:26:38 +0000 (16:26 +0200)]
pmic: Rewrite the pmic command to not only work with single byte transmission
Up till now it was only possible to use 'pmic' command with a single byte
transmission.
The pmic_read|write functions has been replaced with ones, which don't need
the transmission length as a parameter.
Due to that it is possible now to read data from PMICs transmitting more
data than 1 byte at once (e.g. mc34708)
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Lukasz Majewski [Tue, 15 May 2018 14:26:37 +0000 (16:26 +0200)]
pmic: dm: Add support for MC34708 for PMIC DM
This patch adds support for MC34708 PMIC, to be used with driver model
(DM).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Lukasz Majewski [Tue, 15 May 2018 14:26:36 +0000 (16:26 +0200)]
pmic: dm: Rewrite pmic_reg_{read|write|clrsetbits} to support 3 bytes transmissions
This commit provides support for transmissions larger than 1 byte for
PMIC devices used with DM (e.g. MC34708 from NXP).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Lukasz Majewski [Tue, 15 May 2018 14:26:35 +0000 (16:26 +0200)]
pmic: Add support for setting transmission length in uclass private data
The struct uc_pmic_priv's trans_len field stores the number of types to
be transmitted per PMIC transfer.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Lukasz Majewski [Tue, 15 May 2018 14:26:34 +0000 (16:26 +0200)]
pmic: fsl: Define number of bytes sent at once by MC34708 PMIC
This patch adds definition of the number of bytes sent at once by the
MC34708 PMIC.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Lukasz Majewski [Tue, 15 May 2018 14:26:33 +0000 (16:26 +0200)]
pmic: fsl: Provide some more definitions for MC34708 PMIC
This commit adds some more defines for MC34708 PMIC.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Jagan Teki [Mon, 7 May 2018 05:51:40 +0000 (11:21 +0530)]
configs: imx6dl-mamoj: Enable HAB
Enable Secure boot(HAB) for BTicino Mamoj board.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Mon, 7 May 2018 05:51:39 +0000 (11:21 +0530)]
configs: imx6dl-mamoj: Add Falcon mode support
Add Falcon mode support to boot Linux directly after SPL.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Mon, 7 May 2018 05:51:38 +0000 (11:21 +0530)]
configs: imx6dl-mamoj: Add DFU support
Add DFU support for BTicino Mamoj board and update
the same steps in README.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Simone CIANNI <simone.cianni@bticino.it>
Signed-off-by: Raffaele RECALCATI <raffaele.recalcati@bticino.it>
Jagan Teki [Mon, 7 May 2018 05:51:37 +0000 (11:21 +0530)]
configs: imx6dl_mamoj: Enable fastboot and ums
Enable fastboot and ums for host to interact eMMC on
Mamoj board.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Simone CIANNI <simone.cianni@bticino.it>
Signed-off-by: Raffaele RECALCATI <raffaele.recalcati@bticino.it>
Jagan Teki [Mon, 7 May 2018 05:51:36 +0000 (11:21 +0530)]
i.MX6DL: mamoj: Add PFUZE100 support
MX6DL Mamoj boards has Freescale PFUZE100 PMIC, add support
for it through DM_PMIC dt definition.
pmic log:
Reviewed-by: Stefano Babic <sbabic@denx.de>
========
=> pmic list
| Name | Parent name | Parent uclass @ seq
| pfuze100@08 | i2c@
021f8000 | i2c @ 3
=> pmic dev pfuze100@08
dev: 0 @ pfuze100@08
=> pmic dump
Dump pmic: pfuze100@08 registers
0x00: 10 00 00 21 00 01 3f 01 00 7f 00 00 00 00 00 81
0x10: 00 00 3f 00 00 00 00 00 00 00 00 10 00 00 00 00
0x20: 2b 2b 2b 08 c4 00 00 00 00 00 00 00 00 00 2b 2b
0x30: 2b 08 c4 00 00 72 72 72 08 d4 00 00 2c 2c 2c 08
0x40: e4 00 00 2c 2c 2c 08 e4 00 00 6f 6f 6f 08 f4 00
0x50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x60: 00 00 00 00 00 00 48 00 00 00 10 06 1e 1e 17 10
0x70: 1a 1f 00 00 00 00 00 00 00 00 00 00 00 00 00
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Simone CIANNI <simone.cianni@bticino.it>
Signed-off-by: Raffaele RECALCATI <raffaele.recalcati@bticino.it>
Jagan Teki [Mon, 7 May 2018 05:51:35 +0000 (11:21 +0530)]
i.MX6DL: mamoj: Add I2C support
i.MX6DL Mamoj has i2c3 and i2c4 buses, add support
through DM_I2C with dt definition.
i2c log:
Reviewed-by: Stefano Babic <sbabic@denx.de>
=======
=> i2c bus
Bus 2: i2c@
021a8000
Bus 3: i2c@
021f8000
=> i2c dev 2
Setting bus to 2
=> i2c speed 400000
Setting bus speed to 400000 Hz
=> i2c probe
Valid chip addresses: 20 51 53
=> i2c md 53 0xff
00ff: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................
=> i2c md 51 0xff
00ff: a8 08 40 50 09 43 46 52 42 18 80 8e ae a9 d0 53 ..@P.CFRB......S
=> i2c dev 3
Setting bus to 3
=> i2c speed 100000
Setting bus speed to 100000 Hz
=> i2c probe
Valid chip addresses: 08 40 48 4B
=> i2c md 08 0xff
00ff: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Simone CIANNI <simone.cianni@bticino.it>
Signed-off-by: Raffaele RECALCATI <raffaele.recalcati@bticino.it>
Jagan Teki [Mon, 7 May 2018 05:51:34 +0000 (11:21 +0530)]
i.MX6: board: Add BTicino i.MX6DL Mamoj initial support
Add initial support for i.MX6DL BTicino Mamoj board.
Mamoh board added:
- SPL
- SPL_DM
- SPL_OF_CONTROL
- DM for U-Boot proper
- OF_CONTROL for U-Boot proper
- eMMC
- FEC
- Boot from eMMC
- Boot from USB SDP
Signed-off-by: Simone CIANNI <simone.cianni@bticino.it>
Signed-off-by: Raffaele RECALCATI <raffaele.recalcati@bticino.it>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Wed, 11 Apr 2018 12:32:23 +0000 (18:02 +0530)]
ARM: i.MX6: dts: Build dtb based on SOC type
Build dtb's based on SOC type instead building arch type.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Wed, 11 Apr 2018 12:32:22 +0000 (18:02 +0530)]
ARM: dts: i.MX6UL: U-Boot specific dts for u-boot, dm-spl
u-boot,dm-spl property is specific to U-Boot, so move it into
*u-boot.dtsi files for relevant i.MX6UL files.
This make syncing Linux dts files straight forward.
Also update the MAINTAINERS file for dts files.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Wed, 11 Apr 2018 12:32:21 +0000 (18:02 +0530)]
ARM: dts: imx6ul-isiot: Move usdhc2 into dtsi
Move usdhc2 node along with pinctrl to imx6ul-isiot.dts
from imx6ul-isiot-emmc.dts
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Wed, 11 Apr 2018 12:32:20 +0000 (18:02 +0530)]
ARM: dts: i.MX6QDL: U-Boot specific dts for u-boot, dm-spl
u-boot,dm-spl property is specific to U-Boot, so move it into
*u-boot.dtsi files for relevant i.MX6QDL files.
This make syncing Linux dts files straight forward.
Also update the MAINTAINERS file for dts files.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Guillaume GARDET [Wed, 18 Apr 2018 15:04:59 +0000 (17:04 +0200)]
imx6: sabrelite: update defconfig to use distro defaults
Boot tested with boot.scr script and EFI/Grub2 on mmc0 and mmc1 slots on sabrelite board.
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Gary Bisson <gary.bisson@boundarydevices.com>
Guillaume GARDET [Wed, 18 Apr 2018 15:04:58 +0000 (17:04 +0200)]
imx6: Convert sabrelite and nitrogen6x boards to distro boot support
Boot tested on sabrelite board.
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Gary Bisson <gary.bisson@boundarydevices.com>
Tested-by: Denis Pynkin <denis.pynkin@collabora.com>
Lukasz Majewski [Thu, 26 Apr 2018 11:19:13 +0000 (13:19 +0200)]
dts: pinctrl: Provide IMX_PAD_SION definition for imx53 pinctrl
The SION pin must be set for proper operation of I2C when DM is enabled.
When legacy I2C is used, this bit is set implicitly in the u-boot code:
arch/arm/include/asm/arch-mx5/iomux-mx53.h:92:
MX53_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x368, 0x040, 4 |
IOMUX_CONFIG_SION, 0x820, 0, NO_PAD_CTRL),
The Linux kernel uses similar approach with:
arch/arm/boot/dts/imx53-tqma53.dtsi:182:
MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
After applying this patch it is possible to have the I2C working with DM
on imx53 devices:
MX53_PAD_KEY_ROW3__I2C2_SDA (0x1ee | IMX_PAD_SION)
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Lukasz Majewski [Thu, 26 Apr 2018 11:18:00 +0000 (13:18 +0200)]
dts: imx53: Add gpio and i2c nodes to imx53.dtsi file
Those DTS nodes has been ported from Linux kernel (v4.16)
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Sebastian Reichel [Mon, 23 Apr 2018 15:10:43 +0000 (17:10 +0200)]
ge: ppd: move CONFIG_ENV_IS_IN_MMC to defconfig
CONFIG_ENV_IS_IN_MMC must be declared in defconfig to properly
support "env save".
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Peter Robinson [Sat, 12 May 2018 08:48:03 +0000 (09:48 +0100)]
mx6: remove duplicated BOUNCE_BUFFER defines
The mx6_common.h file already defines BOUNCE_BUFFER so no need to
definit it again in specific configs.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
Peter Robinson [Sat, 12 May 2018 08:45:31 +0000 (09:45 +0100)]
mx6: Select CONFIG_MP with MX6_SMP
It makes sense to select the MP multi processor option at the same time we
select the other SMP options needed for SMP capable i.MX6 SoCs.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Peter Robinson [Sat, 12 May 2018 08:44:20 +0000 (09:44 +0100)]
mx7: remove empty ifndef statement
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Peter Robinson [Sat, 12 May 2018 08:43:10 +0000 (09:43 +0100)]
mx6 common: remove dangling comment
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Magnus Lilja [Fri, 11 May 2018 12:06:55 +0000 (14:06 +0200)]
mx31: Convert MX31_HCLK_FREQ and MX31_CLK32 to Kconfig.
Also remove the #ifdef's from clock.h since the Kconfig values defaults
the to old default values in clock.h.
Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Magnus Lilja [Fri, 11 May 2018 12:06:54 +0000 (14:06 +0200)]
mx31pdk: Convert CONFIG_MX31 flag to use Kconfig.
Move CONFIG_MX31 from mx31pdk.h to mx31pdk_defconfig and introduce
necessary Kconfig changes as well.
Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Ian Ray [Wed, 25 Apr 2018 14:57:04 +0000 (16:57 +0200)]
board: ge: bx50v3: remove redundant targets
This replaces TARGET_GE_B{4,6,8}50V3 with common TARGET_GE_BX50V3.
The boards are identified automatically at runtime.
Signed-off-by: Ian Ray <ian.ray@ge.com>
Signed-off-by: Nandor Han <nandor.han@ge.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Ian Ray [Wed, 25 Apr 2018 14:57:03 +0000 (16:57 +0200)]
board: ge: bx50v3: configure video arguments using VPD
Configure video arguments at run-time instead of at compile-time.
Signed-off-by: Ian Ray <ian.ray@ge.com>
Signed-off-by: Nandor Han <nandor.han@ge.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Ian Ray [Wed, 25 Apr 2018 14:57:02 +0000 (16:57 +0200)]
board: ge: bx50v3: use VPD instead of compile-time checks
B{46}50v3s have an internal LCD that needs to be configured,
in comparison with B850v3 which has only external displays.
Use VPD instead of `CONFIG_TARGET_GE_B{4,6,8}50V3' compile-time
checks to correct initialize video based on the monitor type.
Signed-off-by: Ian Ray <ian.ray@ge.com>
Signed-off-by: Nandor Han <nandor.han@ge.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Nandor Han [Wed, 25 Apr 2018 14:57:01 +0000 (16:57 +0200)]
board: ge: bx50v3: detect the monitor type by reading VPD earlier
Move the VPD reading earlier in order to establish the monitor
type as soon as possible.
The configuration of the specific environment variables needs to be
done later after the environment is configured.
Signed-off-by: Nandor Han <nandor.han@ge.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Ian Ray [Wed, 25 Apr 2018 14:57:00 +0000 (16:57 +0200)]
board: ge: bx50v3: fix display support for b{46}50v3
Enable Video PLL to fix non-working display support for Bx50v3
internal displays.
Signed-off-by: Ian Ray <ian.ray@ge.com>
Signed-off-by: Nandor Han <nandor.han@ge.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Nandor Han [Wed, 25 Apr 2018 14:56:59 +0000 (16:56 +0200)]
board: ge: bx50v3: unify two switch statements
Simplify process_vpd() by unifying the switch statements handling
product specific configurations.
Signed-off-by: Nandor Han <nandor.han@ge.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Ian Ray [Wed, 25 Apr 2018 14:56:58 +0000 (16:56 +0200)]
board: ge: bx50v3: rename detect_baseboard function
The detect_baseboard() function actually determines whether there is an
internal LCD panel or not. Rename for clarity.
Signed-off-by: Ian Ray <ian.ray@ge.com>
Signed-off-by: Nandor Han <nandor.han@ge.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Ian Ray [Mon, 23 Apr 2018 15:09:53 +0000 (17:09 +0200)]
board: ge: bx50v3: add winbond SPI NOR support
Add winbond SPI NOR support, which is being used by newer hardware.
Signed-off-by: Ian Ray <ian.ray@ge.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Chris Packham [Wed, 16 May 2018 08:31:43 +0000 (20:31 +1200)]
ARM: re-enable MVGBE for edminiv2
This was unintentionally disabled when moving MVGBE to Kconfig.
Fixes: commit
ed52ea507f12 ("net: add Kconfig for MVGBE")
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Bryan O'Donoghue [Mon, 30 Apr 2018 14:56:10 +0000 (15:56 +0100)]
usb: composite convert __set_bit to generic_set_bit
Compiling the f_mass_storage driver for an x86 target results in a
compilation error as set_bit and clear_bit are provided by bitops.h
To address that situation we discussed on the list moving to
genetic_set_bit() instead.
Doing a quick grep for similar situations in drivers/usb shows that the
composite device is using __set_bit().
This patch switches over to generic_set_bit to maintain consistency between
the two gadget drivers.
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Marek Vasut <marex@denx.de>
Bryan O'Donoghue [Mon, 30 Apr 2018 14:56:09 +0000 (15:56 +0100)]
usb: f_mass_storage: Fix set_bit and clear_bit usage
Compiling the f_mass_storage driver for an x86 target results in a
compilation error as set_bit and clear_bit are provided by bitops.h
Looking at the provenance of the current u-boot code and the git change
history in the kernel, it looks like we have a local copy of set_bit and
clear_bit as a hold-over from porting the Linux driver into u-boot.
These days __set_bit and __clear_bit are optionally provided by an arch and
can be used as inputs to generic_bit_set and generic_bit_clear.
This patch switches over to generic_set_bit and generic_clear_bit to
accommodate.
Tested on i.MX WaRP7 and Intel Edison
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Marek Vasut <marex@denx.de>
Bryan O'Donoghue [Mon, 30 Apr 2018 14:56:08 +0000 (15:56 +0100)]
nds32: Define PLATFORM__CLEAR_BIT for generic_clear_bit()
nds2 bitops.h provides a __clear_bit() but does not define
PLATFORM__CLEAR_BIT as a result generic_clear_bit() is used instead of the
architecturally provided __clear_bit().
This patch defines PLATFORM__CLEAR_BIT which means that __clear_bit() in
nds32 bitops.h will be called whenever generic_clear_bit() is called - as
opposed to the default cross-platform generic_clear_bit().
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Macpaul Lin <macpaul@andestech.com>
Bryan O'Donoghue [Mon, 30 Apr 2018 14:56:07 +0000 (15:56 +0100)]
nds32: Define PLATFORM__SET_BIT for generic_set_bit()
nds32 bitops.h provides a __set_bit() but does not define PLATFORM__SET_BIT
as a result generic_set_bit() is used instead of the architecturally
provided __set_bit().
This patch defines PLATFORM__SET_BIT which means that __set_bit() in nds32
bitops.h will be called whenever generic_set_bit() is called - as opposed
to the default cross-platform generic_set_bit().
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Macpaul Lin <macpaul@andestech.com>
Bryan O'Donoghue [Mon, 30 Apr 2018 14:56:06 +0000 (15:56 +0100)]
nios2: Define PLATFORM__CLEAR_BIT for generic_clear_bit()
nios2 bitops.h provides a __clear_bit() but does not define
PLATFORM__CLEAR_BIT as a result generic_clear_bit() is used instead of the
architecturally provided __clear_bit().
This patch defines PLATFORM__CLEAR_BIT which means that __clear_bit() in
nios2 bitops.h will be called whenever generic_clear_bit() is called - as
opposed to the default cross-platform generic_clear_bit().
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Thomas Chou <thomas@wytron.com.tw>
Bryan O'Donoghue [Mon, 30 Apr 2018 14:56:05 +0000 (15:56 +0100)]
nios2: Define PLATFORM__SET_BIT for generic_set_bit()
nios2 bitops.h provides a __set_bit() but does not define PLATFORM__SET_BIT
as a result generic_set_bit() is used instead of the architecturally
provided __set_bit().
This patch defines PLATFORM__SET_BIT which means that __set_bit() in nios2
bitops.h will be called whenever generic_set_bit() is called - as opposed
to the default cross-platform generic_set_bit().
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Thomas Chou <thomas@wytron.com.tw>
Bryan O'Donoghue [Mon, 30 Apr 2018 14:56:04 +0000 (15:56 +0100)]
riscv: Define PLATFORM__CLEAR_BIT for generic_clear_bit()
riscv bitops.h provides a __clear_bit() but does not define
PLATFORM__CLEAR_BIT as a result generic_clear_bit() is used instead of the
architecturally provided __clear_bit().
This patch defines PLATFORM__CLEAR_BIT which means that __clear_bit() in
riscv bitops.h will be called whenever generic_clear_bit() is called - as
opposed to the default cross-platform generic_clear_bit().
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <green.hu@gmail.com>
Bryan O'Donoghue [Mon, 30 Apr 2018 14:56:03 +0000 (15:56 +0100)]
riscv: Define PLATFORM__SET_BIT for generic_set_bit()
riscv bitops.h provides a __set_bit() but does not define PLATFORM__SET_BIT
as a result generic_set_bit() is used instead of the architecturally
provided __set_bit().
This patch defines PLATFORM__SET_BIT which means that __set_bit() in x86
bitops.h will be called whenever generic_set_bit() is called - as opposed
to the default cross-platform generic_set_bit().
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <green.hu@gmail.com>
Bryan O'Donoghue [Mon, 30 Apr 2018 14:56:02 +0000 (15:56 +0100)]
x86: Define PLATFORM__SET_BIT for generic_set_bit()
x86 bitops.h provides a __set_bit() but does not define PLATFORM__SET_BIT
as a result generic_set_bit() is used instead of the architecturally
provided __set_bit().
This patch defines PLATFORM__SET_BIT which means that __set_bit() in x86
bitops.h will be called whenever generic_set_bit() is called - as opposed
to the default cross-platform generic_set_bit().
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Chris Packham [Tue, 15 May 2018 01:31:11 +0000 (13:31 +1200)]
ARM: mvebu: a38x: Add missing SPDX license identfier
mv_ddr_build_message.c is generated in Marvell's standalone mv_ddr code.
When imported into u-boot we need to add the appropriate SPDX tag and
re-format it slightly.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Tom Rini [Tue, 15 May 2018 12:29:24 +0000 (08:29 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-video
Vasily Khoruzhick [Mon, 14 May 2018 15:16:21 +0000 (08:16 -0700)]
dts: sunxi: add PWM node for sun50i
Add PWM definition to sun50i-a64.dtsi
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Vasily Khoruzhick [Mon, 14 May 2018 15:16:20 +0000 (08:16 -0700)]
pwm: sunxi: add support for PWM found on Allwinner A64
This commit adds basic support for PWM found on Allwinner A64.
It can be used for pwm_backlight driver (e.g. for Pinebook)
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Vasily Khoruzhick [Mon, 14 May 2018 20:49:53 +0000 (13:49 -0700)]
video: dw_hdmi: fix HSYNC and VSYNC polarity settings
Currently dw_hdmi configures HSYNC polarity using VSYNC setting from
EDID and vice versa. Fix it, since it breaks displays where HSYNC
and VSYNC polarity differs
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Vasily Khoruzhick [Mon, 14 May 2018 20:49:52 +0000 (13:49 -0700)]
sunxi: video: HDMI: use correct bits for HSYNC and VSYNC polarity.
HSYNC is bit 8, and VSYNC is bit 9.
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Ramon Fried [Mon, 14 May 2018 12:02:30 +0000 (15:02 +0300)]
mmc: sdhci: Check that ops are defined
The check is necessary to avoid NULL pointer dereference.
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Chris Packham [Thu, 3 May 2018 11:00:35 +0000 (23:00 +1200)]
net: add Kconfig for MVGBE
Add Kconfig for MVGBE and update boards to select this.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Chris Packham [Thu, 3 May 2018 11:00:34 +0000 (23:00 +1200)]
net: mvgbe: remove CONFIG_DOVE
Nothing defines CONFIG_DOVE so remove the code that uses it.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Chris Packham [Thu, 3 May 2018 08:19:03 +0000 (20:19 +1200)]
net: bootp: Fix compile error processing ntpserver option
When the following configuration is set
# CONFIG_CMD_DHCP is not set
CONFIG_CMD_BOOTP=y
CONFIG_BOOTP_NTPSERVER=y
The following compile error is observed
error: used struct type value where scalar is required
if (net_ntp_server)
^~~~~~~~~~~~~~
Resolve this by checking net_ntp_server.s_addr instead.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Chris Packham [Thu, 3 May 2018 08:19:02 +0000 (20:19 +1200)]
net: Add Kconfig option for BOOTP_NTPSERVER
Add a Kconfig option for BOOTP_NTPSERVER to enable the DHCP/BOOTP option
to configure the sntp server address.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Mario Six [Fri, 27 Apr 2018 12:52:21 +0000 (14:52 +0200)]
treewide: Move CONFIG_PHY_MARVELL to Kconfig
The CONFIG_PHY_MARVELL has already been migrated to Kconfig (some boards
already had it in their Kconfig), but had not been moved for older
boards.
Move it to the defconfigs for all boards.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tom Rini [Mon, 14 May 2018 22:13:59 +0000 (18:13 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-rockchip
Jonathan Gray [Tue, 8 May 2018 09:49:05 +0000 (19:49 +1000)]
rockchip: clk: rk3288: handle clk_enable requests for GMAC
Since
b0ba1e7e9d9b9441a18048ec67a3b3100c096975
(rockchip: clk: rk3288: add clk_enable function and support USB HOST0/HSIC)
Ethernet no longer probes on RK3288.
Add no-ops for GMAC clocks observed to be requested which match the
clk_enable cases in RK3368 and RK3399.
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Cc: Wadim Egorov <w.egorov@phytec.de>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Jonathan Gray [Tue, 8 May 2018 10:43:01 +0000 (20:43 +1000)]
rockchip: set SYS_NS16550_MEM32 for all SoCs
Add back part of patch send out as
'rockchip: enable SYS_NS16550 for all SoCs by default' that seems to have
gotten lost when it got merged to set SYS_NS16550_MEM32.
Allows serial output to work on tinker-rk3288 again after
c3c0331db1fb7b1f4ff41e144fc04353b37c785c.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tom Rini [Mon, 14 May 2018 12:52:48 +0000 (08:52 -0400)]
Merge git://git.denx.de/u-boot-marvell
Marek Behún [Fri, 11 May 2018 08:03:39 +0000 (10:03 +0200)]
phy: marvell: a3700: Fix compatible string for ehci
The DTS file for armada-37xx uses the string "marvell,armada3700-ehci",
but the code searched for "marvell,armada-3700-ehci".
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
Chris Packham [Thu, 10 May 2018 01:28:31 +0000 (13:28 +1200)]
ARM: mvebu: a38x: use non-zero size for ddr scrubbing
Make ddr3_calc_mem_cs_size() global scope and use it in
ddr3_new_tip_ecc_scrub to correctly initialize all of DDR memory.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Chris Packham [Thu, 10 May 2018 01:28:30 +0000 (13:28 +1200)]
ARM: mvebu: a38x: restore support for setting timing
This restores support for configuring the timing mode based on the
ddr_topology. This was originally implemented in commit
90bcc3d38d2b
("driver/ddr: Add support for setting timing in hws_topology_map") but
was removed as part of the upstream sync.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Chris Packham [Thu, 10 May 2018 01:28:29 +0000 (13:28 +1200)]
ARM: mvebu: a38x: sync ddr training code with upstream
This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-17.10 branch
of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.
The upstream code is incorporated omitting the ddr4 and apn806 and
folding the nested a38x directory up one level. After that a
semi-automated step is used to drop unused features with unifdef
find drivers/ddr/marvell/a38x/ -name '*.[ch]' | \
xargs unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 \
-UCONFIG_APN806 -UCONFIG_MC_STATIC \
-UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \
-UCONFIG_64BIT
INTER_REGS_BASE is updated to be defined as SOC_REGS_PHY_BASE.
Some now empty files are removed and the ternary license is replaced
with a SPDX GPL-2.0+ identifier.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Chris Packham [Thu, 10 May 2018 01:28:28 +0000 (13:28 +1200)]
ARM: mvebu: a38x: remove some unused code
No in-tree code defines SUPPORT_STATIC_DUNIT_CONFIG or
STATIC_ALGO_SUPPORT. Remove ddr3_a38x_mc_static.h and use unifdef to
remove unused sections in the rest of the ddr/marvell/a38x code.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Chris Packham [Thu, 10 May 2018 01:28:27 +0000 (13:28 +1200)]
ARM: mvebu: a38x: move sys_env_device_rev_get
Move sys_env_device_rev_get() from the ddr training code to
sys_env_lib.c (which currently resides with the serdes code). This
brings sys_env_device_rev_get() into line with sys_env_device_id_get()
and sys_env_model_get().
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Chris Packham [Thu, 10 May 2018 01:28:26 +0000 (13:28 +1200)]
ARM: mvebu: a38x: move definition of PEX_CFG_DIRECT_ACCESS
PEX_CFG_DIRECT_ACCESS was defined in ddr3_hws_hw_training_def.h despite
only being used in the serdes code. Move this definition to ctrl_pex.h
where all the other PEX defines are. Also remove the duplicate
definition of PEX_DEVICE_AND_VENDOR_ID which is already defined in
ctrl_pex.h.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:31 +0000 (17:21 +0200)]
arm64: mvebu: Add basic support for the Turris Mox board
This adds basic support for the Turris Mox board from CZ.NIC, which is
currently being crowdfunded on Indiegogo.
Turris Mox is as modular router based on the Armada 3720 SOC (same as
EspressoBin).
The basic module can be extended by different modules. The device tree
binary for the kernel can be dependent on which modules are connected,
and in what order. Because of this, the board specific code creates
in U-Boot a variable called module_topology, which carries this
information.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:30 +0000 (17:21 +0200)]
watchdog: Add support for Armada 37xx CPU watchdog
This adds support for the CPU watchdog found on Marvell Armada 37xx
SoCs.
There are 4 counters which can be set as CPU watchdog counters.
This driver uses the second counter (ID 1, counting from 0)
(Marvell's Linux also uses second counter by default).
In the future it could be adapted to use other counters, with
definition in the device tree.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:29 +0000 (17:21 +0200)]
net: mvneta: Fix fault when wrong device tree
The driver does not check id phy_connect failed (for example on wrong
property name in device tree). In such a case a fault occurs and the
CPU is restarted.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:28 +0000 (17:21 +0200)]
phy: marvell: core: Cosmetic fixes
Move the reg_set* functions into comphy.h as static inline functions.
Change return type of get_*_string to const char *.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:27 +0000 (17:21 +0200)]
clk: armada-37xx: Support soc_clk_dump
Add support for the clk dump command on Armada 37xx.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:26 +0000 (17:21 +0200)]
spi: mvebu_a3700_spi: Use Armada 37xx clk driver for SPI clock frequency
Since now we have driver for clocks on Armada 37xx, use it to determine
SQF clock frequency for the SPI driver.
Also change the default config files for Armada 37xx devices so that
the clock driver is enabled by default, otherwise the SPI driver cannot
be enabled.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:25 +0000 (17:21 +0200)]
driver: clk: Add support for clocks on Armada 37xx
The drivers are based on Linux driver by Gregory Clement.
The TBG clocks support only the .get_rate method.
- since setting rate is not supported, the driver computes the rates
when probing and so subsequent calls to the .get_rate method do not
read the corresponding registers again
The peripheral clocks support methods .get_rate, .enable and .disable.
- the .set_parent method theoretically could be supported on some clocks
(the parent would have to be one of the TBG clocks)
- the .set_rate method would have to try all the divider values to find
the best approximation of a given rate, and it doesn't seem like
this should be needed in U-Boot, therefore not implemented
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:24 +0000 (17:21 +0200)]
phy: marvell: a3700: Save/restore selector reg in SGMII init
In SGMII initialization PIN_PIPE_SEL has to be zero when resetting
the PHY. Since comphy_mux already set the selector register to
correct values, we have to store it's value before setting it to 0
and restore it after SGMII init.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:23 +0000 (17:21 +0200)]
phy: marvell: a3700: Use comphy_mux on Armada 37xx.
Lane 0 supports SGMII1 and USB3.
Lane 1 supports SGMII0 and PEX0.
Lane 2 supports SATA0 and USB3.
This is needed for Armada 37xx.
This introduces new device tree bindings. AFAIK there is currently no
driver for Armada 37xx comphy in Linux. When such a driver will be
pushed into Linux, this will need to be rewritten accordingly.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:22 +0000 (17:21 +0200)]
phy: marvell: a3700: Fix SGMII cfg and stat register addresses
The register addresses on lanes 0 and 1 are switched, first comes 1 and
then 0.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:21 +0000 (17:21 +0200)]
phy: marvell: mux: Support nontrivial node order in selector register
Currently comphy_mux supports only trivial order of nodes in pin
selector register, that is lane N on position N*bitcount.
Add support for nontrivial order, with map stored in device tree
property mux-lane-order.
This is needed for Armada 37xx.
As far as I know, there is no driver for Armada 37xx comphy in the
kernel. When such a driver comes, this will need to be rewritten to
support the device tree bindings from the kernel.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
zachary [Tue, 24 Apr 2018 15:21:20 +0000 (17:21 +0200)]
phy: marvell: a3700: revise the USB3 comphy setting during power on
This commit is based on commit
d9899826 by
zachary <zhangzg@marvell.com>
from u-boot-marvell, see
github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/
d9899826
- According to design specification, the transmitter should be set to high
impedence mode during electrical idle. Thus transmitter should detect RX
at high impedence mode also, and delay is needed to accommodate high
impedence off latency. Otherwise the USB3 will have detection issue that
most of the time the USB3 device can not be detected at all, or be
detected as USB2 device sometimes.
Modified registers: RD005C302h (R181h) (0051h) Lane Configuration 1
Bit 6: set to 1 to let Tx detect Rx at HiZ mode
Bit [3:4]: set to 2 to be delayed by 2 clock cycles
Bit 0: set to 1 to set transmitter to high impedance mode during idle.
- USB3 De-emphasize level of -3.5dB is mandatory, but USB3 MAC selects 0x2
(emphasize disabled) in the MAC_PHY_TXDEEMPH [1:0], while it is supposed
to select 0x1(3.5dB emphasize). Thus need to override what comes from
the MAC(by setting register 0x1c2 bit2 to 0x1) and to configure the
overridded values of MAC_PHY_TXDEEMPH [1:0] to 0x1(bit15 of register
0x181 and bit0 of register 0x180).
- According to USB3 application note, need to update below comphy
registers:
Set max speed generation to USB3.0 5Gbps(set RD005C04Ah bit[11:10] to 1)
Set capacitor value to 0xF(set RF005C224 bit[3:0] to 0xF)
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:19 +0000 (17:21 +0200)]
phy: marvell: a3700: Set USB3 RX wait depending on ref clock
According to specification, CFG_PM_RXDLOZ_WAIT should be set to 0x7
when reference clock is at 25 MHz. The specification (at least the
version I have) does not mentoin the setting for 40 MHz reference
clock, but Marvell's U-Boot sets 0xC in that case.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:18 +0000 (17:21 +0200)]
phy: marvell: a3700: Access USB3 register indirectly on lane 2
When USB3 is on comphy lane 2 on the Armada 37xx, the registers
have to be accessed indirectly via SATA indirect access.
This is the case of the Turris Mox board from CZ.NIC.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:17 +0000 (17:21 +0200)]
phy: marvell: a3700: Use reg_set_indirect istead of 2 reg_sets
Create a special function for indirect register setting,
reg_set_indirect, and use it instead of the two calls to reg_set.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:16 +0000 (17:21 +0200)]
phy: marvell: a3700: Use (!ret) instead of (ret == 0)
In U-Boot it is usually written this way.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:15 +0000 (17:21 +0200)]
phy: marvell: a3700: Use same timeout for all register polling
The timeout is set to PLL_LOCK_TIMEOUT in every call to
comphy_poll_reg. Remove this parameter from the function.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:14 +0000 (17:21 +0200)]
phy: marvell: a3700: Don't create functional macro for each register
Currently there is for each register special functional macro, ie:
LANE_CFG1_ADDR(u)
GLOB_CLK_SRC_LO_ADDR(u)
...
where can be either PCIE or USB3.
Change this to one function PHY_ADDR(unit, addr). The code becomes:
phy_addr(PCIE, LANE_CFG1)
phy_addr(PCIE, GLOB_CLK_SRC_LO)
...
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:13 +0000 (17:21 +0200)]
phy: marvell: a3700: Use reg_set16 instead of phy_write16
The macro phy_write16 is not used by the rest of the code,
phy_read16 is not used at all.
We also change the macro SGMIIPHY_ADDR to a static inline function.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Tue, 24 Apr 2018 15:21:12 +0000 (17:21 +0200)]
phy: marvell: a3700: Change return type of macro MVEBU_REG
All the calls to reg_set and friends have to cast the first argument
to void __iomem *. Lets change the return type of the MVEBU_REG macro
instead.
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
Marek Vasut [Sat, 14 Apr 2018 22:37:11 +0000 (00:37 +0200)]
mmc: Improve tinification
Drop all the extra content from the MMC core, so that tiny MMC support
is really tiny, no fancy anything. That means the tiny MMC support does
only 1-bit transfers at default speed settings. Moreover, this patch
drops duplicate instance of struct mmc mmc_static, which wasted about
360 bytes. Furthermore, since MMC tiny supports only one controller
at all times, get rid of mallocating the ext csd backup and replace
it with static array. All in all, this patch saves ~4 kiB of bloat
from the MMC core, which on platforms with severe limitations can be
beneficial.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
[trini: Fixup checkpatch.pl style warnings]
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Fri, 11 May 2018 19:22:36 +0000 (15:22 -0400)]
Merge git://git.denx.de/u-boot-tegra
Tom Rini [Fri, 11 May 2018 18:54:57 +0000 (14:54 -0400)]
SPDX: Correct SPDX tags from recent xilinx merge
Correct the SPDX tag format.
Fixes:
3b52847a451a ("Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblaze")
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Fri, 11 May 2018 15:45:28 +0000 (11:45 -0400)]
Merge tag 'xilinx-for-v2018.07' of git://denx.de/git/u-boot-microblaze
Xilinx changes for v2018.07
microblaze:
- Align defconfig
zynq:
- Rework fpga initialization and cpuinfo handling
zynqmp:
- Add ZynqMP R5 support
- Wire and enable watchdog on zcu100-revC
- Setup MMU map for DDR at run time
- Show board info based on DT and cleanup IDENT_STRING
zynqmp tools:
- Add read partition support
- Add initial support for Xilinx bif format for boot.bin generation
mmc:
- Fix get_timer usage on 64bit cpus
- Add support for SD3.0 UHS mode
nand-zynq:
- Add support for 16bit buswidth
- Use address cycles from onfi params
scsi:
- convert ceva sata to UCLASS_AHCI
timer:
- Add Cadence TTC for ZynqMP r5
watchdog:
- Minor cadence driver cleanup
Tom Rini [Fri, 11 May 2018 11:09:21 +0000 (07:09 -0400)]
Merge git://git.denx.de/u-boot-fsl-qoriq