Brian Paul [Fri, 12 Jan 2018 17:21:48 +0000 (10:21 -0700)]
vbo: rename some functions in vbo_save_api.c
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Brian Paul [Fri, 12 Jan 2018 17:16:40 +0000 (10:16 -0700)]
vbo: rename some functions in vbo_save_draw.c
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Brian Paul [Fri, 12 Jan 2018 16:57:29 +0000 (09:57 -0700)]
vbo: add comment that vbo_save_vertex_list::buffer_offset is in bytes
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Brian Paul [Fri, 12 Jan 2018 16:56:42 +0000 (09:56 -0700)]
vbo: minor code simplification in _save_compile_vertex_list()
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Brian Paul [Fri, 12 Jan 2018 16:52:05 +0000 (09:52 -0700)]
vbo: rename prim to prims
Using a plural name makes it easier to see that this is an array and
not a pointer to a single object.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Brian Paul [Fri, 12 Jan 2018 16:48:17 +0000 (09:48 -0700)]
vbo: removed unused ctx parameter for alloc_prim_store()
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Brian Paul [Fri, 12 Jan 2018 16:30:42 +0000 (09:30 -0700)]
vbo: rename vbo_save_context::buffer to buffer_map
And move the field and improve comments.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Brian Paul [Fri, 12 Jan 2018 16:28:37 +0000 (09:28 -0700)]
vbo: remove unused vbo_save_context::count field
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Brian Paul [Fri, 12 Jan 2018 16:27:16 +0000 (09:27 -0700)]
vbo: s/GLuint/GLbitfield/ for vbo_save_context::replay_flags
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Brian Paul [Fri, 12 Jan 2018 16:23:37 +0000 (09:23 -0700)]
vbo: rename vbo_save_vertex_list::count to vertex_count
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Brian Paul [Fri, 12 Jan 2018 16:18:32 +0000 (09:18 -0700)]
vbo: rename vbo_save_vertex_store::buffer to buffer_map
To match other parts of the VBO code and make things easier to understand.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Brian Paul [Fri, 12 Jan 2018 16:12:35 +0000 (09:12 -0700)]
vbo: rename vbo_save_primitive_store::buffer to prims
A little easier to understand.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Brian Paul [Fri, 12 Jan 2018 16:07:05 +0000 (09:07 -0700)]
vbo: whitespace fixes in vbo_save.h
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Brian Paul [Thu, 11 Jan 2018 23:18:38 +0000 (16:18 -0700)]
vbo: whitespace fixes in vbo_save_draw.c
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Brian Paul [Thu, 11 Jan 2018 18:17:45 +0000 (11:17 -0700)]
svga: add num-commands-per-draw HUD query
This query shows the ratio of total commands vs. drawing commands sent
to the vgpu device. This gives some idea of how many state changes
are sent per draw call. The closer the ratio is to 1.0, the better.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Brian Paul [Thu, 11 Jan 2018 18:11:04 +0000 (11:11 -0700)]
gallium/hud: Fix support for PIPE_DRIVER_QUERY_TYPE_FLOAT
Evidently, nobody has used PIPE_DRIVER_QUERY_TYPE_FLOAT up to this
point. Adding a driver query of this type which returns the query
value in pipe_query_result::f resulted in garbage output in the HUD.
The problem is the pipe_query_result::f field was being accessed as
through the u64 field and being added to the query_info::results_cumulative
field. This patch checks for PIPE_DRIVER_QUERY_TYPE_FLOAT in a few
places and scales the float by 1000 before converting to uint64_t.
Also, add some comments to explain the query_info::result_index field.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Brian Paul [Thu, 11 Jan 2018 16:57:50 +0000 (09:57 -0700)]
gallium/hud: remove uint64_t casts in sensor query_sti_load() function
The hud_graph_add_value() function takes a double value, so just pass
the current/critical values as-is since they're doubles.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Brian Paul [Thu, 11 Jan 2018 16:56:12 +0000 (09:56 -0700)]
gallium/hud: compute cpu load, percent with doubles
The hud_graph_add_value() function takes a double precision value,
so compute it that way.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Brian Paul [Thu, 11 Jan 2018 16:50:42 +0000 (09:50 -0700)]
gallium/hud: s/unsigned/enum pipe_query_type/
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Jon Turney [Mon, 15 Jan 2018 19:39:46 +0000 (19:39 +0000)]
meson: Set with_dri from with_gallium when DRI glx is explicitly configured
Set with_dri from with_gallium when DRI GLX is explicitly configured, as
well as when DRI GLX is chosen automatically.
Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
George Kyriazis [Wed, 10 Jan 2018 19:54:26 +0000 (13:54 -0600)]
meson: add llvm dependency for swr build
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Leo Liu [Fri, 12 Jan 2018 15:23:35 +0000 (10:23 -0500)]
st/va: add break for MPEG4 data buffer handling case
Signed-off-by: Leo Liu <leo.liu@amd.com>
Leo Liu [Fri, 12 Jan 2018 15:20:06 +0000 (10:20 -0500)]
st/va: remove TODO line for JPEG data buffer handling
Nothing to do
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Rhys Kidd [Wed, 17 Jan 2018 05:48:07 +0000 (00:48 -0500)]
i915: No longer rely on compatability define in intel_bufmgr.h
Symbol rename from dri_* to drm_intel_* introduced a number of compatability
defines within intel_bufmgr.h.
Replace the old function with the new function, consistent with the balance
of this file.
Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Fri, 12 Jan 2018 01:38:13 +0000 (12:38 +1100)]
radeonsi: bump glsl version to 450 for nir backend
We still have more work to do but piglit results are looking
pretty good.
At GLSL 1.50 we have 30647/31118 piglit tests passing.
At GLSL 4.50 we have 37927/38551 piglit tests passing.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Wed, 10 Jan 2018 02:52:29 +0000 (13:52 +1100)]
radeonsi/nir: add some missing tcs bits to the nir scan pass
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Tue, 9 Jan 2018 02:50:08 +0000 (13:50 +1100)]
ac: rework load_tcs_{inputs,outputs}
This shares more code and calls the new shared load_tess_varyings()
abi so that the radeonsi nir path now supports tcs output loads.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Tue, 9 Jan 2018 01:12:45 +0000 (12:12 +1100)]
ac/radeonsi: add tcs load outputs support
The code to load outputs is essentially the same as load inputs
so we make the interface more generic to maximise code sharing.
We will make use of the new support in the following patch.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Mon, 27 Nov 2017 06:01:01 +0000 (17:01 +1100)]
st/glsl_to_tgsi: add ARB_get_program_binary support using TGSI
This resolves a game bug in Dead Island. The game doesn't properly
handle ARB_get_program_binary with 0 supported formats, and ends up
crashing.
This will enable ARB_get_program_binary binary support for any
driver that currently enables the on-disk shader cache.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85564
Timothy Arceri [Tue, 28 Nov 2017 11:28:31 +0000 (22:28 +1100)]
st/glsl_to_tgsi: add st_get_program_binary_driver_sha1() helper
This will be used by ARB_get_program_binary.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Tue, 28 Nov 2017 05:00:50 +0000 (16:00 +1100)]
st/glsl_to_tgsi: add (de)serialise program helpers
These will be shared between the on-disk shader cache and
ARB_get_program_binary.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Tue, 28 Nov 2017 11:02:17 +0000 (22:02 +1100)]
st/glsl_to_tgsi: stop passing pipe_shader_state to st_store_tgsi_in_disk_cache()
We can instead just get this from st_*_program.
V2: store tokens to to st_compute_program before attempting to
write to cache (fixes crash).
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Tue, 28 Nov 2017 10:43:12 +0000 (21:43 +1100)]
st/glsl_to_tgsi: store num_tgsi_tokens in st_*_program
We will need this for ARB_get_program_binary binary support.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Michel Dänzer [Wed, 3 Jan 2018 11:21:56 +0000 (12:21 +0100)]
loader/dri3: Try to make sure we only process our own NotifyMSC events
We were using a sequence counter value to wait for a specific NotifyMSC
event. However, we can receive events from other clients as well, which
may already be using higher sequence numbers than us. In that case, we
could stop processing after an event from another client, which could
have been received significantly earlier. This would have multiple
undesirable effects:
* The computed MSC and UST values would be lower than they should be
* We could leave a growing number of NotifyMSC events from ourselves and
other clients in XCB's special event queue
I ran into this with Firefox and Thunderbird, whose VSync threads both
seem to use the same window. The result was sluggish screen updates and
growing memory consumption in one of them.
Fix this by checking the XCB sequence number and MSC value of NotifyMSC
events, instead of using our own sequence number.
v2:
* Use the Present event ID for the sequence parameter of the
PresentNotifyMSC request, as another safeguard against processing
events from other clients
* Rebase on drawable mutex changes
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> # v1
Bas Nieuwenhuizen [Tue, 9 Jan 2018 02:35:53 +0000 (03:35 +0100)]
radv: Implement VK_EXT_debug_report.
This is not hooked up to any messages yet, but useful for e.g.
renderdoc if you add some messages during development.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bas Nieuwenhuizen [Tue, 9 Jan 2018 02:22:56 +0000 (03:22 +0100)]
vulkan: move anv VK_EXT_debug_report implementation to common code.
For also using it in radv. I moved the remaining stubs back to
anv_device.c as they were just trivial.
This does not move the vk_errorf/anv_perf_warn or the object
type macros, as those depend on anv types and logging.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Timothy Arceri [Thu, 11 Jan 2018 01:47:31 +0000 (12:47 +1100)]
st/glsl_to_nir: disable io lowering to temps for tess
Lowering these to temps makes a big mess, and results in some
piglit test failures. Also the radeonsi backend (the only backend
to support tess) has support for indirects so there is no need to
lower them anyway.
Fixes the following piglit tests on radeonsi:
tests/spec/arb_tessellation_shader/execution/variable-indexing/tes-input-array-vec3-index-rd.shader_test
tests/spec/arb_tessellation_shader/execution/variable-indexing/tes-input-array-vec4-index-rd.shader_test
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Jason Ekstrand [Sat, 9 Dec 2017 06:21:09 +0000 (22:21 -0800)]
i965: Enable CCS_E sampling of sRGB textures as UNORM
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Tue, 31 Oct 2017 23:29:22 +0000 (16:29 -0700)]
i965/draw: Do resolves properly for textures used by TXF
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Mon, 18 Dec 2017 03:42:09 +0000 (19:42 -0800)]
i965/miptree: Refactor CCS_E and CCS_D cases in render_aux_usage
This commit unifies the CCS_E and CCS_D cases. This should fix a couple
of subtle issues. One is that when you use INTEL_DEBUG=norbc to disable
CCS_E, we don't get the sRGB blending workaround. By unifying the code,
we give CCS_D that workaround as well.
The second issue fixed by this refactor is that the blending workaround
was appears to be enabled on all gens but really only applies on gen9.
Due to a happy accident in the way code was laid out, it was only
getting enabled on gen9: gen8 and earlier don't support non-zero-one
clear colors, and gen10 supports sRGB for CCS_E so it got caught in the
format_ccs_e_compat_with_miptree case. This refactor moves it above the
format_ccs_e_compat_with_miptree case so it's an explicit early exit and
makes it explicitly only on gen9.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "17.3" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Tue, 5 Dec 2017 22:41:48 +0000 (14:41 -0800)]
Re-enable regular fast-clears (CCS_D) on gen9+
This reverts commit
ee57b15ec764736e2d5360beaef9fb2045ed0f68, "i965:
Disable regular fast-clears (CCS_D) on gen9+". How taht we've fixed the
issue with too many different aux usages in the render cache, it should
be safe to re-enable CCS_D for sRGB.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104163
Tested-by: Eero Tamminen <eero.t.tamminen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "17.3" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Thu, 14 Dec 2017 01:25:26 +0000 (17:25 -0800)]
i965: Track format and aux usage in the render cache
This lets us perform render cache flushes whenever a surface goes from
being used with one aux+format to a different aux+format.
This is the "proper" fix for https://bugs.freedesktop.org/102435.
ee57b15ec764736e2d5360beaef9fb2045ed0f68 which was really just a partial
revert of
3e57e9494c2279580ad6a83ab8c065d01e7e634e was just a hack to
get rid of a hang in a bunch of Valve games. This solves the actual
problem responsible for the hang and lets us enable CCS_E once again.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102435
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "17.3" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Thu, 14 Dec 2017 01:23:41 +0000 (17:23 -0800)]
i965: Call brw_cache_flush_for_render in predraw_resolve_framebuffer
This makes sure we flush things out of other caches prior to using a
surface through the render cache. Currently, this is a no-op because GL
won't let you bind anything other than a color surface as color so it
should never end up in the depth cache. However, this does complete the
flush/add_bo pair for regular drawing which will be required for the
next commit.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "17.3" <mesa-stable@lists.freedesktop.org>
Francisco Jerez [Fri, 17 Nov 2017 22:07:21 +0000 (14:07 -0800)]
i965/gen6-7/sol: Bump primitive counter BO size.
Improves performance of SynMark2 OglGSCloth by a further 9.65%±0.59%
due to the reduction in overwraps of the primitive count buffer that
lead to a CPU stall on previous rendering. Cummulative performance
improvement from the series 81.50% ±0.96% (data gathered on VLV).
Tested-By: Eero Tamminen <eero.t.tamminen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Thu, 16 Nov 2017 22:27:41 +0000 (14:27 -0800)]
i965/gen6-7/sol: Keep independent counters for the current and previous begin/end block.
This allows us to aggregate the primitive counts of a completed
transform feedback begin/end block lazily, which in the most typical
case (where glDrawTransformFeedback is not used) will allow us to
avoid aggregating the primitive counters on the CPU altogether,
preventing a stall on previous rendering during
glBeginTransformFeedback(), which dramatically improves performance of
applications that rely heavily on transform feedback.
Improves performance of SynMark2 OglGSCloth by 65.52% ±0.25% (data
gathered on VLV).
Tested-By: Eero Tamminen <eero.t.tamminen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Fri, 17 Nov 2017 22:06:04 +0000 (14:06 -0800)]
i965/gen6-7/sol: Restructure primitive counter into a separate type.
A primitive counter encapsulates a scalar aggregating counter for each
vertex stream along with a section within the primitive tally buffer
which hasn't been read out yet. Defining this as a separate type will
allow us to keep multiple counter objects around for the same
transform feedback object without any code duplication.
Tested-By: Eero Tamminen <eero.t.tamminen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Fri, 12 Jan 2018 05:42:47 +0000 (16:42 +1100)]
st/mesa: enable ARB_enhanced_layouts on nir drivers
I'm guessing this may have been disable because of missing
component packing support. However recent nir linking changes
required nir based gallium drivers to support component packing
so this should now be ok to enable.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Roland Scheidegger [Tue, 16 Jan 2018 16:55:00 +0000 (17:55 +0100)]
draw: remove VSPLIT_CREATE_IDX macro
Just inline the little bit of code.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Roland Scheidegger [Tue, 16 Jan 2018 02:01:56 +0000 (03:01 +0100)]
draw: fix vsplit code when the (post-bias) index value is -1
vsplit_add_cache uses the post-bias index for hashing, but the
vsplit_add_cache_uint/ushort/ubyte ones used the pre-bias index, therefore
the code for handling the special case (because -1 matches the initialization
value of the cache) wasn't actually working.
Commit
78a997f72841310620d18daa9015633343d04db1 actually simplified the
cache logic somewhat, but it looks like this particular problem carried over
(and duplicated to the ushort/ubyte cases, since before only uint needed it).
This could lead to the vsplit cache doing the wrong thing, in particular
later fetch_info might indicate there are 0 values to fetch. This only really
affected edge cases which were bogus to begin with, but it could lead to a
crash with the jit vertex shader, since it cannot handle this case correctly
(the count loop is always executed at least once and we would not allocate
any memory for the shader outputs), so add another assert to catch it there.
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Grazvydas Ignotas [Mon, 15 Jan 2018 21:59:20 +0000 (23:59 +0200)]
st/va: release held locks in error paths
Found with the help of following Coccinelle semantic patch:
// <smpl>
@@
expression E;
@@
\(pthread_mutex_lock\|mtx_lock\|simple_mtx_lock\)(E)
...
(
\(pthread_mutex_unlock\|mtx_unlock\|simple_mtx_unlock\)(E);
...
return ...;
|
+ maybe need_unlock(E);
return ...;
)
// </smpl>
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Cc: mesa-stable@lists.freedesktop.org
Grazvydas Ignotas [Sun, 14 Jan 2018 21:45:05 +0000 (23:45 +0200)]
mesa: remove unneeded semicolons
Trivial. Found by Coccinelle.
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Grazvydas Ignotas [Sun, 14 Jan 2018 21:40:25 +0000 (23:40 +0200)]
radeon: remove unneeded semicolons
Trivial. Found by Coccinelle.
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Grazvydas Ignotas [Sun, 14 Jan 2018 19:52:52 +0000 (21:52 +0200)]
osmesa: don't check SmoothFlag twice
Trivial. Found by Coccinelle.
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Samuel Pitoiset [Mon, 15 Jan 2018 13:51:45 +0000 (14:51 +0100)]
ac: set no-signed-zeros-fp-math when RADV_DEBUG="unsafemath" is used
This is an optimisation that is recommended by Matt Arsenault,
and used by RadeonSI, but it's not compatible with Vulkan.
Note that AC_FLOAT_MODE_UNSAFE_FP_MATH includes the no signed
zeros flag in LLVM.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Mon, 15 Jan 2018 13:51:44 +0000 (14:51 +0100)]
ac: set fast math flags when RADV_DEBUG="unsafemath" is used
When that debug option is not used, we use the default float mode
because the no signed zeros optimisation is not Vulkan compatible.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Mon, 15 Jan 2018 13:51:43 +0000 (14:51 +0100)]
ac: import lp_create_builder() from gallivm
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Thu, 11 Jan 2018 15:45:11 +0000 (16:45 +0100)]
ac: replace llvm.AMDGPU.kilp by llvm.amdgcn.kill with LLVM 6
This also replaces llvm.AMDGPU.kilp by llvm.AMDGPU.kill with
LLVM < 6. Similar to RadeonSI codepath.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Juan A. Suarez Romero [Tue, 16 Jan 2018 18:42:35 +0000 (19:42 +0100)]
glsl/linker: link-error using the same name in unnamed block and outside
According with OpenGL GLSL 4.20 spec, section 4.3.9, page 57:
"It is a link-time error if any particular shader interface
contains:
- two different blocks, each having no instance name, and each
having a member of the same name, or
- a variable outside a block, and a block with no instance name,
where the variable has the same name as a member in the block."
This means that it is a link error if for example we have a vertex
shader with the following definition.
"layout(location=0) uniform Data { float a; float b; };"
and a fragment shader with:
"uniform float a;"
As in both cases we refer to both uniforms as "a", and thus using
glGetUniformLocation() wouldn't know which one we mean.
This fixes KHR-GL*.shaders.uniform_block.common.name_matching.
v2: add fixed tests (Tapani)
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Samuel Thibault [Mon, 15 Jan 2018 14:38:25 +0000 (15:38 +0100)]
glx: fix non-dri build
glXGetDriverConfig parameters do not provide a context to dynamically
check for the presence of the function, so the dispatcher directly calls
glXGetDriverConfig, but in non-dri builds dri_glx.c didn't provide
glXGetDriverConfig.
This change make it just return NULL in that case.
Fixes:
84f764a7591 "glxglvnddispatch: Add missing dispatch for GetDriverConfig
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Indrajit Das [Wed, 10 Jan 2018 09:43:37 +0000 (15:13 +0530)]
st/va: clear pointers for mpeg2 quantiser matrices
This is to fix VA-API issues with GStreamer and MPEG2.
Since gstreamer does not pass quantiser matrices with each frame, invalid
pointers were being passed to the driver. This patch addresses the same.
Signed-off-by: Indrajit Das <indrajit-kumar.das@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Indrajit Das [Wed, 10 Jan 2018 09:42:44 +0000 (15:12 +0530)]
radeon/vcn: update quantiser matrices only when requested
Only update them when the pointers are valid.
Signed-off-by: Indrajit Das <indrajit-kumar.das@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Indrajit Das [Wed, 10 Jan 2018 09:40:17 +0000 (15:10 +0530)]
radeon/uvd: update quantiser matrices only when requested
Only upload them when the pointers are valid.
Signed-off-by: Indrajit Das <indrajit-kumar.das@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Adam Jackson [Mon, 15 Jan 2018 18:47:24 +0000 (13:47 -0500)]
Revert "docs: Mark GLX_ARB_context_flush_control done"
This reverts commit
d547e18184978affd95a72dc524ca648efbe9812.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104490
Signed-off-by: Adam Jackson <ajax@redhat.com>
Adam Jackson [Mon, 15 Jan 2018 18:47:13 +0000 (13:47 -0500)]
Revert "gallium/dri2: Enable {GLX_ARB,EGL_KHR}_context_flush_control"
This reverts commit
0d044351b7043cd0bc94c1cb9b7a2213f8054414.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104490
Signed-off-by: Adam Jackson <ajax@redhat.com>
Adam Jackson [Mon, 15 Jan 2018 18:47:01 +0000 (13:47 -0500)]
Revert "i965: Enable flush control"
This reverts commit
6ce9006d76c050663af0be61cc88c3215d6f8cea.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104490
Signed-off-by: Adam Jackson <ajax@redhat.com>
Samuel Pitoiset [Mon, 15 Jan 2018 12:47:18 +0000 (13:47 +0100)]
Revert "ac/shader: gather If TES reads TESSINNER or TESSOUTER"
This can't work for two reasons:
- TESSINNER/TESSOUTER are shader input values, so never translated
to the intrinsic ops
- the shader info pass scans the current stage but we want to know
in TCS, if TES reads the tess factors.
This fixes 6 regressions related to
deqp-vk/tessellation/shader_input_output/tess_level_{inner,outer}_XXX_tes
This reverts commit
5ba1a61648e2dea96f621a5886ad8b937a471ab4.
Samuel Pitoiset [Thu, 11 Jan 2018 13:56:07 +0000 (14:56 +0100)]
amd/common: fix loading InstanceID for tess on < GFX9
InstanceID is in VGPR2, not 1.
One more failure that CTS didn't catch up...
Reported-by: Alex Smith <asmith@feralinteractive.com>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 12 Jan 2018 11:49:28 +0000 (12:49 +0100)]
ac/shader: gather If TES reads TESSINNER or TESSOUTER
This shouldn't be scanned in the pipeline.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Samuel Pitoiset [Mon, 15 Jan 2018 10:46:52 +0000 (11:46 +0100)]
ac: remove ac_shader_variant_info::fs::output_mask
Unused.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Gert Wollny [Sun, 14 Jan 2018 17:13:31 +0000 (18:13 +0100)]
r600/shader: Initialize max_driver_temp_used correctly for the first time
Without this initialization the temp registers used in tgsi_declaration
may used random indices, and this may result in failing translation from TGSI
with an error message "GPR limit exceeded", because the random index is greater
then the allowed limit implying that the shader uses more temporary registers then
available.
Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Rob Clark [Thu, 11 Jan 2018 21:08:47 +0000 (16:08 -0500)]
freedreno/ir3: "soft" depth scheduling for SFU instructions
First try with a "soft" depth, to try to schedule sfu instructions
further from their consumers, but fall back to hard depth (which might
result in stalling) if nothing else is avail to schedule.
Previously the consumer of a sfu instruction could end up scheduled
immediately after (since "hard" depth from sfu to consumer would be 0).
This works because legalize pass would insert a (ss) sync bit, but it
is sub-optimal since it would cause a stall.
Instead prioritize other instructions for 4 cycles if they would no
cause a nop to be inserted. This minimizes the stalling. There is a
slight penalty in general to overall # of instructions in shader (since
we could end up needing nop's later due to scheduling the "deeper" sfu
consumer later), but ends up being a wash on register pressure.
Overall this seems to be worth a 10+% gain in fps. Increasing the
"soft" depth of sfu consumer beyond 4 helps a bit in some cases, but 4
seems to be a good trade-off between getting 99% of the gain and not
increasing instruction count of shaders too much.
It's possible a similar approach could help for tex/mem instructions,
but the (sy) sync bit seems to trigger a switch to a different thread-
group to hide memory latency (possibly with some limits depending on
number of registers used?).
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Mon, 8 Jan 2018 18:40:22 +0000 (13:40 -0500)]
freedreno/a5xx: work around SWAP vs TILE_MODE constraint
If the blit isn't changing format, but is changing tiling, just lie and
call things ARGB (since the exact component order doesn't matter for a
tiling blit).
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Sun, 31 Dec 2017 20:01:51 +0000 (15:01 -0500)]
freedreno/a5xx: texture tiling
Overall a nice 5-10% gain for most games. And more for things like
glmark2 texture benchmark.
There are some rough edges. In particular, the hardware seems to only
support tiling or component swap. (Ie. from hw PoV, ARGB/ABGR/RGBA/
BGRA are all the same format but with different component swap.) For
tiled formats, only ARGB is possible. This isn't a big problem for
*sampling* since we also have swizzle state there (and since
util_format_compose_swizzles() already takes into account the component
order, we didn't use COLOR_SWAP for sampling). But it is a problem if
you try to render to a tiled BGRA (for example) surface.
The next patch introduces a workaround for blitter, so we can generate
tiled textures in ABGR/RGBA/BGRA, but that doesn't help the render-
target case. To handle that, I think we'd need to keep track that the
tiled format is different from the linear format, which seems like it
would get extra fun with sampler views/etc.
So for now, disabled by default, enable with FD_MESA_DEBUG=ttile. In
practice it works fine for all the games I've tried, but makes piglit
grumpy.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 3 Jan 2018 16:00:01 +0000 (11:00 -0500)]
freedreno: update generated headers
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Sun, 14 Jan 2018 13:57:29 +0000 (08:57 -0500)]
freedreno: add screen->setup_slices() for tex layout
The rules are sufficiently different for a5xx with tiled textures, so
split this out into something that can be implemented per-generation.
The a5xx specific implementation will come in a later patch.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Grazvydas Ignotas [Sun, 14 Jan 2018 19:31:55 +0000 (21:31 +0200)]
r300g: remove double assignment
Trivial. Found by Coccinelle.
Grazvydas Ignotas [Fri, 29 Dec 2017 00:05:05 +0000 (02:05 +0200)]
util: use faster zlib's CRC32 implementaion
zlib provides a faster slice-by-4 CRC32 implementation than the
traditional single byte lookup one used by mesa. As most supported
platforms now link zlib unconditionally, we can easily use it.
Improvement for a 1MB buffer (avg MB/s, n=100, zlib 1.2.8):
i5-6600K C2D E4500
mesa zlib mesa zlib
443 1443 225% +/- 2.1% 403 1175 191% +/- 0.9%
It has been verified the calculation results stay the same after this
change.
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Grazvydas Ignotas [Thu, 28 Dec 2017 23:29:10 +0000 (01:29 +0200)]
android,configure,meson: define HAVE_ZLIB
The next change wants to use some optional zlib functionality, however
not all platforms currently use zlib. Based on earlier Jordan Justen's
patches and their review feedback.
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Grazvydas Ignotas [Fri, 29 Dec 2017 01:48:52 +0000 (03:48 +0200)]
util/crc32: don't drop the const qualifier
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Timothy Arceri [Sat, 13 Jan 2018 23:07:58 +0000 (10:07 +1100)]
ac: add doubles support to isign
Fixes a number of int64 piglit tests, for example:
generated_tests/spec/arb_gpu_shader_int64/execution/built-in-functions/fs-sign-i64vec2.shader_test
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Timothy Arceri [Sat, 13 Jan 2018 23:06:36 +0000 (10:06 +1100)]
ac: add i64_0 and i64_1 to llvm build context
These will be used in the following patch.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Timothy Arceri [Fri, 12 Jan 2018 01:31:00 +0000 (12:31 +1100)]
ac/nir: fix translation of nir_op_b2i for doubles
V2: just zero-extend the 32-bit value.
Fixes a number of int64 piglet tests, for example:
generated_tests/spec/arb_gpu_shader_int64/execution/conversion/frag-conversion-explicit-bool-int64_t.shader_test
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Mauro Rossi [Fri, 12 Jan 2018 14:47:34 +0000 (15:47 +0100)]
ac: fix build error in si_shader
assert() is replaced by unreachable(), to avoid following building error:
external/mesa/src/gallium/drivers/radeonsi/si_shader.c:1967:1:
error: control may reach end of non-void function [-Werror,-Wreturn-type]
}
^
1 error generated.
Fixes: c797cd6 ("ac: add load_patch_vertices_in() to the abi")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Timothy Arceri [Fri, 12 Jan 2018 00:12:09 +0000 (11:12 +1100)]
radv/radeonsi/nir: lower 64bit flrp
Fixes a bunch of arb_gpu_shader_fp64 piglit tests for example:
generated_tests/spec/arb_gpu_shader_fp64/execution/built-in-functions/fs-mix-double-double-double.shader_test
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Eric Anholt [Fri, 12 Jan 2018 23:35:04 +0000 (15:35 -0800)]
broadcom/vc5: Use MSF to ignore discards/non-dispatched channels in loops.
Prevents potential infinite loops when a non-dispatched or discarded
channel never triggers the loop break condition.
Eric Anholt [Fri, 12 Jan 2018 23:38:04 +0000 (15:38 -0800)]
broadcom/vc5: Use XOR instead of SUB for execute flags comparisons.
I think this should be equivalent other than power, and it's the kind of
comparison we use for nir_op_ieq.
Eric Anholt [Fri, 12 Jan 2018 23:34:22 +0000 (15:34 -0800)]
broadcom/vc5: Also check the update flags for avoiding DCE.
I was trying to do a NULL-destination UF, and it got removed.
Eric Anholt [Fri, 12 Jan 2018 21:20:38 +0000 (13:20 -0800)]
broadcom/vc5: Fix up channel swizzling for textures on 4.x.
I had 3.x putting swizzling in the texture state only for 16-bit texture
returns, and in the shader for 32-bit. This may be due to having mixed up
the return channel setup on 3.x back before I had moved it into the
compiler. On 4.x, the non-border-color texwrap tests are passing nicely
with both 16 and 32-bit returns with swizzling in the texture state.
Eric Anholt [Fri, 12 Jan 2018 20:31:14 +0000 (12:31 -0800)]
broadcom/vc5: Port the draw-time state emission to V3D 4.1.
Eric Anholt [Fri, 12 Jan 2018 20:24:36 +0000 (12:24 -0800)]
broadcom/vc5: Rename V3D 3.x Flat Shade Action to match v4.x naming.
Now that the actions are reused for centroid and nonperspective, give them
a more generic name.
Eric Anholt [Fri, 12 Jan 2018 20:02:17 +0000 (12:02 -0800)]
broadcom/vc5: Update pixel center setup for V3D 4.x.
The fxcd/fycd instructions now return half-integer pixel centers when not
doing sample-rate shading.
Eric Anholt [Fri, 12 Jan 2018 01:22:58 +0000 (17:22 -0800)]
broadcom/vc5: Print the buffer name in simulator overflow checks.
Revealed that I was writing past the TSDA, not the Z buffer as I expected.
Eric Anholt [Thu, 11 Jan 2018 19:53:13 +0000 (11:53 -0800)]
broadcom/vc5: Add support for loading varyings in V3D 4.1.
The LDVARY signal now writes an arbitrary register, so I took out the
magic src register file and replaced it with an instruction with LDVARY
set so we have somewhere to hang a QFILE_TEMP destination for register
allocation.
Eric Anholt [Wed, 10 Jan 2018 23:49:47 +0000 (15:49 -0800)]
broadcom/vc5: Update state setup for V3D 4.1.
Eric Anholt [Wed, 10 Jan 2018 20:51:08 +0000 (12:51 -0800)]
broadcom/vc5: Add compiler support for V3D 4.x texturing.
Eric Anholt [Wed, 10 Jan 2018 21:56:11 +0000 (13:56 -0800)]
broadcom/vc5: Add the new TMU write addresses for V3D 4.x (and r5rep).
The V3D 3.x series of TMU writes with meaning depending on the texture
type is replaced with writes to specific registers for each texture
argument semantic.
Eric Anholt [Wed, 10 Jan 2018 20:48:05 +0000 (12:48 -0800)]
broadcom/vc5: Move V3D 3.3 texturing to a separate file.
V3D 4.x texturing changes enough that #ifdefs would just make a mess of
it.
Eric Anholt [Wed, 10 Jan 2018 20:22:38 +0000 (12:22 -0800)]
broadcom/vc5: Move V3D 3.3 VPM write setup to a separate file.
For V4.1 texturing, I need the V4.1 XML, so the main compiler needs to
stop including V3.3 XML.
Eric Anholt [Wed, 10 Jan 2018 00:02:44 +0000 (16:02 -0800)]
broadcom/vc5: Set up depth formats for V3D 4.x.
We no longer have the small depth-specific output format enum, and instead
depth is just at the end of the output image format enum.
Eric Anholt [Wed, 10 Jan 2018 00:09:10 +0000 (16:09 -0800)]
broadcom/vc5: Always use the RGBA8 formats for RGBX8.
The RGBX8 formats were dropped from V3D 4.x, but we don't really need them
anyway (we already handle other non-alpha formats by forcing A to 1).