Tapani Pälli [Thu, 7 May 2020 06:24:44 +0000 (09:24 +0300)]
anv: call base finish only if pass given in DestroyRenderPass
Fixes:
682c81bdfb7 ("vulkan,anv: Add a base object struct type")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4936>
Erik Faye-Lund [Tue, 5 May 2020 20:01:42 +0000 (22:01 +0200)]
st/wgl: allocate and resolve msaa-textures
LLVMpipe recently got the ability to render to MSAA-surfaces, but in
order for this to work on Windows, we need to allocate a separate MSAA
resource and resolve using a blit before we can display it.
Without this, we end up always displaying the first sample instead of
the resolved result.
Acked-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4926>
Erik Faye-Lund [Tue, 5 May 2020 19:59:22 +0000 (21:59 +0200)]
st/wgl: pass st_context_iface into stw_st_framebuffer_present_locked
We're going to need this to be able to resolve MSAA buffers.
Acked-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4926>
Blaž Tomažič [Wed, 6 May 2020 19:34:10 +0000 (21:34 +0200)]
radeonsi: Fix omitted flush when moving suballocated texture
Fixes:
5e805cc74bc52f97de8f6308fc06bc96623e7e09 "radeonsi: flush the context after resource_copy_region for buffer exports"
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4925>
Daniel Schürmann [Wed, 6 May 2020 16:24:38 +0000 (17:24 +0100)]
aco: either copy-propagate or inline create_vector operands
Don't do both at the same time as it breaks DCE
Fixes:
2dc550202e82c5da198ad0a416a5d24dd89addd8 ('aco: copy-propagate p_create_vector copies of vectors')
Fixes: dEQP-VK.glsl.builtin.precision_double.ldexp.compute.scalar on GFX6-GFX7
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4922>
Marek Olšák [Mon, 4 May 2020 11:53:38 +0000 (07:53 -0400)]
ac/surface: override all offsets including metadata offsets
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4863>
Marek Olšák [Mon, 4 May 2020 11:43:44 +0000 (07:43 -0400)]
amd: unify code for overriding offset and stride for imported buffers
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4863>
Marek Olšák [Sat, 2 May 2020 16:23:51 +0000 (12:23 -0400)]
ac/surface,radeonsi: move the set/get_umd_metadata code into ac_surface.c
The indentation is on purpose. The whole file will be reindented to this
code style some other time.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4863>
Marek Olšák [Sat, 2 May 2020 14:58:46 +0000 (10:58 -0400)]
ac/surface,radeonsi: move the set/get_bo_metadata code to ac_surface.c
The indentation is on purpose. The whole file will be reindented to this
code style some other time.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4863>
Marek Olšák [Sat, 2 May 2020 13:19:18 +0000 (09:19 -0400)]
amd: assume HTILE is always rb/pipe_aligned, remove ac_surface.u.gfx9.htile
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4863>
Marek Olšák [Sat, 2 May 2020 13:19:18 +0000 (09:19 -0400)]
amd: assume CMASK is always rb/pipe_aligned, remove ac_surface.u.gfx9.cmask
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4863>
Marek Olšák [Sat, 2 May 2020 13:10:42 +0000 (09:10 -0400)]
amd: remove duplicated definitions from amdgpu_drm.h
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4863>
Marek Olšák [Sat, 2 May 2020 13:05:55 +0000 (09:05 -0400)]
amd: update amdgpu_drm.h
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4863>
Dave Airlie [Thu, 7 May 2020 00:04:16 +0000 (10:04 +1000)]
llvmpipe: make sample position a global array.
I messed this up and LLVM asserts on it.
Use the gallivm struct wrappers to make it clearer.
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2913
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Tested-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4933>
Ian Romanick [Thu, 5 Mar 2020 21:32:07 +0000 (13:32 -0800)]
nir/algebraic: Optimize some bfe patterns
v2: Use -x instead of 32-x in shift counts.
Tiger Lake
total instructions in shared programs:
17597691 ->
17597405 (<.01%)
instructions in affected programs: 224557 -> 224271 (-0.13%)
helped: 74
HURT: 17
helped stats (abs) min: 1 max: 71 x̄: 14.36 x̃: 7
helped stats (rel) min: 0.08% max: 1.80% x̄: 0.50% x̃: 0.37%
HURT stats (abs) min: 1 max: 141 x̄: 45.71 x̃: 40
HURT stats (rel) min: 0.03% max: 3.55% x̄: 1.20% x̃: 1.14%
95% mean confidence interval for instructions value: -10.53 4.24
95% mean confidence interval for instructions %-change: -0.38% 0.01%
Inconclusive result (value mean confidence interval includes 0).
total cycles in shared programs:
333595656 ->
333180770 (-0.12%)
cycles in affected programs:
70056467 ->
69641581 (-0.59%)
helped: 91
HURT: 4
helped stats (abs) min: 1 max: 25174 x̄: 4571.40 x̃: 400
helped stats (rel) min: <.01% max: 2.23% x̄: 0.40% x̃: 0.21%
HURT stats (abs) min: 1 max: 370 x̄: 277.75 x̃: 370
HURT stats (rel) min: 0.01% max: 0.04% x̄: 0.04% x̃: 0.04%
95% mean confidence interval for cycles value: -5981.55 -2752.89
95% mean confidence interval for cycles %-change: -0.48% -0.29%
Cycles are helped.
Ice Lake, Skylake, Broadwell, and Haswell had similar results. (Ice Lake shown)
total instructions in shared programs:
16117204 ->
16116723 (<.01%)
instructions in affected programs: 207109 -> 206628 (-0.23%)
helped: 100
HURT: 0
helped stats (abs) min: 1 max: 9 x̄: 4.81 x̃: 7
helped stats (rel) min: 0.10% max: 1.58% x̄: 0.23% x̃: 0.20%
95% mean confidence interval for instructions value: -5.51 -4.11
95% mean confidence interval for instructions %-change: -0.27% -0.19%
Instructions are helped.
total cycles in shared programs:
330487341 ->
330082421 (-0.12%)
cycles in affected programs:
68037050 ->
67632130 (-0.60%)
helped: 89
HURT: 7
helped stats (abs) min: 2 max: 24610 x̄: 4567.07 x̃: 400
helped stats (rel) min: <.01% max: 1.52% x̄: 0.39% x̃: 0.22%
HURT stats (abs) min: 1 max: 370 x̄: 221.29 x̃: 170
HURT stats (rel) min: 0.01% max: 1.66% x̄: 0.58% x̃: 0.04%
95% mean confidence interval for cycles value: -5780.79 -2655.05
95% mean confidence interval for cycles %-change: -0.42% -0.22%
Cycles are helped.
Ivy Bridge
total instructions in shared programs:
11873641 ->
11873137 (<.01%)
instructions in affected programs: 147464 -> 146960 (-0.34%)
helped: 54
HURT: 0
helped stats (abs) min: 9 max: 10 x̄: 9.33 x̃: 9
helped stats (rel) min: 0.29% max: 0.41% x̄: 0.34% x̃: 0.34%
95% mean confidence interval for instructions value: -9.46 -9.20
95% mean confidence interval for instructions %-change: -0.35% -0.33%
Instructions are helped.
total cycles in shared programs:
175769085 ->
175549519 (-0.12%)
cycles in affected programs:
60770592 ->
60551026 (-0.36%)
helped: 54
HURT: 0
helped stats (abs) min: 252 max: 13434 x̄: 4066.04 x̃: 1290
helped stats (rel) min: 0.02% max: 0.74% x̄: 0.34% x̃: 0.26%
95% mean confidence interval for cycles value: -5323.59 -2808.48
95% mean confidence interval for cycles %-change: -0.41% -0.27%
Cycles are helped.
No changes on any earlier Intel platforms.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4156>
Ian Romanick [Fri, 6 Mar 2020 21:22:45 +0000 (13:22 -0800)]
nir/algebraic: Split ibfe and ubfe with two constant sources
I also tried splitting ubfe instructions with one or zero constants,
and zero shaders in shader-db were affected.
The "lost" shader is a compute shader that was promoted from SIMD8 to
SIMD16, so is also counted as the gained shader.
v2: Further restrict bfe splitting. bfe with multiple constants is
better on at least some Radeon GPUs. Use -x instead of 32-x in shift
counts.
v3: Fix the outer shift count for ibfe lowering. Add c=0 optimizations
to prevent bad lowering. Both suggested by Rhys. Add shift by -32
optimizations.
Tiger Lake
total instructions in shared programs:
17608764 ->
17596316 (-0.07%)
instructions in affected programs: 303765 -> 291317 (-4.10%)
helped: 113
HURT: 46
helped stats (abs) min: 1 max: 458 x̄: 120.67 x̃: 21
helped stats (rel) min: 0.09% max: 11.23% x̄: 3.47% x̃: 1.39%
HURT stats (abs) min: 1 max: 201 x̄: 25.83 x̃: 6
HURT stats (rel) min: 0.23% max: 5.18% x̄: 1.53% x̃: 1.11%
95% mean confidence interval for instructions value: -101.13 -55.45
95% mean confidence interval for instructions %-change: -2.61% -1.44%
Instructions are helped.
total cycles in shared programs:
338390770 ->
333530868 (-1.44%)
cycles in affected programs:
79438330 ->
74578428 (-6.12%)
helped: 112
HURT: 64
helped stats (abs) min: 2 max: 268955 x̄: 44261.93 x̃: 1452
helped stats (rel) min: <.01% max: 29.51% x̄: 4.72% x̃: 2.23%
HURT stats (abs) min: 2 max: 17618 x̄: 1522.41 x̃: 84
HURT stats (rel) min: <.01% max: 7.34% x̄: 1.35% x̃: 0.34%
95% mean confidence interval for cycles value: -37232.47 -17993.69
95% mean confidence interval for cycles %-change: -3.37% -1.65%
Cycles are helped.
total spills in shared programs: 8944 -> 8138 (-9.01%)
spills in affected programs: 3240 -> 2434 (-24.88%)
helped: 67
HURT: 0
total fills in shared programs: 9373 -> 7842 (-16.33%)
fills in affected programs: 4736 -> 3205 (-32.33%)
helped: 67
HURT: 0
LOST: 1
GAINED: 2
Ice Lake and Skylake had similar results. (Ice Lake shown)
total instructions in shared programs:
16123288 ->
16116876 (-0.04%)
instructions in affected programs: 241155 -> 234743 (-2.66%)
helped: 126
HURT: 2
helped stats (abs) min: 1 max: 209 x̄: 50.90 x̃: 7
helped stats (rel) min: 0.07% max: 5.94% x̄: 1.76% x̃: 0.65%
HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel) min: 0.05% max: 0.24% x̄: 0.15% x̃: 0.15%
95% mean confidence interval for instructions value: -61.29 -38.89
95% mean confidence interval for instructions %-change: -2.05% -1.42%
Instructions are helped.
total cycles in shared programs:
335419163 ->
330438819 (-1.48%)
cycles in affected programs:
77515502 ->
72535158 (-6.42%)
helped: 139
HURT: 37
helped stats (abs) min: 2 max: 269140 x̄: 36374.19 x̃: 597
helped stats (rel) min: <.01% max: 28.60% x̄: 3.67% x̃: 1.31%
HURT stats (abs) min: 4 max: 17618 x̄: 2045.08 x̃: 174
HURT stats (rel) min: 0.02% max: 8.32% x̄: 2.61% x̃: 0.62%
95% mean confidence interval for cycles value: -37799.30 -18795.51
95% mean confidence interval for cycles %-change: -3.13% -1.57%
Cycles are helped.
total spills in shared programs: 8065 -> 7306 (-9.41%)
spills in affected programs: 3153 -> 2394 (-24.07%)
helped: 67
HURT: 0
total fills in shared programs: 8710 -> 7412 (-14.90%)
fills in affected programs: 4466 -> 3168 (-29.06%)
helped: 67
HURT: 0
LOST: 1
GAINED: 1
Broadwell
total instructions in shared programs:
14970538 ->
14965967 (-0.03%)
instructions in affected programs: 227040 -> 222469 (-2.01%)
helped: 126
HURT: 2
helped stats (abs) min: 1 max: 136 x̄: 36.29 x̃: 8
helped stats (rel) min: 0.07% max: 6.02% x̄: 1.47% x̃: 0.89%
HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel) min: 0.05% max: 0.24% x̄: 0.14% x̃: 0.14%
95% mean confidence interval for instructions value: -43.05 -28.37
95% mean confidence interval for instructions %-change: -1.69% -1.19%
Instructions are helped.
total cycles in shared programs:
336237662 ->
333035960 (-0.95%)
cycles in affected programs:
72066394 ->
68864692 (-4.44%)
helped: 134
HURT: 42
helped stats (abs) min: 4 max: 122640 x̄: 24344.54 x̃: 1833
helped stats (rel) min: <.01% max: 26.93% x̄: 4.02% x̃: 2.38%
HURT stats (abs) min: 1 max: 17205 x̄: 1439.69 x̃: 92
HURT stats (rel) min: <.01% max: 7.12% x̄: 1.34% x̃: 0.62%
95% mean confidence interval for cycles value: -23753.58 -12629.40
95% mean confidence interval for cycles %-change: -3.50% -1.98%
Cycles are helped.
total spills in shared programs: 21122 -> 20204 (-4.35%)
spills in affected programs: 3644 -> 2726 (-25.19%)
helped: 67
HURT: 0
total fills in shared programs: 24879 -> 23460 (-5.70%)
fills in affected programs: 4883 -> 3464 (-29.06%)
helped: 67
HURT: 0
Haswell
total instructions in shared programs:
13148269 ->
13145444 (-0.02%)
instructions in affected programs: 137046 -> 134221 (-2.06%)
helped: 97
HURT: 3
helped stats (abs) min: 1 max: 137 x̄: 30.58 x̃: 3
helped stats (rel) min: 0.14% max: 4.38% x̄: 1.38% x̃: 0.44%
HURT stats (abs) min: 1 max: 70 x̄: 47.00 x̃: 70
HURT stats (rel) min: 0.05% max: 5.82% x̄: 3.90% x̃: 5.82%
95% mean confidence interval for instructions value: -37.15 -19.35
95% mean confidence interval for instructions %-change: -1.56% -0.89%
Instructions are helped.
total cycles in shared programs:
321221834 ->
318333159 (-0.90%)
cycles in affected programs:
54932349 ->
52043674 (-5.26%)
helped: 95
HURT: 53
helped stats (abs) min: 4 max: 123390 x̄: 30648.39 x̃: 702
helped stats (rel) min: <.01% max: 28.87% x̄: 4.27% x̃: 2.87%
HURT stats (abs) min: 4 max: 2357 x̄: 432.49 x̃: 113
HURT stats (rel) min: <.01% max: 3.44% x̄: 1.03% x̃: 0.54%
95% mean confidence interval for cycles value: -26154.16 -12881.99
95% mean confidence interval for cycles %-change: -3.20% -1.55%
Cycles are helped.
total spills in shared programs: 19878 -> 19293 (-2.94%)
spills in affected programs: 3020 -> 2435 (-19.37%)
helped: 41
HURT: 2
total fills in shared programs: 20918 -> 19875 (-4.99%)
fills in affected programs: 3968 -> 2925 (-26.29%)
helped: 41
HURT: 2
LOST: 0
GAINED: 1
Ivy Bridge
total instructions in shared programs:
11875585 ->
11873641 (-0.02%)
instructions in affected programs: 78065 -> 76121 (-2.49%)
helped: 27
HURT: 0
helped stats (abs) min: 8 max: 134 x̄: 72.00 x̃: 72
helped stats (rel) min: 0.36% max: 4.23% x̄: 2.42% x̃: 2.42%
95% mean confidence interval for instructions value: -83.68 -60.32
95% mean confidence interval for instructions %-change: -2.78% -2.07%
Instructions are helped.
total cycles in shared programs:
178232734 ->
175769085 (-1.38%)
cycles in affected programs:
50018707 ->
47555058 (-4.93%)
helped: 27
HURT: 0
helped stats (abs) min: 82035 max: 99953 x̄: 91246.26 x̃: 92278
helped stats (rel) min: 4.40% max: 5.69% x̄: 4.93% x̃: 4.95%
95% mean confidence interval for cycles value: -93674.20 -88818.32
95% mean confidence interval for cycles %-change: -5.09% -4.78%
Cycles are helped.
total spills in shared programs: 4182 -> 3739 (-10.59%)
spills in affected programs: 1089 -> 646 (-40.68%)
helped: 27
HURT: 0
total fills in shared programs: 5216 -> 4345 (-16.70%)
fills in affected programs: 1874 -> 1003 (-46.48%)
helped: 27
HURT: 0
No changes on any earlier Intel platforms.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4156>
Ian Romanick [Fri, 6 Mar 2020 16:00:42 +0000 (08:00 -0800)]
nir/algebraic: Recognize open-coded byte or word extract from bfe
v2: Move word-extract patterns up near the byte-extract patterns.
Suggested by Rhys.
Tiger Lake
total instructions in shared programs:
21369236 ->
21368712 (<.01%)
instructions in affected programs: 913104 -> 912580 (-0.06%)
helped: 209
HURT: 165
helped stats (abs) min: 1 max: 30 x̄: 5.35 x̃: 3
helped stats (rel) min: 0.03% max: 6.92% x̄: 0.28% x̃: 0.12%
HURT stats (abs) min: 1 max: 18 x̄: 3.61 x̃: 3
HURT stats (rel) min: 0.04% max: 0.87% x̄: 0.16% x̃: 0.12%
95% mean confidence interval for instructions value: -2.04 -0.76
95% mean confidence interval for instructions %-change: -0.14% -0.04%
Instructions are helped.
total cycles in shared programs:
490161481 ->
490175959 (<.01%)
cycles in affected programs:
72557244 ->
72571722 (0.02%)
helped: 193
HURT: 189
helped stats (abs) min: 1 max: 14240 x̄: 509.16 x̃: 71
helped stats (rel) min: <.01% max: 13.71% x̄: 0.44% x̃: 0.05%
HURT stats (abs) min: 2 max: 4210 x̄: 596.53 x̃: 173
HURT stats (rel) min: <.01% max: 5.59% x̄: 0.54% x̃: 0.14%
95% mean confidence interval for cycles value: -96.33 172.13
95% mean confidence interval for cycles %-change: -0.07% 0.16%
Inconclusive result (value mean confidence interval includes 0).
total spills in shared programs: 10780 -> 10782 (0.02%)
spills in affected programs: 18 -> 20 (11.11%)
helped: 0
HURT: 1
total fills in shared programs: 10396 -> 10370 (-0.25%)
fills in affected programs: 2292 -> 2266 (-1.13%)
helped: 27
HURT: 1
Ice Lake
total instructions in shared programs:
19556356 ->
19555446 (<.01%)
instructions in affected programs: 833336 -> 832426 (-0.11%)
helped: 400
HURT: 0
helped stats (abs) min: 1 max: 20 x̄: 2.27 x̃: 2
helped stats (rel) min: 0.07% max: 4.42% x̄: 0.14% x̃: 0.10%
95% mean confidence interval for instructions value: -2.42 -2.13
95% mean confidence interval for instructions %-change: -0.18% -0.11%
Instructions are helped.
total cycles in shared programs:
488026481 ->
488008714 (<.01%)
cycles in affected programs:
81581708 ->
81563941 (-0.02%)
helped: 193
HURT: 206
helped stats (abs) min: 1 max: 3615 x̄: 576.35 x̃: 131
helped stats (rel) min: <.01% max: 4.50% x̄: 0.49% x̃: 0.22%
HURT stats (abs) min: 1 max: 2244 x̄: 453.73 x̃: 170
HURT stats (rel) min: <.01% max: 5.71% x̄: 0.36% x̃: 0.14%
95% mean confidence interval for cycles value: -127.23 38.17
95% mean confidence interval for cycles %-change: -0.12% 0.03%
Inconclusive result (value mean confidence interval includes 0).
total fills in shared programs: 9935 -> 9908 (-0.27%)
fills in affected programs: 2208 -> 2181 (-1.22%)
helped: 27
HURT: 0
Skylake
total instructions in shared programs:
17766078 ->
17765186 (<.01%)
instructions in affected programs: 822017 -> 821125 (-0.11%)
helped: 399
HURT: 1
helped stats (abs) min: 1 max: 20 x̄: 2.27 x̃: 2
helped stats (rel) min: 0.07% max: 4.46% x̄: 0.15% x̃: 0.10%
HURT stats (abs) min: 12 max: 12 x̄: 12.00 x̃: 12
HURT stats (rel) min: 0.50% max: 0.50% x̄: 0.50% x̃: 0.50%
95% mean confidence interval for instructions value: -2.39 -2.07
95% mean confidence interval for instructions %-change: -0.18% -0.11%
Instructions are helped.
total cycles in shared programs:
470905548 ->
470907497 (<.01%)
cycles in affected programs:
78598491 ->
78600440 (<.01%)
helped: 202
HURT: 192
helped stats (abs) min: 1 max: 3690 x̄: 228.98 x̃: 60
helped stats (rel) min: <.01% max: 4.51% x̄: 0.24% x̃: 0.03%
HURT stats (abs) min: 1 max: 2260 x̄: 251.05 x̃: 77
HURT stats (rel) min: <.01% max: 5.31% x̄: 0.24% x̃: 0.06%
95% mean confidence interval for cycles value: -45.01 54.90
95% mean confidence interval for cycles %-change: -0.07% 0.05%
Inconclusive result (value mean confidence interval includes 0).
total spills in shared programs: 9941 -> 9943 (0.02%)
spills in affected programs: 26 -> 28 (7.69%)
helped: 0
HURT: 1
total fills in shared programs: 10293 -> 10268 (-0.24%)
fills in affected programs: 2391 -> 2366 (-1.05%)
helped: 27
HURT: 1
Broadwell
total instructions in shared programs:
17463211 ->
17462366 (<.01%)
instructions in affected programs: 861444 -> 860599 (-0.10%)
helped: 399
HURT: 1
helped stats (abs) min: 1 max: 20 x̄: 2.14 x̃: 2
helped stats (rel) min: 0.03% max: 4.46% x̄: 0.14% x̃: 0.09%
HURT stats (abs) min: 7 max: 7 x̄: 7.00 x̃: 7
HURT stats (rel) min: 0.33% max: 0.33% x̄: 0.33% x̃: 0.33%
95% mean confidence interval for instructions value: -2.26 -1.97
95% mean confidence interval for instructions %-change: -0.17% -0.10%
Instructions are helped.
total cycles in shared programs:
507048912 ->
506898243 (-0.03%)
cycles in affected programs:
79806433 ->
79655764 (-0.19%)
helped: 248
HURT: 136
helped stats (abs) min: 1 max: 8450 x̄: 1124.18 x̃: 64
helped stats (rel) min: <.01% max: 5.91% x̄: 0.83% x̃: 0.05%
HURT stats (abs) min: 2 max: 7632 x̄: 942.12 x̃: 103
HURT stats (rel) min: <.01% max: 5.62% x̄: 0.71% x̃: 0.08%
95% mean confidence interval for cycles value: -647.01 -137.73
95% mean confidence interval for cycles %-change: -0.47% -0.10%
Cycles are helped.
total spills in shared programs: 22996 -> 22998 (<.01%)
spills in affected programs: 31 -> 33 (6.45%)
helped: 0
HURT: 1
total fills in shared programs: 25951 -> 25923 (-0.11%)
fills in affected programs: 2444 -> 2416 (-1.15%)
helped: 29
HURT: 1
Haswell
total instructions in shared programs:
15841325 ->
15840554 (<.01%)
instructions in affected programs: 869679 -> 868908 (-0.09%)
helped: 394
HURT: 6
helped stats (abs) min: 1 max: 20 x̄: 2.15 x̃: 2
helped stats (rel) min: 0.06% max: 4.46% x̄: 0.14% x̃: 0.09%
HURT stats (abs) min: 7 max: 18 x̄: 12.83 x̃: 13
HURT stats (rel) min: 0.32% max: 0.82% x̄: 0.59% x̃: 0.61%
95% mean confidence interval for instructions value: -2.16 -1.69
95% mean confidence interval for instructions %-change: -0.16% -0.09%
Instructions are helped.
total cycles in shared programs:
520417167 ->
520279766 (-0.03%)
cycles in affected programs:
80949963 ->
80812562 (-0.17%)
helped: 246
HURT: 139
helped stats (abs) min: 1 max: 8152 x̄: 790.08 x̃: 129
helped stats (rel) min: <.01% max: 11.46% x̄: 0.70% x̃: 0.09%
HURT stats (abs) min: 1 max: 7085 x̄: 409.78 x̃: 80
HURT stats (rel) min: <.01% max: 5.25% x̄: 0.31% x̃: 0.06%
95% mean confidence interval for cycles value: -526.34 -187.43
95% mean confidence interval for cycles %-change: -0.49% -0.18%
Cycles are helped.
total spills in shared programs: 21714 -> 21729 (0.07%)
spills in affected programs: 174 -> 189 (8.62%)
helped: 0
HURT: 6
total fills in shared programs: 22136 -> 22132 (-0.02%)
fills in affected programs: 2848 -> 2844 (-0.14%)
helped: 31
HURT: 6
Ivy Bridge
total instructions in shared programs:
15177059 ->
15177003 (<.01%)
instructions in affected programs: 79370 -> 79314 (-0.07%)
helped: 29
HURT: 0
helped stats (abs) min: 1 max: 2 x̄: 1.93 x̃: 2
helped stats (rel) min: 0.06% max: 0.16% x̄: 0.08% x̃: 0.07%
95% mean confidence interval for instructions value: -2.03 -1.83
95% mean confidence interval for instructions %-change: -0.09% -0.07%
Instructions are helped.
total cycles in shared programs:
420424359 ->
420417254 (<.01%)
cycles in affected programs:
29562648 ->
29555543 (-0.02%)
helped: 23
HURT: 6
helped stats (abs) min: 2 max: 2741 x̄: 432.57 x̃: 142
helped stats (rel) min: <.01% max: 0.26% x̄: 0.04% x̃: 0.02%
HURT stats (abs) min: 4 max: 1184 x̄: 474.00 x̃: 226
HURT stats (rel) min: <.01% max: 0.11% x̄: 0.05% x̃: 0.05%
95% mean confidence interval for cycles value: -553.48 63.48
95% mean confidence interval for cycles %-change: -0.05% <.01%
Inconclusive result (value mean confidence interval includes 0).
total fills in shared programs: 6420 -> 6393 (-0.42%)
fills in affected programs: 1901 -> 1874 (-1.42%)
helped: 27
HURT: 0
No changes on any earlier Intel platforms.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4156>
Jan Zielinski [Thu, 7 May 2020 14:49:15 +0000 (16:49 +0200)]
gallium/swr: Fix crashes in sampling code
Add missing functions used by the new
sampling code in llvmpipe (num_samples and
sample_stride)
Reviewed-by: Krzysztof Raszkowski <krzysztof.raszkowski@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4947>
Tomeu Vizoso [Thu, 7 May 2020 12:56:53 +0000 (14:56 +0200)]
panfrost: Handle MALI_RGB8_UNORM in panfrost_format_to_bifrost_blend
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4944>
Tomeu Vizoso [Thu, 7 May 2020 12:56:17 +0000 (14:56 +0200)]
panfrost: Don't trample on top of Bifrost-specific unions
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4944>
Alyssa Rosenzweig [Mon, 4 May 2020 16:48:34 +0000 (12:48 -0400)]
pan/decode: Fix flags_hi printing
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4944>
Tomeu Vizoso [Mon, 4 May 2020 07:01:19 +0000 (09:01 +0200)]
panfrost: Add checksum BOs to batch
So they don't get released before the last frame finishes rendering.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4944>
Lionel Landwerlin [Thu, 7 May 2020 08:36:36 +0000 (11:36 +0300)]
anv: don't expose VK_INTEL_performance_query without kernel support
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
2b5f30b1d91b ("anv: implement VK_INTEL_performance_query")
Acked-by: Timothy Strelchun <timothy.strelchun@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4937>
Connor Abbott [Wed, 6 May 2020 22:07:48 +0000 (00:07 +0200)]
tu: Support pipelines without a fragment shader
Apparently this is allowed, and the CTS started doing this more often
recently which resulted in frequent hangs running the entire CTS. I
copied the code to create an empty FS from radv.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4928>
Erik Faye-Lund [Wed, 6 May 2020 13:33:37 +0000 (15:33 +0200)]
util/os_memory: never use os_memory_debug.h
This is currently broken hard, because this code is being used in more
places that it used to be, and fixing that is prohibitively hard right
now.
This is far from ideal, as it leaves the same inconsistency in the
EMBEDDED_DEVICE code-path. But that only used by VMWare, so it's
probably better if they fix it, as they know their requirements better
than we do.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2911
Fixes:
76f79db3f5d ("util: stop including files from mesa/main")
Acked-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4919>
Jose Maria Casanova Crespo [Thu, 7 May 2020 01:50:16 +0000 (03:50 +0200)]
v3d: Include supported DXT formats to enable s3tc/dxt extensions
DXT1_RGBA and sRGB variants of DXT[135] formats are enabled as
valid format on V3D.
Once all S3TC formats supported by V3C are enabled the following
extensions become exposed by gallium.
* GL_ANGLE_texture_compression_dxt3
* GL_ANGLE_texture_compression_dxt5,
* GL_EXT_texture_compression_dxt1
* GL_EXT_texture_compression_s3tc
* GL_S3_s3tc
* GL_EXT_texture_compression_s3tc_srgb
This enables 206 passing piglit test related to gl_compressed.*s3tc_dxt
Cc: 20.0 20.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4934>
Jose Maria Casanova Crespo [Thu, 7 May 2020 01:37:22 +0000 (03:37 +0200)]
v3d: Fix swizzle in DXT3 and DXT5 formats
Swizzles were ignoring the W component of the format DXT3_RGBA and
DXT5_RGBA.
This fixes 15 piglit tests:
spec/!opengl 1.1/copyteximage 2d
spec/!opengl 1.2/copyteximage 3d
spec/arb_texture_compression/fbo-generatemipmap-formats/gl_compressed_rgba
spec/arb_texture_compression/fbo-generatemipmap-formats/gl_compressed_rgba npot
spec/arb_texture_compression/texwrap formats bordercolor-swizzled/gl_compressed_rgba, swizzled, border color only
spec/arb_texture_compression/texwrap formats bordercolor/gl_compressed_rgba, border color only
spec/arb_texture_cube_map/copyteximage cube
spec/arb_texture_cube_map/copyteximage cube samples=2
spec/arb_texture_cube_map/copyteximage cube samples=4
spec/arb_texture_rectangle/copyteximage rect
spec/arb_texture_rectangle/copyteximage rect samples=2
spec/arb_texture_rectangle/copyteximage rect samples=4
spec/ext_texture_array/copyteximage 2d_array
spec/ext_texture_array/copyteximage 2d_array samples=2
spec/ext_texture_array/copyteximage 2d_array samples=4
Fixes:
469bbd8387d1 "broadcom/vc5: Move the formats table to per-V3D-version compile."
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4934>
Rhys Perry [Tue, 5 May 2020 16:39:59 +0000 (17:39 +0100)]
docs/envvars: update RADV_FORCE_FAMILY
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4907>
Rhys Perry [Tue, 5 May 2020 16:31:26 +0000 (17:31 +0100)]
docs/envvars: document ACO_DEBUG
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4907>
Rhys Perry [Tue, 5 May 2020 16:30:16 +0000 (17:30 +0100)]
docs: add src/amd/ to sourcetree.html
This file doesn't seem to have been updated in years but this was pretty
easy to do.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4907>
Pierre Moreau [Tue, 5 May 2020 11:13:19 +0000 (13:13 +0200)]
clover/nir: Check the result of spirv_to_nir
Fixes:
deb04adf2ae ("clover: add support for passing kernels as nir to the driver")
Signed-off-by: Pierre Moreau <dev@pmoreau.org>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4901>
Rhys Perry [Mon, 3 Feb 2020 21:19:52 +0000 (21:19 +0000)]
nir: make fsat return 0.0 with NaN instead of passing it through
This is how lower_fsat and ACO implements fsat and is a more useful
definition since it can be exactly created from fmin(fmax(a, 0.0), 1.0).
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3716>
Rhys Perry [Mon, 3 Feb 2020 21:18:42 +0000 (21:18 +0000)]
compiler/spirv: flag nclamp/nmin/nmax as exact
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3716>
Elie Tournier [Mon, 16 Mar 2020 10:05:33 +0000 (10:05 +0000)]
docs/features: Add ARB_clear_texture to virgl
Signed-off-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4345>
Elie Tournier [Fri, 13 Mar 2020 11:26:04 +0000 (11:26 +0000)]
virgl: Enable CAP_CLEAR_TEXTURE if host supports it
Signed-off-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4345>
Elie Tournier [Fri, 20 Mar 2020 11:50:06 +0000 (11:50 +0000)]
virgl: implement ARB_clear_texture
Signed-off-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4345>
Gert Wollny [Wed, 6 May 2020 16:48:35 +0000 (18:48 +0200)]
r600: Fix warning regarding mixing enums and unsigned in ?: expression
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4939>
Gert Wollny [Wed, 6 May 2020 16:48:05 +0000 (18:48 +0200)]
r600: remove some unused variables to silence warnings
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4939>
Gert Wollny [Wed, 6 May 2020 16:29:44 +0000 (18:29 +0200)]
r600/sb: replace memset by using member initialization/assignment
Closes #2860
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4939>
Gert Wollny [Wed, 6 May 2020 16:10:39 +0000 (18:10 +0200)]
r600: remove unused static functions
Related #2860
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4939>
Gert Wollny [Wed, 6 May 2020 16:09:52 +0000 (18:09 +0200)]
r600: Annotate some case fallthroughs
Also fix indentions where aproprate
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4939>
Samuel Pitoiset [Mon, 4 May 2020 09:48:46 +0000 (11:48 +0200)]
ci: run radv-fossils with Pitcairn (GFX6) and Bonaire (GFX7) too
This job is really small and it shouldn't hurt to cover two more
generations. This will prevent breaking the world on GFX6-GFX7
because we don't regularly test these chips.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4873>
Samuel Pitoiset [Mon, 4 May 2020 09:44:45 +0000 (11:44 +0200)]
ci: set ACO_DEBUG=validateir,validatera global for RADV testing
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4873>
Samuel Pitoiset [Mon, 4 May 2020 09:43:26 +0000 (11:43 +0200)]
ci: remove unused .test-radv-fossilize rule
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4873>
Arcady Goldmints-Orlov [Wed, 29 Apr 2020 00:46:48 +0000 (19:46 -0500)]
anv: increase minUniformBufferOffsetAlignment to 64
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4904>
Rob Clark [Thu, 27 Feb 2020 18:24:49 +0000 (10:24 -0800)]
freedreno/a6xx: enable tiled compressed textures
I wasn't expecting this to be too useful, since compressed textures are
already block based.. but gfxbench gl_fill says otherwise.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4868>
Rob Clark [Thu, 27 Feb 2020 18:16:43 +0000 (10:16 -0800)]
freedreno/a6xx: compressed blit fixes
width/height are not necessarily aligned to block boundaries, so we need
to round up.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4868>
Kristian H. Kristensen [Tue, 5 May 2020 07:18:35 +0000 (00:18 -0700)]
freedreno/a6xx: Set tfetch correctly for compressed formats
The fetchsize is just the blocksize for compressed formats, which gets
rid of the ASTC special cases add handles ETC1/2 as well.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4868>
Kristian H. Kristensen [Tue, 5 May 2020 07:03:18 +0000 (00:03 -0700)]
freedreno/fdl: Align after dividing by block size
For compressed formats, we need to align the number of blocks, not the
logical number of pixels in the texture. Only compressed formats have
block width/height > 1, so we can just unconditionally multiply the
alignment by the block width/height.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4868>
Eric Engestrom [Wed, 6 May 2020 21:48:26 +0000 (23:48 +0200)]
docs: update calendar for 20.1.0-rc2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4927>
Eric Anholt [Tue, 5 May 2020 19:17:49 +0000 (12:17 -0700)]
ci: Fix the nick used in IRC reporting.
robclark found that we needed unique IDs when multiple runners were trying
to report flakes at the same time, but it turns out due to nick limits (16
chars on freenode) we were just getting all the runners appended with
"-142" (or whatever the prefix of the pipelines are these days). And, for
the new flake reporting from baremetal, all the runners ended up being
just "google-freedreno".
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4896>
Eric Anholt [Tue, 5 May 2020 17:44:46 +0000 (10:44 -0700)]
ci: Improve the flakes reports on IRC.
We were incorrectly taking the merge-request on non-MR pipelines (the
master build after merge) due to a missing '$'. And, for those pipelines,
it would be nice to note whether they're for master or a stable branch.
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4896>
Eric Anholt [Fri, 1 May 2020 16:57:00 +0000 (09:57 -0700)]
ci: Enable IRC flake reporting on freedreno baremetal boards.
The IRC channel is useful for me to track and ban flaky tests before they
irritate people too much.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2654
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4896>
Eric Anholt [Mon, 4 May 2020 20:42:41 +0000 (13:42 -0700)]
ci: Clean up setup of the job-specific env vars in baremetal testing.
Avoids copy and paste errors when adding more vars.
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4896>
Marek Olšák [Wed, 6 May 2020 13:42:55 +0000 (09:42 -0400)]
radeonsi: fix compilation of monolithic PS
This was totally broken. Monolithic PS is only used if FBFETCH or
interpolateAtSample are used.
When the PS prolog was built, it overwrote ctx->main_fn.
Discovered by @eefano.
Fixes:
8832a884345686e6a8b2c0c8aa7515ad3f775b9e "radeonsi: move PS LLVM code into si_shader_llvm_ps.c"
Closes: #2814
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4918>
Marek Olšák [Tue, 5 May 2020 16:44:54 +0000 (12:44 -0400)]
tgsi_to_nir: translate non-vec4 image stores correctly
set the correct number of components for src data and the intrinsic
Reviewed-by: Rob Clark <robdclark@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4908>
Danylo Piliaiev [Fri, 27 Mar 2020 14:55:52 +0000 (16:55 +0200)]
i965: Fix out-of-bounds access to brw_stage_state::surf_offset
../src/mesa/drivers/dri/i965/brw_wm_surface_state.c:1378:32: runtime error: index
3503345872 out of bounds for type 'uint32_t [149]'
brw_assign_common_binding_table_offsets has the following comment:
"Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
unused but also make sure that addition of small offsets to them will
trigger some of our asserts that surface indices are < BRW_MAX_SURFACES."
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4350>
Erik Faye-Lund [Tue, 5 May 2020 15:04:46 +0000 (17:04 +0200)]
zink: lower b2b to b2i
Zink requires 1-bit booleans, but this requirement was missed before
b2b1s started getting automatically inserted. Let's lower these away, to
avoid piglit regressions.
Fixes the following piglits:
- shaders@glsl-vs-if-bool
- spec@!opengl 2.0@vertex-program-two-side
Fixes:
c217ee8d35f ("nir: Insert b2b1s around booleans in nir_lower_to")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2902
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4903>
Samuel Pitoiset [Thu, 30 Apr 2020 16:42:27 +0000 (18:42 +0200)]
radv/winsys: do not count visible VRAM buffers twice in the budget
The VRAM size returned to apps is computed as follows:
vram_size = real_hw_vram_size - visible_vram_size.
Visible VRAM buffers should be counted only in the visible VRAM
counter and not twice. Buffers with the NO_CPU_ACCESS flag are
known to not be mappable, so they are counted in the VRAM counter.
Other buffers, with the CPU_ACCESS flag, or without any of both
(imported buffers) are counted in the visible VRAM counter because
they are mappable.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4834>
Samuel Pitoiset [Wed, 29 Apr 2020 12:09:10 +0000 (14:09 +0200)]
radv: display an error message if the winsys init failed
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4806>
Samuel Pitoiset [Wed, 29 Apr 2020 11:53:35 +0000 (13:53 +0200)]
radv: use a linked list for physical devices
Instead of a static array inside the instance object.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4806>
Samuel Pitoiset [Wed, 29 Apr 2020 11:23:22 +0000 (13:23 +0200)]
radv: don't report error with other vendor DRM devices
Enumeration should just skip unsupported DRM devices.
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4806>
Samuel Pitoiset [Wed, 29 Apr 2020 11:24:36 +0000 (13:24 +0200)]
radv: report INITIALIZATION_FAILED when the amdgpu winsys init failed
The driver should be capable if it reaches the winsys initialization.
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4806>
Samuel Pitoiset [Wed, 29 Apr 2020 12:03:24 +0000 (14:03 +0200)]
radv: fix a memleak if the physical device initialization failed
The disk cache object should be freed.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4806>
Samuel Pitoiset [Wed, 29 Apr 2020 09:56:50 +0000 (11:56 +0200)]
radv: rename radv_devices() to radv_enumerate_physical_devices()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4806>
Samuel Pitoiset [Wed, 6 May 2020 06:25:38 +0000 (08:25 +0200)]
radv: cleanup radv_CreateInstance()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4806>
Dave Airlie [Tue, 24 Mar 2020 22:01:27 +0000 (08:01 +1000)]
llvmpipe: enable ARB_sample_shading
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4122>
Dave Airlie [Tue, 24 Mar 2020 21:57:33 +0000 (07:57 +1000)]
llvmpipe: add min samples support to the fragment shader.
This isn't enabled yet until the state gets hooked up
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4122>
Dave Airlie [Mon, 23 Mar 2020 21:48:31 +0000 (07:48 +1000)]
llvmpipe: enable GL_ARB_shader_texture_image_samples
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4122>
Dave Airlie [Mon, 23 Mar 2020 21:47:56 +0000 (07:47 +1000)]
gallivm/nir: hooks up texture samples queries
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4122>
Dave Airlie [Mon, 23 Mar 2020 21:47:16 +0000 (07:47 +1000)]
gallivm/sample: add num samples query for txqs (v2)
v2: add false to the existing users (Roland)
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4122>
Dave Airlie [Fri, 20 Mar 2020 21:40:48 +0000 (07:40 +1000)]
llvmpipe: enable 4x sample MSAA + texture multisample
This enables proper support for 4xMSAA and for texture mulitsample
extension.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4122>
Dave Airlie [Wed, 25 Mar 2020 02:47:20 +0000 (12:47 +1000)]
drisw: add multisample support to sw dri layer.
This allocates the msaa resources like the dri2 layer
and adds the flushes
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4122>
Dave Airlie [Fri, 20 Mar 2020 21:38:13 +0000 (07:38 +1000)]
llvmpipe: don't choose pixel centers for multisample
Don't pick the pixel centers for multisample rendering, fix
the setup program.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4122>
Dave Airlie [Fri, 20 Mar 2020 21:36:35 +0000 (07:36 +1000)]
llvmpipe: choose correct position for multisample
For multisample we don't want pixel centers at this stage,
so don't add them in for that case.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4122>
Dave Airlie [Fri, 20 Mar 2020 21:34:53 +0000 (07:34 +1000)]
llvmpipe: choose multisample rasterizer functions per triangle (v2)
This just picks the correct cmds to add to the scene.
v2: drop using 32-bit ms (Roland)
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4122>
Dave Airlie [Fri, 20 Mar 2020 21:29:04 +0000 (07:29 +1000)]
llvmpipe: generate multisample triangle rasterizer functions (v2)
This uses the templating to generate multisample version of the
tri plane raster functions
This doesn't generate any optimised version for lower plane numbers,
maybe this is worth doing in the future.
v2: drop generating 32-bit msaa (Roland)
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4122>
Dave Airlie [Fri, 20 Mar 2020 21:16:35 +0000 (07:16 +1000)]
llvmpipe: fixup multisample coverage masks for covered tiles
For fully covered tiles just pass in the filled out mask.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4122>
Dave Airlie [Fri, 20 Mar 2020 21:09:15 +0000 (07:09 +1000)]
llvmpipe: build 64-bit coverage mask in rasterizer
This adds the logic to build the per-sample masks at the lowest
level of the rasterizer block hierarchy
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4122>
Dave Airlie [Fri, 20 Mar 2020 21:11:39 +0000 (07:11 +1000)]
llvmpipe: add fixed point sample positions to scene.
These will be used in the rasterizer to generate the coverage masks
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4122>
Dave Airlie [Fri, 20 Mar 2020 21:07:53 +0000 (07:07 +1000)]
llvmpipe: add new rast api to pass full 64-bit mask.
The 64-bit mask is a 16-bit mask per sample for up to 4 samples.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4122>
Dave Airlie [Fri, 20 Mar 2020 20:58:01 +0000 (06:58 +1000)]
llvmpipe: disable opaque variant for multisample
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4122>
Dave Airlie [Tue, 24 Mar 2020 02:54:52 +0000 (12:54 +1000)]
llvmpipe: fix multisample occlusion queries.
This needs to check the per-sample mask inside the loop if
multisample is enabled.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4122>
Dave Airlie [Fri, 20 Mar 2020 20:54:26 +0000 (06:54 +1000)]
llvmpipe: move color storing earlier in frag shader
Move the color storage before the late Z test as for sample
shading it needs to be inside a loop with the fragment shader.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4122>
Dave Airlie [Fri, 20 Mar 2020 20:50:48 +0000 (06:50 +1000)]
llvmpipe: pass mask store into interp for centroid interpolation
This enables centroid interpolation to work, using the current
coverage masks.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4122>
Dave Airlie [Fri, 20 Mar 2020 20:47:31 +0000 (06:47 +1000)]
llvmpipe: don't allow branch to end for early Z with multisample
Don't allow the branching optimisation with multisample enabled
as we have to check all samples.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4122>
Dave Airlie [Fri, 20 Mar 2020 09:38:50 +0000 (19:38 +1000)]
llvmpipe: handle gl_SampleMask writing.
This is using a load/store to make it easier to add sample shading later.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4122>
Dave Airlie [Fri, 20 Mar 2020 09:30:06 +0000 (19:30 +1000)]
llvmpipe: add multisample alpha to one support
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4122>
Dave Airlie [Fri, 20 Mar 2020 09:28:59 +0000 (19:28 +1000)]
llvmpipe: add multisample alpha to coverage support.
Converts alpha into coverage mask.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4122>
Dave Airlie [Fri, 20 Mar 2020 04:29:46 +0000 (14:29 +1000)]
llvmpipe: hook up sample position system value
This creates a global static with the current sample positions,
and passes it to the fragment shader which uses it for interpolation
and sample position support.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4122>
Dave Airlie [Fri, 20 Mar 2020 04:10:48 +0000 (14:10 +1000)]
llvmpipe: handle multisample color stores.
Extract the final per-sample masks and store to the multisample
color buffers using them.
This retypes the pointer to a uint8_t at entry to make the
GEP simpler, then recasts to the blend type.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4122>
Dave Airlie [Wed, 25 Mar 2020 02:47:53 +0000 (12:47 +1000)]
llvmpipe: interpolate Z at sample points for early depth test.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4122>
Dave Airlie [Fri, 20 Mar 2020 04:01:54 +0000 (14:01 +1000)]
llvmpipe: handle multisample early depth test/late depth write
A set of values have to be passed from the early depth test to the
late depth write, when multisampling is enabled, a range of those
values have to be stored between stages, so create storage for them
and pass the values through the storage.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4122>
Dave Airlie [Fri, 20 Mar 2020 03:48:08 +0000 (13:48 +1000)]
llvmpipe: multisample sample mask + early/late depth pass
Start adding support for multisample masks and the depth passes
The depth passes have to run per-sample, this isn't complete support
it adds the loops, and handles the execution masks.
One mask is stored per sample, they are combined post the early Z
pass into a single shader execution mask, and then the resulting
shader execution mask is anded back in for the late Z pass.
Init the vars to NULL to avoid gcc warnings
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4122>
Dave Airlie [Fri, 20 Mar 2020 03:29:13 +0000 (13:29 +1000)]
llvmpipe: move some fs code around
this just moves the num_fs loop around for follow on refactors
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4122>
Dave Airlie [Thu, 19 Mar 2020 05:54:08 +0000 (15:54 +1000)]
llvmpipe: add per-sample depth/stencil test
The current depth stencil test code has some optimisations using
the mask when there is only one depth value, multisample requires
per-sample zstencil testing, and for that case just pass in the
mask that needs updating.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4122>
Dave Airlie [Thu, 19 Mar 2020 05:47:14 +0000 (15:47 +1000)]
llvmpipe: move getting mask value out of depth code. (v2)
In order to add per-sample support to this code, the mask
value is needed not the value from the exec mask.
v2: update comment
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4122>
Dave Airlie [Thu, 19 Mar 2020 05:40:31 +0000 (15:40 +1000)]
llvmpipe: add per-sample interpolation.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4122>
Dave Airlie [Thu, 19 Mar 2020 05:24:11 +0000 (15:24 +1000)]
llvmpipe: add centroid interpolation support.
This just adds the implementation and API to the interpolation builders.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4122>
Dave Airlie [Thu, 19 Mar 2020 04:41:22 +0000 (14:41 +1000)]
llvmpipe: pass interp location into interpolation code.
This just tracks the attribute interpolation location into the
interp code.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4122>