pan/mdg: Use I/O semantics for MRT blend stores

This avoids the silly reliance on the sideband.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>

pan/bi: Remove bi_load_sysval

It is unused and should stay unused, as any use is a violation of Ekstrand's
rule.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>

pan/bi: Lower gl_VertexID in NIR

This gets rid of the hidden gl_BaseVertex system value which violates Ekstrand's
rule.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>

pan/bi: Allow specializing bifrost_nir_options by arch

We need different settings for Bifrost and Valhall. Keeping everything static
simplifies lifetimes.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>

pan/bi: Lower load_output to make sysval explicit

See previous commits for justification. Later, we'll split up NIR processing in
a few steps to give the caller a chance to lower the sysval, at which point the
goofy inputs here will go away.

v2: Only lower in fragment shaders. Likely harmless to run elsewhere but still
wrong because the location enum is defined per-stage.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> [v1]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>

pan/bi: Lower sample mask writes in NIR

This uses the new NIR sysvals to avoid materializing magic sysvals in the
driver, getting us closer to the Ekstrand Rule.

v2: Only lower for fragment shaders. Lowering in vertex shaders should be a
no-op, except that FRAG_RESULT_SAMPLE_MASK shadows a VARYING_SLOT for fog
coords, causing v1 of this patch to regress fog. Caught by the G52 piglit job in
CI. Thank you, Marge.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> [v1]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>

pan/bi: Don't duplicate texture op cases

These two switches are redundant.

Furthermore, bi_tex_op could previously assume its input was a supported texop,
so it returned undefined values for unsupported texops. Now, without the guard
in front of it, bi_tex_op should check for supported texops, so we need to drop
the unsupported texops from the switch.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>

panfrost: Use 0/~0 boolean for MSAA sysval

For consistency with NIR.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>

nir: Add Mali load_output taking converison

Mali's LD_TILE instruction (mapping to NIR's load_output) requires a "conversion
descriptor" specifying how to convert from the register foramt to the tilebuffer
format. To implement framebuffer fetch on OpenGL without shader variants, we
generate these descriptors in the driver and pass them in a uniform. However, to
comply with the Ekstrand Rule, we can't have magically materialized system
values -- they should come only from the NIR where the driver can lower as it
pleases (e.g. PanVK can lower to a constant because it knows the framebuffer
format at pipeline create time). Add intrinsics to model this.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>

nir: Add Panfrost intrinsics to lower sample mask

We want to lower this in NIR instead of the backend IR to give the driver a
chance to lower the "is multisampled?" system value, which makes more sense to
do in NIR. This gets rid of one of the magic compiler materialized sysvals.

Plus, this will let us constant fold away the lowering in Vulkan when we know
that the pipeline is single-sampled / multi-sampled.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>

intel/dev: use GFX_VERx10 to detect genX compilation

Depending on the ordering of includes, GFX_VER may not defined for
intel_device_info.h.  The failure mode of this case is silent:
BITSET_TEST will be called when it could be compiled out.

GFX_VERx10 should be used in place of GFX_VER.  GFX_VERx10 is defined
by a compiler flag, and is always present for genX compilation units.

Fixes: 3c9a8f7a6d2 ("intel/dev: generate helpers to identify platform workarounds")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21908>

intel/dev: fix macro naming convention in gen_wa_helpers.py

intel_device_info.h tests macros in the form `INTEL_WA_{id}_GFX_VER`.
gen_wa_helpers.py produced macros in the form `INTEL_GFX_VER_WA_{id}`

Change the generated code to follow intel_device_info.h

Fixes: 3c9a8f7a6d2 ("intel/dev: generate helpers to identify platform workarounds")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21908>

intel/dev: fix macro string concatenation for INTEL_WA_{id}_GFX_VER

`INTEL_WA_##id_GFX_VER` evaluates to `INTEL_WA_id_GFX_VER`
instead of numbered identifiers like `INTEL_WA_220579888_GFX_VER`.

Fixes: 3c9a8f7a6d2 ("intel/dev: generate helpers to identify platform workarounds")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21908>

dzn: Use mesa_loge for DXIL validation errors

This allows them to be printed to OutputDebugString

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

dzn: Enable variable size bindings

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

dzn: Support descriptor indexing via bindless

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

dzn: Add a debug option for enabling bindless mode

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

dzn: Apply bindless lowering when compiling pipelines

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

dzn: Only bind descriptor sets up to the used amount of the current layout

Prevents setting a root SRV into a slot that's not declared as an SRV
in the root signature if a set is bound into a higher slot from a previous
draw/dispatch op.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

dzn: Ensure root signatures are re-bound after a meta op

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

dzn: When binding a bindless root signature, bind descriptor heaps first

The D3D spec says it must be so, and not doing this causes problems
on some hardware.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

dzn: Add a binding classification in the pipeline layout remapping

This is needed so that we can handle two special cases:
* Dynamic buffer data is allocated out of a command-buffer-owned buffer,
  rather than a descriptor-set-owned buffer, so the remapping puts them
  in their own register space.
* Static samplers should be left alone and not converted to bindless.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

dzn: Bind buffers for bindless descriptor sets

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

dzn: Use separate dirty bits for descriptor sets/dynamic buffers

We'll be able to take advantage of this granularity in bindless mode

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

dzn: Don't dirty bindings if root signature doesn't change

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

dzn: Allocate descriptor sets in buffers for bindless mode

Modify the root signature stored in the pipeline layout too.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

dzn: Delete unused function

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

dzn: Remove defragmenting of descriptor pools

Rather than trying to perfectly defrag, let's just allow re-use.
When a set is allocated for the first time, it locks in its range of
the heap that it'll use. If the last set in the heap is used, then
those descriptors go back to being free, but if a set in the middle
of the heap is freed, those descriptors remain assigned to that set.
A later allocation attempt can reclaim them, as long as the new set
fits.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

dzn: When bindless, only allocate one descriptor per layout entry

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

dzn: Add initial bindless infrastructure

When operating in "bindless" mode, the device will own 2 descriptor
heaps, one for views, and one for samplers. Every time a view is
created (image view, buffer view), a slot is allocated for it out
of the device view heap for each usage type (sampled vs storage).

Then, in a future change, descriptor sets will just contain view/
sampler indices instead of actual descriptors. Instead of copying
these to a cmdbuf-owned descriptor heap, we can directly bind the
descriptor set as a buffer. We'll also modify shaders to perform
an indirection and index into the device heap.

Buffers also get views set up on creation. In a perfect world, we
could just put addresses/sizes in the descriptor set, but DXIL
doesn't support loading from addresses, we need descriptors. When
robust buffer access is disabled *or* descriptor set buffer views
reference the remainder of the buffer, we can just re-use a view
from the buffer and use an offset.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

dzn: Skip setting up UAVs for depth resources

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

dzn: Set up SRV descs for 3D textures correctly

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

dzn: Don't use plane slice 1 for depth+stencil SRVs

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

dzn: Consistently order depth formats before stencil

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

dzn: Put UAVs first for storage images/buffers in descriptor tables

When running in a bindless mode, we won't ever be using SRVs for these.
Change terminology for determining descriptor offsets from "writable"
to "alt" to match naming already used elsewhere.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

dzn: Add some docs around descriptor sets and remove redundant/unused data

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

dzn: Fix a leak in descriptor set layout creation

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

dzn: Remove descriptor heap type from descriptor heap wrapper

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

dzn: Remove device pointers from descriptor heaps

A future change is going to add descriptor heaps *to* the dzn_device,
and having 3x ID3D12Device pointers in a single object just seems
wrong. All of the callers already had a device, so just pass it
along where needed.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

spirv2dxil: Support descriptor indexing capabilities

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

spirv2dxil: Only lower readonly images to SRVs when the option is set

This handles the case where readonly is explicitly marked in the shader,
rather than just inferred based on opt_access.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

spirv2dxil: Add a pass to lower deref tex/image and vulkan ubo/ssbo to bindless

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

microsoft/compiler: Update header docs for binding modes supported by compiler

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

microsoft/compiler: Use store_dest instead of store_dest_value more

The 16bit SSBO load support missed setting the 16bit shader flag.
Make it harder to miss that by only using store_dest_value for things
that don't have a type.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

microsoft/compiler: Support descriptor heap indexing for UBO/SSBO

Treat load_vulkan_descriptor on an input that didn't come from
vulkan_resource_index as a descriptor heap index instead of a
binding index.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

microsoft/compiler: Handle "bindless" image/tex sources as heap indices

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

microsoft/compiler: Split handle annotation into two parts

The first part gets the resource props struct, and the second
actually emits the annotate instruction. Later changes will
get the resource props struct from different sources.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

microsoft/compiler: Add helpers for getting res_props structs

Currently we can get one by looking up already-emitted resource
metadata, but in the future we'll want to be able to get this
info from a call site alone. Depending on the type of call site,
we'll have different sets of info, so add helpers for the
various different kinds of call sites we can support.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

microsoft/compiler: Refactor type -> resource kind helper

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

microsoft/compiler: Only set typed UAV load feature bit for multi-comp loads

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

microsoft/compiler: Fix setting bit 31 in feature flags

Fixes: a84208ee ("microsoft/compiler: Fill out and sort the shader/module flags")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21913>

intel/fs: use generated helpers for Wa_14013363432 / Wa_14012688258

Wa_14013363432 is a clone of Wa_14012688258.  It does not apply to all
gfx 12.5 platforms.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21745>

freedreno/decode: fix possible overflow

```
../src/freedreno/decode/rddecompiler.c:242:65: error: 'sscanf' may overflow; destination buffer in argument 3 has size 32, but the corresponding specifier may require size 33 [-Werror,-Wfortify-source]
         if (sscanf(info->name, "%32[A-Z0-6_][%32[x0-9]].%32s", reg_name,
                                                                ^
../src/freedreno/decode/rddecompiler.c:243:21: error: 'sscanf' may overflow; destination buffer in argument 4 has size 32, but the corresponding specifier may require size 33 [-Werror,-Wfortify-source]
                    reg_idx, field_name) != 3) {
                    ^
../src/freedreno/decode/rddecompiler.c:243:30: error: 'sscanf' may overflow; destination buffer in argument 5 has size 32, but the corresponding specifier may require size 33 [-Werror,-Wfortify-source]
                    reg_idx, field_name) != 3) {
                             ^
```

Reviewed-by: Rob Clark <robclark@freedesktop.org>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22015>

ci/freedreno: do not build tools executables without explicitly enabling them

Reviewed-by: Rob Clark <robclark@freedesktop.org>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22015>

d3d12: Remove now-unused UAV format from shader info

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22093>

d3d12: Fix buffer SRV/UAV creation

Get the format right for UAVs (using the image view instead of
relying on the shader having a format specified) and limit the size
to the API-reported size.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22093>

d3d12: Report correct texel buffer max size

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22093>

microsoft/compiler: Handle writable buffer UAV size queries

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22093>

d3d12: Encode - Only upload headers when written headers size is > 0

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22091>

d3d12: Encode H264/HEVC - Do not write PPS unless different from active

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22091>

d3d12: H264/HEVC Encode - Set both VBV InitialCapacity/Size in CBR Rate Control to same value when requested

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22091>

freedreno/rnn: Fix reg names for regs with variants

Fixes reg names with headergen2, so that if we have separate a6xx and
a7xx variants for a register we get REG_A6XX_foo and REG_A7XX_foo
instead of both being REG_A6XX_foo.  Otherwise generated headers for the
kernel wouldn't compile.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22035>

freedreno, nir, ir3: implement GL_EXT_shader_framebuffer_fetch

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21260>

nir: Add memory coherency information to shaders.

Signed-off-by: Amber Amber <amber@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21260>

nir: allow nir_lower_fb_read to support multiple render targets

Signed-off-by: Amber Amber <amber@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21260>

tu: Fix tile_align_h on a650

This matches what the blob on a650 does and fixes errors when
calculating the tile size due to tile_align_h not being a power of two.

Fixes: 60bc7c0e ("freedreno: Specify GMEM tile alignment per GPU")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22088>

v3d: add link to issue investigating failure

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22089>

frontends/va: check decoder in va surface call

Add a check to see if decoder is valid before using it. Currently we
only support decode and encode operations, return unsupported error
for all other entrypoints.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21905>

anv: Implement Xe version of execute_simple_batch()

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22058>

anv: Handle Xe queue/engine priority

As Xe requires engine info, it is not possible to fetch max priority
from anv_physical_device_get_parameters() call chain, so here
anv_xe_physical_device_max_priority_update() was added.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22058>

anv: Implement Xe version of check_status()

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22058>

anv: Create Xe engines

Xe engine is not equal to hardware engine, it is just a submission
queue that will be scheduled in the hardware engine during process
time slice of the GPU.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22058>

anv: Replace I915_ENGINE_CLASS_VIDEO by INTEL_ENGINE_CLASS_VIDEO

Using the value that is not dependent on the KMD uapi.

Not marking as a fixes because both have the same value, so we
don't need a backport.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22058>

radv: Enable mesh shading on GFX11.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21409>

ac/nir/ngg: Store special MS outputs in attribute ring for PS to read.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21409>

ac/nir/ngg: Fix mesh shader layer on GFX11.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21409>

ac/nir/ngg: Split legacy workgroup index function.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21409>

ac/nir/ngg: Use attribute ring for mesh shader params.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21409>

ac/nir/ngg: Clarify mesh shader scratch ring.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21409>

radv: Adjust mesh draw packets for GFX11.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21409>

radv: Include per-prim params in NUM_INTERP on GFX11.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21409>

radv: Use PRIM_ATTR for PS inputs on GFX11.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21409>

radv: Add extra offset to per-prim params.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21409>

radv: Use per-prim params in has_param_exports.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21409>

radv: Add per-prim attributes to ring_attr stride.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21409>

radv: Use new mesh shading packet defines.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21409>

ac: Add more defines for mesh shading packets.

Add some set macro defines for mesh shading packets.
The naming convention is:
S_(packet opcode)(dword index)_FIELD_NAME

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21409>

ci: bump Alpine to 3.17 (again)

Now with fixed ccache 4.7.5.

`ccache` changelog:
Disabled the inode cache by default again since there have reports of ccache
processes hanging on futex calls related to the inode cache.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22037>

v3d: fix condition for EZ disabling when stencil on

When stencil is enabled and it isn't non-op, Early-Z must be disabled.

The condition that checks this for stencil[0] is correct, but the one
for stencil[1] is wrong: it uses an "and" instead of "or" condition.

This affects dEQP-GLES3.functional.fragment_ops.interaction.basic_shader.14

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22081>

intel/dev: fold Gfx12 URB entries in Gfx12 HW info

Also add a non-zero URB size for intel_stub_gpu

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21949>

intel/devinfo: initialize pci_device_id with from_pci_id()

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Suggested-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21949>

intel/devinfo: dedicated entries for XeHP

Also fixing the max URB entries for VS stage.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reported-by: Chuansheng Liu <chuansheng.liu@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21949>

intel/dev: use generated WA helpers for Wa_22012575642

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21949>

intel/devinfo: printout URB entries

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21949>

intel/devinfo: add an option to pick platform to print

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21949>

ci/windows: Update warp to 1.0.5

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22034>

ac/llvm: add missing type convert for nir_load_buffer_amd

Fixes: afcbccb0781 ("ac/llvm: implement ACCESS_USE_FORMAT_AMD as buffer_load/store_format")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22043>

ac/llvm: respect channel_type when ac_build_buffer_load

Mainly for nir_load_smem_buffer_amd which pass i32 for this parameter.

Fixes: 8030fbcf16a ("nir,ac/llvm: add nir_load_smem_buffer_amd")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22043>

glsl: Write a new test for GLSL and NIR mediump lowering.

The mediump lowering tests are important for poking at the lowering pass
behavior, since you can't really assert the behavior in any given driver,
given that the GLSL spec allows any mediump op to be done in highp.

But, in hacking on mediump lowering, I wanted several things that the old
test couldn't do:

- Be able to assert about the actual NIR code we expect to generate for a
  hypothetical driver (important if other compiler stages might do invalid
  transformations like eliminating highp temps, or if we were to move the
  lowering after GLSL IR)
- Run faster (gtest unit tests rather than python forking off the standalone
  glsl compiler per testcase).
- Express expectations with a lot less escaping of typical syntax.
- High-quality logs for displaying failures.

This new test does all of that, I think, though I haven't converted all of
the unit tests over yet.  In converting, I dropped some of the
combinatorial explosion for float/int variations, instead only doing so
when it gets at some different code path (default precision flags).  I've
also included some new tests I wrote in the process of writing my proposed
gl_nir mediump lowering.

Even if the conversion isn't complete, getting these tests to run faster
is probably a good idea on its own, for anyone iterating running Mesa's
unit tests (80 tests in 25ms, compared to 109 tests in 1.5s!).

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21886>

glsl/standalone: Make all standalone contexts have NewProgram set.

It was in the standalone compiler but not unit tests.  Only the standalone
compiler had done linking and needed it, so far.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21886>