Tobias Burnus [Wed, 15 Feb 2023 10:20:32 +0000 (11:20 +0100)]
libgomp: Fix reverse-offload for GOMP_MAP_TO_PSET
libgomp/
* target.c (gomp_target_rev): Dereference ptr
to get device address.
* testsuite/libgomp.fortran/reverse-offload-5.f90: Add test
for unallocated allocatable.
Tobias Burnus [Wed, 15 Feb 2023 10:17:40 +0000 (11:17 +0100)]
libgomp: Fix 'target enter data' with always pointer
As GOMP_MAP_ALWAYS_POINTER operates on the previous map item, ensure that
with 'target enter data' both are passed together to gomp_map_vars_internal.
libgomp/ChangeLog:
* target.c (gomp_map_vars_internal): Add 'i > 0' before doing a
kind check.
(GOMP_target_enter_exit_data): If the next map item is
GOMP_MAP_ALWAYS_POINTER map it together with the current item.
* testsuite/libgomp.fortran/target-enter-data-3.f90: New test.
Jakub Jelinek [Wed, 15 Feb 2023 08:56:47 +0000 (09:56 +0100)]
powerpc: Fix up expansion for WIDEN_MULT_PLUS_EXPR [PR108787]
WIDEN_MULT_PLUS_EXPR as documented has the factor operands with
the same precision and the addend and result another one at least twice
as wide.
Similarly, {,u}maddMN4 is documented as
'maddMN4'
Multiply operands 1 and 2, sign-extend them to mode N, add operand
3, and store the result in operand 0. Operands 1 and 2 have mode M
and operands 0 and 3 have mode N. Both modes must be integer or
fixed-point modes and N must be twice the size of M.
In other words, 'maddMN4' is like 'mulMN3' except that it also adds
operand 3.
These instructions are not allowed to 'FAIL'.
'umaddMN4'
Like 'maddMN4', but zero-extend the multiplication operands instead
of sign-extending them.
The PR103109 addition of these expanders to rs6000 didn't handle this
correctly though, it treated the last argument as also having mode M
sign or zero extended into N. Unfortunately this means incorrect code
generation whenever the last operand isn't really sign or zero extended
from DImode to TImode.
The following patch removes maddditi4 expander altogether from rs6000.md,
because we'd need
maddhd 9,3,4,5
sradi 10,5,63
maddld 3,3,4,5
sub 9,9,10
add 4,9,6
which is longer than
mulld 9,3,4
mulhd 4,3,4
addc 3,9,5
adde 4,4,6
and nothing would be able to optimize the case of last operand already
sign-extended from DImode to TImode into just
mr 9,3
maddld 3,3,4,5
maddhd 4,9,4,5
or so. And fixes umaddditi4, so that it emits an add at the end to add
the high half of the last operand, fortunately in this case if the high
half of the last operand is known to be zero (i.e. last operand is zero
extended from DImode to TImode) then combine will drop the useless add.
If we wanted to get back the signed op1 * op2 + op3 all in the DImode
into TImode op0, we'd need to introduce a new tree code next to
WIDEN_MULT_PLUS_EXPR and maddMN4 expander, because I'm afraid it can't
be done at expansion time in maddMN4 expander to detect whether the
operand is sign extended especially because of SUBREGs and the awkwardness
of looking at earlier emitted instructions, and combine would need 5
instruction combination.
2023-02-15 Jakub Jelinek <jakub@redhat.com>
PR target/108787
PR target/103109
* config/rs6000/rs6000.md (<u>maddditi4): Change into umaddditi4 only
expander, change operand 3 to be TImode, emit maddlddi4 and
umadddi4_highpart{,_le} with its low half and finally add the high
half to the result.
* gcc.dg/pr108787.c: New test.
* gcc.target/powerpc/pr108787.c: New test.
* gcc.target/powerpc/pr103109-1.c: Adjust expected instruction counts.
Martin Liska [Wed, 15 Feb 2023 08:37:59 +0000 (09:37 +0100)]
docs: document new --param=asan-kernel-mem-intrinsic-prefix
gcc/ChangeLog:
* doc/invoke.texi: Document --param=asan-kernel-mem-intrinsic-prefix.
Jakub Jelinek [Wed, 15 Feb 2023 08:34:41 +0000 (09:34 +0100)]
c++: Add testcases from some Issaquah DRs
The following patch adds testcases for 5 DRs. In the DR2475, DR2530 and
CWG2691 my understanding is we already implement the desired behavior,
in DR2478 partially (I've added 2 dg-bogus there, I think we inherit
rather than overwrite DECL_DECLARED_CONSTINIT_P for explicit specialization
somewhere, still far better than clang++) and DR2673 on the other side the
DR was to codify the clang++ behavior rather than GCC.
Not 100% sure if it is better to commit the 2 with dg-bogus or just wait
until the actual fixes are implemented. BTW, I've noticed
register_specialization does:
FOR_EACH_CLONE (clone, fn)
{
DECL_DECLARED_INLINE_P (clone)
= DECL_DECLARED_INLINE_P (fn);
DECL_SOURCE_LOCATION (clone)
= DECL_SOURCE_LOCATION (fn);
DECL_DELETED_FN (clone)
= DECL_DELETED_FN (fn);
}
but not e.g. constexpr/consteval, have tried to cover that in a testcase
but haven't managed to do so.
2023-02-15 Jakub Jelinek <jakub@redhat.com>
* g++.dg/DRs/dr2475.C: New test.
* g++.dg/DRs/dr2478.C: New test.
* g++.dg/DRs/dr2530.C: New test.
* g++.dg/DRs/dr2673.C: New test.
* c-c++-common/cpp/delimited-escape-seq-8.c: New test.
Richard Biener [Tue, 14 Feb 2023 15:14:51 +0000 (16:14 +0100)]
Fix possible sanopt compile-time hog
While working on bitmap operations I figured sanopt.cc uses
a sbitmap worklist, iterating using bitmap_first_set_bit on it.
That's quadratic since bitmap_first_set_bit for sbitmap is O(n).
The fix is to use regular bitmaps for the worklist and the bitmap
feeding it and to avoid a useless copy.
* sanopt.cc (sanitize_asan_mark_unpoison): Use bitmap
for with_poison and alias worklist to it.
(sanitize_asan_mark_poison): Likewise.
Richard Biener [Thu, 9 Feb 2023 12:40:43 +0000 (13:40 +0100)]
target/108738 - optimize bit operations in STV
The following does low-hanging optimizations, combining bitmap
test and set and removing redundant operations.
PR target/108738
* config/i386/i386-features.cc (scalar_chain::add_to_queue):
Combine bitmap test and set.
(scalar_chain::add_insn): Likewise.
(scalar_chain::analyze_register_chain): Remove redundant
attempt to add to queue and instead strengthen assert.
Sink common attempts to mark the def dual-mode.
(scalar_chain::add_to_queue): Remove redundant insn bitmap
check.
Richard Biener [Thu, 9 Feb 2023 10:03:25 +0000 (11:03 +0100)]
target/108738 - STV bitmap operations compile-time hog
When the set of candidates becomes very large then repeated
bit checks on it during the build of an actual chain can become
slow because of the O(n) nature of bitmap tests. The following
switches the candidates bitmaps to the tree representation before
building the chains to get O(log n) amortized behavior.
For the testcase at hand this improves STV time by 50%.
PR target/108738
* config/i386/i386-features.cc (convert_scalars_to_vector):
Switch candidates bitmaps to tree view before building the chains.
GCC Administrator [Wed, 15 Feb 2023 00:17:49 +0000 (00:17 +0000)]
Daily bump.
Hans-Peter Nilsson [Wed, 15 Feb 2023 00:15:43 +0000 (01:15 +0100)]
gen_reload: Correct parameter for fatal_insn call
Observed when disabling LEGITIMIZE_RELOAD_ADDRESS for
cris-elf: the current code doesn't handle the post-cc0
parallel-with-clobber-of-cc0 sets, dropping down into the
fatal_insn call. Following the code, it's obvious that the
variable "set" is always NULL at the call. The intended
parameter is "in".
* reload1.cc (gen_reload): Correct rtx parameter for fatal_insn
"failure trying to reload" call.
Hans-Peter Nilsson [Wed, 15 Feb 2023 00:09:06 +0000 (01:09 +0100)]
debug: Support "phrs" for dumping a HARD_REG_SET
The debug-function in sel-sched-dump.cc that would be
suitable for a hookup to a command in gdb is guarded by
#ifdef INSN_SCHEDULING, thus can't be used for all targets.
Better move the function marked DEBUG_FUNCTION elsewhere,
here to a file with a suitable static function to call.
There are multiple sets of similar functions dumping
HARD_REG_SETs, but cleaning that up is better left to a
separate commit.
gcc:
* gdbinit.in (phrs): New command.
* sel-sched-dump.cc (debug_hard_reg_set): Remove debug-function.
* ira-color.cc (debug_hard_reg_set): New, calling print_hard_reg_set.
Marek Polacek [Fri, 10 Feb 2023 22:26:57 +0000 (17:26 -0500)]
c++: fix ICE in joust_maybe_elide_copy [PR106675]
joust_maybe_elide_copy checks that the last conversion in the ICS for
the first argument is ck_ref_bind, which is reasonable, because we've
checked that we're dealing with a copy/move constructor. But it can
also happen that we couldn't figure out which conversion function is
better to convert the argument, as in this testcase: joust couldn't
decide if we should go with
operator foo &()
or
operator foo const &()
so we get a ck_ambig, which then upsets joust_maybe_elide_copy. Since
a ck_ambig can validly occur, I think we should just return early, as
in the patch below.
PR c++/106675
gcc/cp/ChangeLog:
* call.cc (joust_maybe_elide_copy): Return false for ck_ambig.
gcc/testsuite/ChangeLog:
* g++.dg/cpp0x/overload-conv-5.C: New test.
David Faust [Tue, 14 Feb 2023 19:23:01 +0000 (11:23 -0800)]
bpf: fix memory constraint of ldx/stx instructions [PR108790]
In some cases where the target memory address for an ldx or stx
instruction could be reduced to a constant, GCC could emit a malformed
instruction like:
ldxdw %r0,0
Rather than the expected form:
ldxdw %rX, [%rY + OFFSET]
This is due to the constraint allowing a const_int operand, which the
output templates do not handle.
Fix it by introducing a new memory constraint for the appropriate
operands of these instructions, which is identical to 'm' except that
it does not accept const_int.
gcc/
PR target/108790
* config/bpf/constraints.md (q): New memory constraint.
* config/bpf/bpf.md (zero_extendhidi2): Use it here.
(zero_extendqidi2): Likewise.
(zero_extendsidi2): Likewise.
(*mov<MM:mode>): Likewise.
gcc/testsuite/
PR target/108790
* gcc.target/bpf/ldxdw.c: New test.
Andrew Pinski [Tue, 31 Jan 2023 05:03:21 +0000 (05:03 +0000)]
Simplify "1 - bool_val" to "bool_val ^ 1"
For bool values, it is easier to deal with
xor 1 rather than having 1 - a. This is because
we are more likely to simplify the xor further in many
cases.
This is a special case for (MASK - b) where MASK
is a powerof2 - 1 and b <= MASK but only for bool
ranges ([0,1]) as that is the main case where the
difference comes into play.
Note this is enabled for gimple folding only
as the ranges are only know while doing gimple
folding and cfun is not always set when fold is called.
OK? Bootstrapped and tested on x86_64-linux-gnu with no
regressions.
gcc/ChangeLog:
PR tree-optimization/108355
PR tree-optimization/96921
* match.pd: Add pattern for "1 - bool_val".
gcc/testsuite/ChangeLog:
PR tree-optimization/108355
PR tree-optimization/96921
* gcc.dg/tree-ssa/bool-minus-1.c: New test.
* gcc.dg/tree-ssa/bool-minus-2.c: New test.
* gcc.dg/tree-ssa/pr108354-1.c: New test.
Gerald Pfeifer [Tue, 14 Feb 2023 21:16:44 +0000 (22:16 +0100)]
libstdc++: Update an open-std.org link
libstdc++-v3/ChangeLog:
* doc/xml/manual/status_cxx2017.xml: Update an open-std.org link
to www.open-std.org and https.
* doc/html/manual/status.html: Regenerate.
Richard Biener [Tue, 14 Feb 2023 13:51:48 +0000 (14:51 +0100)]
Improve VN PHI hash table handling
The hash function of PHIs is weak since we want to be able to CSE
them even across basic-blocks in some cases. The following avoids
weakening the hash for cases we are never going to CSE, reducing
the number of collisions and avoiding redundant work in the
hash and equality functions.
* tree-ssa-sccvn.cc (vn_phi_compute_hash): Key skipping
basic block index hashing on the availability of ->cclhs.
(vn_phi_eq): Avoid re-doing sanity checks for CSE but
rely on ->cclhs availability.
(vn_phi_lookup): Set ->cclhs only when we are eventually
going to CSE the PHI.
(vn_phi_insert): Likewise.
Eric Botcazou [Tue, 14 Feb 2023 12:27:18 +0000 (13:27 +0100)]
Fix small regression in Ada
gcc/
* gimplify.cc (gimplify_save_expr): Add missing guard.
gcc/ada/
* gcc-interface/trans.cc (gnat_gimplify_expr): Add missing guard.
gcc/testsuite/
* gnat.dg/shift2.adb: New test.
Dongsheng Song [Tue, 14 Feb 2023 11:51:29 +0000 (12:51 +0100)]
Fix musl build on Linux
The commit "ada: Add PIE support to backtraces on Linux" uses
_r_debug under Linux unconditionally. It is incorrect since musl
libc does not define _r_debug like glibc.
gcc/ada/
* adaint.c [Linux]: Include <features.h>.
(__gnat_get_executable_load_address) [Linux]: Enable only for
glibc and uClibc.
Richard Biener [Tue, 14 Feb 2023 10:10:56 +0000 (11:10 +0100)]
tree-optimization/108782 - nested first order recurrence vectorization
First order recurrence vectorization isn't possible for nested
loops.
PR tree-optimization/108782
* tree-vect-loop.cc (vect_phi_first_order_recurrence_p):
Make sure we're not vectorizing an inner loop.
* gcc.dg/torture/pr108782.c: New testcase.
Jakub Jelinek [Tue, 14 Feb 2023 11:10:09 +0000 (12:10 +0100)]
asan: Add --param=asan-kernel-mem-intrinsic-prefix= [PR108777]
While in the -fsanitize=address case libasan overloads memcpy, memset,
memmove and many other builtins, such that they are always instrumented,
Linux kernel for -fsanitize=kernel-address recently changed or is changing,
such that memcpy, memset and memmove actually aren't instrumented because
they are often used also from no_sanitize ("kernel-address") functions
and wants __{,hw,}asaN_{memcpy,memset,memmove} to be used instead
for the instrumented calls. See e.g. the https://lkml.org/lkml/2023/2/9/1182
thread. Without appropriate support on the compiler side, that will mean
any time a kernel-address instrumented function (most of them) calls
memcpy/memset/memmove, they will not be instrumented and thus won't catch
kernel bugs. Apparently clang 15 has a param for this.
The following patch implements the same (except it is a usual GCC --param,
not -mllvm argument) on the GCC side. I know this isn't a regression
bugfix, but given that -fsanitize=kernel-address has a single project that
uses it which badly wants this I think it would be worthwhile to make an
exception and get this into GCC 13 rather than waiting another year, it
won't affect non-kernel code, nor even the kernel unless the new parameter
is used.
2023-02-14 Jakub Jelinek <jakub@redhat.com>
PR sanitizer/108777
* params.opt (-param=asan-kernel-mem-intrinsic-prefix=): New param.
* asan.h (asan_memfn_rtl): Declare.
* asan.cc (asan_memfn_rtls): New variable.
(asan_memfn_rtl): New function.
* builtins.cc (expand_builtin): If
param_asan_kernel_mem_intrinsic_prefix and function is
kernel-{,hw}address sanitized, emit calls to
__{,hw}asan_{memcpy,memmove,memset} rather than
{memcpy,memmove,memset}. Use sanitize_flags_p (SANITIZE_ADDRESS)
instead of flag_sanitize & SANITIZE_ADDRESS to check if
asan_intercepted_p functions shouldn't be expanded inline.
* gcc.dg/asan/pr108777-1.c: New test.
* gcc.dg/asan/pr108777-2.c: New test.
* gcc.dg/asan/pr108777-3.c: New test.
* gcc.dg/asan/pr108777-4.c: New test.
* gcc.dg/asan/pr108777-5.c: New test.
* gcc.dg/asan/pr108777-6.c: New test.
* gcc.dg/completion-3.c: Adjust expected multiline output.
Andreas Schwab [Thu, 9 Feb 2023 09:40:39 +0000 (10:40 +0100)]
testsuite: adjust patterns in RISC-V tests to skip unwind table directives
gcc/testsuite/
PR target/108723
* gcc.target/riscv/shorten-memrefs-1.c: Adjust patterns to skip
over cfi directives.
* gcc.target/riscv/shorten-memrefs-2.c: Likewise.
* gcc.target/riscv/shorten-memrefs-3.c: Likewise.
* gcc.target/riscv/shorten-memrefs-4.c: Likewise.
* gcc.target/riscv/shorten-memrefs-5.c: Likewise.
* gcc.target/riscv/shorten-memrefs-6.c: Likewise.
* gcc.target/riscv/shorten-memrefs-8.c: Likewise.
Thomas Schwinge [Tue, 14 Feb 2023 09:11:19 +0000 (10:11 +0100)]
nvptx: Adjust 'scan-assembler' in 'gfortran.dg/weak-1.f90'
Fix-up for recent commit
086a1df4374962787db37c1f0d1bd9beb828f9e3
"Fortran: Add !GCC$ attributes NOINLINE,NORETURN,WEAK".
gcc/testsuite/
* gfortran.dg/weak-1.f90: Adjust 'scan-assembler' for nvptx.
Richard Sandiford [Tue, 14 Feb 2023 09:18:07 +0000 (09:18 +0000)]
vect: Make partial trapping ops use predication [PR96373]
PR96373 points out that a predicated SVE loop currently converts
trapping unconditional ops into unpredicated vector ops. Doing
the operation on inactive lanes can then raise an exception.
As discussed in the PR trail, we aren't 100% consistent about
whether we preserve traps or not. But the direction of travel
is clearly to improve that rather than live with it. This patch
tries to do that for the SVE case.
Doing this regresses gcc.target/aarch64/sve/fabd_1.c. I've added
-fno-trapping-math for now and filed PR108571 to track it.
A similar problem applies to fsubr_1.c.
I think this is likely to regress Power 10, since conditional
operations are only available for masked loops. I think we'll
need to add -fno-trapping-math to any affected testcases,
but I don't have a Power 10 system to test on.
gcc/
PR tree-optimization/96373
* tree-vect-stmts.cc (vectorizable_operation): Predicate trapping
operations on the loop mask. Reject partial vectors if this isn't
possible.
gcc/testsuite/
PR tree-optimization/96373
PR tree-optimization/108571
* gcc.target/aarch64/sve/fabd_1.c: Add -fno-trapping-math.
* gcc.target/aarch64/sve/fsubr_1.c: Likewise.
* gcc.target/aarch64/sve/fmul_1.c: Expect predicate ops.
* gcc.target/aarch64/sve/fp_arith_1.c: Likewise.
Kewen Lin [Tue, 14 Feb 2023 02:03:26 +0000 (20:03 -0600)]
rs6000/test: Adjust some test cases on partial vector [PR96373]
As Richard pointed out in [1] and the testing on Power10, the
proposed fix for PR96373 requires some updates on a few rs6000
test cases which adopt partial vector. This patch is to fix
all of them with one extra option "-fno-trapping-math" as
Richard suggested.
Besides, the original test case also failed on Power10 without
Richard's proposed fix, this patch adds it together for a bit
better testing coverage.
[1] https://gcc.gnu.org/pipermail/gcc-patches/2023-January/610728.html
PR target/96373
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/p9-vec-length-epil-1.c: Add -fno-trapping-math.
* gcc.target/powerpc/p9-vec-length-epil-2.c: Likewise.
* gcc.target/powerpc/p9-vec-length-epil-3.c: Likewise.
* gcc.target/powerpc/p9-vec-length-epil-4.c: Likewise.
* gcc.target/powerpc/p9-vec-length-epil-5.c: Likewise.
* gcc.target/powerpc/p9-vec-length-epil-6.c: Likewise.
* gcc.target/powerpc/p9-vec-length-epil-8.c: Likewise.
* gcc.target/powerpc/p9-vec-length-full-1.c: Likewise.
* gcc.target/powerpc/p9-vec-length-full-2.c: Likewise.
* gcc.target/powerpc/p9-vec-length-full-3.c: Likewise.
* gcc.target/powerpc/p9-vec-length-full-4.c: Likewise.
* gcc.target/powerpc/p9-vec-length-full-5.c: Likewise.
* gcc.target/powerpc/p9-vec-length-full-6.c: Likewise.
* gcc.target/powerpc/p9-vec-length-full-8.c: Likewise.
* gcc.target/powerpc/pr96373.c: New test.
Thomas W Rodgers [Fri, 10 Feb 2023 18:09:06 +0000 (10:09 -0800)]
libstdc++: Add missing free functions for atomic_flag [PR103934]
This patch adds -
atomic_flag_wait
atomic_flag_wait_explicit
atomic_flag_notify
atomic_flag_notify_explicit
Which were missed when commit 83a1be introduced C++20 atomic wait.
libstdc++-v3/ChangeLog:
PR libstdc++/103934
* include/std/atomic (atomic_flag_wait): Add.
(atomic_flag_wait_explicit): Add.
(atomic_flag_notify): Add.
(atomic_flag_notify_explicit): Add.
* testsuite/29_atomics/atomic_flag/wait_notify/1.cc:
Add test case to cover missing atomic_flag free functions.
Thomas W Rodgers [Fri, 10 Feb 2023 17:35:11 +0000 (09:35 -0800)]
libstdc++: Add missing free functions for atomic_flag [PR103934]
This patch adds -
atomic_flag_test
atomic_flag_test_explicit
Which were missed when commit 491ba6 introduced C++20 atomic flag
test.
libstdc++-v3/ChangeLog:
PR libstdc++/103934
* include/std/atomic (atomic_flag_test): Add.
(atomic_flag_test_explicit): Add.
* testsuite/29_atomics/atomic_flag/test/explicit.cc: Add
test case to cover missing atomic_flag free functions.
* testsuite/29_atomics/atomic_flag/test/implicit.cc:
Likewise.
GCC Administrator [Tue, 14 Feb 2023 00:17:33 +0000 (00:17 +0000)]
Daily bump.
Lorenzo Salvadore [Mon, 13 Feb 2023 23:28:11 +0000 (00:28 +0100)]
d: Update __FreeBSD_version values [PR107469]
Update __FreeBSD_version values for the latest supported FreeBSD
versions. In particular, add __FreeBSD_version for FreeBSD 14, which
is necessary to compile libphobos successfully on FreeBSD 14.
libphobos/ChangeLog:
PR d/107469
* libdruntime/core/sys/freebsd/config.d: Update __FreeBSD_version.
Gerald Pfeifer [Mon, 13 Feb 2023 22:30:37 +0000 (23:30 +0100)]
libstdc++: Adjust "The Component Object Model" reference
libstdc++-v3/ChangeLog:
* doc/xml/manual/policy_data_structures_biblio.xml: Adjust
"The Component Object Model" reference.
* doc/html/manual/policy_data_structures.html: Regenerate.
Richard Sandiford [Mon, 13 Feb 2023 21:13:59 +0000 (21:13 +0000)]
lra: Replace subregs in bare uses & clobbers [PR108681]
In this PR we had a write to one vector of a 4-vector tuple.
The vector had mode V1DI, and the target doesn't provide V1DI
moves, so this was converted into:
(clobber (subreg:V1DI (reg/v:V4x1DI 92 [ b ]) 24))
followed by a DImode move. (The clobber isn't really necessary
or helpful for a single word, but would be for wider moves.)
The subreg in the clobber survived until after RA:
(clobber (subreg:V1DI (reg/v:V4x1DI 34 v2 [orig:92 b ] [92]) 24))
IMO this isn't well-formed. If a subreg of a hard register simplifies
to a hard register, it should be replaced by the hard register. If the
subreg doesn't simplify, then target-independent code can't be sure
which parts of the register are affected and which aren't. A clobber
of such a subreg isn't useful and (again IMO) should just be removed.
Conversely, a use of such a subreg is effectively a use of the whole
inner register.
LRA has code to simplify subregs of hard registers, but it didn't
handle bare uses and clobbers. The patch extends it to do that.
One question was whether the final_p argument to alter_subregs
should be true or false. True is IMO dangerous, since it forces
replacements that might not be valid from a dataflow perspective,
and uses and clobbers only exist for dataflow. As said above,
I think the correct way of handling a failed simplification would
be to delete clobbers and replace uses of subregs with uses of
the inner register. But I didn't want to write untested code
to do that.
In the PR, the clobber caused an infinite loop in DCE, because
of a disagreement about what effect the clobber had. But for
the reasons above, I think that was GIGO rather than a bug in
DF or DCE.
gcc/
PR rtl-optimization/108681
* lra-spills.cc (lra_final_code_change): Extend subreg replacement
code to handle bare uses and clobbers.
gcc/testsuite/
PR rtl-optimization/108681
* gcc.target/aarch64/pr108681.c: New test.
Vladimir N. Makarov [Mon, 13 Feb 2023 21:05:04 +0000 (16:05 -0500)]
RA: Clear reg equiv caller_save_p flag when clearing defined_p flag
IRA can invalidate initially setup equivalence in setup_reg_equiv.
Flag caller_saved was not cleared during invalidation although
init_insns were cleared. It resulted in segmentation fault in
get_equiv. Clearing the flag solves the problem. For more
precaution I added clearing the flag in other places too although it
might be not necessary.
PR rtl-optimization/108774
gcc/ChangeLog:
* ira.cc (ira_update_equiv_info_by_shuffle_insn): Clear equiv
caller_save_p flag when clearing defined_p flag.
(setup_reg_equiv): Ditto.
* lra-constraints.cc (lra_constraints): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr108774.c: New.
Harald Anlauf [Mon, 13 Feb 2023 21:02:44 +0000 (22:02 +0100)]
Fortran: error recovery after invalid use of CLASS variable [PR103475]
gcc/fortran/ChangeLog:
PR fortran/103475
* primary.cc (gfc_expr_attr): Avoid NULL pointer dereference for
invalid use of CLASS variable.
gcc/testsuite/ChangeLog:
PR fortran/103475
* gfortran.dg/pr103475.f90: New test.
Uros Bizjak [Mon, 13 Feb 2023 16:17:46 +0000 (17:17 +0100)]
i386: Relax extract location operand mode requirements [PR108516]
Combine pass simplifies zero-extend of a zero-extract to:
Trying 16 -> 6:
16: r86:QI#0=zero_extract(r87:HI,0x8,0x8)
REG_DEAD r87:HI
6: r84:SI=zero_extend(r86:QI)
REG_DEAD r86:QI
Failed to match this instruction:
(set (reg:SI 84 [ s.e2 ])
(zero_extract:SI (reg:HI 87)
(const_int 8 [0x8])
(const_int 8 [0x8])))
which fails instruction recognision. The pattern is valid, since there
is no requirement on the mode of the location operand.
The patch relaxes location operand mode requirements of *extzv and *extv
insn patterns to allow all supported integer modes. The patch also
adds support for a related sign-extend from zero-extracted operand.
2023-02-13 Uroš Bizjak <ubizjak@gmail.com>
gcc/ChangeLog:
PR target/108516
* config/i386/predicates.md (extr_register_operand):
New special predicate.
* config/i386/i386.md (*extv<mode>): Use extr_register_operand
as operand 1 predicate.
(*exzv<mode>): Ditto.
(*extendqi<SWI24:mode>_ext_1): New insn pattern.
gcc/testsuite/ChangeLog:
PR target/108516
* gcc.target/i386/pr108516-1.c: New test.
* gcc.target/i386/pr108516-2.c: Ditto.
Gaius Mulley [Mon, 13 Feb 2023 19:06:36 +0000 (19:06 +0000)]
Cleanup libgm2/libm2iso/RTco.cc
This patch removes the macro tprintf sizeof nop hack and replaces
it with tprintf (...).
libgm2/ChangeLog:
* libm2iso/RTco.cc (tprintf): Replace definition.
Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
Rimvydas Jasinskas [Sun, 12 Feb 2023 06:16:51 +0000 (06:16 +0000)]
Fortran: Add !GCC$ attributes NOINLINE,NORETURN,WEAK
gcc/fortran/ChangeLog:
* decl.cc: Add EXT_ATTR_NOINLINE, EXT_ATTR_NORETURN, EXT_ATTR_WEAK.
* gfortran.h (ext_attr_id_t): Ditto.
* gfortran.texi (GCC$ ATTRIBUTES): Document them.
* trans-decl.cc (build_function_decl): Apply them.
gcc/testsuite/ChangeLog:
* gfortran.dg/noinline.f90: New test.
* gfortran.dg/noreturn-1.f90: New test.
* gfortran.dg/noreturn-2.f90: New test.
* gfortran.dg/noreturn-3.f90: New test.
* gfortran.dg/noreturn-4.f90: New test.
* gfortran.dg/noreturn-5.f90: New test.
* gfortran.dg/weak-1.f90: New test.
Signed-off-by: Rimvydas Jasinskas <rimvydas.jas@gmail.com>
Richard Biener [Mon, 13 Feb 2023 13:41:24 +0000 (14:41 +0100)]
tree-optimization/28614 - high FRE time for gcc.c-torture/compile/
20001226-1.c
I noticed that for gcc.c-torture/compile/
20001226-1.c even -O1 has
around 50% of the compile-time accounted to FRE. That's because
we have blocks with a high incoming edge count and
can_track_predicate_on_edge visits all of them even though it could
stop after the second. The function is also called repeatedly for
the same edge. The following fixes this and reduces the FRE time
to 1% on the testcase.
PR tree-optimization/28614
* tree-ssa-sccvn.cc (can_track_predicate_on_edge): Avoid
walking all edges in most cases.
(vn_nary_op_insert_pieces_predicated): Avoid repeated
calls to can_track_predicate_on_edge unless checking is
enabled.
(process_bb): Instead call it once here for each edge
we register possibly multiple predicates on.
Richard Biener [Mon, 13 Feb 2023 09:41:51 +0000 (10:41 +0100)]
tree-optimization/108691 - indirect calls to setjmp
DCE now chokes on indirect setjmp calls becoming direct because
that exposes them too late to be subject to abnormal edge creation.
The following patch honors gimple_call_ctrl_altering for those and
_not_ treat formerly indirect calls to setjmp as calls to setjmp
in notice_special_calls.
Unfortunately there's no way to have an indirect call to setjmp
properly annotated (the returns_twice attribute is ignored on types).
RTL expansion late discovers returns-twice for the purpose of
adding REG_SETJMP notes and also sets ->calls_setjmp
(instead of asserting it is set). There's no good way to
transfer proper knowledge around here so I'm using ->calls_setjmp
as a flag to indicate whether gimple_call_ctrl_altering_p was set.
PR tree-optimization/108691
* tree-cfg.cc (notice_special_calls): When the CFG is built
honor gimple_call_ctrl_altering_p.
* cfgexpand.cc (expand_call_stmt): Clear cfun->calls_setjmp
temporarily if the call is not control-altering.
* calls.cc (emit_call_1): Do not add REG_SETJMP if
cfun->calls_setjmp is not set. Do not alter cfun->calls_setjmp.
* gcc.dg/pr108691.c: New testcase.
Stefan Schulze Frielinghaus [Mon, 13 Feb 2023 14:33:38 +0000 (15:33 +0100)]
IBM zSystems: Do not propagate scheduler state across basic blocks [PR108102]
So far we propagate scheduler state across basic blocks within EBBs and
reset the state otherwise. In certain circumstances the entry block of
an EBB might be empty, i.e., no_real_insns_p is true. In those cases
scheduler state is not reset and subsequently wrong state is propagated
to following blocks of the same EBB.
Since the performance benefit of tracking state across basic blocks is
questionable on modern hardware, simply reset the state for each basic
block.
Fix also resetting f{p,x}d_longrunning.
gcc/ChangeLog:
PR target/108102
* config/s390/s390.cc (s390_bb_fallthru_entry_likely): Remove.
(struct s390_sched_state): Initialise to zero.
(s390_sched_variable_issue): For better debuggability also emit
the current side.
(s390_sched_init): Unconditionally reset scheduler state.
Jonathan Yong [Sat, 11 Feb 2023 08:30:55 +0000 (08:30 +0000)]
builtin-declaration-mismatch-7: fix LLP64 targets
gcc/testsuite/ChangeLog:
* gcc.dg/Wbuiltin-declaration-mismatch-7.c: Use (long )*
regex pattern to allow long long instead of just long.
Signed-off-by: Jonathan Yong <10walls@gmail.com>
Richard Sandiford [Mon, 13 Feb 2023 11:38:45 +0000 (11:38 +0000)]
ifcvt: Fix regression in aarch64/fcsel_1.c
aarch64/fcsel_1.c contains:
double
f_2 (double a, double b, double c, double d)
{
if (a > b)
return c;
else
return d;
}
which started failing in the GCC 12 timeframe. When it passed,
the RTL had the form:
[A]
(set (reg ret) (reg c))
(set (pc) (if_then_else (gt ...) (label_ref ret) (pc)))
edge to ret, fallthru to else
else:
(set (reg ret) (reg d))
fallthru to ret
ret:
...exit...
i.e. a branch around. Now the RTL has form:
[B]
(set (reg ret) (reg d))
(set (pc) (if_then_else (gt ...) (label_ref then) (pc)))
edge to then, fallthru to ret
ret:
...exit...
then:
(set (reg ret) (reg c))
edge to ret
i.e. a branch out.
Both are valid, of course, and there's no easy way to predict
which we'll get. But ifcvt canonicalises its representation on:
if (cond) goto fallthru else goto non-fallthru
That is, it canoncalises on the branch-around case for half-diamonds.
It therefore wants to invert the comparison in [B] to get:
if (...) goto ret else goto then
But that isn't possible for strict FP gt, so the optimisation fails.
Canonicalising on the branch-around case seems like the wrong choice for
half diamonds. The natural way of expressing a conditional branch is
for the label_ref to be the "then" destination and pc to be the "else"
destination. And the natural choice of condition seems to be the one
under which extra stuff *is* done, rather than the one under which extra
stuff *isn't* done. But that decision goes back at least 20 years and
it doesn't seem like a good idea to change it in stage 4.
This patch instead allows the internal structure to store the
condition in inverted form. For simplicity it handles only
conditional moves, which is the one case that is needed
to fix the known regression. (There are probably unknown
regressions too, but still.)
gcc/
* ifcvt.h (noce_if_info::cond_inverted): New field.
* ifcvt.cc (cond_move_convert_if_block): Swap the then and else
values when cond_inverted is true.
(noce_find_if_block): Allow the condition to be inverted when
handling conditional moves.
Stefan Schulze Frielinghaus [Mon, 13 Feb 2023 11:06:44 +0000 (12:06 +0100)]
IBM zSystems: Fix predicate execute_operation
Use constrain_operands in order to check whether there exists a valid
alternative instead of extract_constrain_insn which ICEs in case no
alternative is found.
gcc/ChangeLog:
* config/s390/predicates.md (execute_operation): Use
constrain_operands instead of extract_constrain_insn in order to
determine wheter there exists a valid alternative.
Claudiu Zissulescu [Wed, 1 Feb 2023 11:02:17 +0000 (13:02 +0200)]
arc: Don't use millicode thunks unless asked for.
ARC has enter_s/leave_s instructions which can save/restore the entire
function context. It is not needed the millicode thunks anylonger when
compiling for size, thus, make their usage optional.
gcc/
* common/config/arc/arc-common.cc (arc_option_optimization_table):
Remove millicode from list.
gcc/testsuite/
* gcc.target/arc/milli-1.c: Update test.
Martin Liska [Mon, 13 Feb 2023 09:15:55 +0000 (10:15 +0100)]
docs: document new param
gcc/ChangeLog:
* doc/invoke.texi: Document ira-simple-lra-insn-threshold.
Richard Biener [Fri, 10 Feb 2023 09:28:29 +0000 (10:28 +0100)]
tree-optimization/106722 - fix CD-DCE edge marking
The following fixes a latent issue when we mark control edges but
end up with marking a block with no stmts necessary. In this case
we fail to mark dependent control edges of that block.
PR tree-optimization/106722
* tree-ssa-dce.cc (mark_last_stmt_necessary): Return
whether we marked a stmt.
(mark_control_dependent_edges_necessary): When
mark_last_stmt_necessary didn't mark any stmt make sure
to mark its control dependent edges.
(propagate_necessity): Likewise.
* gcc.dg/torture/pr108737.c: New testcase.
Kito Cheng [Fri, 21 Oct 2022 09:37:01 +0000 (17:37 +0800)]
RISC-V: Handle vlenb correctly in unwinding
gcc/ChangeLog:
* config/riscv/riscv.h (RISCV_DWARF_VLENB): New.
(DWARF_FRAME_REGISTERS): New.
(DWARF_REG_TO_UNWIND_COLUMN): New.
libgcc/ChangeLog:
* config.host (riscv*-*-*): Add config/riscv/value-unwind.h.
* config/riscv/value-unwind.h: New.
GCC Administrator [Mon, 13 Feb 2023 00:18:02 +0000 (00:18 +0000)]
Daily bump.
Gerald Pfeifer [Sun, 12 Feb 2023 22:35:40 +0000 (23:35 +0100)]
libstdc++: Tweak link to N1780 (C++ standard)
libstdc++-v3/ChangeLog:
* doc/xml/manual/containers.xml: Tweak a link to N1780
(C++ standard).
* doc/html/manual/associative.html: Regenerate.
Gerald Pfeifer [Sun, 12 Feb 2023 11:02:25 +0000 (12:02 +0100)]
doc: Remove direct reference to configure/build docs
This has been broken for years (if not forever), both when it comes
to onlinedocs and local installations.
gcc/ChangeLog:
* doc/sourcebuild.texi: Remove (broken) direct reference to
"The GNU configure and build system".
Jin Ma [Fri, 3 Feb 2023 09:42:59 +0000 (17:42 +0800)]
RISC-V: Change the generation mode of ADJUST_SP_RTX from gen_insn to gen_SET.
The gen_insn method is used to generate ADJUST_SP_RTX here, which has certain
potential risks:
When the architecture adds pre-processing to `define_insn "adddi3"`, such as
`define_expend "adddi3"`, the gen_expand will be automatically called here,
causing the patern to emit directly, which will cause insn to enter REG_NOTE
for `DWARF` instead of patern.
The following error REG_NOTE occurred:
error: invalid rtl sharing found in the insn:
(insn 19 3 20 2 (parallel [
...
])
(expr_list:REG_CFA_ADJUST_CFA
(insn 18 0 0 (set (reg/f:DI 2 sp)
(plus:DI (reg/f:DI 2 sp)
(const_int -16 [0xfffffffffffffff0]))) -1
(nil))))
In fact, the correct one should be the following:
(insn 19 3 20 2 (parallel [
...
])
(expr_list:REG_CFA_ADJUST_CFA
(set (reg/f:DI 2 sp)
(plus:DI (reg/f:DI 2 sp)
(const_int -16 [0xfffffffffffffff0])))))
Following the treatment of arm or other architectures, it is more reasonable to
use gen_SET here.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_adjust_libcall_cfi_prologue): Change
gen_add3_insn to gen_rtx_SET.
(riscv_adjust_libcall_cfi_epilogue): Likewise.
Ju-Zhe Zhong [Fri, 10 Feb 2023 07:03:14 +0000 (15:03 +0800)]
RISC-V: Add vaadd.vv C++ API tests
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vaadd_vv-1.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv-2.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv-3.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_mu-1.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_mu-2.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_mu-3.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_tu-1.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_tu-2.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_tu-3.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_tum-1.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_tum-2.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_tum-3.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vaadd_vv_tumu-3.C: New test.
Ju-Zhe Zhong [Fri, 10 Feb 2023 07:02:13 +0000 (15:02 +0800)]
RISC-V: Add vaadd.vx C++ API tests
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vaadd_vx_mu_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vaadd_vx_mu_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vaadd_vx_mu_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vaadd_vx_mu_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vaadd_vx_mu_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vaadd_vx_mu_rv64-3.C: New test.
* g++.target/riscv/rvv/base/vaadd_vx_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vaadd_vx_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vaadd_vx_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vaadd_vx_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vaadd_vx_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vaadd_vx_rv64-3.C: New test.
* g++.target/riscv/rvv/base/vaadd_vx_tu_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vaadd_vx_tu_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vaadd_vx_tu_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vaadd_vx_tu_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vaadd_vx_tu_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vaadd_vx_tu_rv64-3.C: New test.
* g++.target/riscv/rvv/base/vaadd_vx_tum_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vaadd_vx_tum_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vaadd_vx_tum_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vaadd_vx_tum_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vaadd_vx_tum_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vaadd_vx_tum_rv64-3.C: New test.
* g++.target/riscv/rvv/base/vaadd_vx_tumu_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vaadd_vx_tumu_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vaadd_vx_tumu_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vaadd_vx_tumu_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vaadd_vx_tumu_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vaadd_vx_tumu_rv64-3.C: New test.
Ju-Zhe Zhong [Fri, 10 Feb 2023 07:00:55 +0000 (15:00 +0800)]
RISC-V: Add vaaddu.vv C++ api tests
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vaaddu_vv-1.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vv-2.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vv-3.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vv_mu-1.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vv_mu-2.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vv_mu-3.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vv_tu-1.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vv_tu-2.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vv_tu-3.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vv_tum-1.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vv_tum-2.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vv_tum-3.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vv_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vv_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vv_tumu-3.C: New test.
Ju-Zhe Zhong [Fri, 10 Feb 2023 06:59:45 +0000 (14:59 +0800)]
RISC-V: Add vaaddu.vx C++ Api tests
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vaaddu_vx_mu_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vx_mu_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vx_mu_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vx_mu_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vx_mu_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vx_mu_rv64-3.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vx_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vx_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vx_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vx_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vx_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vx_rv64-3.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vx_tu_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vx_tu_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vx_tu_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vx_tu_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vx_tu_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vx_tu_rv64-3.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vx_tum_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vx_tum_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vx_tum_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vx_tum_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vx_tum_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vx_tum_rv64-3.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vx_tumu_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vx_tumu_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vx_tumu_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vx_tumu_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vx_tumu_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vaaddu_vx_tumu_rv64-3.C: New test.
Ju-Zhe Zhong [Fri, 10 Feb 2023 06:58:40 +0000 (14:58 +0800)]
RISC-V: Add vasub.vv C++ api tests
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vasub_vv-1.C: New test.
* g++.target/riscv/rvv/base/vasub_vv-2.C: New test.
* g++.target/riscv/rvv/base/vasub_vv-3.C: New test.
* g++.target/riscv/rvv/base/vasub_vv_mu-1.C: New test.
* g++.target/riscv/rvv/base/vasub_vv_mu-2.C: New test.
* g++.target/riscv/rvv/base/vasub_vv_mu-3.C: New test.
* g++.target/riscv/rvv/base/vasub_vv_tu-1.C: New test.
* g++.target/riscv/rvv/base/vasub_vv_tu-2.C: New test.
* g++.target/riscv/rvv/base/vasub_vv_tu-3.C: New test.
* g++.target/riscv/rvv/base/vasub_vv_tum-1.C: New test.
* g++.target/riscv/rvv/base/vasub_vv_tum-2.C: New test.
* g++.target/riscv/rvv/base/vasub_vv_tum-3.C: New test.
* g++.target/riscv/rvv/base/vasub_vv_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vasub_vv_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vasub_vv_tumu-3.C: New test.
Ju-Zhe Zhong [Fri, 10 Feb 2023 06:57:30 +0000 (14:57 +0800)]
RISC-V: Add vasub.vx C++ API tests
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vasub_vx_mu_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vasub_vx_mu_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vasub_vx_mu_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vasub_vx_mu_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vasub_vx_mu_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vasub_vx_mu_rv64-3.C: New test.
* g++.target/riscv/rvv/base/vasub_vx_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vasub_vx_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vasub_vx_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vasub_vx_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vasub_vx_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vasub_vx_rv64-3.C: New test.
* g++.target/riscv/rvv/base/vasub_vx_tu_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vasub_vx_tu_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vasub_vx_tu_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vasub_vx_tu_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vasub_vx_tu_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vasub_vx_tu_rv64-3.C: New test.
* g++.target/riscv/rvv/base/vasub_vx_tum_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vasub_vx_tum_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vasub_vx_tum_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vasub_vx_tum_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vasub_vx_tum_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vasub_vx_tum_rv64-3.C: New test.
* g++.target/riscv/rvv/base/vasub_vx_tumu_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vasub_vx_tumu_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vasub_vx_tumu_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vasub_vx_tumu_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vasub_vx_tumu_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vasub_vx_tumu_rv64-3.C: New test.
Ju-Zhe Zhong [Fri, 10 Feb 2023 06:56:15 +0000 (14:56 +0800)]
RISC-V: Add vasubu.vv C++ API tests
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vasubu_vv-1.C: New test.
* g++.target/riscv/rvv/base/vasubu_vv-2.C: New test.
* g++.target/riscv/rvv/base/vasubu_vv-3.C: New test.
* g++.target/riscv/rvv/base/vasubu_vv_mu-1.C: New test.
* g++.target/riscv/rvv/base/vasubu_vv_mu-2.C: New test.
* g++.target/riscv/rvv/base/vasubu_vv_mu-3.C: New test.
* g++.target/riscv/rvv/base/vasubu_vv_tu-1.C: New test.
* g++.target/riscv/rvv/base/vasubu_vv_tu-2.C: New test.
* g++.target/riscv/rvv/base/vasubu_vv_tu-3.C: New test.
* g++.target/riscv/rvv/base/vasubu_vv_tum-1.C: New test.
* g++.target/riscv/rvv/base/vasubu_vv_tum-2.C: New test.
* g++.target/riscv/rvv/base/vasubu_vv_tum-3.C: New test.
* g++.target/riscv/rvv/base/vasubu_vv_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vasubu_vv_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vasubu_vv_tumu-3.C: New test.
Ju-Zhe Zhong [Fri, 10 Feb 2023 06:55:02 +0000 (14:55 +0800)]
RISC-V: Add vasubu.vx C++ API tests
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vasubu_vx_mu_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vasubu_vx_mu_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vasubu_vx_mu_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vasubu_vx_mu_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vasubu_vx_mu_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vasubu_vx_mu_rv64-3.C: New test.
* g++.target/riscv/rvv/base/vasubu_vx_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vasubu_vx_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vasubu_vx_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vasubu_vx_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vasubu_vx_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vasubu_vx_rv64-3.C: New test.
* g++.target/riscv/rvv/base/vasubu_vx_tu_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vasubu_vx_tu_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vasubu_vx_tu_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vasubu_vx_tu_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vasubu_vx_tu_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vasubu_vx_tu_rv64-3.C: New test.
* g++.target/riscv/rvv/base/vasubu_vx_tum_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vasubu_vx_tum_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vasubu_vx_tum_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vasubu_vx_tum_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vasubu_vx_tum_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vasubu_vx_tum_rv64-3.C: New test.
* g++.target/riscv/rvv/base/vasubu_vx_tumu_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vasubu_vx_tumu_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vasubu_vx_tumu_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vasubu_vx_tumu_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vasubu_vx_tumu_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vasubu_vx_tumu_rv64-3.C: New test.
Ju-Zhe Zhong [Fri, 10 Feb 2023 06:53:44 +0000 (14:53 +0800)]
RISC-V: Add vnclip C++ API tests
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vnclip_vv-1.C: New test.
* g++.target/riscv/rvv/base/vnclip_vv-2.C: New test.
* g++.target/riscv/rvv/base/vnclip_vv-3.C: New test.
* g++.target/riscv/rvv/base/vnclip_vv_mu-1.C: New test.
* g++.target/riscv/rvv/base/vnclip_vv_mu-2.C: New test.
* g++.target/riscv/rvv/base/vnclip_vv_mu-3.C: New test.
* g++.target/riscv/rvv/base/vnclip_vv_tu-1.C: New test.
* g++.target/riscv/rvv/base/vnclip_vv_tu-2.C: New test.
* g++.target/riscv/rvv/base/vnclip_vv_tu-3.C: New test.
* g++.target/riscv/rvv/base/vnclip_vv_tum-1.C: New test.
* g++.target/riscv/rvv/base/vnclip_vv_tum-2.C: New test.
* g++.target/riscv/rvv/base/vnclip_vv_tum-3.C: New test.
* g++.target/riscv/rvv/base/vnclip_vv_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vnclip_vv_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vnclip_vv_tumu-3.C: New test.
* g++.target/riscv/rvv/base/vnclip_vx-1.C: New test.
* g++.target/riscv/rvv/base/vnclip_vx-2.C: New test.
* g++.target/riscv/rvv/base/vnclip_vx-3.C: New test.
* g++.target/riscv/rvv/base/vnclip_vx_mu-1.C: New test.
* g++.target/riscv/rvv/base/vnclip_vx_mu-2.C: New test.
* g++.target/riscv/rvv/base/vnclip_vx_mu-3.C: New test.
* g++.target/riscv/rvv/base/vnclip_vx_tu-1.C: New test.
* g++.target/riscv/rvv/base/vnclip_vx_tu-2.C: New test.
* g++.target/riscv/rvv/base/vnclip_vx_tu-3.C: New test.
* g++.target/riscv/rvv/base/vnclip_vx_tum-1.C: New test.
* g++.target/riscv/rvv/base/vnclip_vx_tum-2.C: New test.
* g++.target/riscv/rvv/base/vnclip_vx_tum-3.C: New test.
* g++.target/riscv/rvv/base/vnclip_vx_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vnclip_vx_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vnclip_vx_tumu-3.C: New test.
* g++.target/riscv/rvv/base/vnclipu_vv-1.C: New test.
* g++.target/riscv/rvv/base/vnclipu_vv-2.C: New test.
* g++.target/riscv/rvv/base/vnclipu_vv-3.C: New test.
* g++.target/riscv/rvv/base/vnclipu_vv_mu-1.C: New test.
* g++.target/riscv/rvv/base/vnclipu_vv_mu-2.C: New test.
* g++.target/riscv/rvv/base/vnclipu_vv_mu-3.C: New test.
* g++.target/riscv/rvv/base/vnclipu_vv_tu-1.C: New test.
* g++.target/riscv/rvv/base/vnclipu_vv_tu-2.C: New test.
* g++.target/riscv/rvv/base/vnclipu_vv_tu-3.C: New test.
* g++.target/riscv/rvv/base/vnclipu_vv_tum-1.C: New test.
* g++.target/riscv/rvv/base/vnclipu_vv_tum-2.C: New test.
* g++.target/riscv/rvv/base/vnclipu_vv_tum-3.C: New test.
* g++.target/riscv/rvv/base/vnclipu_vv_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vnclipu_vv_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vnclipu_vv_tumu-3.C: New test.
* g++.target/riscv/rvv/base/vnclipu_vx-1.C: New test.
* g++.target/riscv/rvv/base/vnclipu_vx-2.C: New test.
* g++.target/riscv/rvv/base/vnclipu_vx-3.C: New test.
* g++.target/riscv/rvv/base/vnclipu_vx_mu-1.C: New test.
* g++.target/riscv/rvv/base/vnclipu_vx_mu-2.C: New test.
* g++.target/riscv/rvv/base/vnclipu_vx_mu-3.C: New test.
* g++.target/riscv/rvv/base/vnclipu_vx_tu-1.C: New test.
* g++.target/riscv/rvv/base/vnclipu_vx_tu-2.C: New test.
* g++.target/riscv/rvv/base/vnclipu_vx_tu-3.C: New test.
* g++.target/riscv/rvv/base/vnclipu_vx_tum-1.C: New test.
* g++.target/riscv/rvv/base/vnclipu_vx_tum-2.C: New test.
* g++.target/riscv/rvv/base/vnclipu_vx_tum-3.C: New test.
* g++.target/riscv/rvv/base/vnclipu_vx_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vnclipu_vx_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vnclipu_vx_tumu-3.C: New test.
Ju-Zhe Zhong [Fri, 10 Feb 2023 06:52:32 +0000 (14:52 +0800)]
RISC-V: Add vsmul.vv C++ API tests
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vsmul_vv-1.C: New test.
* g++.target/riscv/rvv/base/vsmul_vv-2.C: New test.
* g++.target/riscv/rvv/base/vsmul_vv-3.C: New test.
* g++.target/riscv/rvv/base/vsmul_vv_mu-1.C: New test.
* g++.target/riscv/rvv/base/vsmul_vv_mu-2.C: New test.
* g++.target/riscv/rvv/base/vsmul_vv_mu-3.C: New test.
* g++.target/riscv/rvv/base/vsmul_vv_tu-1.C: New test.
* g++.target/riscv/rvv/base/vsmul_vv_tu-2.C: New test.
* g++.target/riscv/rvv/base/vsmul_vv_tu-3.C: New test.
* g++.target/riscv/rvv/base/vsmul_vv_tum-1.C: New test.
* g++.target/riscv/rvv/base/vsmul_vv_tum-2.C: New test.
* g++.target/riscv/rvv/base/vsmul_vv_tum-3.C: New test.
* g++.target/riscv/rvv/base/vsmul_vv_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vsmul_vv_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vsmul_vv_tumu-3.C: New test.
Ju-Zhe Zhong [Fri, 10 Feb 2023 06:51:18 +0000 (14:51 +0800)]
RISC-V: Add vsmul.vx C++ API tests
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vsmul_vx_mu_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vsmul_vx_mu_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vsmul_vx_mu_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vsmul_vx_mu_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vsmul_vx_mu_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vsmul_vx_mu_rv64-3.C: New test.
* g++.target/riscv/rvv/base/vsmul_vx_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vsmul_vx_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vsmul_vx_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vsmul_vx_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vsmul_vx_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vsmul_vx_rv64-3.C: New test.
* g++.target/riscv/rvv/base/vsmul_vx_tu_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vsmul_vx_tu_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vsmul_vx_tu_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vsmul_vx_tu_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vsmul_vx_tu_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vsmul_vx_tu_rv64-3.C: New test.
* g++.target/riscv/rvv/base/vsmul_vx_tum_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vsmul_vx_tum_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vsmul_vx_tum_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vsmul_vx_tum_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vsmul_vx_tum_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vsmul_vx_tum_rv64-3.C: New test.
* g++.target/riscv/rvv/base/vsmul_vx_tumu_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vsmul_vx_tumu_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vsmul_vx_tumu_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vsmul_vx_tumu_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vsmul_vx_tumu_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vsmul_vx_tumu_rv64-3.C: New test.
Ju-Zhe Zhong [Fri, 10 Feb 2023 06:50:17 +0000 (14:50 +0800)]
RISC-V: Add vssra.vv C++ API tests
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vssra_vv-1.C: New test.
* g++.target/riscv/rvv/base/vssra_vv-2.C: New test.
* g++.target/riscv/rvv/base/vssra_vv-3.C: New test.
* g++.target/riscv/rvv/base/vssra_vv_mu-1.C: New test.
* g++.target/riscv/rvv/base/vssra_vv_mu-2.C: New test.
* g++.target/riscv/rvv/base/vssra_vv_mu-3.C: New test.
* g++.target/riscv/rvv/base/vssra_vv_tu-1.C: New test.
* g++.target/riscv/rvv/base/vssra_vv_tu-2.C: New test.
* g++.target/riscv/rvv/base/vssra_vv_tu-3.C: New test.
* g++.target/riscv/rvv/base/vssra_vv_tum-1.C: New test.
* g++.target/riscv/rvv/base/vssra_vv_tum-2.C: New test.
* g++.target/riscv/rvv/base/vssra_vv_tum-3.C: New test.
* g++.target/riscv/rvv/base/vssra_vv_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vssra_vv_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vssra_vv_tumu-3.C: New test.
Ju-Zhe Zhong [Fri, 10 Feb 2023 06:49:07 +0000 (14:49 +0800)]
RISC-V: Add vssra.vx C++ API tests
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vssra_vx-1.C: New test.
* g++.target/riscv/rvv/base/vssra_vx-2.C: New test.
* g++.target/riscv/rvv/base/vssra_vx-3.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_mu-1.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_mu-2.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_mu-3.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_tu-1.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_tu-2.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_tu-3.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_tum-1.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_tum-2.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_tum-3.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_tumu-3.C: New test.
Ju-Zhe Zhong [Fri, 10 Feb 2023 06:47:58 +0000 (14:47 +0800)]
RISC-V: Add vssrl.vv C++ API tests
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vssrl_vv-1.C: New test.
* g++.target/riscv/rvv/base/vssrl_vv-2.C: New test.
* g++.target/riscv/rvv/base/vssrl_vv-3.C: New test.
* g++.target/riscv/rvv/base/vssrl_vv_mu-1.C: New test.
* g++.target/riscv/rvv/base/vssrl_vv_mu-2.C: New test.
* g++.target/riscv/rvv/base/vssrl_vv_mu-3.C: New test.
* g++.target/riscv/rvv/base/vssrl_vv_tu-1.C: New test.
* g++.target/riscv/rvv/base/vssrl_vv_tu-2.C: New test.
* g++.target/riscv/rvv/base/vssrl_vv_tu-3.C: New test.
* g++.target/riscv/rvv/base/vssrl_vv_tum-1.C: New test.
* g++.target/riscv/rvv/base/vssrl_vv_tum-2.C: New test.
* g++.target/riscv/rvv/base/vssrl_vv_tum-3.C: New test.
* g++.target/riscv/rvv/base/vssrl_vv_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vssrl_vv_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vssrl_vv_tumu-3.C: New test.
Ju-Zhe Zhong [Fri, 10 Feb 2023 06:46:34 +0000 (14:46 +0800)]
RISC-V: Add vssrl.vx C++ API tests
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vssrl_vx-1.C: New test.
* g++.target/riscv/rvv/base/vssrl_vx-2.C: New test.
* g++.target/riscv/rvv/base/vssrl_vx-3.C: New test.
* g++.target/riscv/rvv/base/vssrl_vx_mu-1.C: New test.
* g++.target/riscv/rvv/base/vssrl_vx_mu-2.C: New test.
* g++.target/riscv/rvv/base/vssrl_vx_mu-3.C: New test.
* g++.target/riscv/rvv/base/vssrl_vx_tu-1.C: New test.
* g++.target/riscv/rvv/base/vssrl_vx_tu-2.C: New test.
* g++.target/riscv/rvv/base/vssrl_vx_tu-3.C: New test.
* g++.target/riscv/rvv/base/vssrl_vx_tum-1.C: New test.
* g++.target/riscv/rvv/base/vssrl_vx_tum-2.C: New test.
* g++.target/riscv/rvv/base/vssrl_vx_tum-3.C: New test.
* g++.target/riscv/rvv/base/vssrl_vx_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vssrl_vx_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vssrl_vx_tumu-3.C: New test.
Ju-Zhe Zhong [Fri, 10 Feb 2023 06:45:16 +0000 (14:45 +0800)]
RISC-V: Add vaadd.vv C api tests
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/binop_vx_constraint-122.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv_m-1.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv_m-2.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv_m-3.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vv_tumu-3.c: New test.
Ju-Zhe Zhong [Fri, 10 Feb 2023 06:43:56 +0000 (14:43 +0800)]
RISC-V: Add vaadd.vx C api tests
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vaadd_vx_m_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vx_m_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vx_m_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vx_m_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vx_m_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vx_m_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vx_mu_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vx_mu_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vx_mu_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vx_mu_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vx_mu_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vx_mu_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vx_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vx_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vx_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vx_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vx_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vx_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vx_tu_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vx_tu_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vx_tu_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vx_tu_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vx_tu_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vx_tu_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vx_tum_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vx_tum_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vx_tum_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vx_tum_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vx_tum_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vx_tum_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vx_tumu_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vx_tumu_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vx_tumu_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vx_tumu_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vx_tumu_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vaadd_vx_tumu_rv64-3.c: New test.
Ju-Zhe Zhong [Fri, 10 Feb 2023 06:42:48 +0000 (14:42 +0800)]
RISC-V: Add vaaddu.vv C api tests
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vaaddu_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv_m-1.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv_m-2.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv_m-3.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vv_tumu-3.c: New test.
Ju-Zhe Zhong [Fri, 10 Feb 2023 06:41:41 +0000 (14:41 +0800)]
RISC-V: Add vaaddu.vx C API tests
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vaaddu_vx_m_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vx_m_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vx_m_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vx_m_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vx_m_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vx_m_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vx_mu_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vx_mu_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vx_mu_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vx_mu_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vx_mu_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vx_mu_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vx_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vx_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vx_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vx_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vx_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vx_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vx_tu_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vx_tu_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vx_tu_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vx_tu_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vx_tu_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vx_tu_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vx_tum_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vx_tum_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vx_tum_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vx_tum_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vx_tum_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vx_tum_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vx_tumu_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vx_tumu_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vx_tumu_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vx_tumu_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vx_tumu_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vaaddu_vx_tumu_rv64-3.c: New test.
Ju-Zhe Zhong [Fri, 10 Feb 2023 06:38:22 +0000 (14:38 +0800)]
RISC-V: Add vasub.vv C API tests
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vasub_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv_m-1.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv_m-2.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv_m-3.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vasub_vv_tumu-3.c: New test.
Ju-Zhe Zhong [Fri, 10 Feb 2023 06:37:01 +0000 (14:37 +0800)]
RISC-V: Add vasub.vx C API tests
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vasub_vx_m_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vasub_vx_m_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vasub_vx_m_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vasub_vx_m_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vasub_vx_m_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vasub_vx_m_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vasub_vx_mu_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vasub_vx_mu_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vasub_vx_mu_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vasub_vx_mu_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vasub_vx_mu_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vasub_vx_mu_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vasub_vx_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vasub_vx_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vasub_vx_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vasub_vx_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vasub_vx_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vasub_vx_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vasub_vx_tu_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vasub_vx_tu_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vasub_vx_tu_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vasub_vx_tu_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vasub_vx_tu_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vasub_vx_tu_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vasub_vx_tum_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vasub_vx_tum_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vasub_vx_tum_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vasub_vx_tum_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vasub_vx_tum_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vasub_vx_tum_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vasub_vx_tumu_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vasub_vx_tumu_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vasub_vx_tumu_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vasub_vx_tumu_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vasub_vx_tumu_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vasub_vx_tumu_rv64-3.c: New test.
Ju-Zhe Zhong [Fri, 10 Feb 2023 06:35:47 +0000 (14:35 +0800)]
RISC-V: Add vasubu.vv C API tests
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vasubu_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv_m-1.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv_m-2.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv_m-3.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vv_tumu-3.c: New test.
Ju-Zhe Zhong [Fri, 10 Feb 2023 06:34:26 +0000 (14:34 +0800)]
RISC-V: Add vasubu.vx C API tests
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vasubu_vx_m_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vx_m_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vx_m_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vx_m_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vx_m_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vx_m_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vx_mu_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vx_mu_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vx_mu_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vx_mu_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vx_mu_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vx_mu_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vx_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vx_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vx_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vx_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vx_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vx_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vx_tu_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vx_tu_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vx_tu_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vx_tu_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vx_tu_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vx_tu_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vx_tum_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vx_tum_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vx_tum_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vx_tum_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vx_tum_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vx_tum_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vx_tumu_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vx_tumu_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vx_tumu_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vx_tumu_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vx_tumu_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vasubu_vx_tumu_rv64-3.c: New test.
Ju-Zhe Zhong [Fri, 10 Feb 2023 06:32:58 +0000 (14:32 +0800)]
RISC-V: Add vnclip C API tests
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vnclip_wv-1.c: New test.
* gcc.target/riscv/rvv/base/vnclip_wv-2.c: New test.
* gcc.target/riscv/rvv/base/vnclip_wv-3.c: New test.
* gcc.target/riscv/rvv/base/vnclip_wv_m-1.c: New test.
* gcc.target/riscv/rvv/base/vnclip_wv_m-2.c: New test.
* gcc.target/riscv/rvv/base/vnclip_wv_m-3.c: New test.
* gcc.target/riscv/rvv/base/vnclip_wv_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vnclip_wv_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vnclip_wv_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vnclip_wv_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vnclip_wv_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vnclip_wv_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vnclip_wv_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vnclip_wv_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vnclip_wv_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vnclip_wv_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vnclip_wv_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vnclip_wv_tumu-3.c: New test.
* gcc.target/riscv/rvv/base/vnclip_wx-1.c: New test.
* gcc.target/riscv/rvv/base/vnclip_wx-2.c: New test.
* gcc.target/riscv/rvv/base/vnclip_wx-3.c: New test.
* gcc.target/riscv/rvv/base/vnclip_wx_m-1.c: New test.
* gcc.target/riscv/rvv/base/vnclip_wx_m-2.c: New test.
* gcc.target/riscv/rvv/base/vnclip_wx_m-3.c: New test.
* gcc.target/riscv/rvv/base/vnclip_wx_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vnclip_wx_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vnclip_wx_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vnclip_wx_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vnclip_wx_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vnclip_wx_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vnclip_wx_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vnclip_wx_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vnclip_wx_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vnclip_wx_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vnclip_wx_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vnclip_wx_tumu-3.c: New test.
* gcc.target/riscv/rvv/base/vnclipu_wv-1.c: New test.
* gcc.target/riscv/rvv/base/vnclipu_wv-2.c: New test.
* gcc.target/riscv/rvv/base/vnclipu_wv-3.c: New test.
* gcc.target/riscv/rvv/base/vnclipu_wv_m-1.c: New test.
* gcc.target/riscv/rvv/base/vnclipu_wv_m-2.c: New test.
* gcc.target/riscv/rvv/base/vnclipu_wv_m-3.c: New test.
* gcc.target/riscv/rvv/base/vnclipu_wv_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vnclipu_wv_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vnclipu_wv_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vnclipu_wv_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vnclipu_wv_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vnclipu_wv_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vnclipu_wv_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vnclipu_wv_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vnclipu_wv_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vnclipu_wv_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vnclipu_wv_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vnclipu_wv_tumu-3.c: New test.
* gcc.target/riscv/rvv/base/vnclipu_wx-1.c: New test.
* gcc.target/riscv/rvv/base/vnclipu_wx-2.c: New test.
* gcc.target/riscv/rvv/base/vnclipu_wx-3.c: New test.
* gcc.target/riscv/rvv/base/vnclipu_wx_m-1.c: New test.
* gcc.target/riscv/rvv/base/vnclipu_wx_m-2.c: New test.
* gcc.target/riscv/rvv/base/vnclipu_wx_m-3.c: New test.
* gcc.target/riscv/rvv/base/vnclipu_wx_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vnclipu_wx_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vnclipu_wx_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vnclipu_wx_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vnclipu_wx_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vnclipu_wx_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vnclipu_wx_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vnclipu_wx_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vnclipu_wx_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vnclipu_wx_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vnclipu_wx_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vnclipu_wx_tumu-3.c: New test.
Ju-Zhe Zhong [Fri, 10 Feb 2023 06:31:47 +0000 (14:31 +0800)]
RISC-V: Add vsmul.vv C API tests
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vsmul_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv_m-1.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv_m-2.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv_m-3.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vv_tumu-3.c: New test.
Ju-Zhe Zhong [Fri, 10 Feb 2023 06:30:32 +0000 (14:30 +0800)]
RISC-V: Add vsmul.vx C API tests
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vsmul_vx_m_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vx_m_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vx_m_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vx_m_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vx_m_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vx_m_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vx_mu_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vx_mu_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vx_mu_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vx_mu_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vx_mu_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vx_mu_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vx_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vx_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vx_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vx_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vx_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vx_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vx_tu_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vx_tu_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vx_tu_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vx_tu_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vx_tu_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vx_tu_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vx_tum_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vx_tum_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vx_tum_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vx_tum_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vx_tum_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vx_tum_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vx_tumu_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vx_tumu_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vx_tumu_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vx_tumu_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vx_tumu_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vsmul_vx_tumu_rv64-3.c: New test.
Ju-Zhe Zhong [Fri, 10 Feb 2023 06:29:21 +0000 (14:29 +0800)]
RISC-V: Add vssra.vv C API tests
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vssra_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv_m-1.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv_m-2.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv_m-3.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vssra_vv_tumu-3.c: New test.
Ju-Zhe Zhong [Fri, 10 Feb 2023 06:27:38 +0000 (14:27 +0800)]
RISC-V: Add vssra.vx C API tests
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vssra_vx-1.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx-2.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx-3.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_m-1.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_m-2.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_m-3.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_tumu-3.c: New test.
Ju-Zhe Zhong [Fri, 10 Feb 2023 06:26:07 +0000 (14:26 +0800)]
RISC-V: Add vssrl.vv C API tests
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vssrl_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv_m-1.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv_m-2.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv_m-3.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vv_tumu-3.c: New test.
Ju-Zhe Zhong [Fri, 10 Feb 2023 06:24:46 +0000 (14:24 +0800)]
RISC-V: Add vssrl.vx C API tests
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vssrl_vx-1.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx-2.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx-3.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_m-1.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_m-2.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_m-3.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vssrl_vx_tumu-3.c: New test.
Ju-Zhe Zhong [Fri, 10 Feb 2023 06:21:31 +0000 (14:21 +0800)]
RISC-V: Add fixed-point support
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc (class sat_op): New class.
(class vnclip): Ditto.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (vaadd): Ditto.
(vasub): Ditto.
(vaaddu): Ditto.
(vasubu): Ditto.
(vsmul): Ditto.
(vssra): Ditto.
(vssrl): Ditto.
(vnclipu): Ditto.
(vnclip): Ditto.
* config/riscv/vector-iterators.md (su): Add instruction.
(aadd): Ditto.
(vaalu): Ditto.
* config/riscv/vector.md (@pred_<sat_op><mode>): New pattern.
(@pred_<sat_op><mode>_scalar): Ditto.
(*pred_<sat_op><mode>_scalar): Ditto.
(*pred_<sat_op><mode>_extended_scalar): Ditto.
(@pred_narrow_clip<v_su><mode>): Ditto.
(@pred_narrow_clip<v_su><mode>_scalar): Ditto.
Gerald Pfeifer [Sat, 11 Feb 2023 14:58:15 +0000 (15:58 +0100)]
libstdc++: Change www.unix.org to unix.org
www.unix.org now redirects to unix.org.
libstdc++-v3/ChangeLog:
* doc/xml/manual/ctype.xml: Change www.unix.org to unix.org.
* doc/html/manual/facets.html: Regenerate.
Ju-Zhe Zhong [Thu, 9 Feb 2023 22:02:14 +0000 (06:02 +0800)]
RISC-V: Add vmerge C++ API test
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vmerge_vvm-1.C: New test.
* g++.target/riscv/rvv/base/vmerge_vvm-2.C: New test.
* g++.target/riscv/rvv/base/vmerge_vvm-3.C: New test.
* g++.target/riscv/rvv/base/vmerge_vvm-4.C: New test.
* g++.target/riscv/rvv/base/vmerge_vvm-5.C: New test.
* g++.target/riscv/rvv/base/vmerge_vvm-6.C: New test.
* g++.target/riscv/rvv/base/vmerge_vvm_tu-1.C: New test.
* g++.target/riscv/rvv/base/vmerge_vvm_tu-2.C: New test.
* g++.target/riscv/rvv/base/vmerge_vvm_tu-3.C: New test.
* g++.target/riscv/rvv/base/vmerge_vvm_tu-4.C: New test.
* g++.target/riscv/rvv/base/vmerge_vvm_tu-5.C: New test.
* g++.target/riscv/rvv/base/vmerge_vvm_tu-6.C: New test.
* g++.target/riscv/rvv/base/vmerge_vxm_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vmerge_vxm_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vmerge_vxm_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vmerge_vxm_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vmerge_vxm_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vmerge_vxm_rv64-3.C: New test.
* g++.target/riscv/rvv/base/vmerge_vxm_tu_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vmerge_vxm_tu_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vmerge_vxm_tu_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vmerge_vxm_tu_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vmerge_vxm_tu_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vmerge_vxm_tu_rv64-3.C: New test.
Ju-Zhe Zhong [Thu, 9 Feb 2023 22:01:03 +0000 (06:01 +0800)]
RISC-V: Add vncvt/vmv C++ API tests
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vmv_v-1.C: New test.
* g++.target/riscv/rvv/base/vmv_v_tu-1.C: New test.
* g++.target/riscv/rvv/base/vmv_v_x_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vmv_v_x_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vmv_v_x_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vmv_v_x_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vmv_v_x_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vmv_v_x_rv64-3.C: New test.
* g++.target/riscv/rvv/base/vncvt_x-1.C: New test.
* g++.target/riscv/rvv/base/vncvt_x-2.C: New test.
* g++.target/riscv/rvv/base/vncvt_x-3.C: New test.
* g++.target/riscv/rvv/base/vncvt_x_mu-1.C: New test.
* g++.target/riscv/rvv/base/vncvt_x_mu-2.C: New test.
* g++.target/riscv/rvv/base/vncvt_x_mu-3.C: New test.
* g++.target/riscv/rvv/base/vncvt_x_tu-1.C: New test.
* g++.target/riscv/rvv/base/vncvt_x_tu-2.C: New test.
* g++.target/riscv/rvv/base/vncvt_x_tu-3.C: New test.
* g++.target/riscv/rvv/base/vncvt_x_tum-1.C: New test.
* g++.target/riscv/rvv/base/vncvt_x_tum-2.C: New test.
* g++.target/riscv/rvv/base/vncvt_x_tum-3.C: New test.
* g++.target/riscv/rvv/base/vncvt_x_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vncvt_x_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vncvt_x_tumu-3.C: New test.
Ju-Zhe Zhong [Thu, 9 Feb 2023 21:59:43 +0000 (05:59 +0800)]
RISC-V: Add vnsra C++ API tests
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vnsra_vv-1.C: New test.
* g++.target/riscv/rvv/base/vnsra_vv-2.C: New test.
* g++.target/riscv/rvv/base/vnsra_vv-3.C: New test.
* g++.target/riscv/rvv/base/vnsra_vv_mu-1.C: New test.
* g++.target/riscv/rvv/base/vnsra_vv_mu-2.C: New test.
* g++.target/riscv/rvv/base/vnsra_vv_mu-3.C: New test.
* g++.target/riscv/rvv/base/vnsra_vv_tu-1.C: New test.
* g++.target/riscv/rvv/base/vnsra_vv_tu-2.C: New test.
* g++.target/riscv/rvv/base/vnsra_vv_tu-3.C: New test.
* g++.target/riscv/rvv/base/vnsra_vv_tum-1.C: New test.
* g++.target/riscv/rvv/base/vnsra_vv_tum-2.C: New test.
* g++.target/riscv/rvv/base/vnsra_vv_tum-3.C: New test.
* g++.target/riscv/rvv/base/vnsra_vv_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vnsra_vv_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vnsra_vv_tumu-3.C: New test.
* g++.target/riscv/rvv/base/vnsra_vx-1.C: New test.
* g++.target/riscv/rvv/base/vnsra_vx-2.C: New test.
* g++.target/riscv/rvv/base/vnsra_vx-3.C: New test.
* g++.target/riscv/rvv/base/vnsra_vx_mu-1.C: New test.
* g++.target/riscv/rvv/base/vnsra_vx_mu-2.C: New test.
* g++.target/riscv/rvv/base/vnsra_vx_mu-3.C: New test.
* g++.target/riscv/rvv/base/vnsra_vx_tu-1.C: New test.
* g++.target/riscv/rvv/base/vnsra_vx_tu-2.C: New test.
* g++.target/riscv/rvv/base/vnsra_vx_tu-3.C: New test.
* g++.target/riscv/rvv/base/vnsra_vx_tum-1.C: New test.
* g++.target/riscv/rvv/base/vnsra_vx_tum-2.C: New test.
* g++.target/riscv/rvv/base/vnsra_vx_tum-3.C: New test.
* g++.target/riscv/rvv/base/vnsra_vx_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vnsra_vx_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vnsra_vx_tumu-3.C: New test.
Ju-Zhe Zhong [Thu, 9 Feb 2023 21:58:35 +0000 (05:58 +0800)]
RISC-V: Add vnsrl C++ API tests
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vnsrl_vv-1.C: New test.
* g++.target/riscv/rvv/base/vnsrl_vv-2.C: New test.
* g++.target/riscv/rvv/base/vnsrl_vv-3.C: New test.
* g++.target/riscv/rvv/base/vnsrl_vv_mu-1.C: New test.
* g++.target/riscv/rvv/base/vnsrl_vv_mu-2.C: New test.
* g++.target/riscv/rvv/base/vnsrl_vv_mu-3.C: New test.
* g++.target/riscv/rvv/base/vnsrl_vv_tu-1.C: New test.
* g++.target/riscv/rvv/base/vnsrl_vv_tu-2.C: New test.
* g++.target/riscv/rvv/base/vnsrl_vv_tu-3.C: New test.
* g++.target/riscv/rvv/base/vnsrl_vv_tum-1.C: New test.
* g++.target/riscv/rvv/base/vnsrl_vv_tum-2.C: New test.
* g++.target/riscv/rvv/base/vnsrl_vv_tum-3.C: New test.
* g++.target/riscv/rvv/base/vnsrl_vv_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vnsrl_vv_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vnsrl_vv_tumu-3.C: New test.
* g++.target/riscv/rvv/base/vnsrl_vx-1.C: New test.
* g++.target/riscv/rvv/base/vnsrl_vx-2.C: New test.
* g++.target/riscv/rvv/base/vnsrl_vx-3.C: New test.
* g++.target/riscv/rvv/base/vnsrl_vx_mu-1.C: New test.
* g++.target/riscv/rvv/base/vnsrl_vx_mu-2.C: New test.
* g++.target/riscv/rvv/base/vnsrl_vx_mu-3.C: New test.
* g++.target/riscv/rvv/base/vnsrl_vx_tu-1.C: New test.
* g++.target/riscv/rvv/base/vnsrl_vx_tu-2.C: New test.
* g++.target/riscv/rvv/base/vnsrl_vx_tu-3.C: New test.
* g++.target/riscv/rvv/base/vnsrl_vx_tum-1.C: New test.
* g++.target/riscv/rvv/base/vnsrl_vx_tum-2.C: New test.
* g++.target/riscv/rvv/base/vnsrl_vx_tum-3.C: New test.
* g++.target/riscv/rvv/base/vnsrl_vx_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vnsrl_vx_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vnsrl_vx_tumu-3.C: New test.
Ju-Zhe Zhong [Thu, 9 Feb 2023 21:57:13 +0000 (05:57 +0800)]
RISC-V: Add vmerge C API tests
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vmerge-1.c: New test.
* gcc.target/riscv/rvv/base/vmerge-2.c: New test.
* gcc.target/riscv/rvv/base/vmerge-3.c: New test.
* gcc.target/riscv/rvv/base/vmerge-4.c: New test.
* gcc.target/riscv/rvv/base/vmerge_vvm-1.c: New test.
* gcc.target/riscv/rvv/base/vmerge_vvm-2.c: New test.
* gcc.target/riscv/rvv/base/vmerge_vvm-3.c: New test.
* gcc.target/riscv/rvv/base/vmerge_vvm-4.c: New test.
* gcc.target/riscv/rvv/base/vmerge_vvm-5.c: New test.
* gcc.target/riscv/rvv/base/vmerge_vvm-6.c: New test.
* gcc.target/riscv/rvv/base/vmerge_vvm_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vmerge_vvm_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vmerge_vvm_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vmerge_vvm_tu-4.c: New test.
* gcc.target/riscv/rvv/base/vmerge_vvm_tu-5.c: New test.
* gcc.target/riscv/rvv/base/vmerge_vvm_tu-6.c: New test.
* gcc.target/riscv/rvv/base/vmerge_vxm_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vmerge_vxm_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vmerge_vxm_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vmerge_vxm_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vmerge_vxm_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vmerge_vxm_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv64-3.c: New test.
Ju-Zhe Zhong [Thu, 9 Feb 2023 21:56:12 +0000 (05:56 +0800)]
RISC-V: Add vmv.v.x C API tests
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vmv_v_x_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_x_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_x_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_x_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_x_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_x_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-3.c: New test.
Ju-Zhe Zhong [Thu, 9 Feb 2023 21:55:02 +0000 (05:55 +0800)]
RISC-V: Add vmv C API tests
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vmv_v_v-1.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_v-2.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_v-3.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_v_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_v_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vmv_v_v_tu-3.c: New test.
Ju-Zhe Zhong [Thu, 9 Feb 2023 21:53:54 +0000 (05:53 +0800)]
RISC-V: Add vncvt C API tests
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vncvt_x-1.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x-2.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x-3.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x_m-1.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x_m-2.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x_m-3.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vncvt_x_tumu-3.c: New test.
Ju-Zhe Zhong [Thu, 9 Feb 2023 21:52:41 +0000 (05:52 +0800)]
RISC-V: Add vnsra C API tests
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vnsra_wv-1.c: New test.
* gcc.target/riscv/rvv/base/vnsra_wv-2.c: New test.
* gcc.target/riscv/rvv/base/vnsra_wv-3.c: New test.
* gcc.target/riscv/rvv/base/vnsra_wv_m-1.c: New test.
* gcc.target/riscv/rvv/base/vnsra_wv_m-2.c: New test.
* gcc.target/riscv/rvv/base/vnsra_wv_m-3.c: New test.
* gcc.target/riscv/rvv/base/vnsra_wv_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vnsra_wv_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vnsra_wv_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vnsra_wv_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vnsra_wv_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vnsra_wv_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vnsra_wv_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vnsra_wv_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vnsra_wv_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vnsra_wv_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vnsra_wv_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vnsra_wv_tumu-3.c: New test.
* gcc.target/riscv/rvv/base/vnsra_wx-1.c: New test.
* gcc.target/riscv/rvv/base/vnsra_wx-2.c: New test.
* gcc.target/riscv/rvv/base/vnsra_wx-3.c: New test.
* gcc.target/riscv/rvv/base/vnsra_wx_m-1.c: New test.
* gcc.target/riscv/rvv/base/vnsra_wx_m-2.c: New test.
* gcc.target/riscv/rvv/base/vnsra_wx_m-3.c: New test.
* gcc.target/riscv/rvv/base/vnsra_wx_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vnsra_wx_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vnsra_wx_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vnsra_wx_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vnsra_wx_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vnsra_wx_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vnsra_wx_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vnsra_wx_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vnsra_wx_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vnsra_wx_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vnsra_wx_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vnsra_wx_tumu-3.c: New test.
Ju-Zhe Zhong [Thu, 9 Feb 2023 21:50:19 +0000 (05:50 +0800)]
RISC-V: Add vnsrl C API tests
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vnsrl_wv-1.c: New test.
* gcc.target/riscv/rvv/base/vnsrl_wv-2.c: New test.
* gcc.target/riscv/rvv/base/vnsrl_wv-3.c: New test.
* gcc.target/riscv/rvv/base/vnsrl_wv_m-1.c: New test.
* gcc.target/riscv/rvv/base/vnsrl_wv_m-2.c: New test.
* gcc.target/riscv/rvv/base/vnsrl_wv_m-3.c: New test.
* gcc.target/riscv/rvv/base/vnsrl_wv_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vnsrl_wv_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vnsrl_wv_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vnsrl_wv_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vnsrl_wv_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vnsrl_wv_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vnsrl_wv_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vnsrl_wv_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vnsrl_wv_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vnsrl_wv_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vnsrl_wv_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vnsrl_wv_tumu-3.c: New test.
* gcc.target/riscv/rvv/base/vnsrl_wx-1.c: New test.
* gcc.target/riscv/rvv/base/vnsrl_wx-2.c: New test.
* gcc.target/riscv/rvv/base/vnsrl_wx-3.c: New test.
* gcc.target/riscv/rvv/base/vnsrl_wx_m-1.c: New test.
* gcc.target/riscv/rvv/base/vnsrl_wx_m-2.c: New test.
* gcc.target/riscv/rvv/base/vnsrl_wx_m-3.c: New test.
* gcc.target/riscv/rvv/base/vnsrl_wx_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vnsrl_wx_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vnsrl_wx_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vnsrl_wx_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vnsrl_wx_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vnsrl_wx_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vnsrl_wx_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vnsrl_wx_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vnsrl_wx_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vnsrl_wx_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vnsrl_wx_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vnsrl_wx_tumu-3.c: New test.
Ju-Zhe Zhong [Thu, 9 Feb 2023 21:45:44 +0000 (05:45 +0800)]
RISC-V: Add vnsrl/vnsra/vncvt/vmerge/vmv C/C++ support
gcc/ChangeLog:
* config/riscv/constraints.md (Wbr): Remove unused constraint.
* config/riscv/predicates.md: Fix move operand predicate.
* config/riscv/riscv-vector-builtins-bases.cc (class vnshift): New class.
(class vncvt_x): Ditto.
(class vmerge): Ditto.
(class vmv_v): Ditto.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (vsra): Ditto.
(vsrl): Ditto.
(vnsrl): Ditto.
(vnsra): Ditto.
(vncvt_x): Ditto.
(vmerge): Ditto.
(vmv_v): Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct narrow_alu_def): Ditto.
(struct move_def): Ditto.
(SHAPE): Ditto.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_WEXTI_OPS): New variable.
(DEF_RVV_WEXTU_OPS): Ditto
* config/riscv/riscv-vector-builtins.def (x_x_w): Fix type for suffix.
(v_v): Ditto.
(v_x): Ditto.
(x_w): Ditto.
(x): Ditto.
* config/riscv/riscv.cc (riscv_print_operand): Refine ASM printting rule.
* config/riscv/vector-iterators.md (nmsac):New iterator.
(nmsub): New iterator.
* config/riscv/vector.md (@pred_merge<mode>): New pattern.
(@pred_merge<mode>_scalar): New pattern.
(*pred_merge<mode>_scalar): New pattern.
(*pred_merge<mode>_extended_scalar): New pattern.
(@pred_narrow_<optab><mode>): New pattern.
(@pred_narrow_<optab><mode>_scalar): New pattern.
(@pred_trunc<mode>): New pattern.
Ju-Zhe Zhong [Wed, 8 Feb 2023 20:58:37 +0000 (04:58 +0800)]
RISC-V: Add vmsbc C++ API tests
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vmsbc_vv-1.C: New test.
* g++.target/riscv/rvv/base/vmsbc_vv-2.C: New test.
* g++.target/riscv/rvv/base/vmsbc_vv-3.C: New test.
* g++.target/riscv/rvv/base/vmsbc_vvm-1.C: New test.
* g++.target/riscv/rvv/base/vmsbc_vvm-2.C: New test.
* g++.target/riscv/rvv/base/vmsbc_vvm-3.C: New test.
* g++.target/riscv/rvv/base/vmsbc_vx_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vmsbc_vx_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vmsbc_vx_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vmsbc_vx_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vmsbc_vx_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vmsbc_vx_rv64-3.C: New test.
* g++.target/riscv/rvv/base/vmsbc_vxm_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vmsbc_vxm_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vmsbc_vxm_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vmsbc_vxm_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vmsbc_vxm_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vmsbc_vxm_rv64-3.C: New test.
Ju-Zhe Zhong [Wed, 8 Feb 2023 20:57:26 +0000 (04:57 +0800)]
RISC-V: Add vmadc C++ API tests
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vmadc_vv-1.C: New test.
* g++.target/riscv/rvv/base/vmadc_vv-2.C: New test.
* g++.target/riscv/rvv/base/vmadc_vv-3.C: New test.
* g++.target/riscv/rvv/base/vmadc_vvm-1.C: New test.
* g++.target/riscv/rvv/base/vmadc_vvm-2.C: New test.
* g++.target/riscv/rvv/base/vmadc_vvm-3.C: New test.
* g++.target/riscv/rvv/base/vmadc_vx_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vmadc_vx_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vmadc_vx_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vmadc_vx_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vmadc_vx_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vmadc_vx_rv64-3.C: New test.
* g++.target/riscv/rvv/base/vmadc_vxm_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vmadc_vxm_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vmadc_vxm_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vmadc_vxm_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vmadc_vxm_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vmadc_vxm_rv64-3.C: New test.
Ju-Zhe Zhong [Wed, 8 Feb 2023 20:56:15 +0000 (04:56 +0800)]
RISC-V: Add vmsbc C API tests
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vmsbc-1.c: New test.
* gcc.target/riscv/rvv/base/vmsbc-2.c: New test.
* gcc.target/riscv/rvv/base/vmsbc-3.c: New test.
* gcc.target/riscv/rvv/base/vmsbc-4.c: New test.
* gcc.target/riscv/rvv/base/vmsbc-5.c: New test.
* gcc.target/riscv/rvv/base/vmsbc-6.c: New test.
* gcc.target/riscv/rvv/base/vmsbc-7.c: New test.
* gcc.target/riscv/rvv/base/vmsbc-8.c: New test.
* gcc.target/riscv/rvv/base/vmsbc_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vmsbc_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vmsbc_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vmsbc_vvm-1.c: New test.
* gcc.target/riscv/rvv/base/vmsbc_vvm-2.c: New test.
* gcc.target/riscv/rvv/base/vmsbc_vvm-3.c: New test.
* gcc.target/riscv/rvv/base/vmsbc_vx_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vmsbc_vx_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vmsbc_vx_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vmsbc_vx_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vmsbc_vx_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vmsbc_vx_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vmsbc_vxm_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vmsbc_vxm_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vmsbc_vxm_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vmsbc_vxm_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vmsbc_vxm_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vmsbc_vxm_rv64-3.c: New test.
Ju-Zhe Zhong [Wed, 8 Feb 2023 20:54:48 +0000 (04:54 +0800)]
RISC-V: Add vmadc C API tests
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vmadc-1.c: New test.
* gcc.target/riscv/rvv/base/vmadc-2.c: New test.
* gcc.target/riscv/rvv/base/vmadc-3.c: New test.
* gcc.target/riscv/rvv/base/vmadc-4.c: New test.
* gcc.target/riscv/rvv/base/vmadc-5.c: New test.
* gcc.target/riscv/rvv/base/vmadc-6.c: New test.
* gcc.target/riscv/rvv/base/vmadc-7.c: New test.
* gcc.target/riscv/rvv/base/vmadc-8.c: New test.
* gcc.target/riscv/rvv/base/vmadc_vv-1.c: New test.
* gcc.target/riscv/rvv/base/vmadc_vv-2.c: New test.
* gcc.target/riscv/rvv/base/vmadc_vv-3.c: New test.
* gcc.target/riscv/rvv/base/vmadc_vvm-1.c: New test.
* gcc.target/riscv/rvv/base/vmadc_vvm-2.c: New test.
* gcc.target/riscv/rvv/base/vmadc_vvm-3.c: New test.
* gcc.target/riscv/rvv/base/vmadc_vx_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vmadc_vx_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vmadc_vx_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vmadc_vx_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vmadc_vx_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vmadc_vx_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vmadc_vxm_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vmadc_vxm_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vmadc_vxm_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vmadc_vxm_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vmadc_vxm_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vmadc_vxm_rv64-3.c: New test.
Ju-Zhe Zhong [Wed, 8 Feb 2023 20:52:36 +0000 (04:52 +0800)]
RISC-V: Add vmadc/vmsbc C/C++ API support
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc (class vmadc): New class.
(class vmsbc): Ditto.
(BASE): Define new class.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (vmadc): New define.
(vmsbc): Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct return_mask_def):
New class.
(SHAPE): Ditto.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_exact_insn): Adjust for new support
* config/riscv/riscv-vector-builtins.h
(function_base::has_merge_operand_p): New function.
* config/riscv/vector-iterators.md: New iterator.
* config/riscv/vector.md (@pred_madc<mode>): New pattern.
(@pred_msbc<mode>): Ditto.
(@pred_madc<mode>_scalar): Ditto.
(@pred_msbc<mode>_scalar): Ditto.
(*pred_madc<mode>_scalar): Ditto.
(*pred_madc<mode>_extended_scalar): Ditto.
(*pred_msbc<mode>_scalar): Ditto.
(*pred_msbc<mode>_extended_scalar): Ditto.
(@pred_madc<mode>_overflow): Ditto.
(@pred_msbc<mode>_overflow): Ditto.
(@pred_madc<mode>_overflow_scalar): Ditto.
(@pred_msbc<mode>_overflow_scalar): Ditto.
(*pred_madc<mode>_overflow_scalar): Ditto.
(*pred_madc<mode>_overflow_extended_scalar): Ditto.
(*pred_msbc<mode>_overflow_scalar): Ditto.
(*pred_msbc<mode>_overflow_extended_scalar): Ditto.
Ju-Zhe Zhong [Wed, 8 Feb 2023 02:47:25 +0000 (10:47 +0800)]
RISC-V: Add vadc C++ API tests
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vadc_vvm-1.C: New test.
* g++.target/riscv/rvv/base/vadc_vvm-2.C: New test.
* g++.target/riscv/rvv/base/vadc_vvm-3.C: New test.
* g++.target/riscv/rvv/base/vadc_vvm_tu-1.C: New test.
* g++.target/riscv/rvv/base/vadc_vvm_tu-2.C: New test.
* g++.target/riscv/rvv/base/vadc_vvm_tu-3.C: New test.
* g++.target/riscv/rvv/base/vadc_vxm_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vadc_vxm_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vadc_vxm_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vadc_vxm_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vadc_vxm_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vadc_vxm_rv64-3.C: New test.
* g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-3.C: New test.
Ju-Zhe Zhong [Wed, 8 Feb 2023 02:49:10 +0000 (10:49 +0800)]
RISC-V: Add vsbc C++ API tests
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vsbc_vvm-1.C: New test.
* g++.target/riscv/rvv/base/vsbc_vvm-2.C: New test.
* g++.target/riscv/rvv/base/vsbc_vvm-3.C: New test.
* g++.target/riscv/rvv/base/vsbc_vvm_tu-1.C: New test.
* g++.target/riscv/rvv/base/vsbc_vvm_tu-2.C: New test.
* g++.target/riscv/rvv/base/vsbc_vvm_tu-3.C: New test.
* g++.target/riscv/rvv/base/vsbc_vxm_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vsbc_vxm_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vsbc_vxm_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vsbc_vxm_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vsbc_vxm_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vsbc_vxm_rv64-3.C: New test.
* g++.target/riscv/rvv/base/vsbc_vxm_tu_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vsbc_vxm_tu_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vsbc_vxm_tu_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vsbc_vxm_tu_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vsbc_vxm_tu_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vsbc_vxm_tu_rv64-3.C: New test.
Ju-Zhe Zhong [Wed, 8 Feb 2023 02:34:30 +0000 (10:34 +0800)]
RISC-V: Add vsbc.vvm/vsbc.vxm C API tests
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vsbc-1.c: New test.
* gcc.target/riscv/rvv/base/vsbc-2.c: New test.
* gcc.target/riscv/rvv/base/vsbc-3.c: New test.
* gcc.target/riscv/rvv/base/vsbc-4.c: New test.
* gcc.target/riscv/rvv/base/vsbc_vvm-1.c: New test.
* gcc.target/riscv/rvv/base/vsbc_vvm-2.c: New test.
* gcc.target/riscv/rvv/base/vsbc_vvm-3.c: New test.
* gcc.target/riscv/rvv/base/vsbc_vvm_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vsbc_vvm_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vsbc_vvm_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vsbc_vxm_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vsbc_vxm_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vsbc_vxm_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vsbc_vxm_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vsbc_vxm_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vsbc_vxm_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv64-3.c: New test.
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