Martin Sebor [Wed, 11 May 2016 03:04:03 +0000 (03:04 +0000)]
PR c++/38611 - missing -Wattributes on a typedef with attribute aligned
From-SVN: r236112
Alan Modra [Wed, 11 May 2016 02:09:38 +0000 (11:39 +0930)]
[RS6000] complex long double ABI_V4 fix
Revision 235794 regressed compat/scalar-by-value-6 for powerpc-linux
-m32 due to accidentally changing the ABI. By another historical
accident, complex long double is stupidly passed in gprs for -m32.
* config/rs6000/rs6000.c (is_complex_IBM_long_double,
abi_v4_pass_in_fpr): New functions.
(rs6000_function_arg_boundary): Exclude complex IBM long double
from 64-bit alignment when ABI_V4.
(rs6000_function_arg, rs6000_function_arg_advance_1,
rs6000_gimplify_va_arg): Use abi_v4_pass_in_fpr.
From-SVN: r236111
GCC Administrator [Wed, 11 May 2016 00:16:19 +0000 (00:16 +0000)]
Daily bump.
From-SVN: r236110
Segher Boessenkool [Tue, 10 May 2016 23:31:27 +0000 (01:31 +0200)]
cfgcleanup: Handle a branch with just a return in both arms (PR71028)
If we have a conditional jump that has only a return in both the branch
path and the fallthrough path, and the return on the branch path can not
be made a conditional return, we will try to make a conditional return
from the fallthrough path, and that does not work because we then try
to redirect the (new) jump in the fallthrough block to the original
dest in the branch path, which is the exit block.
For the testcase on ARM we end up in this situation because before the
jump2 pass there are some other insns in the return blocks as well, but
the same insns in both, so those are moved above the conditional jump.
Only later (in the ce3 pass) are the conditional jump and two returns
melded into one return, so we need to handle this strange case here.
PR rtl-optimization/71028
* cfgcleanup.c (try_optimize_cfg): Do not flip a conditional
jump with just a return in the fallthrough block if the branch
block contains just a returns as well.
From-SVN: r236106
Marc Glisse [Tue, 10 May 2016 19:52:20 +0000 (21:52 +0200)]
Simple bitop reassoc in match.pd
2016-05-10 Marc Glisse <marc.glisse@inria.fr>
gcc/
* fold-const.c (fold_binary_loc) [(X ^ Y) & Y]: Remove and merge with...
* match.pd ((X & Y) ^ Y): ... this.
((X & Y) & Y, (X | Y) | Y, (X ^ Y) ^ Y, (X & Y) & (X & Z), (X | Y)
| (X | Z), (X ^ Y) ^ (X ^ Z)): New transformations.
gcc/testsuite/
* gcc.dg/tree-ssa/bit-assoc.c: New testcase.
* gcc.dg/tree-ssa/pr69270.c: Adjust.
* gcc.dg/tree-ssa/vrp59.c: Disable forwprop.
From-SVN: r236103
David Malcolm [Tue, 10 May 2016 18:28:10 +0000 (18:28 +0000)]
Simplify read-md.c and read-rtl.c using require_char_ws
read-md.c and read-rtl.c repeatedly use this pattern:
c = read_skip_spaces ();
if (c != ')')
fatal_expected_char (')', c);
Simplify them by introduce a helper function to do this.
gcc/ChangeLog:
* read-md.c (require_char_ws): New function.
(read_string): Simplify using require_char_ws.
(handle_constants): Likewise.
(handle_enum): Likewise.
(handle_file): Likewise.
* read-md.h (require_char_ws): New declaration.
* read-rtl.c (read_conditions): Simplify using require_char_ws.
(read_mapping): Likewise.
(read_rtx_code): Likewise.
(read_nested_rtx): Likewise.
From-SVN: r236101
James Norris [Tue, 10 May 2016 18:05:02 +0000 (18:05 +0000)]
sysv4.h (CRTOFFLOADBEGIN): Define.
* config/rs6000/sysv4.h (CRTOFFLOADBEGIN): Define. Add crtoffloadbegin.o
if offloading is enabled and -fopenacc or -fopenmp is specified.
(CRTOFFLOADEND): Likewise.
(STARTFILE_LINUX_SPEC): Add CRTOFFLOADBEGIN.
(ENDFILE_LINUX_SPEC): Add CRTOFFLOADEND.
From-SVN: r236098
Uros Bizjak [Tue, 10 May 2016 17:17:20 +0000 (19:17 +0200)]
i386.c (legitimize_pic_address): Merge 64-bit and 32-bit gotoff_operand code paths.
* config/i386/i386.c (legitimize_pic_address): Merge 64-bit and 32-bit
gotoff_operand code paths. Use copy_to_suggested_regs and
expand_simple_binop where appropriate. Cleanup.
From-SVN: r236096
Matthias Klose [Tue, 10 May 2016 16:44:19 +0000 (16:44 +0000)]
configure.ac: Move AC_USE_SYSTEM_EXTENSIONS behind AM_ENABLE_MULTILIB.
2016-05-10 Matthias Klose <doko@ubuntu.com>
* configure.ac: Move AC_USE_SYSTEM_EXTENSIONS behind AM_ENABLE_MULTILIB.
* configure: Regenerate.
From-SVN: r236093
Ilya Enkovich [Tue, 10 May 2016 16:08:42 +0000 (16:08 +0000)]
re PR target/70799 (STV pass does not convert DImode shifts)
gcc/
PR target/70799
* config/i386/i386.c (dimode_scalar_to_vector_candidate_p): Allow
integer constants.
(dimode_scalar_chain::vector_const_cost): New.
(dimode_scalar_chain::compute_convert_gain): Handle constants.
(dimode_scalar_chain::convert_op): Likewise.
(dimode_scalar_chain::convert_insn): Likewise.
gcc/testsuite/
PR target/70799
* gcc.target/i386/pr70799-1.c: New test.
From-SVN: r236090
Ilya Enkovich [Tue, 10 May 2016 16:06:36 +0000 (16:06 +0000)]
re PR middle-end/70877 ([MPX] ICE in in convert_move)
gcc/
PR middle-end/70877
* tree-chkp.c (chkp_add_bounds_to_call_stmt): Handle
calls with type casted fndecl.
gcc/testsuite/
PR middle-end/70877
* gcc.target/i386/pr70877.c: New test.
From-SVN: r236088
Pierre-Marie de Rodat [Tue, 10 May 2016 15:57:37 +0000 (15:57 +0000)]
DWARF: fix stack usage assessment for DW_OP_neg
When the DWARF back-end generates DW_OP_neg operations in DWARF
procedures, we get an ICE because of inconsistent stack usage
computation for the embedding expression. This is because
resolve_args_picking_1 thinks DW_OP_neg is a binary operation (pops 2
stack slots, pushes 1) whereas it really is an unary one (one pop, one
push).
This change fixes resolve_args_picking_1 and adds a regression testcase
(which crashes with the current trunk). Bootstrapped and regtested
without regression on x86_64-linux.
gcc/
* dwarf2out.c (resolve_args_picking_1): Consider DW_OP_neg as an
unary operation, not a binary one.
gcc/testsuite/
* gnat.dg/debug6.adb, gnat.dg/debug6_pkg.ads: New testcase.
From-SVN: r236087
Ilya Enkovich [Tue, 10 May 2016 15:56:27 +0000 (15:56 +0000)]
re PR tree-optimization/70876 (ICE in chkp_find_bounds: Unexpected tree code with_size_expr)
gcc/
PR tree-optimization/70786
* tree-chkp.c (chkp_find_bounds_1): Support WITH_SIZE_EXPR.
* gcc/calls.c (initialize_argument_information): Bind bounds
with corresponding args passed by reference.
gcc/testsuite/
PR tree-optimization/70786
* gcc.target/i386/pr70876.c: New test.
From-SVN: r236086
Jonathan Wakely [Tue, 10 May 2016 15:39:20 +0000 (16:39 +0100)]
Test begin and end functions for directory iterators
* include/experimental/bits/fs_dir.h (begin, end): Add noexcept.
* testsuite/experimental/filesystem/iterators/directory_iterator.cc:
Test begin and end functions.
* testsuite/experimental/filesystem/iterators/
recursive_directory_iterator.cc: Likewise.
From-SVN: r236085
Jonathan Wakely [Tue, 10 May 2016 15:39:14 +0000 (16:39 +0100)]
libstdc++/71038 fix error checks in filesystem::copy_file
PR libstdc++/71038
* src/filesystem/ops.cc (do_copy_file): Fix backwards conditions.
* testsuite/experimental/filesystem/operations/copy_file.cc: New test.
From-SVN: r236084
Jakub Jelinek [Tue, 10 May 2016 14:30:02 +0000 (16:30 +0200)]
re PR target/70927 ([6 only] avx512dq instructions emitted even with -mavx512vl -mno-avx512dq)
PR target/70927
* config/i386/sse.md (<sse>_andnot<mode>3<mask_name>),
*<code><mode>3<mask_name>): For !TARGET_AVX512DQ and EVEX encoding,
use vp*[dq] instead of v*p[sd] instructions and adjust mode attribute
accordingly.
* gcc.target/i386/avx512vl-logic-1.c: New test.
* gcc.target/i386/avx512vl-logic-2.c: New test.
* gcc.target/i386/avx512dq-logic-2.c: New test.
From-SVN: r236083
Bill Schmidt [Tue, 10 May 2016 14:27:12 +0000 (14:27 +0000)]
re PR target/70963 (vec_cts/vec_ctf intrinsics produce wrong results for 64-bit floating point)
[gcc]
2016-05-10 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
PR target/70963
* config/rs6000/vsx.md (vsx_xvcvdpsxds_scale): Generate correct
code for a zero scale factor.
(vsx_xvcvdpuxds_scale): Likewise.
[gcc/testsuite]
2016-05-10 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
PR target/70963
* gcc.target/powerpc/pr70963.c: New.
From-SVN: r236082
David Malcolm [Tue, 10 May 2016 13:28:41 +0000 (13:28 +0000)]
Add debugging ruler to diagnostic-show-locus.c
When debugging diagnostic-show-locus.c, it's invaluable to have a
"ruler" showing column numbers.
This patch adds in support via a new "show_ruler_p" flag within
the diagnostic_context. There's no direct way for end-users to enable
this, but plugins can enable it by setting the flag, so the
plugin that tests the diagnostic subsystem uses this to verify that
the ruler is correctly printed.
gcc/ChangeLog:
* diagnostic-show-locus.c (layout::layout): Call show_ruler
if show_ruler_p was set on the context.
(layout::show_ruler): New method.
* diagnostic.h (struct diagnostic_context): Add field
"show_ruler_p".
gcc/testsuite/ChangeLog:
* gcc.dg/plugin/diagnostic-test-show-locus-bw.c
(test_very_wide_line): Add ruler to expected output.
* gcc.dg/plugin/diagnostic-test-show-locus-color.c
(test_very_wide_line): Likewise.
* gcc.dg/plugin/diagnostic_plugin_test_show_locus.c
(test_show_locus): Within the handling of "test_very_wide_line",
enable show_ruler_p on the diagnostic context.
From-SVN: r236080
Richard Biener [Tue, 10 May 2016 13:13:59 +0000 (13:13 +0000)]
re PR tree-optimization/71039 (ICE: verify_ssa failed (error: definition in block 4 does not dominate use in block 5) w/ -O1 and above)
2016-05-10 Richard Biener <rguenther@suse.de>
PR tree-optimization/71039
* tree-ssa-phiprop.c: Include tree-ssa-loop.h.
(chk_uses): New function.
(propagate_with_phi): Verify we can safely replicate the lhs of an
aggregate assignment on all incoming edges.
* gcc.dg/torture/pr71039.c: New testcase.
From-SVN: r236079
Jonathan Wakely [Tue, 10 May 2016 13:09:22 +0000 (14:09 +0100)]
Optimize __directory_iterator_proxy for the common case
* include/experimental/bits/fs_dir.h (__directory_iterator_proxy):
Overload operator* to move from rvalues.
From-SVN: r236078
Nathan Sidwell [Tue, 10 May 2016 13:05:57 +0000 (13:05 +0000)]
nested-func-10.c: Requires alloca.
* gcc.dg/nested-func-10.c: Requires alloca.
* gcc.dg/nested-func-9.c: Requires alloca.
* gcc.c-torture/execute/pr70460.c: Requires labels.
* gcc.c-torture/compile/pr70199.c: Requires labels.
* gcc.target/nvptx/decl.c: Compile only.
* gcc.target/nvptx/trailing-init.c: Compile only.
* gcc.target/nvptx/ary-init.c: Compile only.
From-SVN: r236077
Jonathan Wakely [Tue, 10 May 2016 13:04:21 +0000 (14:04 +0100)]
libstdc++/71036 Handle EEXIST in filesystem::create_directory
PR libstdc++/71036
* src/filesystem/ops.cc (create_dir): Handle EEXIST from mkdir.
* testsuite/experimental/filesystem/operations/create_directory.cc:
New test.
From-SVN: r236076
Oleg Endo [Tue, 10 May 2016 12:53:44 +0000 (12:53 +0000)]
Add rudimentary support for atomics on RX.
Add rudimentary support for atomics on RX. It is implemented by flipping
interrupts off/on around the atomic sequences.
gcc/
* config/rx/rx-protos.h (is_interrupt_func, is_fast_interrupt_func):
Forward declare.
(rx_atomic_sequence): New class.
* config/rx/rx.c (rx_print_operand): Use symbolic names for PSW bits.
(is_interrupt_func, is_fast_interrupt_func): Make non-static and
non-inline.
(rx_atomic_sequence::rx_atomic_sequence,
rx_atomic_sequence::~rx_atomic_sequence): New functions.
* config/rx/rx.md (CTRLREG_PSW, CTRLREG_USP, CTRLREG_FPSW, CTRLREG_CPEN,
CTRLREG_BPSW, CTRLREG_BPC, CTRLREG_ISP, CTRLREG_FINTV,
CTRLREG_INTB): New constants.
(FETCHOP): New code iterator.
(fethcop_name, fetchop_name2): New iterator code attributes.
(QIHI): New mode iterator.
(atomic_exchange<mode>, atomic_exchangesi, xchg_mem<mode>,
atomic_fetch_<fetchop_name>si, atomic_fetch_nandsi,
atomic_<fetchop_name>_fetchsi, atomic_nand_fetchsi): New patterns.
From-SVN: r236075
Jonathan Wakely [Tue, 10 May 2016 12:22:32 +0000 (13:22 +0100)]
libstdc++/71037 Add base path to filesystem::canonical exceptions
PR libstdc++/71037
* src/filesystem/ops.cc (canonical(const path&, const path&)): Add
base path to exception.
* testsuite/experimental/filesystem/operations/canonical.cc: Test
paths contained in exception.
From-SVN: r236074
Jonathan Wakely [Tue, 10 May 2016 12:04:22 +0000 (13:04 +0100)]
2.cc: Remove unused using declaration.
* testsuite/experimental/type_erased_allocator/2.cc: Remove unused
using declaration.
From-SVN: r236073
Jonathan Wakely [Tue, 10 May 2016 11:25:06 +0000 (12:25 +0100)]
libstdc++/71005 fix post-increment for filesystem iterators
PR libstdc++/71005
* include/experimental/bits/fs_dir.h (__directory_iterator_proxy):
New type.
(directory_iterator::operator++(int)): Return proxy.
(recursive_directory_iterator::operator++(int)): Likewise.
* testsuite/experimental/filesystem/iterators/directory_iterator.cc:
Test post-increment.
* testsuite/experimental/filesystem/iterators/
recursive_directory_iterator.cc: Likewise.
From-SVN: r236072
Marek Polacek [Tue, 10 May 2016 10:22:16 +0000 (10:22 +0000)]
re PR c/70255 (change of the order of summation of floating point numbers despite no-associative-math)
PR c/70255
* c-decl.c (diagnose_mismatched_decls): Warn for optimize attribute
on a declaration following the definition.
* gcc.dg/attr-opt-1.c: New test.
From-SVN: r236071
Martin Liska [Tue, 10 May 2016 10:17:58 +0000 (12:17 +0200)]
Handle memory leak in tree-inline.c.
* tree-inline.c (remap_dependence_clique): Do not remap
debugging statements.
From-SVN: r236070
Andreas Krebbel [Tue, 10 May 2016 09:00:53 +0000 (09:00 +0000)]
S/390: Disable scalar vector instructions with -mno-vx.
Although the scalar variants of the vector instructions aren't
actually vector instructions they are still executed in the vector
facility and therefore need to be disabled when disabling the facility
with -mno-vx.
Fixed with the attached patch. Committed to head, GCC 6, and GCC 5
branches.
gcc/ChangeLog:
2016-05-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/s390/s390.md ("*vec_cmp<insn_cmp>df_cconly")
("*fixuns_truncdfdi2_z13")
("*fixuns_trunc<FP:mode><GPR:mode>2_z196")
("*fix_truncdfdi2_bfp_z13", "*floatunsdidf2_z13")
("*extendsfdf2_z13"): Replace TARGET_Z13 with TARGET_VX.
From-SVN: r236067
Richard Biener [Tue, 10 May 2016 08:20:43 +0000 (08:20 +0000)]
re PR tree-optimization/70497 (Missed CSE of subregs on GIMPLE)
2016-05-10 Richard Biener <rguenther@suse.de>
PR tree-optimization/70497
PR tree-optimization/28367
* tree-ssa-sccvn.c (vn_nary_build_or_lookup): New function
split out from ...
(visit_reference_op_load): ... here.
(vn_reference_lookup_3): Use it to handle subreg-like accesses
with simplified BIT_FIELD_REFs.
* tree-ssa-pre.c (eliminate_insert): Handle inserting BIT_FIELD_REFs.
* tree-complex.c (extract_component): Handle BIT_FIELD_REFs
correctly.
* gcc.dg/torture/
20160404-1.c: New testcase.
* gcc.dg/tree-ssa/ssa-fre-54.c: Likewise.
* gcc.dg/tree-ssa/ssa-fre-55.c: Likewise.
From-SVN: r236066
Pierre-Marie de Rodat [Tue, 10 May 2016 08:03:49 +0000 (08:03 +0000)]
DWARF: add abstract origin links on lexical blocks DIEs
Track from which abstract lexical block concrete ones come from in DWARF
so that debuggers can inherit the former from the latter. This enables
debuggers to properly handle the following case:
* function Child2 is nested in a lexical block, itself nested in
function Child1;
* function Child1 is inlined into some call site;
* function Child2 is never inlined.
Here, Child2 is described in DWARF only in the abstract instance of
Child1. So when debuggers decode Child1's concrete instances, they need
to fetch the definition for Child2 in the corresponding abstract
instance: the DW_AT_abstract_origin link on the lexical block that
embeds Child1 enables them to do that.
Bootstrapped and regtested on x86_64-linux.
gcc/ChangeLog:
* dwarf2out.c (add_abstract_origin_attribute): Adjust
documentation comment. For BLOCK nodes, add a
DW_AT_abstract_origin attribute that points to the DIE generated
for the origin BLOCK.
(gen_lexical_block_die): Call add_abstract_origin_attribute for
blocks from inlined functions.
gcc/testsuite/Changelog:
* gcc.dg/debug/dwarf2/nested_fun.c: New testcase.
From-SVN: r236065
Joel Sherrill [Tue, 10 May 2016 07:11:00 +0000 (07:11 +0000)]
[RTEMS] Fix moxie libgcc support
libgcc/
PR libgcc/70720
* config.host (moxie-*-rtems*): Merge this stanza with other moxie
targets so the same extra_parts are built. Also have tmake_file add
on to its value rather than override.
From-SVN: r236064
Sebastian Huber [Tue, 10 May 2016 06:52:48 +0000 (06:52 +0000)]
[libatomic] Add missing files for RTEMS support
Add missing files for:
2016-04-27 Sebastian Huber <sebastian.huber@embedded-brains.de>
* configure.tgt (configure_tgt_pre_target_cpu_XCFLAGS): New variable.
(*-*-rtems*): New supported target.
* config/rtems/host-config.h: New file.
* config/rtems/lock.c: Likewise.
From-SVN: r236060
GCC Administrator [Tue, 10 May 2016 00:16:20 +0000 (00:16 +0000)]
Daily bump.
From-SVN: r236056
Alan Modra [Mon, 9 May 2016 23:12:20 +0000 (08:42 +0930)]
[RS6000] Stop regrename twiddling with split-stack prologue
PR target/70947
* config/rs6000/rs6000.c (rs6000_expand_split_stack_prologue): Stop
regrename modifying insns saving lr before __morestack call.
* config/rs6000/rs6000.md (split_stack_return): Similarly for
insns restoring lr after __morestack call.
From-SVN: r236052
Joseph Myers [Mon, 9 May 2016 22:09:09 +0000 (23:09 +0100)]
* sv.po: Update.
From-SVN: r236050
Jakub Jelinek [Mon, 9 May 2016 20:09:29 +0000 (22:09 +0200)]
i386.md (set_got, [...]): Remove constraints from expanders.
* config/i386/i386.md (set_got, set_got_labelled, lwp_llwpcb,
lwp_lwpval<mode>3, lwp_lwpins<mode>3): Remove constraints from
expanders.
* config/i386/sse.md (vec_interleave_high<mode>,
vec_interleave_low<mode>, <avx512>_vpermi2var<mode>3_maskz,
<avx512>_vpermt2var<mode>3_maskz): Likewise.
From-SVN: r236045
Aaron Sawdey [Mon, 9 May 2016 16:56:30 +0000 (16:56 +0000)]
rs6000.c (rs6000_reassociation_width): Add function for TARGET_SCHED_REASSOCIATION_WIDTH to enable parallel...
* config/rs6000/rs6000.c (rs6000_reassociation_width): Add
function for TARGET_SCHED_REASSOCIATION_WIDTH to enable
parallel reassociation for power8 and forward.
From-SVN: r236043
Uros Bizjak [Mon, 9 May 2016 15:37:30 +0000 (17:37 +0200)]
i386.md (absneg splitters with general regs): Use general_reg_operand predicate.
* config/i386/i386.md (absneg splitters with general regs): Use
general_reg_operand predicate.
(btsq peephole2): Use x86_64_immediate_operand to check if new
value is suitable for immediate operand. Generate emitted insn
using RTL expressions.
(btcq peephole2): Ditto.
(btrq peephole2): Ditto. Generate correct immediate operand
for AND masking.
testsuite/ChangeLog:
* gcc.target/i386/fabsneg-1.c New test.
From-SVN: r236042
Richard Sandiford [Mon, 9 May 2016 15:30:32 +0000 (15:30 +0000)]
Fix handling of negative bitpos in expand_debug_expr
expand_debug_expr handled negative bit positions using:
else if (bitpos < 0)
{
HOST_WIDE_INT units
= (-bitpos + BITS_PER_UNIT - 1) / BITS_PER_UNIT;
op0 = adjust_address_nv (op0, mode1, units);
bitpos += units * BITS_PER_UNIT;
}
Here "units" is the negative of the (negative) byte offset, so I think
we should be offsetting OP0 by -units instead. E.g. a bitpos of -17
would give units==3, so this code would move OP0 up by 3 bytes and set
bitpos to 7, giving a total bitpos of 31.
Just noticed by inspection. An assert triggered for:
gcc.target/i386/mpx/bitfields-1-lbv.c
gcc.target/i386/mpx/field-addr-7-lbv.c
gcc.target/i386/mpx/reference-3-lbv.cpp
gcc.target/i386/mpx/reference-4-lbv.cpp
at -m32 but otherwise this case doesn't seem to trigger during a
bootstrap and regtest.
Tested on x86_64-linux-gnu.
gcc/
* cfgexpand.c (expand_debug_expr): Fix address offset for negative
bitpos.
From-SVN: r236041
Richard Sandiford [Mon, 9 May 2016 15:29:03 +0000 (15:29 +0000)]
Missing pointer dereference in tree-affine.c
wide_int_constant_multiple_p used:
if (*mult_set && mult != 0)
return false;
to check whether we had previously seen a nonzero multiple, but "mult" is
a pointer to the previous value rather than the previous value itself.
Noticed by inspection while working on another patch, so I don't have a
testcase. I tried adding an assert for combinations that were wrongly
rejected before but it didn't trigger during a bootstrap and regtest.
Tested on x86_64-linux-gnu.
gcc/
* tree-affine.c (wide_int_constant_multiple_p): Add missing
pointer dereference.
From-SVN: r236040
Aaron Sawdey [Mon, 9 May 2016 13:59:46 +0000 (13:59 +0000)]
MAINTAINERS (Write After Approval): Add myself.
2016-05-09 Aaron Sawdey <acsawdey@linux.vnet.ibm.com>
* MAINTAINERS (Write After Approval): Add myself.
From-SVN: r236034
Alan Modra [Mon, 9 May 2016 12:35:25 +0000 (22:05 +0930)]
[RS6000] Fragile testcase breaks with -frename-registers
PR testsuite/70826
* gcc.target/powerpc/savres.c: Compile with -fno-rename-registers.
From-SVN: r236033
Richard Biener [Mon, 9 May 2016 12:23:11 +0000 (12:23 +0000)]
re PR tree-optimization/70985 (ICE on valid code at -O3 on x86_64-linux-gnu: verify_gimple failed)
2016-05-09 Richard Biener <rguenther@suse.de>
PR tree-optimization/70985
* match.pd (BIT_FIELD_REF -> (type)): Disable on GIMPLE when
op0 isn't a gimple register.
* gcc.dg/torture/pr70985.c: New testcase.
From-SVN: r236032
Prachi Godbole [Mon, 9 May 2016 12:04:25 +0000 (12:04 +0000)]
Add pipeline description for MSA.
gcc/
* config/mips/i6400.md (i6400_fpu_intadd, i6400_fpu_logic)
(i6400_fpu_div, i6400_fpu_cmp, i6400_fpu_float, i6400_fpu_store)
(i6400_fpu_long_pipe, i6400_fpu_logic_l, i6400_fpu_float_l)
(i6400_fpu_mult): New cpu units.
(i6400_msa_add_d, i6400_msa_int_add, i6400_msa_short_logic3)
(i6400_msa_short_logic2, i6400_msa_short_logic, i6400_msa_move)
(i6400_msa_cmp, i6400_msa_short_float2, i6400_msa_div_d)
(i6400_msa_div_w, i6400_msa_div_h, i6400_msa_div_b)
(i6400_msa_copy, i6400_msa_branch, i6400_fpu_msa_store)
(i6400_fpu_msa_load, i6400_fpu_msa_move, i6400_msa_long_logic1)
(i6400_msa_long_logic2, i6400_msa_mult, i6400_msa_long_float2)
(i6400_msa_long_float4, i6400_msa_long_float5)
(i6400_msa_long_float8, i6400_msa_fdiv_df)
(i6400_msa_fdiv_sf): New reservations.
* config/mips/p5600.md (p5600_fpu_intadd, p5600_fpu_cmp)
(p5600_fpu_float, p5600_fpu_logic_a, p5600_fpu_logic_b)
(p5600_fpu_div, p5600_fpu_logic, p5600_fpu_float_a)
(p5600_fpu_float_b, p5600_fpu_float_c, p5600_fpu_float_d)
(p5600_fpu_mult, p5600_fpu_fdiv, p5600_fpu_load): New cpu units.
(msa_short_int_add, msa_short_logic, msa_short_logic_move_v)
(msa_short_cmp, msa_short_float2, msa_short_logic3)
(msa_short_store4, msa_long_load, msa_short_store)
(msa_long_logic, msa_long_float2, msa_long_float4)
(msa_long_float5, msa_long_float8, msa_long_mult)
(msa_long_fdiv, msa_long_div): New reservations.
From-SVN: r236031
Robert Suchanek [Mon, 9 May 2016 12:04:09 +0000 (12:04 +0000)]
Add support for MIPS SIMD Architecture (MSA).
gcc/
* config.gcc: Add MSA header file for mips*-*-* target.
* config/mips/constraints.md (YI, YC, YZ, Unv5, Uuv5, Usv5, Uuv6)
(Ubv8i, Urv8): New constraints.
* config/mips/mips-ftypes.def: Add function types for MSA
builtins.
* config/mips/mips-modes.def (V16QI, V8HI, V4SI, V2DI, V4SF)
(V2DF, V32QI, V16HI, V8SI, V4DI, V8SF, V4DF): New modes.
* config/mips/mips-msa.md: New file.
* config/mips/mips-protos.h
(mips_split_128bit_const_insns): New prototype.
(mips_msa_idiv_insns): Likewise.
(mips_split_128bit_move): Likewise.
(mips_split_128bit_move_p): Likewise.
(mips_split_msa_copy_d): Likewise.
(mips_split_msa_insert_d): Likewise.
(mips_split_msa_fill_d): Likewise.
(mips_expand_msa_branch): Likewise.
(mips_const_vector_same_val_p): Likewise.
(mips_const_vector_same_bytes_p): Likewise.
(mips_const_vector_same_int_p): Likewise.
(mips_const_vector_shuffle_set_p): Likewise.
(mips_const_vector_bitimm_set_p): Likewise.
(mips_const_vector_bitimm_clr_p): Likewise.
(mips_msa_vec_parallel_const_half): Likewise.
(mips_msa_output_division): Likewise.
(mips_ldst_scaled_shift): Likewise.
(mips_expand_vec_cond_expr): Likewise.
* config/mips/mips.c (enum mips_builtin_type): Add
MIPS_BUILTIN_MSA_TEST_BRANCH.
(mips_gen_const_int_vector_shuffle): New prototype.
(mips_const_vector_bitimm_set_p): New function.
(mips_const_vector_bitimm_clr_p): Likewise.
(mips_const_vector_same_val_p): Likewise.
(mips_const_vector_same_bytes_p): Likewise.
(mips_const_vector_same_int_p): Likewise.
(mips_const_vector_shuffle_set_p): Likewise.
(mips_symbol_insns): Forbid loading symbols via immediate for
MSA.
(mips_valid_offset_p): Limit offset to 10-bit for MSA loads and
stores.
(mips_valid_lo_sum_p): Forbid loadings symbols via %lo(base) for
MSA.
(mips_lx_address_p): Add support load indexed address for MSA.
(mips_address_insns): Add calculation of instructions needed for
stores and loads for MSA.
(mips_const_insns): Move CONST_DOUBLE below CONST_VECTOR. Handle
CONST_VECTOR for MSA and let it fall through.
(mips_ldst_scaled_shift): New function.
(mips_subword_at_byte): Likewise.
(mips_msa_idiv_insns): Likewise.
(mips_legitimize_move): Validate MSA moves.
(mips_rtx_costs): Add UNGE, UNGT, UNLE, UNLT cases. Add
calculation of costs for MSA division.
(mips_split_move_p): Check if MSA moves need splitting.
(mips_split_move): Split MSA moves if necessary.
(mips_split_128bit_move_p): New function.
(mips_split_128bit_move): Likewise.
(mips_split_msa_copy_d): Likewise.
(mips_split_msa_insert_d): Likewise.
(mips_split_msa_fill_d): Likewise.
(mips_output_move): Handle MSA moves.
(mips_expand_msa_branch): New function.
(mips_print_operand): Add 'E', 'B', 'w', 'v' and 'V' modifiers.
Reinstate 'y' modifier.
(mips_file_start): Add MSA .gnu_attribute.
(mips_hard_regno_mode_ok_p): Allow TImode and 128-bit vectors in
FPRs.
(mips_hard_regno_nregs): Always return 1 for MSA supported mode.
(mips_class_max_nregs): Add register size for MSA supported mode.
(mips_cannot_change_mode_class): Allow conversion between MSA
vector modes and TImode.
(mips_mode_ok_for_mov_fmt_p): Allow MSA to use move.v
instruction.
(mips_secondary_reload_class): Force MSA loads/stores via memory.
(mips_preferred_simd_mode): Add preffered modes for MSA.
(mips_vector_mode_supported_p): Add MSA supported modes.
(mips_autovectorize_vector_sizes): New function.
(mips_msa_output_division): Likewise.
(MSA_BUILTIN, MIPS_BUILTIN_DIRECT_NO_TARGET)
(MSA_NO_TARGET_BUILTIN, MSA_BUILTIN_TEST_BRANCH): New macros.
(CODE_FOR_msa_adds_s_b, CODE_FOR_msa_adds_s_h)
(CODE_FOR_msa_adds_s_w, CODE_FOR_msa_adds_s_d)
(CODE_FOR_msa_adds_u_b, CODE_FOR_msa_adds_u_h)
(CODE_FOR_msa_adds_u_w, CODE_FOR_msa_adds_u_du
(CODE_FOR_msa_addv_b, CODE_FOR_msa_addv_h, CODE_FOR_msa_addv_w)
(CODE_FOR_msa_addv_d, CODE_FOR_msa_and_v, CODE_FOR_msa_bmnz_v)
(CODE_FOR_msa_bmnzi_b, CODE_FOR_msa_bmz_v, CODE_FOR_msa_bmzi_b)
(CODE_FOR_msa_bnz_v, CODE_FOR_msa_bz_v, CODE_FOR_msa_bsel_v)
(CODE_FOR_msa_bseli_b, CODE_FOR_msa_ceqi_h, CODE_FOR_msa_ceqi_w)
(CODE_FOR_msa_ceqi_d, CODE_FOR_msa_clti_s_b)
(CODE_FOR_msa_clti_s_h, CODE_FOR_msa_clti_s_w)
(CODE_FOR_msa_clti_s_d, CODE_FOR_msa_clti_u_b)
(CODE_FOR_msa_clti_u_h, CODE_FOR_msa_clti_u_w)
(CODE_FOR_msa_clti_u_d, CODE_FOR_msa_clei_s_b)
(CODE_FOR_msa_clei_s_h, CODE_FOR_msa_clei_s_w)
(CODE_FOR_msa_clei_s_d, CODE_FOR_msa_clei_u_b)
(CODE_FOR_msa_clei_u_h, CODE_FOR_msa_clei_u_w)
(CODE_FOR_msa_clei_u_d, CODE_FOR_msa_div_s_b)
(CODE_FOR_msa_div_s_h, CODE_FOR_msa_div_s_w)
(CODE_FOR_msa_div_s_d, CODE_FOR_msa_div_u_b)
(CODE_FOR_msa_div_u_h, CODE_FOR_msa_div_u_w)
(CODE_FOR_msa_div_u_d, CODE_FOR_msa_fadd_w, CODE_FOR_msa_fadd_d)
(CODE_FOR_msa_fexdo_w, CODE_FOR_msa_ftrunc_s_w)
(CODE_FOR_msa_ftrunc_s_d, CODE_FOR_msa_ftrunc_u_w)
(CODE_FOR_msa_ftrunc_u_d, CODE_FOR_msa_ffint_s_w)
(CODE_FOR_msa_ffint_s_d, CODE_FOR_msa_ffint_u_w)
(CODE_FOR_msa_ffint_u_d, CODE_FOR_msa_fsub_w)
(CODE_FOR_msa_fsub_d, CODE_FOR_msa_fmsub_d, CODE_FOR_msa_fmadd_w)
(CODE_FOR_msa_fmadd_d, CODE_FOR_msa_fmsub_w, CODE_FOR_msa_fmul_w)
(CODE_FOR_msa_fmul_d, CODE_FOR_msa_fdiv_w, CODE_FOR_msa_fdiv_d)
(CODE_FOR_msa_fmax_w, CODE_FOR_msa_fmax_d, CODE_FOR_msa_fmax_a_w)
(CODE_FOR_msa_fmax_a_d, CODE_FOR_msa_fmin_w, CODE_FOR_msa_fmin_d)
(CODE_FOR_msa_fmin_a_w, CODE_FOR_msa_fmin_a_d)
(CODE_FOR_msa_fsqrt_w, CODE_FOR_msa_fsqrt_d)
(CODE_FOR_msa_max_s_b, CODE_FOR_msa_max_s_h)
(CODE_FOR_msa_max_s_w, CODE_FOR_msa_max_s_d)
(CODE_FOR_msa_max_u_b, CODE_FOR_msa_max_u_h)
(CODE_FOR_msa_max_u_w, CODE_FOR_msa_max_u_d)
(CODE_FOR_msa_min_s_b, CODE_FOR_msa_min_s_h)
(CODE_FOR_msa_min_s_w, CODE_FOR_msa_min_s_d)
(CODE_FOR_msa_min_u_b, CODE_FOR_msa_min_u_h)
(CODE_FOR_msa_min_u_w, CODE_FOR_msa_min_u_d)
(CODE_FOR_msa_mod_s_b, CODE_FOR_msa_mod_s_h)
(CODE_FOR_msa_mod_s_w, CODE_FOR_msa_mod_s_d)
(CODE_FOR_msa_mod_u_b, CODE_FOR_msa_mod_u_h)
(CODE_FOR_msa_mod_u_w, CODE_FOR_msa_mod_u_d)
(CODE_FOR_msa_mod_s_b, CODE_FOR_msa_mod_s_h)
(CODE_FOR_msa_mod_s_w, CODE_FOR_msa_mod_s_d)
(CODE_FOR_msa_mod_u_b, CODE_FOR_msa_mod_u_h)
(CODE_FOR_msa_mod_u_w, CODE_FOR_msa_mod_u_d)
(CODE_FOR_msa_mulv_b, CODE_FOR_msa_mulv_h, CODE_FOR_msa_mulv_w)
(CODE_FOR_msa_mulv_d, CODE_FOR_msa_nlzc_b, CODE_FOR_msa_nlzc_h)
(CODE_FOR_msa_nlzc_w, CODE_FOR_msa_nlzc_d, CODE_FOR_msa_nor_v)
(CODE_FOR_msa_or_v, CODE_FOR_msa_ori_b, CODE_FOR_msa_nori_b)
(CODE_FOR_msa_pcnt_b, CODE_FOR_msa_pcnt_h, CODE_FOR_msa_pcnt_w)
(CODE_FOR_msa_pcnt_d, CODE_FOR_msa_xor_v, CODE_FOR_msa_xori_b)
(CODE_FOR_msa_sll_b, CODE_FOR_msa_sll_h, CODE_FOR_msa_sll_w)
(CODE_FOR_msa_sll_d, CODE_FOR_msa_slli_b, CODE_FOR_msa_slli_h)
(CODE_FOR_msa_slli_w, CODE_FOR_msa_slli_d, CODE_FOR_msa_sra_b)
(CODE_FOR_msa_sra_h, CODE_FOR_msa_sra_w, CODE_FOR_msa_sra_d)
(CODE_FOR_msa_srai_b, CODE_FOR_msa_srai_h, CODE_FOR_msa_srai_w)
(CODE_FOR_msa_srai_d, CODE_FOR_msa_srl_b, CODE_FOR_msa_srl_h)
(CODE_FOR_msa_srl_w, CODE_FOR_msa_srl_d, CODE_FOR_msa_srli_b)
(CODE_FOR_msa_srli_h, CODE_FOR_msa_srli_w, CODE_FOR_msa_srli_d)
(CODE_FOR_msa_subv_b, CODE_FOR_msa_subv_h, CODE_FOR_msa_subv_w)
(CODE_FOR_msa_subv_d, CODE_FOR_msa_subvi_b, CODE_FOR_msa_subvi_h)
(CODE_FOR_msa_subvi_w, CODE_FOR_msa_subvi_d, CODE_FOR_msa_move_v)
(CODE_FOR_msa_vshf_b, CODE_FOR_msa_vshf_h, CODE_FOR_msa_vshf_w)
(CODE_FOR_msa_vshf_d, CODE_FOR_msa_ilvod_d, CODE_FOR_msa_ilvev_d)
(CODE_FOR_msa_pckod_d, CODE_FOR_msa_pckdev_d, CODE_FOR_msa_ldi_b)
(CODE_FOR_msa_ldi_hi, CODE_FOR_msa_ldi_w)
(CODE_FOR_msa_ldi_d): New code_aliasing macros.
(mips_builtins): Add MSA sll_b, sll_h, sll_w, sll_d, slli_b,
slli_h, slli_w, slli_d, sra_b, sra_h, sra_w, sra_d, srai_b,
srai_h, srai_w, srai_d, srar_b, srar_h, srar_w, srar_d, srari_b,
srari_h, srari_w, srari_d, srl_b, srl_h, srl_w, srl_d, srli_b,
srli_h, srli_w, srli_d, srlr_b, srlr_h, srlr_w, srlr_d, srlri_b,
srlri_h, srlri_w, srlri_d, bclr_b, bclr_h, bclr_w, bclr_d,
bclri_b, bclri_h, bclri_w, bclri_d, bset_b, bset_h, bset_w,
bset_d, bseti_b, bseti_h, bseti_w, bseti_d, bneg_b, bneg_h,
bneg_w, bneg_d, bnegi_b, bnegi_h, bnegi_w, bnegi_d, binsl_b,
binsl_h, binsl_w, binsl_d, binsli_b, binsli_h, binsli_w,
binsli_d, binsr_b, binsr_h, binsr_w, binsr_d, binsri_b, binsri_h,
binsri_w, binsri_d, addv_b, addv_h, addv_w, addv_d, addvi_b,
addvi_h, addvi_w, addvi_d, subv_b, subv_h, subv_w, subv_d,
subvi_b, subvi_h, subvi_w, subvi_d, max_s_b, max_s_h, max_s_w,
max_s_d, maxi_s_b, maxi_s_h, maxi_s_w, maxi_s_d, max_u_b,
max_u_h, max_u_w, max_u_d, maxi_u_b, maxi_u_h, maxi_u_w,
maxi_u_d, min_s_b, min_s_h, min_s_w, min_s_d, mini_s_b, mini_s_h,
mini_s_w, mini_s_d, min_u_b, min_u_h, min_u_w, min_u_d, mini_u_b,
mini_u_h, mini_u_w, mini_u_d, max_a_b, max_a_h, max_a_w, max_a_d,
min_a_b, min_a_h, min_a_w, min_a_d, ceq_b, ceq_h, ceq_w, ceq_d,
ceqi_b, ceqi_h, ceqi_w, ceqi_d, clt_s_b, clt_s_h, clt_s_w,
clt_s_d, clti_s_b, clti_s_h, clti_s_w, clti_s_d, clt_u_b,
clt_u_h, clt_u_w, clt_u_d, clti_u_b, clti_u_h, clti_u_w,
clti_u_d, cle_s_b, cle_s_h, cle_s_w, cle_s_d, clei_s_b, clei_s_h,
clei_s_w, clei_s_d, cle_u_b, cle_u_h, cle_u_w, cle_u_d, clei_u_b,
clei_u_h, clei_u_w, clei_u_d, ld_b, ld_h, ld_w, ld_d, st_b, st_h,
st_w, st_d, sat_s_b, sat_s_h, sat_s_w, sat_s_d, sat_u_b, sat_u_h,
sat_u_w, sat_u_d, add_a_b, add_a_h, add_a_w, add_a_d, adds_a_b,
adds_a_h, adds_a_w, adds_a_d, adds_s_b, adds_s_h, adds_s_w,
adds_s_d, adds_u_b, adds_u_h, adds_u_w, adds_u_d, ave_s_b,
ave_s_h, ave_s_w, ave_s_d, ave_u_b, ave_u_h, ave_u_w, ave_u_d,
aver_s_b, aver_s_h, aver_s_w, aver_s_d, aver_u_b, aver_u_h,
aver_u_w, aver_u_d, subs_s_b, subs_s_h, subs_s_w, subs_s_d,
subs_u_b, subs_u_h, subs_u_w, subs_u_d, subsuu_s_b, subsuu_s_h,
subsuu_s_w, subsuu_s_d, subsus_u_b, subsus_u_h, subsus_u_w,
subsus_u_d, asub_s_b, asub_s_h, asub_s_w, asub_s_d, asub_u_b,
asub_u_h, asub_u_w, asub_u_d, mulv_b, mulv_h, mulv_w, mulv_d,
maddv_b, maddv_h, maddv_w, maddv_d, msubv_b, msubv_h, msubv_w,
msubv_d, div_s_b, div_s_h, div_s_w, div_s_d, div_u_b, div_u_h,
div_u_w, div_u_d, hadd_s_h, hadd_s_w, hadd_s_d, hadd_u_h,
hadd_u_w, hadd_u_d, hsub_s_h, hsub_s_w, hsub_s_d, hsub_u_h,
hsub_u_w, hsub_u_d, mod_s_b, mod_s_h, mod_s_w, mod_s_d, mod_u_b,
mod_u_h, mod_u_w, mod_u_d, dotp_s_h, dotp_s_w, dotp_s_d,
dotp_u_h, dotp_u_w, dotp_u_d, dpadd_s_h, dpadd_s_w, dpadd_s_d,
dpadd_u_h, dpadd_u_w, dpadd_u_d, dpsub_s_h, dpsub_s_w, dpsub_s_d,
dpsub_u_h, dpsub_u_w, dpsub_u_d, sld_b, sld_h, sld_w, sld_d,
sldi_b, sldi_h, sldi_w, sldi_d, splat_b, splat_h, splat_w,
splat_d, splati_b, splati_h, splati_w, splati_d, pckev_b,
pckev_h, pckev_w, pckev_d, pckod_b, pckod_h, pckod_w, pckod_d,
ilvl_b, ilvl_h, ilvl_w, ilvl_d, ilvr_b, ilvr_h, ilvr_w, ilvr_d,
ilvev_b, ilvev_h, ilvev_w, ilvev_d, ilvod_b, ilvod_h, ilvod_w,
ilvod_d, vshf_b, vshf_h, vshf_w, vshf_d, and_v, andi_b, or_v,
ori_b, nor_v, nori_b, xor_v, xori_b, bmnz_v, bmnzi_b, bmz_v,
bmzi_b, bsel_v, bseli_b, shf_b, shf_h, shf_w, bnz_v, bz_v,
fill_b, fill_h, fill_w, fill_d, pcnt_b, pcnt_h, pcnt_w,
pcnt_d, nloc_b, nloc_h, nloc_w, nloc_d, nlzc_b, nlzc_h, nlzc_w,
nlzc_d, copy_s_b, copy_s_h, copy_s_w, copy_s_d, copy_u_b,
copy_u_h, copy_u_w, copy_u_d, insert_b, insert_h, insert_w,
insert_d, insve_b, insve_h, insve_w, insve_d, bnz_b, bnz_h,
bnz_w, bnz_d, bz_b, bz_h, bz_w, bz_d, ldi_b, ldi_h, ldi_w, ldi_d,
fcaf_w, fcaf_d, fcor_w, fcor_d, fcun_w, fcun_d, fcune_w, fcune_d,
fcueq_w, fcueq_d, fceq_w, fceq_d, fcne_w, fcne_d, fclt_w, fclt_d,
fcult_w, fcult_d, fcle_w, fcle_d, fcule_w, fcule_d, fsaf_w,
fsaf_d, fsor_w, fsor_d, fsun_w, fsun_d, fsune_w, fsune_d,
fsueq_w, fsueq_d, fseq_w, fseq_d, fsne_w, fsne_d, fslt_w,
fslt_d, fsult_w, fsult_d, fsle_w, fsle_d, fsule_w, fsule_d,
fadd_w, fadd_d, fsub_w, fsub_d, fmul_w, fmul_d, fdiv_w, fdiv_d,
fmadd_w, fmadd_d, fmsub_w, fmsub_d, fexp2_w, fexp2_d, fexdo_h,
fexdo_w, ftq_h, ftq_w, fmin_w, fmin_d, fmin_a_w, fmin_a_d,
fmax_w, fmax_d, fmax_a_w, fmax_a_d, mul_q_h, mul_q_w, mulr_q_h,
mulr_q_w, madd_q_h, madd_q_w, maddr_q_h, maddr_q_w, msub_q_h,
msub_q_w, msubr_q_h, msubr_q_w, fclass_w, fclass_d, fsqrt_w,
fsqrt_d, frcp_w, frcp_d, frint_w, frint_d, frsqrt_w, frsqrt_d,
flog2_w, flog2_d, fexupl_w, fexupl_d, fexupr_w, fexupr_d, ffql_w,
ffql_d, ffqr_w, ffqr_d, ftint_s_w, ftint_s_d, ftint_u_w,
ftint_u_d, ftrunc_s_w, ftrunc_s_d, ftrunc_u_w, ftrunc_u_d,
ffint_s_w, ffint_s_d, ffint_u_w, ffint_u_d, ctcmsa, cfcmsa,
move_v builtins.
(mips_get_builtin_decl_index): New array.
(MIPS_ATYPE_QI, MIPS_ATYPE_HI, MIPS_ATYPE_V2DI, MIPS_ATYPE_V4SI)
(MIPS_ATYPE_V8HI, MIPS_ATYPE_V16QI, MIPS_ATYPE_V2DF)
(MIPS_ATYPE_V4SF, MIPS_ATYPE_UV2DI, MIPS_ATYPE_UV4SI)
(MIPS_ATYPE_UV8HI, MIPS_ATYPE_UV16QI): New.
(mips_init_builtins): Initialize mips_get_builtin_decl_index
array.
(TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION): Define target
hook.
(mips_expand_builtin_insn): Prepare operands for
CODE_FOR_msa_addvi_b, CODE_FOR_msa_addvi_h, CODE_FOR_msa_addvi_w,
CODE_FOR_msa_addvi_d, CODE_FOR_msa_clti_u_b,
CODE_FOR_msa_clti_u_h, CODE_FOR_msa_clti_u_w,
CODE_FOR_msa_clti_u_d, CODE_FOR_msa_clei_u_b,
CODE_FOR_msa_clei_u_h, CODE_FOR_msa_clei_u_w,
CODE_FOR_msa_clei_u_d, CODE_FOR_msa_maxi_u_b,
CODE_FOR_msa_maxi_u_h, CODE_FOR_msa_maxi_u_w,
CODE_FOR_msa_maxi_u_d, CODE_FOR_msa_mini_u_b,
CODE_FOR_msa_mini_u_h, CODE_FOR_msa_mini_u_w,
CODE_FOR_msa_mini_u_d, CODE_FOR_msa_subvi_b,
CODE_FOR_msa_subvi_h, CODE_FOR_msa_subvi_w, CODE_FOR_msa_subvi_d,
CODE_FOR_msa_ceqi_b, CODE_FOR_msa_ceqi_h, CODE_FOR_msa_ceqi_w,
CODE_FOR_msa_ceqi_d, CODE_FOR_msa_clti_s_b,
CODE_FOR_msa_clti_s_h, CODE_FOR_msa_clti_s_w,
CODE_FOR_msa_clti_s_d, CODE_FOR_msa_clei_s_b,
CODE_FOR_msa_clei_s_h, CODE_FOR_msa_clei_s_w,
CODE_FOR_msa_clei_s_d, CODE_FOR_msa_maxi_s_b,
CODE_FOR_msa_maxi_s_h, CODE_FOR_msa_maxi_s_w,
CODE_FOR_msa_maxi_s_d, CODE_FOR_msa_mini_s_b,
CODE_FOR_msa_mini_s_h, CODE_FOR_msa_mini_s_w,
CODE_FOR_msa_mini_s_d, CODE_FOR_msa_andi_b, CODE_FOR_msa_ori_b,
CODE_FOR_msa_nori_b, CODE_FOR_msa_xori_b, CODE_FOR_msa_bmzi_b,
CODE_FOR_msa_bmnzi_b, CODE_FOR_msa_bseli_b, CODE_FOR_msa_fill_b,
CODE_FOR_msa_fill_h, CODE_FOR_msa_fill_w, CODE_FOR_msa_fill_d,
CODE_FOR_msa_ilvl_b, CODE_FOR_msa_ilvl_h, CODE_FOR_msa_ilvl_w,
CODE_FOR_msa_ilvl_d, CODE_FOR_msa_ilvr_b, CODE_FOR_msa_ilvr_h,
CODE_FOR_msa_ilvr_w, CODE_FOR_msa_ilvr_d, CODE_FOR_msa_ilvev_b,
CODE_FOR_msa_ilvev_h, CODE_FOR_msa_ilvev_w, CODE_FOR_msa_ilvod_b,
CODE_FOR_msa_ilvod_h, CODE_FOR_msa_ilvod_w, CODE_FOR_msa_pckev_b,
CODE_FOR_msa_pckev_h, CODE_FOR_msa_pckev_w, CODE_FOR_msa_pckod_b,
CODE_FOR_msa_pckod_h, CODE_FOR_msa_pckod_w, CODE_FOR_msa_slli_b,
CODE_FOR_msa_slli_h, CODE_FOR_msa_slli_w, CODE_FOR_msa_slli_d,
CODE_FOR_msa_srai_b, CODE_FOR_msa_srai_h, CODE_FOR_msa_srai_w,
CODE_FOR_msa_srai_d, CODE_FOR_msa_srli_b, CODE_FOR_msa_srli_h,
CODE_FOR_msa_srli_w, CODE_FOR_msa_srli_d, CODE_FOR_msa_insert_b,
CODE_FOR_msa_insert_h, CODE_FOR_msa_insert_w,
CODE_FOR_msa_insert_d, CODE_FOR_msa_insve_b,
CODE_FOR_msa_insve_h, CODE_FOR_msa_insve_w, CODE_FOR_msa_insve_d,
CODE_FOR_msa_shf_b, CODE_FOR_msa_shf_h, CODE_FOR_msa_shf_w,
CODE_FOR_msa_shf_w_f, CODE_FOR_msa_vshf_b, CODE_FOR_msa_vshf_h,
CODE_FOR_msa_vshf_w, CODE_FOR_msa_vshf_d.
(mips_expand_builtin): Add case for MIPS_BULTIN_MSA_TEST_BRANCH.
(mips_set_compression_mode): Disallow MSA with MIPS16 code.
(mips_option_override): -mmsa requires -mfp64 and -mhard-float.
These are set implicitly and an error is reported if overridden.
(mips_expand_builtin_msa_test_branch): New function.
(mips_expand_msa_shuffle): Likewise.
(MAX_VECT_LEN): Increase maximum length of a vector to 16 bytes.
(TARGET_SCHED_REASSOCIATION_WIDTH): Define target hook.
(TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES): Likewise.
(mips_expand_vec_unpack): Add support for MSA.
(mips_expand_vector_init): Likewise.
(mips_expand_vi_constant): Use CONST0_RTX (element_mode)
instead of const0_rtx.
(mips_msa_vec_parallel_const_half): New function.
(mips_gen_const_int_vector): Likewise.
(mips_gen_const_int_vector_shuffle): Likewise.
(mips_expand_msa_cmp): Likewise.
(mips_expand_vec_cond_expr): Likewise.
* config/mips/mips.h
(TARGET_CPU_CPP_BUILTINS): Add __mips_msa and __mips_msa_width.
(OPTION_DEFAULT_SPECS): Ignore --with-fp-32 if -mmsa is
specified.
(ASM_SPEC): Pass mmsa and mno-msa to the assembler.
(ISA_HAS_MSA): New macro.
(UNITS_PER_MSA_REG): Likewise.
(BITS_PER_MSA_REG): Likewise.
(BIGGEST_ALIGNMENT): Redefine using ISA_HAS_MSA.
(MSA_REG_FIRST): New macro.
(MSA_REG_LAST): Likewise.
(MSA_REG_NUM): Likewise.
(MSA_REG_P): Likewise.
(MSA_REG_RTX_P): Likewise.
(MSA_SUPPORTED_MODE_P): Likewise.
(HARD_REGNO_CALL_PART_CLOBBERED): Redefine using TARGET_MSA.
(ADDITIONAL_REGISTER_NAMES): Add named registers $w0-$w31.
* config/mips/mips.md: Include mips-msa.md.
(alu_type): Add simd_add.
(mode): Add V2DI, V4SI, V8HI, V16QI, V2DF, V4SF.
(type): Add simd_div, simd_fclass, simd_flog2, simd_fadd,
simd_fcvt, simd_fmul, simd_fmadd, simd_fdiv, simd_bitins,
simd_bitmov, simd_insert, simd_sld, simd_mul, simd_fcmp,
simd_fexp2, simd_int_arith, simd_bit, simd_shift, simd_splat,
simd_fill, simd_permute, simd_shf, simd_sat, simd_pcnt,
simd_copy, simd_branch, simd_cmsa, simd_fminmax, simd_logic,
simd_move, simd_load, simd_store. Choose "multi" for moves
for "qword_mode".
(qword_mode): New attribute.
(insn_count): Add instruction count for quad moves.
Increase the count for MIPS SIMD division.
(UNITMODE): Add UNITMODEs for vector types.
(addsub): New code iterator.
* config/mips/mips.opt (mmsa): New option.
* config/mips/msa.h: New file.
* config/mips/mti-elf.h: Don't infer -mfpxx if -mmsa is
specified.
* config/mips/mti-linux.h: Likewise.
* config/mips/predicates.md
(const_msa_branch_operand): New constraint.
(const_uimm3_operand): Likewise.
(const_uimm4_operand): Likewise.
(const_uimm5_operand): Likewise.
(const_uimm8_operand): Likewise.
(const_imm5_operand): Likewise.
(aq10b_operand): Likewise.
(aq10h_operand): Likewise.
(aq10w_operand): Likewise.
(aq10d_operand): Likewise.
(const_m1_operand): Likewise.
(reg_or_m1_operand): Likewise.
(const_exp_2_operand): Likewise.
(const_exp_4_operand): Likewise.
(const_exp_8_operand): Likewise.
(const_exp_16_operand): Likewise.
(const_vector_same_val_operand): Likewise.
(const_vector_same_simm5_operand): Likewise.
(const_vector_same_uimm5_operand): Likewise.
(const_vector_same_uimm6_operand): Likewise.
(const_vector_same_uimm8_operand): Likewise.
(par_const_vector_shf_set_operand): Likewise.
(reg_or_vector_same_val_operand): Likewise.
(reg_or_vector_same_simm5_operand): Likewise.
(reg_or_vector_same_uimm6_operand): Likewise.
* doc/extend.texi (MIPS SIMD Architecture Functions): New
section.
* doc/invoke.texi (-mmsa): Document new option.
Co-Authored-By: Chao-ying Fu <chao-ying.fu@imgtec.com>
Co-Authored-By: Graham Stott <graham.stott@imgtec.com>
Co-Authored-By: Matthew Fortune <matthew.fortune@imgtec.com>
Co-Authored-By: Sameera Deshpande <sameera.deshpande@imgtec.com>
From-SVN: r236030
Rainer Orth [Mon, 9 May 2016 11:54:55 +0000 (11:54 +0000)]
Error out on -fvtable-verify without --enable-vtable-verify
* configure.ac (enable_vtable_verify): Handle --enable-vtable-verify.
* configure: Regenerate.
* config.in: Regenerate.
* gcc.c (VTABLE_VERIFICATION_SPEC) [!ENABLE_VTABLE_VERIFY]: Error
on -fvtable-verify.
* config/sol2.h [!ENABLE_VTABLE_VERIFY] (STARTFILE_VTV_SPEC): Define.
(ENDFILE_VTV_SPEC): Define.
From-SVN: r236029
Jonathan Wakely [Mon, 9 May 2016 11:50:01 +0000 (12:50 +0100)]
libstdc++/71004 fix recent additions to testcase
PR libstdc++/71004
* testsuite/experimental/filesystem/iterators/
recursive_directory_iterator.cc: Fix test02 to not call member
functions on invalid iterator, and use VERIFY not assert.
From-SVN: r236028
Kaushik Phatak [Mon, 9 May 2016 11:44:58 +0000 (11:44 +0000)]
rl78.c (rl78_expand_prologue): Save the MDUC related registers in all interrupt handlers if necessary.
* config/rl78/rl78.c (rl78_expand_prologue): Save the MDUC related
registers in all interrupt handlers if necessary.
(rl78_option_override): Add warning.
(MUST_SAVE_MDUC_REGISTERS): New macro.
(rl78_expand_epilogue): Restore the MDUC registers if necessary.
* config/rl78/rl78.c (check_mduc_usage): New function.
(mduc_regs): New structure to hold MDUC register data.
* config/rl78/rl78.md (is_g13_muldiv_insn): New attribute.
(mulsi3_g13): Add is_g13_muldiv_insn attribute.
(udivmodsi4_g13): Add is_g13_muldiv_insn attribute.
(mulhi3_g13): Add is_g13_muldiv_insn attribute.
* config/rl78/rl78.opt (msave-mduc-in-interrupts): New option.
* doc/invoke.texi (RL78 Options): Add -msave-mduc-in-interrupts.
From-SVN: r236027
Bin Cheng [Mon, 9 May 2016 11:44:03 +0000 (11:44 +0000)]
tree-if-conv.c (tree-ssa-loop.h): Include header file.
* tree-if-conv.c (tree-ssa-loop.h): Include header file.
(tree-ssa-loop-niter.h): Ditto.
(idx_within_array_bound, ref_within_array_bound): New functions.
(ifcvt_memrefs_wont_trap): Check if array ref is within bound.
Factor out check on writable base object to ...
(base_object_writable): ... here.
gcc/testsuite/
* gcc.dg/tree-ssa/ifc-9.c: New test.
* gcc.dg/tree-ssa/ifc-10.c: New test.
* gcc.dg/tree-ssa/ifc-11.c: New test.
* gcc.dg/tree-ssa/ifc-12.c: New test.
* gcc.dg/vect/pr61194.c: Remove XFAIL.
* gcc.dg/vect/vect-23.c: Remove XFAIL.
* gcc.dg/vect/vect-mask-store-move-1.c: Revise test check.
From-SVN: r236026
Ville Voutilainen [Mon, 9 May 2016 11:03:36 +0000 (14:03 +0300)]
Avoid endless run-time recursion for copying single-element tuples where the...
Avoid endless run-time recursion for copying single-element
tuples where the element type is by-value constructible
from any type.
* include/std/tuple (_NotSameTuple): New.
* include/std/tuple (tuple(_UElements&&...): Use it.
* testsuite/20_util/tuple/cons/element_accepts_anything_byval.cc: New.
From-SVN: r236025
Kyrylo Tkachov [Mon, 9 May 2016 10:21:06 +0000 (10:21 +0000)]
[ARM] Add mode to probe_stack set operands
* config/arm/arm.md (probe_stack): Add modes to set source
and destination.
From-SVN: r236024
Jonathan Wakely [Mon, 9 May 2016 10:09:37 +0000 (11:09 +0100)]
libstdc++/71004 fix recursive_directory_iterator default constructor
PR libstdc++/71004
* include/experimental/bits/fs_dir.h (recursive_directory_iterator):
Initialize scalar member variables in default constructor.
* testsuite/experimental/filesystem/iterators/
recursive_directory_iterator.cc: Teste default construction.
From-SVN: r236023
Bernd Schmidt [Mon, 9 May 2016 09:44:30 +0000 (09:44 +0000)]
regrename.c (base_reg_class_for_rename): New static function.
* regrename.c (base_reg_class_for_rename): New static function.
(scan_rtx_address, scan_rtx): Use it instead of base_reg_class.
From-SVN: r236022
Richard Biener [Mon, 9 May 2016 07:42:45 +0000 (07:42 +0000)]
re PR fortran/70937 (ICE: tree code ‘ssa_name’ is not supported in LTO streams)
2016-05-09 Richard Biener <rguenther@suse.de>
PR fortran/70937
* trans-decl.c: Include gimplify.h for unshare_expr.
(gfc_trans_vla_one_sizepos): Unshare exprs before inserting
them into the IL.
* gfortran.dg/pr70937.f90: New testcase.
From-SVN: r236021
GCC Administrator [Mon, 9 May 2016 00:16:21 +0000 (00:16 +0000)]
Daily bump.
From-SVN: r236017
Kaz Kojima [Sun, 8 May 2016 23:01:58 +0000 (23:01 +0000)]
config/sh/sh.h: Remove extra colon from subtarget specs.
From-SVN: r236013
Jan Hubicka [Sun, 8 May 2016 18:44:02 +0000 (20:44 +0200)]
cgraph.c (thunk_adjust): Export.
* cgraph.c (thunk_adjust): Export.
* cgraphclones.c (cgraph_node::create_clone): Clone thunk info.
* cgraphunit.c (thunk_adjust): Export.
(cgraph_node::assemble_thunks_and_aliases): Do not assemble inlined
thunks.
* ipa-inline-analyssi.c (compute_inline_parameters): Thunks are
inlinable.
* tree-inline.c (expand_call_inline): Expand thunks inline.
From-SVN: r236012
Uros Bizjak [Sun, 8 May 2016 18:18:42 +0000 (20:18 +0200)]
re PR target/70998 (ICE in pre_and_rev_post_order_compute, at cfganal.c)
PR target/70998
* config/i386/sse.md (*sse2_vd_cvtsd2ss): New insn pattern.
(*sse2_vd_cvtss2sd): Ditto.
* config/i386/i386.md
(TARGET_SSE_PARTIAL_REG_DEPENDENCY float_truncate df->sf splitter):
Generate *sse2_vd_cvtsd2ss pattern.
(TARGET_SSE_PARTIAL_REG_DEPENDENCY float_extend sf->df splitter):
Generate *sse2_vd_cvtss2sd pattern.
From-SVN: r236011
Oleg Endo [Sun, 8 May 2016 14:15:24 +0000 (14:15 +0000)]
sh.h (GET_SH_ARG_CLASS): Convert macro into ...
gcc/
* config/sh/sh.h (GET_SH_ARG_CLASS): Convert macro into ...
* config/sh/sh.c (get_sh_arg_class): ... this new function. Update its
users.
From-SVN: r236009
Oleg Endo [Sun, 8 May 2016 14:08:09 +0000 (14:08 +0000)]
sh-protos.h (sh_media_register_for_return): Remove.
gcc/
* config/sh/sh-protos.h (sh_media_register_for_return): Remove.
* config/sh/sh.c: Define and declare variables on first use throughout
the file.
(current_function_interrupt): Change to bool type.
(frame_insn): Rename to emit_frame_insn and update users.
(push_regs): Use bool for 'interrupt_handler' argument.
(save_schedule_s): Remove.
(TARGET_ASM_UNALIGNED_DI_OP, TARGET_ASM_ALIGNED_DI_OP): Remove.
(sh_option_override): Don't nullify targetm.asm_out.aligned_op.di and
targetm.asm_out.unaligned_op.di.
(gen_far_branch): Remove redundant forward declaration.
(sh_media_register_for_return, MAX_SAVED_REGS, save_entry_s, save_entry,
MAX_TEMPS, save_schedule_ssave_schedule): Remove.
(sh_set_return_address, sh_function_ok_for_sibcall,
scavenge_reg): Update comments.
(sh_builtin_saveregs): Use TRAGET_FPU_ANY condition.
(sh2a_get_function_vector_number, sh2a_function_vector_p): Use for loop.
(sh_attr_renesas_p): Remove unnecessary parentheses.
(branch_dest): Simplify.
* config/sh/sh.h (sh_args): Remove byref, byref_regs, stack_regs fields.
Change force_mem, prototype_p, outgoing, renesas_abi fields to bool.
(CUMULATIVE_ARGS): Change macro to typedef.
(current_function_interrupt): Change to bool type.
(sh_arg_class, sh_args, CUMULATIVE_ARGS, current_function_interrupt):
Surround with __cplusplus ifdef.
(sh_compare_op0, sh_compare_op1): Remove.
(EPILOGUE_USES): Use TARGET_FPU_ANY condition.
From-SVN: r236008
Rainer Orth [Sun, 8 May 2016 11:52:38 +0000 (11:52 +0000)]
Fix gcc.dg/ipa/pure-const-3.c scan
* gcc.dg/ipa/pure-const-3.c: Scan local-pure-const1 dump.
From-SVN: r236007
GCC Administrator [Sun, 8 May 2016 00:16:19 +0000 (00:16 +0000)]
Daily bump.
From-SVN: r236003
Fritz Reese [Sat, 7 May 2016 23:16:23 +0000 (23:16 +0000)]
re PR fortran/56226 (Add support for DEC UNION and MAP extensions)
2016-05-07 Fritz Reese <fritzoreese@gmail.com>
PR fortran/56226
* module.c (dt_upper_string): Rename to gfc_dt_upper_string
(dt_lower_string): Likewise.
* gfortran.h: Make new gfc_dt_upper/lower_string global.
* class.c: Use gfc_dt_upper_string.
* decl.c: Likewise.
* symbol.c: Likewise.
* resolve.c (resolve_component): New function.
(resolve_fl_derived0): Move component loop code to resolve_component.
* parse.c (check_component): New function.
(parse_derived): Move loop code to check_component.
* lang.opt, invoke.texi, options.c : New option -fdec-structure.
* libgfortran.h (bt): New basic type BT_UNION.
* gfortran.h (gfc_option): New option -fdec-structure.
(gfc_get_union_type, gfc_compare_union_types): New prototypes.
(gfc_bt_struct, gfc_fl_struct, case_bt_struct, case_fl_struct): New
macros.
(gfc_find_component): Change prototype.
* match.h (gfc_match_member_sep, gfc_match_map, gfc_match_union,
gfc_match_structure_decl): New prototypes.
* parse.h (gfc_comp_struct): New macro.
* symbol.c (gfc_find_component): Search for components in nested unions
* class.c (insert_component_ref, gfc_add_component_ref, add_proc_comp,
copy_vtab_proc_comps): Update calls to gfc_find_component.
* primary.c (gfc_convert_to_structure_constructor): Likewise.
* symbol.c (gfc_add_component): Likewise.
* resolve.c (resolve_typebound_function, resolve_typebound_subroutine,
resolve_typebound_procedure, resolve_component, resolve_fl_derived):
Likewise.
* expr.c (get_union_init, component_init): New functions.
* decl.c (match_clist_expr, match_record_decl, get_struct_decl,
gfc_match_map, gfc_match_union, gfc_match_structure_decl): Likewise.
* interface.c (compare_components, gfc_compare_union_types): Likewise.
* match.c (gfc_match_member_sep): Likewise.
* parse.c (check_component, parse_union, parse_struct_map): Likewise.
* resolve.c (resolve_fl_struct): Likewise.
* symbol.c (find_union_component): Likewise.
* trans-types.c (gfc_get_union_type): Likewise.
* parse.c (parse_derived): Use new functions.
* interface.c (gfc_compare_derived_types, gfc_compare_types): Likewise.
* expr.c (gfc_default_initializer): Likewise.
* gfortran.texi: Support for DEC structures, unions, and maps.
* gfortran.h (gfc_statement, sym_flavor): Likewise.
* check.c (gfc_check_kill_sub): Likewise.
* expr.c (gfc_copy_expr, simplify_const_ref,
gfc_has_default_initializer): Likewise.
* decl.c (build_sym, match_data_constant, add_init_expr_to_sym,
match_pointer_init, build_struct, variable_decl,
gfc_match_decl_type_spec, gfc_mach_data-decl, gfc_match_entry,
gfc_match_end, gfc_match_derived_decl): Likewise.
* interface.c (check_interface0, check_interface1,
gfc_search_interface): Likewise.
* misc.c (gfc_basic_typename, gfc_typename): Likewise.
* module.c (add_true_name, build_tnt, bt_types, mio_typespec,
fix_mio_expr, load_needed, mio_symbol, read_module, write_symbol,
gfc_get_module_backend_decl): Likewise.
* parse.h (gfc_compile_state): Likewise.
* parse.c (decode_specification_statement, decode_statement,
gfc_ascii_statement, verify_st_order, parse_spec): Likewise.
* primary.c (gfc_match_varspec, gfc_match_structure_constructor,
gfc_match_rvalue, match_variable): Likewise.
* resolve.c (find_arglists, resolve_structure_cons,
is_illegal_recursion, resolve_generic_f, get_declared_from_expr,
resolve_typebound_subroutine, resolve_allocate_expr,
nonscalar_typebound_assign, generate_component_assignments,
resolve_fl_variable_derived, check_defined_assignments,
resolve_component, resolve_symbol, resolve_equivalence_derived):
Likewise.
* symbol.c (flavors, check_conflict, gfc_add_flavor, gfc_use_derived,
gfc_restore_last_undo_checkpoint, gfc_type_compatible,
gfc_find_dt_in_generic): Likewise.
* trans-decl.c (gfc_get_module_backend_decl, create_function_arglist,
gfc_create_module_variable, check_constant_initializer): Likewise.
* trans-expr.c (gfc_conv_component_ref, gfc_conv_initializer,
gfc_trans_alloc_subarray_assign, gfc_trans_subcomponent_assign,
gfc_conv_structure, gfc_trans_scalar_assign, copyable_array_p):
Likewise.
* trans-io.c (transfer_namelist_element, transfer_expr,
gfc_trans_transfer): Likewise.
* trans-stmt.c (gfc_trans_deallocate): Likewise.
* trans-types.c (gfc_typenode_for_spec, gfc_copy_dt_decls_ifequal,
gfc_get_derived_type): Likewise.
2016-05-07 Fritz Reese <fritzoreese@gmail.com>
PR fortran/56226
* gfortran.dg/dec_structure_1.f90: New testcase.
* gfortran.dg/dec_structure_2.f90: Ditto.
* gfortran.dg/dec_structure_3.f90: Ditto.
* gfortran.dg/dec_structure_4.f90: Ditto.
* gfortran.dg/dec_structure_5.f90: Ditto.
* gfortran.dg/dec_structure_6.f90: Ditto.
* gfortran.dg/dec_structure_7.f90: Ditto.
* gfortran.dg/dec_structure_8.f90: Ditto.
* gfortran.dg/dec_structure_9.f90: Ditto.
* gfortran.dg/dec_structure_10.f90: Ditto.
* gfortran.dg/dec_structure_11.f90: Ditto.
* gfortran.dg/dec_union_1.f90: Ditto.
* gfortran.dg/dec_union_2.f90: Ditto.
* gfortran.dg/dec_union_3.f90: Ditto.
* gfortran.dg/dec_union_4.f90: Ditto.
* gfortran.dg/dec_union_5.f90: Ditto.
* gfortran.dg/dec_union_6.f90: Ditto.
* gfortran.dg/dec_union_7.f90: Ditto.
From-SVN: r235999
Jim Wilson [Sat, 7 May 2016 23:11:57 +0000 (23:11 +0000)]
Emit vmov.i64 to load 0.0 into FP reg when neon enabled.
* config/arm/arm.md: (arch): Add neon.
(arch_enabled): Return yes for arch neon when TARGET_NEON.
* config/arm/vfp.md (movdf_vfp): Add w/G as alternative 3. Add
neon_move as type for alt 3. Add arch attr enabling alt 3 for neon.
Emit vmov.i64 for alt 3. Renumber alternatives 3 to 8. Adjust
attributes for alt renumbering. Mark alt 3 as non-predicable.
(thumb2_movdf_vfp): Likewise.
From-SVN: r235998
Uros Bizjak [Sat, 7 May 2016 14:36:11 +0000 (16:36 +0200)]
i386.md (*addqi_1): Add preferred_for_speed attribute to disparage alternatives 3 and 4 for...
* config/i386/i386.md (*addqi_1): Add preferred_for_speed attribute
to disparage alternatives 3 and 4 for TARGET_PARTIAL_REG_STALL targets.
(*andqi_1): Add preferred_for_speed attribute to disparage
alternative 2 for TARGET_PARTIAL_REG_STALL targets.
(*<code>qi_1): Ditto.
(*one_cmplqi2_1): Add preferred_for_speed attribute to disparage
alternative 1 for TARGET_PARTIAL_REG_STALL targets.
(*ashlqi3_1): Ditto.
(*swap<mode>): Merge from *swap<mode>_1 and *swap<mode>_2 patterns.
Add preferred_for_size attribute to disparage alternative 0 and
preferred_for_speed attribute to disparage alternative 1 for
TARGET_PARTIAL_REG_STALL targets.
From-SVN: r235996
Tom de Vries [Sat, 7 May 2016 06:47:07 +0000 (06:47 +0000)]
Handle NULL def in build_cross_bb_scalars_def
2016-05-07 Tom de Vries <tom@codesourcery.com>
PR tree-optimization/70956
* graphite-scop-detection.c (build_cross_bb_scalars_def): Handle NULL
def.
* gcc.dg/graphite/pr70956.c: New test.
From-SVN: r235994
Oleg Endo [Sat, 7 May 2016 01:43:12 +0000 (01:43 +0000)]
sh-protos.h (sh_cbranch_distance): Declare new function.
gcc/
* config/sh/sh-protos.h (sh_cbranch_distance): Declare new function.
* config/sh/sh.c (sh_cbranch_distance): Implement it.
* config/sh/sh.md (branch_zero): Remove define_attr.
(define_delay): Disable delay slot if branch distance is one insn.
From-SVN: r235993
GCC Administrator [Sat, 7 May 2016 00:16:19 +0000 (00:16 +0000)]
Daily bump.
From-SVN: r235992
Ian Lance Taylor [Fri, 6 May 2016 21:24:19 +0000 (21:24 +0000)]
escape: Add escape graph nodes.
Introduces the nodes used to model connectivity in the escape graph
and related state: a node's escape level and an encoding that will
be added to import and export data.
Reviewed-on: https://go-review.googlesource.com/18268
From-SVN: r235988
Uros Bizjak [Fri, 6 May 2016 21:14:20 +0000 (23:14 +0200)]
i386.md (LEAMODE): New mode attribute.
* config/i386/i386.md (LEAMODE): New mode attribute.
(plus to LEA splitter): Rewrite splitter using LEAMODE mode attribute.
(ashift to LEA splitter): Rewrte splitter using SWI mode iterator
and LEAMODE mode attribute. Use VOIDmode const_0_to_3_operand as
operand 2 predicate.
(*lea<mode>_general_2): Use VOIDmode for const248_operand.
(*lea<mode>_general_3): Ditto.
(*lea<mode>_general_4): Use VOIDmode for const_0_to_3_operand.
From-SVN: r235987
Jakub Jelinek [Fri, 6 May 2016 20:42:10 +0000 (22:42 +0200)]
* genmddump.c (main): Convert argv from char ** to const char **.
From-SVN: r235985
Uros Bizjak [Fri, 6 May 2016 18:24:40 +0000 (20:24 +0200)]
i386.md (int cmove peephole2s): Use general_reg_operand instead of register_and_not_any_fp_reg_operand as...
* config/i386/i386.md (int cmove peephole2s): Use general_reg_operand
instead of register_and_not_any_fp_reg_operand as operand 0 predicate.
* config/i386/predicates.md (register_and_not_any_fp_reg_operand):
Remove unused predicate.
(register_and_not_fp_reg_operand): Ditto.
From-SVN: r235983
Chris Manghane [Fri, 6 May 2016 17:37:55 +0000 (17:37 +0000)]
escape: Add skeleton for gc analysis.
Introduces a skeleton replacement escape analysis
which contains four different phases extracted from the escape
analysis implementation in gc/esc.go. Also introduces the
Escape_context each phase uses to make decisions.
Reviewed-on: https://go-review.googlesource.com/18220
From-SVN: r235982
David Malcolm [Fri, 6 May 2016 17:02:01 +0000 (17:02 +0000)]
Add OVERRIDE and FINAL macros to coretypes.h
gcc/ChangeLog:
* coretypes.h (OVERRIDE): New macro.
(FINAL): New macro.
From-SVN: r235981
Eric Botcazou [Fri, 6 May 2016 15:54:15 +0000 (15:54 +0000)]
tree-ssa-coalesce.c (gimple_can_coalesce_p): In the optimized case, allow coalescing if the types are compatible.
* tree-ssa-coalesce.c (gimple_can_coalesce_p): In the optimized case,
allow coalescing if the types are compatible.
From-SVN: r235980
Jakub Jelinek [Fri, 6 May 2016 15:23:56 +0000 (17:23 +0200)]
re PR target/70941 (Test miscompiled with -O2.)
PR middle-end/70941
* gcc.dg/torture/pr70941.c (abort): Remove prototype.
(a, b, c, d): Change type from char to signed char.
(main): Compare against (signed char) -
1634678893 instead of
hardcoded -109. Use __builtin_abort instead of abort.
From-SVN: r235978
David Malcolm [Fri, 6 May 2016 15:18:59 +0000 (15:18 +0000)]
Move name_to_pass_map into class pass_manager
gcc/ChangeLog:
* pass_manager.h (pass_manager::register_pass_name): New method.
(pass_manager::get_pass_by_name): New method.
(pass_manager::create_pass_tab): New method.
(pass_manager::m_name_to_pass_map): New field.
* passes.c (name_to_pass_map): Delete global in favor of field
"m_name_to_pass_map" of pass_manager.
(register_pass_name): Rename from a function to...
(pass_manager::register_pass_name): ...this method, updating
for renaming of global "name_to_pass_map" to field
"m_name_to_pass_map".
(create_pass_tab): Rename from a function to...
(pass_manager::create_pass_tab): ...this method, updating
for renaming of global "name_to_pass_map" to field.
(get_pass_by_name): Rename from a function to...
(pass_manager::get_pass_by_name): ...this method.
(enable_disable_pass): Convert use of get_pass_by_name to
a method call, locating the pass_manager singleton.
From-SVN: r235977
David Malcolm [Fri, 6 May 2016 15:14:05 +0000 (15:14 +0000)]
Make argv const char ** in read_md_files etc
gcc/ChangeLog:
* genattr-common.c (main): Convert argv from
char ** to const char **.
* genattr.c (main): Likewise.
* genattrtab.c (main): Likewise.
* genautomata.c (initiate_automaton_gen): Likewise.
(main): Likewise.
* gencodes.c (main): Likewise.
* genconditions.c (main): Likewise.
* genconfig.c (main): Likewise.
* genconstants.c (main): Likewise.
* genemit.c (main): Likewise.
* genenums.c (main): Likewise.
* genextract.c (main): Likewise.
* genflags.c (main): Likewise.
* genmddeps.c (main): Likewise.
* genopinit.c (main): Likewise.
* genoutput.c (main): Likewise.
* genpeep.c (main): Likewise.
* genpreds.c (main): Likewise.
* genrecog.c (main): Likewise.
* gensupport.c (init_rtx_reader_args_cb): Likewise.
(init_rtx_reader_args): Likewise.
* gensupport.h (init_rtx_reader_args_cb): Likewise.
(init_rtx_reader_args): Likewise.
* gentarget-def.c (main): Likewise.
* read-md.c (read_md_files): Likewise.
* read-md.h (read_md_files): Likewise.
From-SVN: r235976
Uros Bizjak [Fri, 6 May 2016 14:34:58 +0000 (16:34 +0200)]
i386.md (int cmove peephole2s): Use general_reg_operand instead of register_and_not_any_fp_reg_operand as...
* config/i386/i386.md (int cmove peephole2s): Use general_reg_operand
instead of register_and_not_any_fp_reg_operand as operand 0 predicate.
* config/i386/predicates.md (register_and_not_any_fp_reg_operand):
Remove unused predicate.
(register_and_not_fp_reg_operand): Ditto.
From-SVN: r235975
Martin Liska [Fri, 6 May 2016 14:26:23 +0000 (16:26 +0200)]
Fix memory leak in tree-if-conv.c
* tree-if-conv.c (ifcvt_split_critical_edges): Use auto_vec
instead of vec as the vector is local to the function.
From-SVN: r235974
Jakub Jelinek [Fri, 6 May 2016 13:16:00 +0000 (15:16 +0200)]
sse.md (*<code>v8hi3, [...]): Add avx512bw alternative.
* config/i386/sse.md (*<code>v8hi3, *<code>v16qi3): Add
avx512bw alternative.
From-SVN: r235973
Jakub Jelinek [Fri, 6 May 2016 13:15:24 +0000 (15:15 +0200)]
sse.md (<mask_codefor>ashr<mode>3<mask_name>): Move before the ashr<mode>3 pattern.
* config/i386/sse.md (<mask_codefor>ashr<mode>3<mask_name>): Move
before the ashr<mode>3 pattern.
* gcc.target/i386/avx512bw-vpsraw-3.c: New test.
* gcc.target/i386/avx512vl-vpsrad-3.c: New test.
From-SVN: r235972
Jakub Jelinek [Fri, 6 May 2016 13:14:34 +0000 (15:14 +0200)]
sse.md (*avx2_pmaddwd, [...]): Use v instead of x in vex or maybe_vex alternatives...
* config/i386/sse.md (*avx2_pmaddwd, *sse2_pmaddwd): Use
v instead of x in vex or maybe_vex alternatives, use
maybe_evex instead of vex in prefix.
* gcc.target/i386/avx512bw-vpmaddwd-3.c: New test.
From-SVN: r235971
Jakub Jelinek [Fri, 6 May 2016 13:13:09 +0000 (15:13 +0200)]
sse.md (*vec_extractv4sf_0, [...]): Use v instead of x in vex or maybe_vex alternatives...
* config/i386/sse.md (*vec_extractv4sf_0, *sse4_1_extractps,
*vec_extractv4sf_mem, vec_extract_lo_v16hi, vec_extract_hi_v16hi,
vec_extract_lo_v32qi, vec_extract_hi_v32qi): Use v instead of x
in vex or maybe_vex alternatives, use maybe_evex instead of vex
in prefix.
From-SVN: r235970
Jakub Jelinek [Fri, 6 May 2016 13:12:32 +0000 (15:12 +0200)]
sse.md (*vec_concatv2sf_sse4_1, [...]): Use v instead of x in vex or maybe_vex alternatives...
* config/i386/sse.md (*vec_concatv2sf_sse4_1, *vec_concatv4sf): Use
v instead of x in vex or maybe_vex alternatives, use
maybe_evex instead of vex in prefix.
From-SVN: r235969
Jakub Jelinek [Fri, 6 May 2016 13:11:56 +0000 (15:11 +0200)]
sse.md (sse_shufps_<mode>, [...]): Use v instead of x in vex or maybe_vex alternatives...
* config/i386/sse.md (sse_shufps_<mode>, sse_storehps, sse_loadhps,
sse_storelps, sse_movss, avx2_vec_dup<mode>, avx2_vec_dupv8sf_1,
sse2_shufpd_<mode>, sse2_storehpd, sse2_storelpd, sse2_loadhpd,
sse2_loadlpd, sse2_movsd): Use v instead of x in vex or maybe_vex
alternatives, use maybe_evex instead of vex in prefix.
From-SVN: r235968
Jakub Jelinek [Fri, 6 May 2016 13:11:17 +0000 (15:11 +0200)]
* config/i386/sse.md (vec_interleave_lowv4sf,
*vec_interleave_highv2df, *vec_interleave_lowv2df): Use
v instead of x in vex or maybe_vex alternatives, use
maybe_evex instead of vex in prefix.
From-SVN: r235967
Jakub Jelinek [Fri, 6 May 2016 13:10:39 +0000 (15:10 +0200)]
sse.md (sse_movhlps, [...]): Use v instead of x in vex or maybe_vex alternatives...
* config/i386/sse.md (sse_movhlps, sse_movlhps): Use
v instead of x in vex or maybe_vex alternatives, use
maybe_evex instead of vex in prefix.
From-SVN: r235966
Jakub Jelinek [Fri, 6 May 2016 13:09:53 +0000 (15:09 +0200)]
sse.md (*avx_cvtpd2dq256_2, [...]): Use v constraint instead of x.
* config/i386/sse.md (*avx_cvtpd2dq256_2, *avx_cvtps2pd256_2): Use
v constraint instead of x.
From-SVN: r235965
Nathan Sidwell [Fri, 6 May 2016 13:02:42 +0000 (13:02 +0000)]
gimple.c (gimple_call_same_target_p): Unique functions are eq.
* gimple.c (gimple_call_same_target_p): Unique functions are eq.
* tree-ssa-tail-merge.c (same_succ::equal): Check pointer eq
equality first.
From-SVN: r235964
Richard Biener [Fri, 6 May 2016 12:53:26 +0000 (12:53 +0000)]
re PR tree-optimization/70948 (r235622 caused gcc.c-torture/execute/va-arg-pack-1.c execution failure AArch64)
2016-05-06 Richard Biener <rguenther@suse.de>
PR tree-optimization/70948
* tree-ssa-structalias.c (find_func_aliases_for_builtin_call):
Properly clobber all fields of va_list for __builtin_va_start.
From-SVN: r235963
Yuri Rumyantsev [Fri, 6 May 2016 12:07:25 +0000 (12:07 +0000)]
re PR debug/70935 (ICE: verify_ssa failed (error: definition in block 9 does not dominate use in block 12) w/ -O3 -g)
gcc/
2016-05-06 Yuri Rumyantsev <ysrumyan@gmail.com>
PR debug/70935
* tree-ssa-loop-unswitch.c (find_loop_guard): Reject guard edge with
loop latch destination.
gcc/testsuite/
2016-05-06 Yuri Rumyantsev <ysrumyan@gmail.com>
PR debug/70935
* gcc.dg/torture/pr70935.c: New test.
From-SVN: r235962
Martin Liska [Fri, 6 May 2016 11:27:28 +0000 (13:27 +0200)]
Manual changes to GCC coding style in tree-ssa-uninit.c
* tree-ssa-uninit.c: Apply manual changes
to the GNU coding style.
(prune_uninit_phi_opnds): Rename from
prune_uninit_phi_opnds_in_unrealizable_paths.
From-SVN: r235961
Oleg Endo [Fri, 6 May 2016 11:05:49 +0000 (11:05 +0000)]
sh.opt (madjust-unroll, [...]): Remove deprecated options.
gcc/
* config/sh/sh.opt (madjust-unroll, minvalid-symbols, msoft-atomic,
mspace): Remove deprecated options.
* doc/invoke.texi (SH options): Remove -mspace.
From-SVN: r235960
Oleg Endo [Fri, 6 May 2016 10:35:42 +0000 (10:35 +0000)]
sh.md (ic_invalidate_line_sh4a): Fix insn length.
gcc/
* config/sh/sh.md (ic_invalidate_line_sh4a): Fix insn length.
From-SVN: r235957
Oleg Endo [Fri, 6 May 2016 10:29:33 +0000 (10:29 +0000)]
sh.md (*cmpeqsi_t): Remove combine insn pattern and similar corresponding combine split pattern.
gcc/
* config/sh/sh.md (*cmpeqsi_t): Remove combine insn pattern and similar
corresponding combine split pattern.
From-SVN: r235956
Oleg Endo [Fri, 6 May 2016 10:23:48 +0000 (10:23 +0000)]
Fix ChangeLog formatting.
From-SVN: r235955
Oleg Endo [Fri, 6 May 2016 10:20:13 +0000 (10:20 +0000)]
re PR target/58219 ([SH] mov.l insn length is wrong on SH2A)
gcc/
PR target/58219
* config/sh/predicates.md (long_displacement_mem_operand): New.
* config/sh/sh.md (movsi_i): Allow for SH2A, disallow for any FPU.
Add movi20, movi20s alternatives. Adjust length attribute for
alternatives.
(movsi_ie): Allow for any FPU. Adjust length attribute for
alternatives.
(movsi_i_lowpart): Add movi20, movi20s alternatives. Adjust length
attribute for alternatives.
(*mov<mode>): Use long_displacement_mem_operand for length attribute.
(*movdi_i, movdf_k, movdf_i4, movsf_i, movsf_ie, movsf_ie_ra): Adjust
length attribute for alternatives.
gcc/testsuite/
PR target/58219
*gcc.target/sh/pr58219.c: New tests.
From-SVN: r235954
Richard Biener [Fri, 6 May 2016 10:18:59 +0000 (10:18 +0000)]
re PR tree-optimization/70960 (ICE: tree check: expected ssa_name, have integer_cst in ifcvt_walk_pattern_tree, at tree-if-conv.c:2465)
2016-05-06 Richard Biener <rguenther@suse.de>
PR tree-optimization/70960
* tree-if-conv.c (ifcvt_walk_pattern_tree): Handle non-SSA ops.
* gfortran.fortran-torture/compile/pr70960.f90: New testcase.
From-SVN: r235953
projects / platform / upstream / gcc.git / log