Xiang, Haihao [Fri, 13 Sep 2013 05:21:09 +0000 (13:21 +0800)]
VPP: MADI on IVB
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
219452451ede9d52d8940be55cd38feda50baea7)
Conflicts:
src/i965_drv_video.c
Xiang, Haihao [Fri, 13 Sep 2013 02:12:53 +0000 (10:12 +0800)]
VPP: track the frame sequence for DI on IVB
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
c008b4222d593594330fbb087204ff53722f9765)
Xiang, Haihao [Wed, 11 Sep 2013 03:05:03 +0000 (11:05 +0800)]
VPP: move the BO for STMM into sub-contexts
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
6ce827df0a9d6cb841308813ec54a019e3c63d37)
Xiang, Haihao [Wed, 11 Sep 2013 02:33:25 +0000 (10:33 +0800)]
VPP: Create separate sub-context for each processing
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
4faf6bf47f8e4e2fe587e3bb6a004340edd59c4c)
Conflicts:
src/i965_post_processing.c
src/i965_post_processing.h
Xiang, Haihao [Wed, 11 Sep 2013 01:04:52 +0000 (09:04 +0800)]
VPP: the similar fix to Bob DI on SNB
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
c55cc476b1f75ddf0504a8b85ac80c0168585c5c)
Xiang, Haihao [Wed, 11 Sep 2013 00:43:17 +0000 (08:43 +0800)]
VPP: Update DEINTERLACE_SAMPLER_STATE on IVB
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
b05729d0feea5ceb4217997f26442d5a8d94fa48)
Xiang, Haihao [Tue, 10 Sep 2013 08:45:30 +0000 (16:45 +0800)]
VPP: VAProcFilterParameterBufferDeinterlacing::flags overrides VAProcPipelineParameterBuffer::filter_flags
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
5334ca07c5ad1a2edeb279784bde3d03cbb10c49)
Xiang, Haihao [Mon, 9 Sep 2013 07:16:56 +0000 (15:16 +0800)]
Update NEWS
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Gwenole Beauchesne [Fri, 26 Jul 2013 11:08:27 +0000 (13:08 +0200)]
allow vaDeriveImage() to work for UYVY formats
Hi,
I would push the following as obvious around next week.
Add support for UYVY format to vaDeriveImage(). Also remove dead code
along the way, i.e. packed YUV 4:2:2 formats have a single plane.
Regards,
Gwenole.
Gwenole Beauchesne [Thu, 25 Jul 2013 08:52:31 +0000 (10:52 +0200)]
vpp: fix output filter count from QueryVideoProcFilters().
When vaQueryVideoProcFilters() returns VA_STATUS_ERROR_MAX_NUM_EXCEEDED,
i.e. when the caller allocated too few entries for the filters argument,
then the num_filters argument shall be adjusted to correct number of
entries that need to be re-allocated.
https://bugs.freedesktop.org/show_bug.cgi?id=67292
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Gwenole Beauchesne [Fri, 26 Jul 2013 08:23:39 +0000 (10:23 +0200)]
vpp: add basic processing support for packed YUV to packed YUV.
Add support for video processing from packed YUV 4:2:2 formats (YUY2, UYVY)
to packed YUV 4:2:2 formats. In particular, add support for HW accelerated
vaPutImage() for packed YUV formats.
https://bugs.freedesktop.org/show_bug.cgi?id=67338
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
[Haihao: the shader for IVB+ has been added in 0eb2288]
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 9 Sep 2013 06:44:53 +0000 (14:44 +0800)]
VPP: Packed 4:2:2 to packed 4:2:2 on IVB+
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 9 Sep 2013 06:03:17 +0000 (14:03 +0800)]
VPP: cleanup code
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 9 Sep 2013 05:18:43 +0000 (13:18 +0800)]
Return the status of image processing
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 23 Aug 2013 05:39:07 +0000 (13:39 +0800)]
More conversions between two images with different pixel formsts
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 20 Aug 2013 14:02:09 +0000 (22:02 +0800)]
Convert RGBx/RGBA into non-NV12 format
It is the combined conversions of RGBx/RGBA->NV12 and NV12->non-NV12.
It would be better to implement RGBx/RGBA->YUV444 and YUV444->non-444 later
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 2 Sep 2013 08:23:36 +0000 (16:23 +0800)]
Support B frame for reference frame
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Zhao Yakui [Mon, 12 Aug 2013 07:13:24 +0000 (15:13 +0800)]
Remove the unnecessary shader binary for MPEG2 encoding on Haswell/Ivb
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
42bb613e72d235bcbe141c906dec9431e4c29661)
Zhao Yakui [Mon, 12 Aug 2013 07:13:24 +0000 (15:13 +0800)]
Optimize quantization rounding precision for MPEG2 encoding on Ivy
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
05ea96da3e0b09648bfdeb35967f6ab9bb3b23e4)
Zhao Yakui [Mon, 12 Aug 2013 07:13:24 +0000 (15:13 +0800)]
Optimize the VME shader for MPEG2 encoding on Ivb
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
15db142076321e9523db0c8be8e6bae5e1b64c8a)
Zhao Yakui [Mon, 12 Aug 2013 07:13:24 +0000 (15:13 +0800)]
Optimize MPEG2 encoding on Ivb
This is backported from Haswell. The scoreboard/walker/cost-center
is applied.
Signed-off-by: Zhao yakui <yakui.zhao@intel.com>
(cherry picked from commit
cc7452d14f7faa1d5b5fa8c16db3e3cb3fd4f53d)
Zhao Yakui [Mon, 12 Aug 2013 07:13:24 +0000 (15:13 +0800)]
Rewrite the VME shader for MPEG2 encoding on Ivy
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
6200c9a7779c1309f5a85b7c62aec1b9796793c6)
Zhao Yakui [Mon, 12 Aug 2013 07:13:24 +0000 (15:13 +0800)]
Remove the dead code in file of gen7_vme.c
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
d15582b54486847811f3feab46ddd51181561776)
Zhao Yakui [Mon, 12 Aug 2013 07:13:24 +0000 (15:13 +0800)]
Pass the constant buffer info for MPEG2 encoding correctly on Ivb
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
7690091889eac91dcab53e0318f9810c25071e18)
Zhao Yakui [Mon, 12 Aug 2013 07:13:24 +0000 (15:13 +0800)]
Optimize quantization rounding precision for MPEG2 encoding on haswell
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
24d8bf31c8aeb326bc8b33c1ac9700ec1d169666)
Zhao Yakui [Mon, 12 Aug 2013 07:13:23 +0000 (15:13 +0800)]
Optimize the VME shader for MPEG2 on Haswell
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
19e93152f0e10f94ecaf3ddecf95c1dc7b97dfed)
Zhao Yakui [Mon, 12 Aug 2013 07:13:23 +0000 (15:13 +0800)]
Configure the cost-center of MPEG2 VME shader on haswell
This is derived from the neighbour macroblock based on MPEG2 spec.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
a51860aba2d2713a9c8c817c430ffa93abd5145a)
Zhao Yakui [Mon, 12 Aug 2013 07:13:23 +0000 (15:13 +0800)]
Use the scoreboard/walker to assure MB dependency for MPEG2 encoding
If MVP is added for MPEG2 encoding, it must be assured that the left macroblock
should be already finished before processing the current macroblock.
And this needs the scoreboard/walker mechanism to assure MB dependency.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
5d2163d02d395fc0a794d834979a06c287bf9ba5)
Zhao Yakui [Mon, 12 Aug 2013 07:13:23 +0000 (15:13 +0800)]
configure the dynamic VME MV/mode cost for MPEG2 encoding on Haswell
Currently it uses the constant VME MV/mode cost when executing the mode/motion
vector prediction for MPEG2 encoding on Haswell, which causes that the unoptimized
mode/MV is used for MPEG2 encoding.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
6fec7e353704dc23c9675966467caffa95f792fe)
Zhao Yakui [Mon, 12 Aug 2013 07:13:23 +0000 (15:13 +0800)]
Enable the Intra-prediction for MPEG2 P-B frame
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
c074d4d61ad931d044fbe0836a45c49768090b4b)
Zhao Yakui [Mon, 12 Aug 2013 07:13:23 +0000 (15:13 +0800)]
Restrict the MV search range based on MPEG2 encoding LEVEL
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
c05073b1f8764271ccf4fe1aa037f881dedd3818)
Zhao Yakui [Mon, 12 Aug 2013 07:13:23 +0000 (15:13 +0800)]
Rewrite inter-frame shader for MPEG2 encoding on HSW to follow MPEG2 spec
Now the MPEG2/H264 uses the same mode/motion vector prediction shader. But
the MV search region of mpeg2 is different with that on H264, which causes
that the wrong mode/motion vector prediction is used for MPEG2.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
(cherry picked from commit
6842f08aa375b5942cee4b9d06421609c212895a)
Xiang, Haihao [Fri, 9 Aug 2013 05:52:16 +0000 (13:52 +0800)]
Convert 422H/422V/411P/444P into other formats for internal using
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
232ef48766c1f91a87a3d41f951fd2ac26dcf2ae)
Xiang, Haihao [Fri, 9 Aug 2013 05:40:10 +0000 (13:40 +0800)]
A separate batch buffer for video processing
It is easy to result in multithread issue if the rendering code
and video processing code share the same batch buffer
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
ce0984814269e0923f44196e47f1c7cc2dddc55c)
Xiang, Haihao [Thu, 8 Aug 2013 02:01:50 +0000 (10:01 +0800)]
Use the right wight/height to initialize the internal buffers for MPEG-2 encoding
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
3ecbff585af918d96959ce791eec29be25360d91)
Xiang, Haihao [Thu, 8 Aug 2013 01:52:33 +0000 (09:52 +0800)]
Cleanup profile tracking in encoder
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
edd25a94e92b9cec23594dc978691506a1c8cfab)
Xiang, Haihao [Thu, 8 Aug 2013 01:35:30 +0000 (09:35 +0800)]
Rename the macros
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
3ab97be8db1b8e55d0d5b95f577863416a87c6ff)
Zhao Halley [Thu, 25 Jul 2013 01:09:41 +0000 (09:09 +0800)]
Enable the Bay Trail platform.
This patch adds PCI IDs for Bay Trail (sometimes called Valley View).
As far as the video driver is concerned, it's very similar to
Ivybridge GT1 except VP8 decoding support.
(cherry picked from commit
b3afeef8092dc4eb7cb73fce672ddf7a55205f34)
Li Xiaowei [Thu, 18 Jul 2013 11:18:54 +0000 (19:18 +0800)]
VPP: remove needless functions and parameters in gpe pipeline
(cherry picked from commit
ab0546e76967e5e7c465569f90e192b560678d8c)
Xiang, Haihao [Tue, 23 Jul 2013 05:22:16 +0000 (13:22 +0800)]
Fixes valgrind warning
"Conditional jump or move depends on uninitialised value(s)"
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
cbd00deb6c5cad58ebd5e6ce5b89aaaded0f78a5)
Xiang, Haihao [Tue, 23 Jul 2013 05:14:48 +0000 (13:14 +0800)]
Release the private driver data when call vaTerminate()
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
c735d9e58dd49c9a92ad0042b5649a9d3fe7c2c4)
Xiang, Haihao [Tue, 23 Jul 2013 05:08:05 +0000 (13:08 +0800)]
VPP: check the filter when query the video filter capabilities
Return VA_STATUS_ERROR_UNSUPPORTED_FILTER if an unsupported filter
was supplied
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
428723853f88b4d5cac436f5fd62e6cc64a9e8e9)
Xiang, Haihao [Wed, 3 Jul 2013 02:31:17 +0000 (10:31 +0800)]
Insert a phantom slice for H.264 deocdong on SNB
If the first slice does't start at 0, a phantom slice is added
before the first slice.
This fixes the GPU hang issue mentioned in https://bugs.freedesktop.org/show_bug.cgi?id=63946
(not the original issue).
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Tested-by: Krzysztof Kotlenga <pocek@users.sf.net>
(cherry picked from commit
11115e3f0427d056367c1c5946585e3f7cead662)
Xiang, Haihao [Wed, 10 Jul 2013 06:16:02 +0000 (14:16 +0800)]
Check the returned pointer from malloc() before using it
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
1caf179b1425b13cacaa421c688c6df8369668c6)
Xiang, Haihao [Mon, 1 Jul 2013 04:47:28 +0000 (12:47 +0800)]
Add the dependency to the ring supported by the underlying OS for VPP filters
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
a532539cbc7048f5c01b64dfe239f1570123c959)
Xiang, Haihao [Mon, 1 Jul 2013 02:40:19 +0000 (10:40 +0800)]
Check whether VEBOX is supported by the underlying OS
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
c586c80d29d8860011d95e78d1609ff3683f3cc4)
Xiang, Haihao [Fri, 28 Jun 2013 06:03:34 +0000 (14:03 +0800)]
Won't build the shaders for Sharpening on HSW
This fixes https://bugs.freedesktop.org/show_bug.cgi?id=66258
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Gwenole Beauchesne [Thu, 27 Jun 2013 09:26:34 +0000 (11:26 +0200)]
build: fix make dist for packaging.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Xiang, Haihao [Wed, 26 Jun 2013 05:14:44 +0000 (13:14 +0800)]
Udate the micro version
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 26 Jun 2013 05:10:15 +0000 (13:10 +0800)]
Bump version for development
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 26 Jun 2013 02:18:25 +0000 (10:18 +0800)]
Intel driver 1.2.0
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 26 Jun 2013 02:16:07 +0000 (10:16 +0800)]
NEWS: updates
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 25 Jun 2013 07:41:27 +0000 (15:41 +0800)]
Update the dependency on libdrm
libdrm 2.4.45 is required to support VEBOX on HSW
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 25 Jun 2013 07:56:05 +0000 (15:56 +0800)]
Revert "Make it built against the current upstream libdrm"
The upstream libdrm now has supported VEBOX, hence remove the
definition of I915_EXEC_VEBOX
This reverts commit
6fdd5a24a5099d45a01da5a9f1337d26749898bb.
Xiang, Haihao [Fri, 21 Jun 2013 04:21:58 +0000 (12:21 +0800)]
Silence the warning
CC i965_drv_video_la-gen75_vpp_vebox.lo
gen75_vpp_vebox.c: In function ‘hsw_veb_dndi_iecp_command’:
gen75_vpp_vebox.c:697:5: warning: suggest parentheses around arithmetic in operand of ‘|’
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 21 Jun 2013 00:52:41 +0000 (08:52 +0800)]
VPP: Filter parameters are stored in system memory
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 17 Jun 2013 07:06:11 +0000 (15:06 +0800)]
Fix copy&paste error
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 14 Jun 2013 06:54:53 +0000 (14:54 +0800)]
VEBOX: output 2 frames for advanced DI
Both current frame and previous frame are outputted
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 14 Jun 2013 06:40:26 +0000 (14:40 +0800)]
VEBOX: motion adaptive DI on HSW
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 14 Jun 2013 03:40:42 +0000 (11:40 +0800)]
VEBOX: update internal surface
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 13 Jun 2013 12:31:11 +0000 (20:31 +0800)]
VEBOX: track the frame sequence
Preparation work for advanced DI
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 13 Jun 2013 12:50:58 +0000 (20:50 +0800)]
VEBOX: clean up
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 13 Jun 2013 08:39:13 +0000 (16:39 +0800)]
VEBOX: Update VEBOX_STATE for Bob DI
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 13 Jun 2013 07:55:27 +0000 (15:55 +0800)]
VEBOX: Update DNDI table on Haswell
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 13 Jun 2013 03:31:36 +0000 (11:31 +0800)]
Update the supported render target format and pixel format
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 7 Jun 2013 08:56:45 +0000 (16:56 +0800)]
Update the implementation of vaQueryVideoProcFilterCaps()
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 30 May 2013 08:41:09 +0000 (16:41 +0800)]
Update the implementation of vaQueryVideoProcFilters()
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 30 May 2013 06:52:15 +0000 (14:52 +0800)]
VAProcFilterNone isn't a actual filter
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 7 Jun 2013 01:47:22 +0000 (09:47 +0800)]
Return supported external memory types in vaQuerySurfaceAttributes()
Return the number of elements actually filled in output as well.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 6 Jun 2013 08:51:02 +0000 (16:51 +0800)]
Add support for vaQuerySurfaceAttributes()
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 6 Jun 2013 07:38:09 +0000 (15:38 +0800)]
Add support for VA_SURFACE_ATTRIB_MEM_TYPE_KERNEL_DRM and VA_SURFACE_ATTRIB_MEM_TYPE_DRM_PRIME
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Li Xiaowei [Wed, 19 Jun 2013 18:07:48 +0000 (02:07 +0800)]
VEBOX: Fix image garbage at border when pro amp
Aligned width/height are required to be registered
to surface state, instead of original width/height
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
Li Xiaowei [Wed, 19 Jun 2013 17:33:01 +0000 (01:33 +0800)]
VEBOX: Fix endingX setting for dndi/iecp command
The endingX need be aligned to 64 and subtract 1
before setting to VEBOX command.
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
Li Xiaowei [Sun, 9 Jun 2013 15:26:15 +0000 (23:26 +0800)]
VEBOX: Turn off CSC function in VEBOX pipeline
all surface format conversion process and CSC will
be done through shader, this will simplify the pipeline
data flow especially for multiple filters case.
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
Xiang, Haihao [Sun, 9 Jun 2013 07:43:08 +0000 (15:43 +0800)]
More reserved PCI IDs for Haswell
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
a9c66609b289c815b2bfc0385dc1f3bff6677125)
Xiang, Haihao [Sun, 9 Jun 2013 07:34:20 +0000 (15:34 +0800)]
Update max_wm_threads on Haswell
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
c31f6130793c68a83d1cb1116da60489d5e4a1d4)
Xiang, Haihao [Sun, 9 Jun 2013 07:29:15 +0000 (15:29 +0800)]
Fix Haswell GT3
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
3c9e778718cb4d24695a880afb45e32cdf43a434)
Xiang, Haihao [Mon, 27 May 2013 02:19:10 +0000 (10:19 +0800)]
A workaround for clearing a Y-tiled surface
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
9c698455fec340ced7dbf93cc5be004bb4a1eb22)
Xiang, Haihao [Wed, 22 May 2013 06:23:53 +0000 (14:23 +0800)]
version 1.2.0.pre1
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 22 May 2013 05:34:16 +0000 (13:34 +0800)]
VPP: Update the mapping of VPP filter to internal flag
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 22 May 2013 05:30:53 +0000 (13:30 +0800)]
remove VAProcFilterColorStandard
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 21 May 2013 08:48:54 +0000 (16:48 +0800)]
VPP/HSW: don't use VAProcFilterColorStandard
VAProcFilterColorStandard will be removed from va_vpp.h
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 20 May 2013 08:08:54 +0000 (16:08 +0800)]
Support tiled surface for IMC1/IMC3
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 20 May 2013 08:19:41 +0000 (16:19 +0800)]
Use IMC3 for JPEG decoding
To match the pre-defined VA FOURCC in va.h
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Zhao Yakui [Thu, 9 May 2013 08:53:07 +0000 (16:53 +0800)]
Add the config attribute of EncMaxRefFrames
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Thu, 9 May 2013 05:53:50 +0000 (13:53 +0800)]
PAK encoding uses the reference list parsed from slice_param instead of hacked DPB
Of course it still can work if the slice_param doesn't contain the
valid REfPicList0/1(Hacked DPB mode). This is to be compatible with
the older version of avcenc tool.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Thu, 9 May 2013 05:52:31 +0000 (13:52 +0800)]
Unify the AVC ref frame index setting on Snb/Ivy/HSW
This is to remove the duplicated code.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Thu, 9 May 2013 05:52:28 +0000 (13:52 +0800)]
VME uses reference frame parsed from slice_param instead of hacked DPB
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Xiang, Haihao [Wed, 24 Apr 2013 08:54:09 +0000 (16:54 +0800)]
Clean up gen7_vme_context_init()
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Zhao Yakui [Wed, 3 Apr 2013 01:48:58 +0000 (09:48 +0800)]
Rework the VPP CSC shader from NV12 to RGB to eliminate corruption
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Wed, 3 Apr 2013 01:48:12 +0000 (09:48 +0800)]
Fix the incorrect VPP parameter setting on Ivy/Haswell
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Wed, 3 Apr 2013 01:47:53 +0000 (09:47 +0800)]
Handle the pitch when using RGBX surface in VPP
Signed-off-by: Ung, Teng En <teng.en.ung@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Xiang, Haihao [Wed, 3 Apr 2013 00:58:13 +0000 (08:58 +0800)]
Merge branch 'master' into staging
Conflicts:
NEWS
configure.ac
src/Makefile.am
src/gen6_mfc.c
src/gen6_mfd.c
src/gen6_vme.c
src/gen6_vme.h
src/gen75_mfc.c
src/gen75_mfd.c
src/gen75_vme.c
src/gen75_vpp_vebox.c
src/gen75_vpp_vebox.h
src/gen7_mfd.c
src/i965_avc_bsd.c
src/i965_decoder.h
src/i965_decoder_utils.c
src/i965_defines.h
src/i965_drv_video.c
src/i965_drv_video.h
src/i965_encoder.c
src/i965_encoder.h
src/i965_output_dri.c
src/i965_post_processing.c
src/i965_post_processing.h
src/i965_render.c
src/i965_structs.h
src/intel_driver.c
src/object_heap.c
src/shaders/post_processing/Common/AYUV_Load_16x8.asm
src/shaders/post_processing/Common/AYUV_Load_16x8.inc
src/shaders/post_processing/Common/Init_All_Regs.asm
src/shaders/post_processing/Makefile.am
src/shaders/post_processing/gen5_6/Common/AYUV_Load_16x8.asm
src/shaders/post_processing/gen5_6/Common/AYUV_Load_16x8.inc
src/shaders/post_processing/gen5_6/Common/Init_All_Regs.asm
src/shaders/post_processing/gen5_6/Common/NV12_Load_8x4.asm
src/shaders/post_processing/gen5_6/Common/RGBX_Load_16x8.asm
src/shaders/post_processing/gen5_6/Common/RGBX_Load_16x8.inc
src/shaders/post_processing/gen5_6/Makefile.am
src/shaders/post_processing/gen5_6/nv12_avs_nv12.g4b.gen5
src/shaders/post_processing/gen5_6/nv12_avs_nv12.g6b
src/shaders/post_processing/gen5_6/nv12_dn_nv12.g4b.gen5
src/shaders/post_processing/gen5_6/nv12_dn_nv12.g6b
src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5
src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b
src/shaders/post_processing/gen5_6/nv12_load_save_nv12.g4b.gen5
src/shaders/post_processing/gen5_6/nv12_load_save_nv12.g6b
src/shaders/post_processing/gen5_6/nv12_load_save_pa.g4b.gen5
src/shaders/post_processing/gen5_6/nv12_load_save_pa.g6b
src/shaders/post_processing/gen5_6/nv12_load_save_pl3.g4b.gen5
src/shaders/post_processing/gen5_6/nv12_load_save_pl3.g6b
src/shaders/post_processing/gen5_6/pa_load_save_nv12.g4b.gen5
src/shaders/post_processing/gen5_6/pa_load_save_nv12.g6b
src/shaders/post_processing/gen5_6/pa_load_save_pl3.g4b.gen5
src/shaders/post_processing/gen5_6/pa_load_save_pl3.g6b
src/shaders/post_processing/gen5_6/pl3_load_save_nv12.g4b.gen5
src/shaders/post_processing/gen5_6/pl3_load_save_nv12.g6b
src/shaders/post_processing/gen5_6/pl3_load_save_pa.g4b.gen5
src/shaders/post_processing/gen5_6/pl3_load_save_pa.g6b
src/shaders/post_processing/gen5_6/pl3_load_save_pl3.g4b.gen5
src/shaders/post_processing/gen5_6/pl3_load_save_pl3.g6b
src/shaders/post_processing/gen7/EOT.g4a
src/shaders/post_processing/gen7/Makefile.am
src/shaders/post_processing/gen7/PA_AVS_Buf_0.g4a
src/shaders/post_processing/gen7/PA_AVS_Buf_1.g4a
src/shaders/post_processing/gen7/PA_AVS_Buf_2.g4a
src/shaders/post_processing/gen7/PA_AVS_Buf_3.g4a
src/shaders/post_processing/gen7/PL2_AVS_Buf_0.g4a
src/shaders/post_processing/gen7/PL2_AVS_Buf_1.g4a
src/shaders/post_processing/gen7/PL2_AVS_Buf_2.g4a
src/shaders/post_processing/gen7/PL2_AVS_Buf_3.g4a
src/shaders/post_processing/gen7/PL3_AVS_Buf_0.g4a
src/shaders/post_processing/gen7/PL3_AVS_Buf_1.g4a
src/shaders/post_processing/gen7/PL3_AVS_Buf_2.g4a
src/shaders/post_processing/gen7/PL3_AVS_Buf_3.g4a
src/shaders/post_processing/gen7/Save_AVS_NV12.g4a
src/shaders/post_processing/gen7/Save_AVS_PA.g4a
src/shaders/post_processing/gen7/Save_AVS_PL3.g4a
src/shaders/post_processing/gen7/Save_AVS_RGB.g4a
src/shaders/post_processing/gen7/Set_AVS_Buf_0123_BGRA.g4a
src/shaders/post_processing/gen7/Set_AVS_Buf_0123_PL2.g4a
src/shaders/post_processing/gen7/Set_AVS_Buf_0123_PL3.g4a
src/shaders/post_processing/gen7/Set_AVS_Buf_0123_VUYA.g4a
src/shaders/post_processing/gen7/Set_AVS_Buf_0123_VYUA.g4a
src/shaders/post_processing/gen7/Set_Layer_0.g4a
src/shaders/post_processing/gen7/VP_Setup.g4a
src/shaders/vme/Makefile.am
src/shaders/vme/inter_frame_haswell.asm
src/shaders/vme/inter_frame_haswell.g75b
src/shaders/vme/intra_frame_haswell.asm
src/shaders/vme/intra_frame_haswell.g75b
src/shaders/vme/vme75.inc
src/shaders/vme/vme7_mpeg2.inc
Li Xiaowei [Tue, 26 Mar 2013 01:06:18 +0000 (09:06 +0800)]
Fix the obj_image error in i965_hw_putimage
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
Xiang, Haihao [Tue, 19 Mar 2013 05:00:10 +0000 (13:00 +0800)]
Bump version for development.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 19 Mar 2013 02:19:23 +0000 (10:19 +0800)]
libva-intel-driver 1.0.20
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Armin K [Fri, 15 Mar 2013 17:22:10 +0000 (18:22 +0100)]
Automake 1.13 fixups
error: 'AM_CONFIG_HEADER': this macro is obsolete.
You should use the 'AC_CONFIG_HEADERS' macro instead.
warning: 'INCLUDES' is the old name for 'AM_CPPFLAGS' (or '*_CPPFLAGS')
Added NOCONFIGURE check to autogen.sh
Xiang, Haihao [Fri, 15 Mar 2013 07:39:35 +0000 (15:39 +0800)]
Fix the size to malloc()
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 15 Mar 2013 07:19:49 +0000 (15:19 +0800)]
Check the pointer is NULL or not
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 15 Mar 2013 07:32:01 +0000 (15:32 +0800)]
Fix potential buffer overflow for JPEG decoding
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
projects / platform / upstream / libva-intel-driver.git / log