Tom Rini [Tue, 24 May 2016 12:20:43 +0000 (08:20 -0400)]
Merge branch 'master' of git://denx.de/git/u-boot-microblaze
Tom Rini [Tue, 24 May 2016 11:22:55 +0000 (07:22 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-atmel
Michal Simek [Fri, 20 May 2016 12:59:33 +0000 (14:59 +0200)]
ARM: zynq: Simplify zynq configuration
Extending Kconfig for adding new platform is a lot of work
for nothing. Setting SYS_CONFIG_NAME directly in Kconfig and
remove all dependencies on TARGET_ZYNQ_* options including SPL.
As a side-effect it also remove custom init folder for ps7_init_gpl.*
files. Folder is chosen based on device-tree file.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 18 May 2016 12:46:28 +0000 (14:46 +0200)]
phy: marvell: Do not reset phy after negotiation
The patch
"net: phy: do not read configuration register on reset"
(sha1:
a058052c358c3ecf5f394ff37def6a45eb26768c)
was causing regression on zynq zc702 board where Marwell 88e1118
phy was resetted after negotiation was setup.
Phy reset is done pretty early in phy_connect_dev() and doens't need to
be called again in phy code.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 18 May 2016 12:37:23 +0000 (14:37 +0200)]
phy: Wire return value from phy_config()
Fix zynq_gem driver to handle error from phy_config correctly.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 17 May 2016 12:03:50 +0000 (14:03 +0200)]
image: Add boot_get_fpga() to load fpga with bootm
Add function boot_get_fpga() which find and load bitstream to
programmable logic if fpga entry is present.
Function is supported on Xilinx devices for full and partial bitstreams
in BIN and BIT format.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Remove additional blankline in image.h
Michal Simek [Wed, 18 May 2016 10:46:12 +0000 (12:46 +0200)]
net: phy: Handle phy_startup() error codes properly
Propagate error code from genphy_update_link() to phy startup().
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Michal Simek [Wed, 18 May 2016 10:48:57 +0000 (12:48 +0200)]
phy: Return correct error code when timeout happens
Return -ETIMEDOUT if timeout happens.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Michal Simek [Wed, 18 May 2016 10:37:22 +0000 (12:37 +0200)]
net: xilinx: Handle error value from phy_startup()
Handle error returned by phy_startup() properly.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Michal Simek [Tue, 17 May 2016 11:58:44 +0000 (13:58 +0200)]
mkimage: Report information about fpga
Add FIT_FPGA_PROP that user can identify an optional
entry for fpga.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Michal Simek [Tue, 17 May 2016 12:32:00 +0000 (14:32 +0200)]
fpga: Fix typo in function comment
Trivial patch.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 17 May 2016 11:33:11 +0000 (13:33 +0200)]
ARM64: zynqmp: Enable CLK framework
ZynqMP is using fixed clocks now that's why enabling it to be available
for drivers.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 20 Nov 2015 12:17:22 +0000 (13:17 +0100)]
ARM64: zynqmp: Add SPL support support
Support RAM and MMC boot mode in SPL also with SPL_FIT images.
In MMC boot mode two boot options are available:
1) Boot flow with ATF(EL3) and full U-Boot(EL2):
aarch64-linux-gnu-objcopy -O binary bl31.elf bl31.bin
mkimage -A arm64 -O linux -T kernel -C none -a 0xfffe5000 -e 0xfffe5000
-d bl31.bin atf.ub
cp spl/boot.bin <sdcard fat partition>
cp atf.ub <sdcard fat partition>
cp u-boot.bin <sdcard fat partition>
2) Boot flow with full U-Boot(EL3):
cp spl/boot.bin <sdcard>
cp u-boot*.img <sdcard>
3) emmc boot mode
dd if=/dev/zero of=sd.img bs=1024 count=1024
parted sd.img mktable msdos
parted sd.img mkpart p fat32 0% 100%
kpartx -a sd.img
mkfs.vfat /dev/mapper/loop0p1
mount /dev/mapper/loop0p1 /mnt/
cp spl/boot.bin /mnt
cp u-boot.img /mnt
cp u-boot.bin /mnt
cp atf.ub /mnt
umount /dev/mapper/loop0p1
kpartx -d sd.img
cp sd.img /tftpboot/
and program it via u-boot
tftpb 10000 sd.img
mmcinfo
mmc write 10000 0 $filesize
mmc rescan
mmc part
ls mmc 0
psu_init() function contains low level SoC setup generated for every HW
design by Xilinx design tools. xil_io.h is only supporting file to fix
all dependencies from tools. The same solution was used on Xilinx Zynq.
The patch also change CONFIG_SYS_INIT_SP_ADDR to the end of OCM which
stays at the same location all the time.
Bootrom expects starting address to be at 0xfffc0000 that's why this
address is SPL_TEXT_BASE.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 22 Feb 2016 08:57:27 +0000 (09:57 +0100)]
ARM64: zynqmp: Add missing u-boot,dm-pre-reloc to DTSI
Add missing u-boot,dm-pre-reloc to get IPs initialized.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Alexander Graf [Thu, 12 May 2016 11:44:01 +0000 (13:44 +0200)]
ARM64: zynqmp: Align gic ranges for 64k in device tree
The GIC ranges in the zynqmp device tree are only 4kb aligned. Since
commit
12e14066f we automatically deal with aliases GIC regions though,
so we can map them transparently into guests even on 64kb page size
systems.
This patch makes use of that features and sets GICC and GICV to 64kb
aligned and sized regions.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 27 Apr 2016 12:03:29 +0000 (14:03 +0200)]
tools: zynqmpimage: Add Xilinx ZynqMP boot header generation
Add support for the zynqmpimage to mkimage.
Only basic functionality is supported without encryption and register
initialization with one partition which is filled by U-Boot SPL.
For more detail information look at Xilinx ZynqMP TRM.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Michal Simek [Thu, 28 Apr 2016 07:54:16 +0000 (09:54 +0200)]
SPL: FIT: Enable SPL_FIT_LOAD in RAM based boot mode
Support loading FIT in SPL for RAM bootmode.
CONFIG_SPL_LOAD_FIT_ADRESS points to address where FIT image is stored
in memory.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Michal Simek [Tue, 10 May 2016 05:55:52 +0000 (07:55 +0200)]
ARM: zynq: Call ps7_post_config() for SPL
If ps7_post_config() is defined call it. It is enabling for example
level shifters for PL bitstreams.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 10 May 2016 07:50:35 +0000 (09:50 +0200)]
ARM64: zynqmp: Enable option to overwrite default variables
Enable overwriting variables out of main config file.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 10 May 2016 05:54:20 +0000 (07:54 +0200)]
spl: Introduce new function spl_board_prepare_for_boot
Call this function before passing control from SPL.
For fpga case it is necessary to enable for example level shifters
when bitstream is programmed.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Michal Simek [Wed, 4 May 2016 10:33:22 +0000 (12:33 +0200)]
ARM64: zynqmp: Add debug uart for zc1751-dc1
It is helpful for debugging.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 17 Mar 2016 22:02:37 +0000 (23:02 +0100)]
ARM64: zynqmp: Enable SPI_FLASH and FLASH_BAR for ep108
Add missing SPI flash options.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 29 Apr 2016 11:04:02 +0000 (13:04 +0200)]
ARM64: zynqmp: Remove CONFIG_PREBOOT
CONFIG_PREBOOT variable is breaking ./test/py framework.
Remove it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 3 May 2016 12:20:17 +0000 (14:20 +0200)]
ARM: zynq: Add support for SPL_LOAD_FIT
Enable minimal function to be able to compile SPL_LOAD_FIT.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 22 Apr 2016 06:50:45 +0000 (08:50 +0200)]
ARM64: zynqmp: Wire up debug_uart setup
It has to be enabled by debug_uart_init().
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 26 Apr 2016 14:03:42 +0000 (16:03 +0200)]
ARM64: zynqmp: Enable eMMC boot partitions commands
Enable some additional features of the eMMC boot partitions.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 22 Apr 2016 09:48:49 +0000 (11:48 +0200)]
ARM64: zynqmp: Add support for reading MAC from eeprom
Add support for on board eeprom with programmed MAC for using in u-boot
to have uniq address for every board.
Most of the time uniq MAC address is on a label on the board.
If address is not programmed use these command to program it.
On zcu102:
ZynqMP> mm.b 0
00000000: 00 ? 00
00000001: a0 ? 0a
00000002: 35 ? 35
00000003: 02 ? 02
00000004: 00 ? ef
00000005: 00 ? 67
00000006: 00 ? q
i2c dev 5
i2c write 0 54 20 6
i2c md 54 20
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 22 Apr 2016 12:28:17 +0000 (14:28 +0200)]
ARM64: zynqmp: Enable missing distro default options
Enable all options which distros requires.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 22 Apr 2016 11:04:42 +0000 (13:04 +0200)]
ARM64: zynqmp: Enable HUSH parser for all zynqmp targets
Enable HUSH for all zynqmp boards which don't have it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Masahiro Yamada [Mon, 25 Apr 2016 03:14:43 +0000 (12:14 +0900)]
ARM: dts: zynq: describe SLCR as simple-mfd rather than simple-bus
Commit
9f56917ab88a ("dm: core: make simple-bus compatible to
simple-mfd") made possible to import the following commit:
Linux commit:
bc5ba9b98435bf76d92e0954da1784695aa449f1
The SLCR (System-Level Control Registers) block is an MFD (Multi
Function Device) rather than a bus.
"simple-mfd" seems a more suitable compatible string than "simple-bus".
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 4 Mar 2016 14:56:50 +0000 (15:56 +0100)]
gpio: zynq: Add support for reading gpio pin state
Add zynq_gpio_get_function() which return status on gpio pin.
This function enables gpio status command.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Masahiro Yamada [Wed, 13 Apr 2016 21:52:26 +0000 (06:52 +0900)]
ARM: zynq: load u-boot.img whether CONFIG_OF_SEPARATE is defined or not
Since commit
ad1ecd2063da ("fdt: Build a U-Boot binary without device
tree"), u-boot-dtb.img is identical to u-boot.img, so SPL can always
load u-boot.img whether CONFIG_OF_SEPARATE is defined or not.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Marek Vasut [Fri, 22 Apr 2016 19:56:21 +0000 (21:56 +0200)]
ARM: sama5d2: Implement boot device autodetection
Implement support for saving ARM register R4 early during boot using
save_boot_params . Implement support for decoding the stored register
R4 value in spl_boot_device() to obtain boot device from which the
SoC booted. This way, the SPL will always load U-Boot from the same
device from which the SPL itself booted instead of using hard-coded
boot device.
This functionality is useful for example when booting sama5d2-xplained
from SD card, where by default the SPL would try loading the U-Boot
from eMMC and fail. This is because eMMC is on SDHCI0 (BOOT_DEVICE_MMC1),
while SD slot is on SDHCI1 (BOOT_DEVICE_MMC2) and the SPL was hard-wired
to always boot from BOOT_DEVICE_MMC1.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Marek Vasut [Mon, 18 Apr 2016 16:30:41 +0000 (18:30 +0200)]
ARM: atmel: Enable FIT image support for SAMA5Dx
Enable the fitImage support for the entire SAMA5Dx lineup of CPUs.
The fitImage is superior image format to uImage and it is useful
to have it available.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
[rebase on current ToT]
Signed-off-by: Andreas Bießmann <andreas@biessmann.org>
Wenyou Yang [Mon, 11 Apr 2016 08:41:33 +0000 (16:41 +0800)]
board: sama5d2_xplained: change SDHCI GCK's clock source to UPLL
Change the clock source of the SDHCI's generated clock from PLLA to
UPLL clock to align to Linux driver.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Wenyou Yang [Mon, 11 Apr 2016 08:41:32 +0000 (16:41 +0800)]
ARM: at91: clock: complete the GCK's clock sources
Add the UPLL clock and master clock as a clock source for getting
the generated clock frequency to complete its clock sources support.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Wenyou Yang [Mon, 11 Apr 2016 08:41:31 +0000 (16:41 +0800)]
ARM: at91: clock: fix the GCK's clock source
Before enabling a generated clock whose source is from the UPLL
clock, check and enable the UPLL clock.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Wenyou Yang [Mon, 11 Apr 2016 06:07:17 +0000 (14:07 +0800)]
board: atmel: sama5d2_xplained: fix the missing pin config of SDMMC0
Fix the missing pin config of the SDMMC0 interface.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Wenyou Yang [Fri, 26 Feb 2016 09:20:26 +0000 (17:20 +0800)]
board: atmel: add SAMA5D2 PTC Engineering board
The board supports following features:
- Boot media support: NAND Flash/SPI Flash
- Support ethernet
- Support USB mass storage
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Wenyou Yang [Fri, 26 Feb 2016 09:20:25 +0000 (17:20 +0800)]
ARM: at91: sama5d2: add macro & field definitions
They will be used on SAMA5D2 PTC board.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Tom Rini [Mon, 23 May 2016 22:32:47 +0000 (18:32 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-x86
Tom Rini [Sat, 21 May 2016 00:43:27 +0000 (20:43 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-mips
Masahiro Yamada [Fri, 20 May 2016 03:13:10 +0000 (12:13 +0900)]
ARM: fix ifdef in ARMv8 lowlevel_init() again
Commit
116611937faa ("ARM: fix ifdefs in ARMv8 lowlevel_init()")
accidentally inverted the logic of CONFIG_ARMV8_MULTIENTRY.
Fixes:
116611937faa ("ARM: fix ifdefs in ARMv8 lowlevel_init()")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tom Rini [Mon, 23 May 2016 15:51:13 +0000 (11:51 -0400)]
SPL: fat: Fix spl_parse_image_header() return value handling
The spl_parse_image_header() can return 0 and it is not an error.
Only treat non-zero return value as an error.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Peng Fan <van.freenix@gmail.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Martin Hejnfelt [Thu, 19 May 2016 07:11:58 +0000 (09:11 +0200)]
omap3: Fix SPI registers on am33xx and am43xx
When the base registers are read from device tree the base is not
0x48030100 as the driver expects, but 0x48030000, resulting in
non functioning SPI. To deal with this, use same idea as how this
is done in the linux kernel (drivers/spi/spi-omap2-mcspi.c) and
add a structure with a field that is used to shift the registers
on these systems.
v2: Fixed commit subject line to correct cpu
Signed-off-by: Martin Hejnfelt <mh@newtec.dk>
Tom Rini [Fri, 13 May 2016 14:54:04 +0000 (10:54 -0400)]
kbuild: fixdep: Check fstat(2) return value
Coverity has recently added a check that will find when we don't check
the return code from fstat(2). Copy/paste the checking logic that
print_deps() has with an appropriate re-wording of the perror() message.
[ Linux commit :
46fe94ad18aa7ce6b3dad8c035fb538942020f2b ]
Signed-off-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Michal Marek <mmarek@suse.com>
Michal Simek [Wed, 4 May 2016 13:14:11 +0000 (15:14 +0200)]
spl: Setup default value for OF_LIST
OF_LIST can't remain empty that's why setup it up to default DTB.
If it is empty u-boot.img is created without FDT partition:
For example:
./tools/mkimage -f auto -A arm -T firmware -C none -O u-boot -a
0x8000000 -e 0 -n "U-Boot 2016.05-rc3 ..." -E -b -d u-boot-nodtb.bin u-boot.img
Can't set 'timestamp' property for '' node (FDT_ERR_NOSPACE)
FIT description: Firmware image with one or more FDT blobs
Created: Wed May 4 15:02:52 2016
Image 0 (firmware@1)
Description: U-Boot 2016.05-rc3-00080-gff2e12ae22a8-dirty for zynqmp
board
Created: Wed May 4 15:02:52 2016
Type: Firmware
Compression: uncompressed
Data Size: unavailable
Architecture: ARM
Load Address: 0x08000000
Default Configuration: 'conf@1'
Configuration 0 (conf@1)
Description: unavailable
Kernel: unavailable
And then image like this doesn't contain description and link to FDT and
can't boot.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Michal Simek [Wed, 4 May 2016 13:08:00 +0000 (15:08 +0200)]
spl: fit: Print error message when FDT is not present
When FDT is not present in the image user doesn't get any error what's
wrong. Print error message if LIBCOMMON_SUPPORT is enabled.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Seris-cc: uboot
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 1 May 2016 19:55:38 +0000 (13:55 -0600)]
mkimage: Add a quiet mode
Some build systems want to be quiet unless there is a problem. At present
mkimage displays quite a bit of information when generating a FIT file. Add
a '-q' flag to silence this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Simon Glass [Sun, 1 May 2016 19:55:37 +0000 (13:55 -0600)]
image-fit: Don't display an error in fit_set_timestamp()
This function returns an error code and its caller may be able to fix the
error. For example fit_handle_file() expands the device tree to fit if there
is a lack of space.
In this case the caller does not want an error displayed. It is confusing,
since it suggests that something is wrong, when it fact everything is fine.
Drop the error.
Signed-off-by: Simon Glass <sjg@chromium.org>
Stephen Warren [Mon, 25 Apr 2016 21:55:42 +0000 (15:55 -0600)]
malloc: improve memalign fragmentation fix
Commit
4f144a416469 "malloc: work around some memalign fragmentation
issues" enhanced memalign() so that it can succeed in more cases where
heap fragmentation is present. However, it did not solve as many cases
as it could. This patch enhances the code to cover more cases.
The alignment code works by allocating more space than the user requests,
then adjusting the returned pointer to achieve alignment. In general, one
must allocate "alignment" bytes more than the user requested in order to
guarantee that alignment is possible. This is what the original code does.
The previous enhancement attempted a second allocation if the padded
allocation failed, and succeeded if that allocation just happened to be
aligned; a fluke that happened often in practice. There are still cases
where this could fail, yet where it is still possible to honor the user's
allocation request. In particular, if the heap contains a free region that
is large enough for the user's request, and for leading padding to ensure
alignment, but has no or little space for any trailing padding. In this
case, we can make a third(!) allocation attempt after calculating exactly
the size of the leading padding required to achieve alignment, which is
the minimal over-allocation needed for the overall memalign() operation to
succeed if the third and second allocations end up at the same location.
This patch isn't checkpatch-clean, since it conforms to the existing
coding style in dlmalloc.c, which is different to the rest of U-Boot.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Bin Meng [Sun, 22 May 2016 08:45:39 +0000 (01:45 -0700)]
x86: galileo: Override SMBIOS product name
Override the default product name U-Boot reports in the SMBIOS
table, to be compatible with the Intel provided UEFI BIOS, as
Linux kernel drivers (drivers/mfd/intel_quark_i2c_gpio.c and
drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c) make use of
it to do different board level configuration.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sun, 22 May 2016 08:45:38 +0000 (01:45 -0700)]
x86: Switch to use SMBIOS Kconfig options when writing SMBIOS tables
Make use of the newly added Kconfig options of board manufacturer
and product name to write SMBIOS tables.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sun, 22 May 2016 08:45:37 +0000 (01:45 -0700)]
x86: kconfig: Add two options for SMBIOS manufacturer and product name
This introduces two Kconfig options to be used by SMBIOS tables:
board manufacturer and product name.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sun, 22 May 2016 08:45:36 +0000 (01:45 -0700)]
x86: galileo: Enable MP table generation
Now that we have added CPU uclass driver and fixed the IOAPIC ID
conflict, enable MP table generation so that IOAPIC can be used
by the Linux kernel.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sun, 22 May 2016 08:45:35 +0000 (01:45 -0700)]
x86: broadwell: Correct I/O APIC ID
Currently ID 2 is assgined to broadwell I/O APIC, however per
chromebook_samus.dts 2 is the core#2 LAPIC ID. Now we change
I/O APIC ID to 4 to avoid conflict.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sun, 22 May 2016 08:45:34 +0000 (01:45 -0700)]
x86: quark: Assign a unique I/O APIC ID
After power-on, both LAPIC and I/O APIC appear with the same APIC ID
zero, which creates an ID conflict. When generating MP table, U-Boot
reports zero as the LAPIC ID in the processor entry, and zero as the
I/O APIC ID in the I/O APIC as well as the I/O interrupt assignment
entries. Such MP table confuses Linux kernel and finally a kernel
panic is seen during boot:
BUG: unable to handle kernel paging request at
ffff9000
IP: [<
c101d462>] native_io_apic_write+0x22/0x30
*pdpt =
00000000014fb001 *pde =
00000000014ff067 *pte =
0000000000000000
Oops: 0002 [#1]
Modules linked in:
Pid: 1, comm: swapper Tainted: G W 3.8.7 #3 intel galileo/galileo
EIP: 0060:[<
c101d462>] EFLAGS:
00010086 CPU: 0
EIP is at native_io_apic_write+0x22/0x30
...
Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000009
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sun, 22 May 2016 08:45:33 +0000 (01:45 -0700)]
x86: Call lapic_setup() in interrupt_init()
Let's configure LAPIC in a common place - interrupt_init().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sun, 22 May 2016 08:45:32 +0000 (01:45 -0700)]
x86: Remove SMP limitation in lapic_setup()
At present LAPIC is enabled and configured as virtual wire mode
in lapic_setup() only when CONFIG_SMP is on. This limitation is
however not necessary as for uniprocessor this is still needed.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sun, 22 May 2016 08:45:31 +0000 (01:45 -0700)]
x86: Don't touch IA32_APIC_BASE MSR on Intel Quark
Intel Quark processor core provides an integrated Local APIC but
does not support the IA32_APIC_BASE MSR. As a result, the Local
APIC is always globally enabled and the Local APIC base address
is fixed at 0xfee00000. Attempting to access the IA32_APIC_BASE
MSR causes a general protection fault.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sun, 22 May 2016 08:45:30 +0000 (01:45 -0700)]
x86: galileo: Enable CPU driver
Add a cpu node in the device tree and enable CPU driver.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 23 May 2016 07:25:20 +0000 (15:25 +0800)]
x86: Use latest microcode for all BayTrail boards
Update board device tree to include latest microcode, and remove
the old no longer needed microcode.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Bin Meng [Sun, 22 May 2016 08:45:28 +0000 (01:45 -0700)]
x86: baytrail: Update to latest microcode
Update BayTrail microcde to rev 325 (for CPUID 30673), rev 907
(for CPUID 30679).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sun, 22 May 2016 08:45:27 +0000 (01:45 -0700)]
x86: Add some notes for MRC cache with Intel FSP
MRC cache relies on Intel FSP to produce a special GUID that
contains the MRC cache data. Add such information in the
CONFIG_ENABLE_MRC_CACHE help entry.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sun, 22 May 2016 08:45:26 +0000 (01:45 -0700)]
x86: crownbay: Disable boot stage support
It is observed that when enabling boot stage support, occasionally
the board reboots during boot over and over again, and eventually
boots to shell. This was seen on my board, but not on Jian's board.
Debugging shows that the TSC timer calibration against PIT fails
as boot stage APIs utilize timer in a very early stage and at that
time TSC/PIT may not be stable enough for the calibration to pass.
Disable it for now.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Cc: Jian Luo <Jian.Luo4@boschrexroth.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sun, 22 May 2016 08:45:25 +0000 (01:45 -0700)]
acpi: Clean IASL generated intermediate files
For boards that support ACPI, there are dsdt.aml, dsdt.asl.tmp and
dsdt.c in the board directory after a successful build. These are
intermediate files generated by IASL, and should be removed during
a 'make clean'.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 11 May 2016 14:45:12 +0000 (07:45 -0700)]
x86: doc: Add porting hints for ACPI with Windows
Windows might cache system information and only detect ACPI changes
if you modify the ACPI table versions.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 11 May 2016 14:45:11 +0000 (07:45 -0700)]
x86: baytrail: Add GPIO ASL description
Since BayTrail, Intel starts to use new GPIO IPs in their chipset.
This adds the GPIO ASL, so that OS can load corresponding drivers
for it. On Linux, this is BayTrail pinctrl driver.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 11 May 2016 14:45:10 +0000 (07:45 -0700)]
x86: baytrail: Add internal UART ASL description
BayTrail integrates an internal ns15550 compatible UART (PNP0501).
Its IRQ is hardwired to IRQ3 in old revision chipset, but in newer
revision one IRQ4 is being used for ISA compatibility. Handle this
correctly in the ASL file.
Linux does not need this ASL, but Windows need this to correctly
discover a COM port existing in the system so that Windows can
show it in the 'Device Manager' window, and expose this COM port
to any terminal emulation application.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 11 May 2016 14:45:09 +0000 (07:45 -0700)]
acpi: Quieten IASL output when 'make -s' is used
IASL compiler does not provide a command line option to turn off
its non-warning message. To quieten the output when 'make -s',
redirect its output to /dev/null.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 11 May 2016 14:45:08 +0000 (07:45 -0700)]
x86: doc: Mention Ubuntu/Windows installation and boot support
As of now, U-Boot can support installing and booting Ubuntu/Windows
with the help of SeaBIOS. Update the documentation.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 11 May 2016 14:45:07 +0000 (07:45 -0700)]
x86: baytrail: Enable SeaBIOS on all boards
SeaBIOS can be loaded by U-Boot to aid the installation of Ubuntu
and Windows to a SATA drive and boot from there. Enable it on all
BayTrail boards.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 11 May 2016 14:45:06 +0000 (07:45 -0700)]
x86: doc: Update information about IGD with SeaBIOS
Document how to make SeaBIOS load and run the VGA ROM of Intel
IGD device when loaded by U-Boot.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 11 May 2016 14:45:05 +0000 (07:45 -0700)]
x86: acpi: Remove header length check when writing tables
Before moving 'current' pointer during ACPI table writing, we always
check the table length to see if it is larger than the table header.
Since our purpose is to generate valid tables, the check logic is
always true, which can be avoided.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 11 May 2016 14:45:04 +0000 (07:45 -0700)]
x86: acpi: Remove the unnecessary checksum calculation of DSDT
The generated AmlCode[] from IASL already has the calculated DSDT
table checksum in place. No need for us to calculate it again.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 11 May 2016 14:45:03 +0000 (07:45 -0700)]
x86: acpi: Switch to ACPI mode by ourselves instead of requested by OSPM
Per ACPI spec, during ACPI OS initialization, OSPM can determine
that the ACPI hardware registers are owned by SMI (by way of the
SCI_EN bit in the PM1_CNT register), in which case the ACPI OS
issues the ACPI_ENABLE command to the SMI_CMD port. The SCI_EN bit
effectively tracks the ownership of the ACPI hardware registers.
However since U-Boot does not support SMI, we report all 3 fields
in FADT (SMI_CMD, ACPI_ENABLE, ACPI_DISABLE) as zero, by following
the spec who says: these fields are reserved and must be zero on
system that does not support System Management mode.
U-Boot seems to behave in a correct way that the ACPI spec allows,
at least Linux does not complain, but apparently Windows does not
think so. During Windows bring up debugging, it is observed that
even these 3 fields are zero, Windows are still trying to issue SMI
with hardcoded SMI port address and commands, and expecting SCI_EN
to be changed by the firmware. Eventually Windows gives us a BSOD
(Blue Screen of Death) saying ACPI_BIOS_ERROR and refuses to start.
To fix this, turn on the SCI_EN bit by ourselves. With this patch,
now U-Boot can install and boot Windows 8.1/10 successfully with
the help of SeaBIOS using legacy interface (non-UEFI mode).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 11 May 2016 14:45:02 +0000 (07:45 -0700)]
x86: Use high_table_malloc() for tables passing to SeaBIOS
Now that we already reserved high memory for configuration tables,
call high_table_malloc() to allocate tables from the region.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 11 May 2016 14:45:01 +0000 (07:45 -0700)]
x86: Reserve configuration tables in high memory
When SeaBIOS is on, reserve configuration tables in reserve_arch().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 11 May 2016 14:45:00 +0000 (07:45 -0700)]
x86: Unify reserve_arch() for all x86 boards
Instead of asking each platform to provide reserve_arch(),
supply it in arch/x86/cpu/cpu.c in a unified way.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 11 May 2016 14:44:59 +0000 (07:44 -0700)]
x86: Prepare configuration tables in dedicated high memory region
Currently when CONFIG_SEABIOS is on, U-Boot allocates configuration
tables via normal malloc(). To simplify, use a dedicated memory
region which is reserved on the stack before relocation for this
purpose. Add functions for reserve and malloc.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 11 May 2016 14:44:58 +0000 (07:44 -0700)]
x86: Compile coreboot_table.c only for SeaBIOS
coreboot_table.c only needs to be built when SeaBIOS is used.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 11 May 2016 14:44:57 +0000 (07:44 -0700)]
x86: Fix up PIRQ routing table checksum earlier
PIRQ routing table checksum is fixed up in copy_pirq_routing_table(),
which is fine if we only write the configuration table once. But with
the SeaBIOS case, when we write the table for the second time, the
checksum will be fixed up to zero per the checksum algorithm, which
is caused by the checksum field not being zero before fix up, since
the checksum has already been calculated in the first run.
To fix this, move the checksum fixup to create_pirq_routing_table(),
so that copy_pirq_routing_table() only does what its function name
suggests: copy the table to somewhere else.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 11 May 2016 14:44:56 +0000 (07:44 -0700)]
x86: Call board_final_cleanup() in last_stage_init()
At present board_final_cleanup() is called before booting a Linux
kernel. This actually needs to be done before booting anything,
like SeaBIOS, VxWorks or Windows.
Move the call to last_stage_init() instead.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 11 May 2016 14:44:55 +0000 (07:44 -0700)]
x86: minnowmax: Adjust U-Boot environment address in SPI flash
Currently U-Boot environment address is at offset 0x7fe00 of a 8MB
SPI flash. When creating a partial u-boot.rom image without flash
descriptor and ME firmware, U-Boot actually occupies the last 1MB
of the flash, and reprograming U-Boot causes previous environment
settings get lost which is not convenient during testing.
Adjust the environment address to 0x6ef000 instead (before the MRC
cache data region in the flash).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Miao Yan [Mon, 23 May 2016 02:37:22 +0000 (19:37 -0700)]
config: sandbox: enable qfw and cmd_qfw for testing
This patch enables qfw and cmd_qfw on sandbox for build coverage test
Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Miao Yan [Mon, 23 May 2016 02:37:21 +0000 (19:37 -0700)]
x86: qemu: rename qemu/acpi_table.c
Rename qemu/acpi_table.c to qemu/e820.c, because ACPI stuff is moved
to qfw core, this file only contains code for installing e820 table.
Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Miao Yan [Mon, 23 May 2016 02:37:20 +0000 (19:37 -0700)]
cmd: qfw: bring ACPI generation code into qfw core
Loading ACPI table from QEMU's fw_cfg interface is not x86 specific
(ARM64 may also make use of it). So move the code to common place.
Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Miao Yan [Mon, 23 May 2016 02:37:19 +0000 (19:37 -0700)]
cmd: qfw: do not depend on x86
The qfw command interface used to depend on X86, this patch removes
this restriction so it can be built for sandbox for testing. For normal
usage, it can only be used with CONFIG_QEMU.
Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Miao Yan [Mon, 23 May 2016 02:37:18 +0000 (19:37 -0700)]
cmd: qfw: do not require default macros when building qfw command
The qfw command interface makes use of CONFIG_LOADADDR and
CONFIG_RAMDISKADDR to setup kernel. But not all boards have these macros,
which causes build problem on those platforms.
This patch fixes this issue.
Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Miao Yan [Mon, 23 May 2016 02:37:17 +0000 (19:37 -0700)]
cmd: qfw: rename qemu_fw_cfg.[c|h] to qfw.[c|h]
Make file names consistent with CONFIG_QFW and CONFIG_CMD_QFW
Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Miao Yan [Mon, 23 May 2016 02:37:16 +0000 (19:37 -0700)]
x86: qemu: add comment about qfw register endianness
This patch adds some comments about qfw register endianness for clarity.
Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Miao Yan [Mon, 23 May 2016 02:37:15 +0000 (19:37 -0700)]
x86: qemu: move x86 specific operations out of qfw core
The original implementation of qfw includes several x86 specific
operations, like directly calling outb/inb and using some inline
assembly code which prevents it being ported to other architectures.
This patch adds callback functions and moves those to arch/x86/
Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Miao Yan [Mon, 23 May 2016 02:37:14 +0000 (19:37 -0700)]
x86: qemu: split qfw command interface and qfw core
This patch splits qfw command interface and qfw core function into two
files, and introduces a new Kconfig option (CONFIG_QFW) for qfw core.
Now when qfw command interface is enabled, it will automatically select
qfw core. This patch also makes the ACPI table generation select
CONFIG_QFW.
Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Miao Yan [Mon, 23 May 2016 02:37:13 +0000 (19:37 -0700)]
cmd: qfw: make fwcfg_present and fwcfg_dma_present public
This patch is part of the qfw refactor work. This patch makes
qemu_fwcfg_present() and qemu_fwcfg_dma_present() public functions.
Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Miao Yan [Mon, 23 May 2016 02:37:12 +0000 (19:37 -0700)]
cmd: qfw: remove qemu_fwcfg_free_files()
This patch is part of the qfw refactor work.
The qemu_fwcfg_free_files() function is only used in error handling in
ACPI table generation, let's not make this a core function and move it
to the right place.
Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Miao Yan [Mon, 23 May 2016 02:37:11 +0000 (19:37 -0700)]
cmd: qfw: add API to iterate firmware list
This patch is part of the refactor work of qfw. It adds 3 APIs to qfw
core to iterate firmware list.
Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Miao Yan [Mon, 23 May 2016 02:37:10 +0000 (19:37 -0700)]
x86: qemu: fix ACPI Kconfig options
CONFIG_GENENRATE_ACPI_TABLE controls the generation of ACPI table which
uses U-Boot's built-in methods and CONFIG_QEMU_ACPI_TABLE controls whether
to load ACPI table from QEMU's fw_cfg interface.
But with commit "
697ec431469ce0a4c2fc2c02d8685d907491af84 x86: qemu: Drop
our own ACPI implementation", there is only one way to support ACPI table
for QEMU targets which is the fw_cfg interface. Having two Kconfig options
for this purpose is not necessary any more, so this patch consolidates
the two.
Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tom Rini [Fri, 6 May 2016 14:40:22 +0000 (10:40 -0400)]
x86: qemu: Move qfw command over to cmd and add Kconfig entry
- Move the command portion of arch/x86/cpu/qemu/fw_cfg.c into
cmd/qemu_fw_cfg.c
- Move arch/x86/include/asm/fw_cfg.h to include/qemu_fw_cfg.h
- Rename ACPI table portion to arch/x86/cpu/qemu/acpi_table.c
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Sat, 7 May 2016 14:46:37 +0000 (07:46 -0700)]
x86: doc: Document ACPI support
Remove ACPI from the TODO list and add a new section to document
current ACPI support in U-Boot.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sat, 7 May 2016 14:46:36 +0000 (07:46 -0700)]
x86: doc: Minor update for accuracy
This updates the doc for the following places:
- Mention CRB for Bayley Bay
- Mention Congatec QEVAL 2.0 & conga-QA3/E3845
- Limit part of the QEMU paragraphs to 80 cols
- Correct some typos (drive, it's, Ubuntu)
- Add description for "console=ttyS0,115200"
- Remove CONFIG_BOOTDELAY description which is already
in x86-common.h
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>