platform/kernel/linux-rpi.git
3 years agodrm/amdkfd: rm BO resv on validation to avoid deadlock
Alex Sierra [Thu, 7 Oct 2021 17:04:09 +0000 (12:04 -0500)]
drm/amdkfd: rm BO resv on validation to avoid deadlock

This fix the deadlock with the BO reservations during SVM_BO evictions
while allocations in VRAM are concurrently performed. More specific,
while the ttm waits for the fence to be signaled (ttm_bo_wait), it
already has the BO reserved. In parallel, the restore worker might be
running, prefetching memory to VRAM. This also requires to reserve the
BO, but blocks the mmap semaphore first. The deadlock happens when the
SVM_BO eviction worker kicks in and waits for the mmap semaphore held
in restore worker. Preventing signal the fence back, causing the
deadlock until the ttm times out.

We don't need to hold the BO reservation anymore during validation
and mapping. Now the physical addresses are taken from hmm_range_fault.
We also take migrate_mutex to prevent range migration while
validate_and_map update GPU page table.

Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Philip Yang <philip.yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Fix Werror when building
Wayne Lin [Fri, 8 Oct 2021 07:08:37 +0000 (15:08 +0800)]
drm/amd/display: Fix Werror when building

[Why & How]
Got Werror when building with Clang-13:

drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dpia.c:195:2:
error: variable 'ts' is used uninitialized whenever switch default is
taken [-Werror,-Wsometimes-uninitialized]

        default:

        ^~~~~~~

drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dpia.c:200:9:
note: uninitialized use occurs here

        return ts;

               ^~

drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dpia.c:180:2:
note: variable 'ts' is declared here

        enum dpia_set_config_ts ts;

        ^

1 error generated.

Fix it.

Reported-by: Mike Lothian <mike@fireburn.co.uk>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: add missing case for HDP for renoir
Alex Deucher [Fri, 1 Oct 2021 17:20:34 +0000 (13:20 -0400)]
drm/amdgpu: add missing case for HDP for renoir

Missing 4.1.2.

Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Remove redundant initialization of variable result
Colin Ian King [Thu, 7 Oct 2021 12:06:37 +0000 (13:06 +0100)]
drm/amd/display: Remove redundant initialization of variable result

The variable result is being initialized with a value that is never
read, it is being updated immediately afterwards in both branches
of an if statement. The assignment is redundant and can be removed.

Addresses-Coverity: ("Unused value")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/discovery: add missing case for SMU 11.0.5
Alex Deucher [Thu, 7 Oct 2021 14:02:13 +0000 (10:02 -0400)]
drm/amdgpu/discovery: add missing case for SMU 11.0.5

Was missed when converting the driver over to IP based
initialization.

Tested-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: unify BO evicting method in amdgpu_ttm
Nirmoy Das [Wed, 6 Oct 2021 15:55:00 +0000 (17:55 +0200)]
drm/amdgpu: unify BO evicting method in amdgpu_ttm

Unify BO evicting functionality for possible memory
types in amdgpu_ttm.c.

Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Add 120Hz support for freesync video mode
Solomon Chiu [Tue, 5 Oct 2021 12:52:42 +0000 (20:52 +0800)]
drm/amd/display: Add 120Hz support for freesync video mode

[Why]
For those video format with 60 fps, the user space player could
ask for 120Hz for playback.

[How]
Add 120 in the table of common rates.

Signed-off-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: Register MCE notifier for Aldebaran RAS
Mukul Joshi [Wed, 22 Sep 2021 18:49:43 +0000 (14:49 -0400)]
drm/amdgpu: Register MCE notifier for Aldebaran RAS

On Aldebaran, GPU driver will handle bad page retirement
for GPU memory even though UMC is host managed. As a result,
register a bad page retirement handler on the mce notifier
chain to retire bad pages on Aldebaran.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agox86/MCE/AMD: Export smca_get_bank_type symbol
Mukul Joshi [Sun, 28 Mar 2021 02:54:04 +0000 (22:54 -0400)]
x86/MCE/AMD: Export smca_get_bank_type symbol

Export smca_get_bank_type for use in the AMD GPU
driver to determine MCA bank while handling correctable
and uncorrectable errors in GPU UMC.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Acked-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: return early if debugfs is not initialized
Nirmoy Das [Wed, 6 Oct 2021 09:06:33 +0000 (11:06 +0200)]
drm/amdgpu: return early if debugfs is not initialized

Check first if debugfs is initialized before creating
amdgpu debugfs files.

References: https://gitlab.freedesktop.org/drm/amd/-/issues/1686
Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: USB4 bring up set correct address
Jude Shih [Wed, 29 Sep 2021 03:16:51 +0000 (11:16 +0800)]
drm/amd/display: USB4 bring up set correct address

[Why]
YELLOW_CARP_B0 address was not correct

[How]
Set YELLOW_CARP_B0 to 0x1A.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Wayne Lin <Wayne.Lin@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Jude Shih <shenshih@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Fix USB4 Aux via DMUB terminate unexpectedly
Jude Shih [Wed, 29 Sep 2021 03:13:56 +0000 (11:13 +0800)]
drm/amd/display: Fix USB4 Aux via DMUB terminate unexpectedly

[Why]
Condition variable sometimes terminated unexpectedly

[How]
Use wait_for_completion_timeout to avoid unexpected termination of CV

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Wayne Lin <Wayne.Lin@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Jude Shih <shenshih@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Deadlock/HPD Status/Crash Bug Fix
Jude Shih [Mon, 13 Sep 2021 06:41:34 +0000 (14:41 +0800)]
drm/amd/display: Deadlock/HPD Status/Crash Bug Fix

[why]
1. HPD callback function has deadlock problem
2. HPD status is not assigned
3. There is crash due to null pointer
4. link_enc is NULL in DPIA case

[How]
1. Fix deadlock problem by moving it out of the
   drm_modeset_lock
2. Assign HPD status from the notify of outbox
   from dmub FW
3. Fix the crash by checking if pin or enc exists
4. Use link_enc_cfg_get_link_enc_used_by_link to
   dynamically assign

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Wayne Lin <Wayne.Lin@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Jude Shih <shenshih@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Fix for access for ddc pin and aux engine.
Meenakshikumar Somasundaram [Fri, 13 Aug 2021 17:09:25 +0000 (13:09 -0400)]
drm/amd/display: Fix for access for ddc pin and aux engine.

[Why & How]
1. Remove unnecessary dummy interrupt source for USB4 HPD & HPD RX
2. Adjust parameter for DPCD writing of link training process of DPIA link
3. Adjust specific AUX defer delay for DPIA link

Reviewed-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
Acked-by: Wayne Lin <Wayne.Lin@amd.com>
Acked-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Add debug flags for USB4 DP link training.
Jimmy Kizito [Thu, 26 Aug 2021 01:26:33 +0000 (21:26 -0400)]
drm/amd/display: Add debug flags for USB4 DP link training.

[Why & How]
Additional debug flags that can be useful for testing USB4 DP
link training.

Add flags:
- 0x2 : Forces USB4 DP link to non-LTTPR mode
- 0x4 : Extends status read intervals to about 60s.

Reviewed-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Wayne Lin <Wayne.Lin@amd.com>
Acked-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Fix DIG_HPD_SELECT for USB4 display endpoints.
Jimmy Kizito [Mon, 23 Aug 2021 21:23:24 +0000 (17:23 -0400)]
drm/amd/display: Fix DIG_HPD_SELECT for USB4 display endpoints.

[Why]
DIB_BE_CNTL<i>.DIG_HPD_SELECT selects the HPD block being used
by the display endpoint assigned to DIG<i>. In the case of USB4
display endpoints, no physical HPD block is assigned.

[How]
Setting DIB_BE_CNTL<i>.DIG_HPD_SELECT to 5 indicates that no HPD
is assigned to a display endpoint. Firmware decrements the
HPD_SELECT value by 1 before writing it to the register.

Reviewed-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Acked-by: Wayne Lin <Wayne.Lin@amd.com>
Acked-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Support for SET_CONFIG processing with DMUB
Jude Shih [Wed, 11 Aug 2021 06:41:34 +0000 (14:41 +0800)]
drm/amd/display: Support for SET_CONFIG processing with DMUB

[Why]
To process SET_CONFIG transactions with DMUB using inbox1 and
outbox1 mail boxes.

[How]
1) DMUB posts SET_CONFIG reply as an Outbox1 message of type
   DMUB_OUT_CMD__SET_CONFIG_REPLY.
2) The dmub async to sync mechanism for AUX is modified to accommodate
   SET_CONFIG commands for both command issue and reply code paths.

Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Wayne Lin <Wayne.Lin@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Jude Shih <shenshih@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Add dpia debug options
Meenakshikumar Somasundaram [Wed, 23 Jun 2021 21:33:19 +0000 (17:33 -0400)]
drm/amd/display: Add dpia debug options

[Why & How]
To add support for dpia debug options.

Reviewed-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
Acked-by: Wayne Lin <Wayne.Lin@amd.com>
Acked-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Read USB4 DP tunneling data from DPCD.
Jimmy Kizito [Fri, 14 May 2021 23:56:19 +0000 (19:56 -0400)]
drm/amd/display: Read USB4 DP tunneling data from DPCD.

[Why]
We requires information from DPCD in order to identify USB4 DP
tunneling targets.

[How]
Add USB4 DP tunneling fields to DPCD struct and populate these fields
during sink detection.

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Wayne Lin <Wayne.Lin@amd.com>
Acked-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Support for SET_CONFIG processing with DMUB
Meenakshikumar Somasundaram [Fri, 30 Apr 2021 23:02:33 +0000 (19:02 -0400)]
drm/amd/display: Support for SET_CONFIG processing with DMUB

[Why]
To process SET_CONFIG transactions with DMUB using inbox1 and
outbox1 mail boxes.

[How]
1) Added inbox1 DPIA command subtype DMUB_CMD__DPIA_SET_CONFIG_ACCESS to
   issue SET_CONFIG command to DMUB in dc_process_dmub_set_config_async().
   DMUB processes the command with DPIA sends reply back immediately or
   in an outbox1 message triggering an outbox1 interrupt to driver.
2) DMUB posts SET_CONFIG reply as an Outbox1 message of type
   DMUB_OUT_CMD__SET_CONFIG_REPLY.
3) The dmub async to sync mechanism for AUX is modified to accommodate
   SET_CONFIG commands for both command issue and reply code paths.

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Wayne Lin <Wayne.Lin@amd.com>
Acked-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Implement end of training for hop in DPIA display path
Jimmy Kizito [Wed, 21 Apr 2021 14:34:34 +0000 (10:34 -0400)]
drm/amd/display: Implement end of training for hop in DPIA display path

[Why & How]
Clear training pattern sequence for hop in display path once clock
recovery and equalization phases of DP tunnel link training completed.

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Wayne Lin <Wayne.Lin@amd.com>
Acked-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Implement DPIA equalisation phase
Jimmy Kizito [Mon, 19 Apr 2021 19:12:01 +0000 (15:12 -0400)]
drm/amd/display: Implement DPIA equalisation phase

[Why]
Equalisation is the mandatory second phase of DisplayPort link training
over a USB4 DP tunnel.

[How]
Implement equalisation phase for DP tunneled over USB4 in DPIA
training module.

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Wayne Lin <Wayne.Lin@amd.com>
Acked-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Implement DPIA clock recovery phase
Jimmy Kizito [Tue, 27 Apr 2021 22:46:11 +0000 (18:46 -0400)]
drm/amd/display: Implement DPIA clock recovery phase

[Why]
Clock recovery is the mandatory first phase of DP link training.

[How]
- Implement clock recovery phase in DPIA training module.
- Add helper functions for building SET_CONFIG messages.

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Wayne Lin <Wayne.Lin@amd.com>
Acked-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Implement DPIA link configuration
Jimmy Kizito [Mon, 12 Apr 2021 20:03:11 +0000 (16:03 -0400)]
drm/amd/display: Implement DPIA link configuration

[Why]
Training settings need to be applied to DPIA link at start of each
training loop. Note: FEC readiness should be configured before link
training while FEC enablement should be configured once training is
complete.

[How]
- Implement DPIA link configuration function.
- Account for dynamically assigned link encoders during link
configuration.

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Wayne Lin <Wayne.Lin@amd.com>
Acked-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Implement DPIA training loop
Jimmy Kizito [Sat, 10 Apr 2021 02:23:53 +0000 (22:23 -0400)]
drm/amd/display: Implement DPIA training loop

[Why]
Training of DPIA link differs enough from that of conventional
DP link to warrant a separate implementation.

[How]
- Implement top-level of DPIA training loop.
- Make functions shared between DP and DPIA link training "public".

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Wayne Lin <Wayne.Lin@amd.com>
Acked-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Train DPIA links with fallback
Jimmy Kizito [Wed, 7 Apr 2021 22:56:19 +0000 (18:56 -0400)]
drm/amd/display: Train DPIA links with fallback

[Why & How]
Conventional links are trained with fallback during sink detection.
Have DPIA links trained with fallback too.

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Wayne Lin <Wayne.Lin@amd.com>
Acked-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Skip DPCD read for DPTX-to-DPIA hop
Jimmy Kizito [Mon, 5 Apr 2021 22:05:09 +0000 (18:05 -0400)]
drm/amd/display: Skip DPCD read for DPTX-to-DPIA hop

[why & how]
Driver does not need to train the first hop.

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Wayne Lin <Wayne.Lin@amd.com>
Acked-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Add stub to get DPIA tunneling device data
Jimmy Kizito [Thu, 1 Apr 2021 16:59:54 +0000 (12:59 -0400)]
drm/amd/display: Add stub to get DPIA tunneling device data

[why & how]
1. Add stub for getting tunneling device data
2. Add check for phy_repeater_cnt < 0xff to LTTPR check
3. Add two more bits of information to DPIA links

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Wayne Lin <Wayne.Lin@amd.com>
Acked-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Stub out DPIA link training call
Jimmy Kizito [Wed, 6 Jan 2021 20:21:11 +0000 (15:21 -0500)]
drm/amd/display: Stub out DPIA link training call

[why & how]
Add stub for DPIA link training and define new DPIA DMUB commands
to support it.

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Wayne Lin <Wayne.Lin@amd.com>
Acked-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Set DPIA link endpoint type
Jimmy Kizito [Tue, 5 Jan 2021 19:25:23 +0000 (14:25 -0500)]
drm/amd/display: Set DPIA link endpoint type

[why & how]
We will need a way to distinguish physically connected
links and DPIA endpoints.

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Wayne Lin <Wayne.Lin@amd.com>
Acked-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Support for DMUB HPD and HPD RX interrupt handling
Meenakshikumar Somasundaram [Wed, 27 Jan 2021 06:05:28 +0000 (01:05 -0500)]
drm/amd/display: Support for DMUB HPD and HPD RX interrupt handling

[WHY]
To add support for HPD & HPD RX interrupt handling for USB4 DPIA in
YELLOW_CARP_B0. USB4 DPIA HPD & HPD RX interrupts are issued from DMUB to
driver as a outbox1 message.

[HOW]
1) Created get_link_index_from_dpia_port_index() to retrieve link index
   from dpia port index for HPD & HPD RX dmub notifications.
2) Added DMUB HPD & HPD RX handling in dmub_srv_stat_get_notification().

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Wayne Lin <Wayne.Lin@amd.com>
Acked-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: USB4 DPIA enumeration and AUX Tunneling
Meenakshikumar Somasundaram [Tue, 26 Jan 2021 20:15:33 +0000 (15:15 -0500)]
drm/amd/display: USB4 DPIA enumeration and AUX Tunneling

[WHY]
To enable dc links for USB4 DPIA ports and AUX command tunneling
for YELLOW_CARP_B0.

[HOW]
1) Created dc links for all USB4 DPIA ports in create_links().
   dc_link_construct() implementation is split for legacy DDC and DPIAs.
   As usb4 has no ddc, ddc->ddc_pin will be set to NULL for its dc link
   and this parameter will be used to identify the dc links as DPIA. The
   dc link for DPIA is further to be enhanced with implementation for link
   encoder and link initialization.
2) usb4_dpia_count in struct resource_pool will be initialized to 4 in
   dcn31_resource_construct() if the DCN is YELLOW_CARP_B0.
3) Enabled DMUB AUX via outbox for YELLOW_CARP_B0.

Reviewed-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
Acked-by: Wayne Lin <Wayne.Lin@amd.com>
Acked-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Update link encoder object creation.
Jimmy Kizito [Tue, 5 Jan 2021 15:17:05 +0000 (10:17 -0500)]
drm/amd/display: Update link encoder object creation.

[Why & How]
USB4 endpoints are dynamically mapped. We create additional link
encoders for USB4 use when DC is created and destroy them when DC
is destructed

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Wayne Lin <Wayne.Lin@amd.com>
Acked-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: fix DCC settings for DCN3
Marek Olšák [Thu, 30 Sep 2021 15:13:59 +0000 (11:13 -0400)]
drm/amd/display: fix DCC settings for DCN3

ind_block_64b_no_128bcl means INDEP_64B && INDEP_128B &&
MAX_COMPRESSED_BLOCK_SIZE == 64B. Only used by gfx10.3.

ind_block_64b means INDEP_64B && !INDEP_128B &&
MAX_COMPRESSED_BLOCK_SIZE == 64B. Only used by gfx9 and gfx10.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Fix error in dmesg at boot
Leo (Hanghong) Ma [Fri, 1 Oct 2021 14:36:20 +0000 (22:36 +0800)]
drm/amd/display: Fix error in dmesg at boot

[Why]
During DQE's promotion test, error appears in dmesg at boot
on dcn3.1;

[How]
Add NULL pointor check for the pointor to the amdgpu_dm_connector;

Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Fix concurrent dynamic encoder assignment.
Jimmy Kizito [Fri, 1 Oct 2021 14:36:19 +0000 (22:36 +0800)]
drm/amd/display: Fix concurrent dynamic encoder assignment.

[Why]
Trying to enable multiple displays simultaneously exposed shortcomings
with the algorithm for dynamic link encoder assignment.

The main problems were:
- Assuming stream order remained constant across states would
sometimes lead to invalid DIG encoder assignment.
- Incorrect logic for deciding whether or not a DIG could support a
stream would also sometimes lead to invalid DIG encoder assignment.
- Changes in encoder assignment were wholesale while updating of the
pipe backend is incremental. This would lead to the hardware state
not matching the software state even with valid encoder assignments.

[How]

The following changes fix the identified problems.
- Use stream pointer rather than stream index to track streams across
states.
- Fix DIG compatibility check by examining the link signal type
rather than the stream signal type.
- Modify assignment algorithm to make incremental updates so software
and hardware states remain coherent.

Additionally:
- Add assertions and an encoder assignment validation
function link_enc_cfg_validate() to detect potential problems with
encoder assignment closer to their root cause.
- Reduce the frequency with which the assignment algorithm is
executed. It should not be necessary for fast state validation.

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Add helper for blanking all dp displays
Leo (Hanghong) Ma [Fri, 1 Oct 2021 14:36:18 +0000 (22:36 +0800)]
drm/amd/display: Add helper for blanking all dp displays

[Why & How]
The codes to blank all dp display have been called many times,
so add a helper in dc_link to make it more concise.

Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: 3.2.156
Aric Cyr [Fri, 1 Oct 2021 14:36:17 +0000 (22:36 +0800)]
drm/amd/display: 3.2.156

This version brings along following fixes:
- New firmware version
- Fix DMUB problems on stress test.
- Improve link training by skip overrride for preferred link
- Refinement of FPU code structure for DCN2
- Fix 3DLUT skipped programming
- Fix detection of 4 lane for DPALT
- Fix dcn3 failure due to dmcbu_abm not created
- Limit display scaling to up to 4k for DCN 3.1
- Add helper for blanking all dp displays

Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: [FW Promotion] Release 0.0.87
Anthony Koo [Fri, 1 Oct 2021 14:36:16 +0000 (22:36 +0800)]
drm/amd/display: [FW Promotion] Release 0.0.87

Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Fix detection of 4 lane for DPALT
Hansen [Fri, 1 Oct 2021 14:36:15 +0000 (22:36 +0800)]
drm/amd/display: Fix detection of 4 lane for DPALT

[Why]
DPALT detection for B0 PHY has its own set of RDPCSPIPE registers

[How]
Use RDPCSPIPE registers to detect if DPALT lane is 4 lane

Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Hansen <Hansen.Dsouza@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Limit display scaling to up to 4k for DCN 3.1
Nikola Cornij [Fri, 1 Oct 2021 14:36:14 +0000 (22:36 +0800)]
drm/amd/display: Limit display scaling to up to 4k for DCN 3.1

[why]
The existing limit was mistakenly bigger than 4k for DCN 3.1

Reviewed-by: Zhan Liu <Zhan.Liu@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Added root clock optimization flags
Jake Wang [Fri, 1 Oct 2021 14:36:13 +0000 (22:36 +0800)]
drm/amd/display: Added root clock optimization flags

[Why & How]
Added root clock optimization debug flags for future debugging.

Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Jake Wang <haonan.wang2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Re-arrange FPU code structure for dcn2x
Qingqing Zhuo [Fri, 1 Oct 2021 14:36:10 +0000 (22:36 +0800)]
drm/amd/display: Re-arrange FPU code structure for dcn2x

[Why]
Current FPU code for DCN2x is located under dml/dcn2x.
This is not aligned with DC's general source tree
structure.

[How]
Move FPU code for DCN2x to dml/dcn20.

Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Skip override for preferred link settings during link training
George Shen [Fri, 1 Oct 2021 14:36:09 +0000 (22:36 +0800)]
drm/amd/display: Skip override for preferred link settings during link training

[Why]
Overriding link setting inside override_training_settings
result in fallback link settings being ignored. This can
potentially cause link training to always fail and consequently
result in an infinite loop of link training to occur in
dp_verify_link_cap during detection.

[How]
Since preferred link settings are already considered inside
decide_link_settings, skip the check in override_training_settings
to avoid infinite link training loops.

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: handle the case of pci_channel_io_frozen only in amdgpu_pci_resume
Guchun Chen [Fri, 1 Oct 2021 01:48:50 +0000 (09:48 +0800)]
drm/amdgpu: handle the case of pci_channel_io_frozen only in amdgpu_pci_resume

In current code, when a PCI error state pci_channel_io_normal is detectd,
it will report PCI_ERS_RESULT_CAN_RECOVER status to PCI driver, and PCI
driver will continue the execution of PCI resume callback report_resume by
pci_walk_bridge, and the callback will go into amdgpu_pci_resume
finally, where write lock is releasd unconditionally without acquiring
such lock first. In this case, a deadlock will happen when other threads
start to acquire the read lock.

To fix this, add a member in amdgpu_device strucutre to cache
pci_channel_state, and only continue the execution in amdgpu_pci_resume
when it's pci_channel_io_frozen.

Fixes: c9a6b82f45e2 ("drm/amdgpu: Implement DPC recovery")
Suggested-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: print warning and taint kernel if lockup timeout is disabled
Christian König [Thu, 30 Sep 2021 09:59:14 +0000 (11:59 +0200)]
drm/amdgpu: print warning and taint kernel if lockup timeout is disabled

Make sure that we notice this in error reports.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: revert "Add autodump debugfs node for gpu reset v8"
Christian König [Thu, 30 Sep 2021 09:22:51 +0000 (11:22 +0200)]
drm/amdgpu: revert "Add autodump debugfs node for gpu reset v8"

This reverts commit 728e7e0cd61899208e924472b9e641dbeb0775c4.

Further discussion reveals that this feature is severely broken
and needs to be reverted ASAP.

GPU reset can never be delayed by userspace even for debugging or
otherwise we can run into in kernel deadlocks.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Nirmoy Das <nirmoy.das@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: init iommu after amdkfd device init
Yifan Zhang [Tue, 28 Sep 2021 07:42:35 +0000 (15:42 +0800)]
drm/amdgpu: init iommu after amdkfd device init

This patch is to fix clinfo failure in Raven/Picasso:

Number of platforms: 1
  Platform Profile: FULL_PROFILE
  Platform Version: OpenCL 2.2 AMD-APP (3364.0)
  Platform Name: AMD Accelerated Parallel Processing
  Platform Vendor: Advanced Micro Devices, Inc.
  Platform Extensions: cl_khr_icd cl_amd_event_callback

  Platform Name: AMD Accelerated Parallel Processing Number of devices: 0

Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Tested-by: James Zhu <James.Zhu@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdkfd: remove redundant iommu cleanup code
Yifan Zhang [Fri, 24 Sep 2021 03:15:35 +0000 (11:15 +0800)]
drm/amdkfd: remove redundant iommu cleanup code

kfd_resume doesn't involve iommu operation, remove
redundant iommu cleanup code.

Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Tested-by: James Zhu <James.Zhu@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/display: fix dependencies for DRM_AMD_DC_SI
Alex Deucher [Fri, 1 Oct 2021 19:40:00 +0000 (15:40 -0400)]
drm/amdgpu/display: fix dependencies for DRM_AMD_DC_SI

Depends on DRM_AMDGPU_SI and DRM_AMD_DC

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/gmc9: convert to IP version checking
Alex Deucher [Fri, 1 Oct 2021 18:00:03 +0000 (14:00 -0400)]
drm/amdgpu/gmc9: convert to IP version checking

Use IP versions rather than asic_type to differentiate
IP version specific features.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: Prevent using DMUB rptr that is out-of-bounds
Wyatt Wood [Tue, 21 Sep 2021 13:17:27 +0000 (09:17 -0400)]
drm/amd/display: Prevent using DMUB rptr that is out-of-bounds

[Why]
Running into bugchecks during stress test where rptr is 0xFFFFFFFF.
Typically this is caused by a hard hang, and can come from HW outside
of DCN.

[How]
To prevent bugchecks when writing the DMUB rptr, fist check that the
rptr is valid.

Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Wyatt Wood <wyatt.wood@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/display: fold DRM_AMD_DC_DCN201 into DRM_AMD_DC_DCN
Alex Deucher [Fri, 1 Oct 2021 14:29:02 +0000 (10:29 -0400)]
drm/amdgpu/display: fold DRM_AMD_DC_DCN201 into DRM_AMD_DC_DCN

No need for a separate kconfig option at this point.

Reviewed-by: Zhan Liu <zhan.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: remove some repeated includings
Guo Zhengkui [Fri, 1 Oct 2021 10:13:46 +0000 (18:13 +0800)]
drm/amdgpu: remove some repeated includings

Remove two repeated includings in line 46 and 47.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Guo Zhengkui <guozhengkui@vivo.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: During s0ix don't wait to signal GFXOFF
Lijo Lazar [Fri, 1 Oct 2021 08:49:07 +0000 (16:49 +0800)]
drm/amdgpu: During s0ix don't wait to signal GFXOFF

In the rare event when GFX IP suspend coincides with a s0ix entry, don't
schedule a delayed work, instead signal PMFW immediately to allow GFXOFF
entry. GFXOFF is a prerequisite for s0ix entry. PMFW needs to be
signaled about GFXOFF status before amd-pmc module passes OS HINT
to PMFW telling that everything is ready for a safe s0ix entry.

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1712

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Mario Limonciello <mario.limonciell@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agoDocumentation/gpu: remove spurious "+" in amdgpu.rst
Alex Deucher [Wed, 29 Sep 2021 17:42:08 +0000 (13:42 -0400)]
Documentation/gpu: remove spurious "+" in amdgpu.rst

Not sure why that was there.  Remove it.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: consolidate case statements
Alex Deucher [Wed, 29 Sep 2021 16:06:03 +0000 (12:06 -0400)]
drm/amdgpu: consolidate case statements

IP_VERSION(11, 0, 13) does the exact same thing as
IP_VERSION(11, 0, 12) so squash them together.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/jpeg: add jpeg2.6 start/end
James Zhu [Wed, 29 Sep 2021 19:42:34 +0000 (15:42 -0400)]
drm/amdgpu/jpeg: add jpeg2.6 start/end

Add jpeg2.6 start/end with updated PCTL0_MMHUB_DEEPSLEEP_IB address.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.lilu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/jpeg2: move jpeg2 shared macro to header file
James Zhu [Wed, 29 Sep 2021 19:33:25 +0000 (15:33 -0400)]
drm/amdgpu/jpeg2: move jpeg2 shared macro to header file

Move jpeg2 shared macro to header file

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.lilu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdkfd: fix a potential ttm->sg memory leak
Lang Yu [Wed, 29 Sep 2021 06:54:39 +0000 (14:54 +0800)]
drm/amdkfd: fix a potential ttm->sg memory leak

Memory is allocated for ttm->sg by kmalloc in kfd_mem_dmamap_userptr,
but isn't freed by kfree in kfd_mem_dmaunmap_userptr. Free it!

Fixes: 264fb4d332f5 ("drm/amdgpu: Add multi-GPU DMA mapping helpers")
Signed-off-by: Lang Yu <lang.yu@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: add an option to override IP discovery table from a file
Alex Deucher [Fri, 17 Sep 2021 15:23:45 +0000 (11:23 -0400)]
drm/amdgpu: add an option to override IP discovery table from a file

If you set amdgpu.discovery=2 you can force the the driver to
fetch the IP discovery table from a file rather than from the
table shipped on the device.  This is useful for debugging and
for device bring up and emulation when the tables may be in flux.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdkfd: convert kfd_device.c to use GC IP version
Alex Deucher [Thu, 12 Aug 2021 19:56:51 +0000 (15:56 -0400)]
drm/amdkfd: convert kfd_device.c to use GC IP version

rather than asic type.

v2: fix up CZ case

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdkfd: clean up parameters in kgd2kfd_probe
Alex Deucher [Thu, 12 Aug 2021 19:06:24 +0000 (15:06 -0400)]
drm/amdkfd: clean up parameters in kgd2kfd_probe

We can get the pdev and asic type from the adev.  No need
to pass them explicitly.

v2: squash in build fix for !CONFIG_HSA_AMD from Anson

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: add support for SRIOV in IP discovery path
Alex Deucher [Tue, 10 Aug 2021 21:06:02 +0000 (17:06 -0400)]
drm/amdgpu: add support for SRIOV in IP discovery path

Handle SRIOV requirements when adding IP blocks.

v2: add comment about UVD/VCE support on vega20 SR-IOV

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: clean up set IP function
Alex Deucher [Tue, 10 Aug 2021 19:21:10 +0000 (15:21 -0400)]
drm/amdgpu: clean up set IP function

Split into several smaller per IP functions to make it
easier to handle ordering issues for things like
SR-IOV in a follow up patch.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: convert IP version array to include instances
Alex Deucher [Mon, 4 Oct 2021 19:19:10 +0000 (15:19 -0400)]
drm/amdgpu: convert IP version array to include instances

Allow us to query instances versions more cleanly.

Instancing support is not consistent unfortunately. SDMA is a
good example.  Sienna cichlid has 4 total SDMA instances, each
enumerated separately (HWIDs 42, 43, 68, 69).  Arcturus has 8
total SDMA instances, but they are enumerated as multiple
instances of the same HWIDs (4x HWID 42, 4x HWID 43).  UMC
is another example.  On most chips there are multiple
instances with the same HWID.  This allows us to support both
forms.

v2: rebase
v3: clarify instancing support

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: set CHIP_IP_DISCOVERY as the asic type by default
Alex Deucher [Mon, 9 Aug 2021 21:28:34 +0000 (17:28 -0400)]
drm/amdgpu: set CHIP_IP_DISCOVERY as the asic type by default

For new chips with no explicit entry in the PCI ID list.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: add new asic_type for IP discovery
Alex Deucher [Mon, 9 Aug 2021 21:26:21 +0000 (17:26 -0400)]
drm/amdgpu: add new asic_type for IP discovery

Add a new asic type for asics where we don't have an
explicit entry in the PCI ID list.  We don't need
an asic type for these asics, other than something higher
than the existing ones, so just use this for all new
asics.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/ucode: add default behavior
Alex Deucher [Mon, 9 Aug 2021 20:47:54 +0000 (16:47 -0400)]
drm/amdgpu/ucode: add default behavior

Default to PSP ucode loading unless the user specifies
direct.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: get VCN harvest information from IP discovery table
Alex Deucher [Mon, 9 Aug 2021 17:17:10 +0000 (13:17 -0400)]
drm/amdgpu: get VCN harvest information from IP discovery table

Use the table rather than asic specific harvest registers.

v2: remove harvesting register checking

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/vcn: remove manual instance setting
Alex Deucher [Mon, 9 Aug 2021 16:41:29 +0000 (12:41 -0400)]
drm/amdgpu/vcn: remove manual instance setting

Handled by IP discovery now.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/sdma: remove manual instance setting
Alex Deucher [Mon, 9 Aug 2021 16:29:56 +0000 (12:29 -0400)]
drm/amdgpu/sdma: remove manual instance setting

Handled by IP discovery now.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: get VCN and SDMA instances from IP discovery table
Alex Deucher [Mon, 9 Aug 2021 15:50:23 +0000 (11:50 -0400)]
drm/amdgpu: get VCN and SDMA instances from IP discovery table

Rather than hardcoding it.  We already have the number of VCN
instances from a previous patch, so just update the VCN
instances for chips with static tables.

v2: squash in checks for SDMA3,4 (Guchun)
v3: clarify VCN changes

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: add HWID of SDMA instance 2 and 3
Guchun Chen [Fri, 3 Sep 2021 10:03:40 +0000 (18:03 +0800)]
drm/amdgpu: add HWID of SDMA instance 2 and 3

They are missed.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: add VCN1 hardware IP
Alex Deucher [Mon, 9 Aug 2021 16:18:08 +0000 (12:18 -0400)]
drm/amdgpu: add VCN1 hardware IP

So we can store the VCN IP revision for each instance of VCN.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amd/display: fix error case handling
Guchun Chen [Mon, 9 Aug 2021 07:44:29 +0000 (15:44 +0800)]
drm/amd/display: fix error case handling

Otherwise, we will run into error case path.

v2: fix build when CONFIG_DRM_AMD_DC_DCN is not set

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/soc15: convert to IP version checking
Alex Deucher [Wed, 4 Aug 2021 21:44:15 +0000 (17:44 -0400)]
drm/amdgpu/soc15: convert to IP version checking

Use IP versions rather than asic_type to differentiate
IP version specific features.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/vcn2.5: convert to IP version checking
Alex Deucher [Wed, 4 Aug 2021 21:10:52 +0000 (17:10 -0400)]
drm/amdgpu/vcn2.5: convert to IP version checking

Use IP versions rather than asic_type to differentiate
IP version specific features.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/amdgpu_vcn: convert to IP version checking
Alex Deucher [Wed, 4 Aug 2021 21:03:30 +0000 (17:03 -0400)]
drm/amdgpu/amdgpu_vcn: convert to IP version checking

Use IP versions rather than asic_type to differentiate
IP version specific features.

v2: squash in fix for navy flounder and sienna cichlid

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/pm/amdgpu_smu: convert more IP version checking
Alex Deucher [Wed, 4 Aug 2021 19:26:53 +0000 (15:26 -0400)]
drm/amdgpu/pm/amdgpu_smu: convert more IP version checking

Use IP versions rather than asic_type to differentiate
IP version specific features.

v2: switch if statement to a switch statement

Acked-by: Christian König <christian.koenig@amd.com> (v1)
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/pm/smu_v13.0: convert IP version checking
Alex Deucher [Fri, 20 Aug 2021 17:51:10 +0000 (13:51 -0400)]
drm/amdgpu/pm/smu_v13.0: convert IP version checking

Use IP versions rather than asic_type to differentiate
IP version specific features.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/pm/smu_v11.0: update IP version checking
Alex Deucher [Wed, 4 Aug 2021 19:11:18 +0000 (15:11 -0400)]
drm/amdgpu/pm/smu_v11.0: update IP version checking

Use IP versions rather than asic_type to differentiate
IP version specific features.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/psp_v13.0: convert to IP version checking
Alex Deucher [Wed, 4 Aug 2021 19:01:33 +0000 (15:01 -0400)]
drm/amdgpu/psp_v13.0: convert to IP version checking

Use IP versions rather than asic_type to differentiate
IP version specific features.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/psp_v11.0: convert to IP version checking
Alex Deucher [Wed, 4 Aug 2021 18:55:32 +0000 (14:55 -0400)]
drm/amdgpu/psp_v11.0: convert to IP version checking

Use IP versions rather than asic_type to differentiate
IP version specific features.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/amdgpu_psp: convert to IP version checking
Alex Deucher [Thu, 16 Sep 2021 20:36:52 +0000 (16:36 -0400)]
drm/amdgpu/amdgpu_psp: convert to IP version checking

Use IP versions rather than asic_type to differentiate
IP version specific features.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/gfx9.0: convert to IP version checking
Alex Deucher [Tue, 3 Aug 2021 22:28:35 +0000 (18:28 -0400)]
drm/amdgpu/gfx9.0: convert to IP version checking

Use IP versions rather than asic_type to differentiate
IP version specific features.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/hdp4.0: convert to IP version checking
Alex Deucher [Tue, 3 Aug 2021 22:17:01 +0000 (18:17 -0400)]
drm/amdgpu/hdp4.0: convert to IP version checking

Use IP versions rather than asic_type to differentiate
IP version specific features.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/sdma4.0: convert to IP version checking
Alex Deucher [Tue, 3 Aug 2021 22:09:43 +0000 (18:09 -0400)]
drm/amdgpu/sdma4.0: convert to IP version checking

Use IP versions rather than asic_type to differentiate
IP version specific features.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/display/dm: convert RAVEN to IP version checking
Alex Deucher [Tue, 3 Aug 2021 21:47:14 +0000 (17:47 -0400)]
drm/amdgpu/display/dm: convert RAVEN to IP version checking

Use IP versions rather than asic_type to differentiate
IP version specific features.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: default to true in amdgpu_device_asic_has_dc_support
Alex Deucher [Tue, 3 Aug 2021 21:39:01 +0000 (17:39 -0400)]
drm/amdgpu: default to true in amdgpu_device_asic_has_dc_support

We are not going to support any new chips with the old
non-DC code so make it the default.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: drive all vega asics from the IP discovery table
Alex Deucher [Fri, 30 Jul 2021 19:50:38 +0000 (15:50 -0400)]
drm/amdgpu: drive all vega asics from the IP discovery table

Rather than hardcoding based on asic_type, use the IP
discovery table to configure the driver.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/soc15: get rev_id in soc15_common_early_init
Alex Deucher [Fri, 30 Jul 2021 19:30:58 +0000 (15:30 -0400)]
drm/amdgpu/soc15: get rev_id in soc15_common_early_init

for consistency with other SoCs.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: add initial IP discovery support for vega based parts
Alex Deucher [Fri, 30 Jul 2021 18:51:54 +0000 (14:51 -0400)]
drm/amdgpu: add initial IP discovery support for vega based parts

Hardcode the IP versions for asics without IP discovery tables
and then enumerate the asics based on the IP versions.

TODO: fix SR-IOV support

v2: Squash in HDP fix for Renoir

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/soc15: export common IP functions
Alex Deucher [Fri, 30 Jul 2021 18:50:07 +0000 (14:50 -0400)]
drm/amdgpu/soc15: export common IP functions

So they can be driven by IP discovery table.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: add DCI HWIP
Alex Deucher [Fri, 30 Jul 2021 16:44:07 +0000 (12:44 -0400)]
drm/amdgpu: add DCI HWIP

So we can track grab the appropriate DCE info out of the
IP discovery table.  This is a separare IP from DCN.

Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/display/dm: convert to IP version checking
Alex Deucher [Wed, 29 Sep 2021 18:04:42 +0000 (14:04 -0400)]
drm/amdgpu/display/dm: convert to IP version checking

Use IP versions rather than asic_type to differentiate
IP version specific features.

v2: drop unrelated change

Acked-by: Christian König <christian.koenig@amd.com> (v1)
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu: drive all navi asics from the IP discovery table
Alex Deucher [Wed, 28 Jul 2021 15:16:12 +0000 (11:16 -0400)]
drm/amdgpu: drive all navi asics from the IP discovery table

Rather than hardcoding based on asic_type, use the IP
discovery table to configure the driver.

v2: rebase

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/nv: convert to IP version checking
Alex Deucher [Wed, 28 Jul 2021 16:10:20 +0000 (12:10 -0400)]
drm/amdgpu/nv: convert to IP version checking

Use IP versions rather than asic_type to differentiate
IP version specific features.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/sienna_cichlid_ppt: convert to IP version checking
Alex Deucher [Tue, 27 Jul 2021 21:40:58 +0000 (17:40 -0400)]
drm/amdgpu/sienna_cichlid_ppt: convert to IP version checking

Use IP versions rather than asic_type to differentiate
IP version specific features.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
3 years agodrm/amdgpu/navi10_ppt: convert to IP version checking
Alex Deucher [Tue, 27 Jul 2021 21:32:55 +0000 (17:32 -0400)]
drm/amdgpu/navi10_ppt: convert to IP version checking

Use IP versions rather than asic_type to differentiate
IP version specific features.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>