Rob Clark [Wed, 20 Sep 2023 22:59:18 +0000 (15:59 -0700)]
freedreno/decode: Lookup device info
First step for migration to chip_id. With newer devices we won't be
able to decode the chip_id in any meaningful way, ie. it is just a
number. But we can use the device table to figure out things like
generation which are needed to properly decode cmdstream, etc.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25333>
Caio Oliveira [Thu, 14 Sep 2023 15:22:57 +0000 (08:22 -0700)]
util: Add more PRINTFLIKE and MALLOCLIKE annotations
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25230>
Caio Oliveira [Fri, 22 Sep 2023 17:23:06 +0000 (10:23 -0700)]
microsoft/compiler: Fix printf formatting string issues
Found when adding PRINTFLIKE macro to util functions.
Suggested-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25230>
Caio Oliveira [Thu, 21 Sep 2023 20:35:42 +0000 (13:35 -0700)]
intel/compiler: Don't allocate memory for SIMD select error handling
The position in the error array already indicate the SIMD in question,
so take off all the formatted printing from the errors -- which in some
cases were just not needed. We lose a little bit of extra context but
it is all easily derivable from the message and the SIMD.
This also will remove the overhead when SIMD selection is being used to
just to find the selected dispatch width -- at a point where the shaders
were already compiled -- and the errors are not used at all.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9849
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25336>
Caio Oliveira [Fri, 22 Sep 2023 07:02:35 +0000 (00:02 -0700)]
compiler: Only enable mesaclc helper if we have OpenCL SPIR-V support
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25341>
Caio Oliveira [Fri, 22 Sep 2023 06:58:55 +0000 (23:58 -0700)]
clover: Only compile/depend libclspirv and libclnir when using SPIR-V support
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25341>
Caio Oliveira [Fri, 22 Sep 2023 06:50:14 +0000 (23:50 -0700)]
clover: Hide SPIR-V related code behind HAVE_CLOVER_SPIRV
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25341>
Caio Oliveira [Wed, 20 Sep 2023 18:40:24 +0000 (11:40 -0700)]
rusticl: Ensure NIR generated headers will be available
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25314>
Caio Oliveira [Wed, 20 Sep 2023 18:44:36 +0000 (11:44 -0700)]
meson: Remove unnecessary inc_compiler mentions
The inc_compiler should come as part of idep_compiler, idep_nir or
idep_nir_headers dependency.
Acked-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> (v3dv)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25314>
Caio Oliveira [Wed, 20 Sep 2023 18:22:22 +0000 (11:22 -0700)]
compiler: Use a meson dependency for libcompiler
That will make sure the include directories are passed on and also
make sure the generated headers are properly built before whoever code
depends on it. NIR dependency propagates that dependency too.
Since the right include directory is always propagated, we can remove
the extra "compiler/" prefix from the `#include`s in glsl_types.h.
Note: NIR has a special "header only" dependency, so include the
generated headers for compiler there too.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9843
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25314>
Helen Koike [Thu, 14 Sep 2023 23:32:07 +0000 (20:32 -0300)]
ci: separate hiden jobs to -inc.yml files
make it easier to re-use the hidden jobs by other project (e.g. linux)
without enabling the executable jobs.
Signed-off-by: Helen Koike <helen.koike@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25238>
Mike Blumenkrantz [Thu, 21 Sep 2023 17:50:10 +0000 (13:50 -0400)]
zink: fix semaphore signal ordering
the timeline semaphore must always be on the last submit in order to
mimic fence behavior
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25334>
Mike Blumenkrantz [Wed, 6 Sep 2023 11:48:24 +0000 (07:48 -0400)]
zink: add a ZINK_DEBUG=validation alias
typing validation all the time makes my hands hurt
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25290>
Mike Blumenkrantz [Tue, 5 Sep 2023 19:03:17 +0000 (15:03 -0400)]
zink: set workgroup_memory_explicit_layout for shader validation
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25290>
Mike Blumenkrantz [Thu, 6 Apr 2023 23:22:08 +0000 (19:22 -0400)]
lavapipe: set separate_shaders for shader objects
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25292>
Mike Blumenkrantz [Fri, 18 Aug 2023 17:53:00 +0000 (13:53 -0400)]
zink: delete a non-maintenance5 workaround for shobj use
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25289>
Mike Blumenkrantz [Fri, 18 Aug 2023 17:52:52 +0000 (13:52 -0400)]
zink: require maintenance5 for shobj
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25289>
Mike Blumenkrantz [Fri, 18 Aug 2023 17:48:38 +0000 (13:48 -0400)]
zink: delete injected pointsize during shader creation
maintenance5 is best maintenance.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25289>
Konstantin Seurer [Wed, 20 Sep 2023 16:07:42 +0000 (18:07 +0200)]
lavapipe/ci: Fix asan expectations
Those failures were fixed in
b2f6de8f0d86b8143084212f970af072780fc201.
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25309>
Konstantin Seurer [Mon, 18 Sep 2023 16:32:07 +0000 (18:32 +0200)]
nir/deref: Layer rematerialization helpers
nir_rematerialize_derefs_in_use_blocks_impl can be implemented on top of
nir_rematerialize_deref_in_use_blocks.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23712>
Konstantin Seurer [Fri, 28 Jul 2023 15:09:34 +0000 (17:09 +0200)]
nir/lcssa: Fix rematerializing derefs
This would pull derefs out of loops by emitting the pattern
`deref(phi(deref))` which is not allowed by nir_validate.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23712>
Konstantin Seurer [Fri, 28 Jul 2023 15:07:49 +0000 (17:07 +0200)]
nir: Add nir_rematerialize_deref_in_use_blocks
nir_rematerialize_deref_in_use_blocks can be used in passes that don't
run on the whole function.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23712>
Rhys Perry [Fri, 23 Jun 2023 14:39:32 +0000 (15:39 +0100)]
nir/deref: remove rematerialize_deref_in_block cache
Nothing was ever inserted into this.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23712>
Konstantin Seurer [Wed, 20 Sep 2023 14:32:07 +0000 (16:32 +0200)]
nir: Add nir_foreach_block_in_cf_node_reverse
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23712>
Konstantin Seurer [Wed, 20 Sep 2023 14:31:05 +0000 (16:31 +0200)]
nir: Add nir_cf_node_cf_tree_prev
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23712>
Eric Engestrom [Fri, 22 Sep 2023 07:56:24 +0000 (08:56 +0100)]
ci/zink+radv: bump the timeout of zink-radv-navi10-valve by 10 minutes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25342>
Eric Engestrom [Fri, 22 Sep 2023 07:55:33 +0000 (08:55 +0100)]
ci/zink+radv: specify that zink-radv-navi10-valve should run in the mupuf farm
Fixes:
8c98ee6f3addb1d1b41d ("radv/ci: move vkcts-navi10 testing to KWS")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25342>
Corentin Noël [Tue, 19 Sep 2023 14:33:05 +0000 (16:33 +0200)]
virgl: Cover all the formats defined in the virgl definition
Add all the formats currently defined in u_formats.h
Also make sure that no format on virgl protocol has the same number as another one.
Make so that the virgl_formats_conv_table is following the same order as virgl_formats
Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25295>
Konstantin Seurer [Tue, 15 Aug 2023 12:55:10 +0000 (14:55 +0200)]
aco/spill: Make sure that offset stays in bounds
If a shader spills a lot, the offset can be above the HW limit.
cc: mesa-stable
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24652>
Rob Clark [Thu, 21 Sep 2023 21:27:44 +0000 (14:27 -0700)]
freedreno/fence: Hold a strong ref to batch
We don't want a unflushed fence to outlive it's batch, otherwise we run
into trouble when it comes time to wait on the fence. For ex:
1. Create a fence before framebuffer state is set, with the
PIPE_FLUSH_DEFERRED flags. This creates a new batch, to which the
ctx holds the only reference (unless the fence also holds a ref)
2. set_framebuffer_state() creates a new batch and drops the ctx->batch
reference.
3. Later something tries to wait on the fence
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8621
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25337>
Rob Clark [Thu, 21 Sep 2023 21:27:09 +0000 (14:27 -0700)]
freedreno: Add reformatting commits to .git-blame-ignore-revs
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25337>
Timothy Arceri [Thu, 21 Sep 2023 06:55:49 +0000 (16:55 +1000)]
glsl: remove unused validate_first_and_last_interface_explicit_locations()
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25318>
Timothy Arceri [Thu, 21 Sep 2023 06:50:21 +0000 (16:50 +1000)]
glsl: switch to nir validate_first_and_last_interface_explicit_locations()
Use the new nir version. The glsl ir version will be removed in the
following patch.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25318>
Timothy Arceri [Wed, 13 Sep 2023 02:23:11 +0000 (12:23 +1000)]
glsl: add nir version of validate_first_and_last_interface_explicit_locations()
The glsl ir version will be removed in a following commit.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25318>
Timothy Arceri [Thu, 21 Sep 2023 06:48:22 +0000 (16:48 +1000)]
glsl: move get_varying_type() declaration earlier
Required for the following patch to keep this file somewhat organised.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25318>
Jordan Justen [Tue, 28 Jun 2022 21:31:11 +0000 (14:31 -0700)]
intel/isl: Build for Xe2
This is only *build* support in isl for Xe2. Before adding LNL PCI
IDs, subsequent patches will fill in ISL updates for Xe2.
Rework:
* Rohan: Update isl_genX_declare_get_func
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25253>
Jordan Justen [Tue, 28 Jun 2022 19:04:51 +0000 (12:04 -0700)]
intel/genxml: Build with gen20.xml
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25253>
Martin Roukala (né Peres) [Thu, 21 Sep 2023 10:32:39 +0000 (13:32 +0300)]
radv/ci: add more tests to the navi10 vkcts flake list
Since I had to aggregate the results of a lot of run, this commit also
ends up ordering some of the flakes to fit the alphabetical order.
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25324>
Martin Roukala (né Peres) [Mon, 18 Sep 2023 13:23:52 +0000 (16:23 +0300)]
radv/ci: move vkcts-navi10 testing to KWS
We now have 2 more navi10 DUTs at KWS, so let's use them to speed
up vkcts testing!
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25324>
Ian Romanick [Mon, 5 Dec 2022 22:18:33 +0000 (14:18 -0800)]
nir/rematerialize: Rematerialize ALUs used only by compares with zero
This was 4th on the list of things to try in
3ee2e84c608 ("nir:
Rematerialize compare instructions"). This is implemented as a separate
subpass that tries to find ALU instructions (with restrictions) that are
only used by comparisons with zero that are in turn only used as
conditions for bcsel or if-statements.
There are two restrictions implemented. One of the sources must be a
constant. This is done in an attempt to prevent increasing register
pressure. Additionally, the opcode of the instruction must be one that
has a high probablility of getting a conditional modifier on Intel
GPUs. Not all instructions can have a conditional modifiers (e.g., min
and max), so I don't think there is any benefit to moving these
instructions.
v2: Rebase on many, many recent NIR infrastructure changes.
v3: Make data in commit message more clear. Suggested by Matt. Rebase on
b5d6b7c402a ("nir: Drop most uses if nir_instr_rewrite_src()").
All of the affected shaders on ILK and G45 are in CS:GO. There is some
brief analysis of the changes in the MR.
Reviewed-by: Matt Tuner <mattst88@gmail.com>
Shader-db results:
DG2
total instructions in shared programs:
22824637 ->
22824258 (<.01%)
instructions in affected programs: 365742 -> 365363 (-0.10%)
helped: 190 / HURT: 97
total cycles in shared programs:
832186193 ->
832157290 (<.01%)
cycles in affected programs:
41245259 ->
41216356 (-0.07%)
helped: 208 / HURT: 117
total spills in shared programs: 4072 -> 4060 (-0.29%)
spills in affected programs: 366 -> 354 (-3.28%)
helped: 4 / HURT: 2
total fills in shared programs: 3601 -> 3607 (0.17%)
fills in affected programs: 708 -> 714 (0.85%)
helped: 4 / HURT: 2
LOST: 0
GAINED: 1
Tiger Lake and Ice Lake had similar results. (Ice Lake shown)
total instructions in shared programs:
20320934 ->
20320689 (<.01%)
instructions in affected programs: 236592 -> 236347 (-0.10%)
helped: 176 / HURT: 29
total cycles in shared programs:
849846341 ->
849843856 (<.01%)
cycles in affected programs:
41277336 ->
41274851 (<.01%)
helped: 195 / HURT: 110
LOST: 0
GAINED: 1
Skylake
total instructions in shared programs:
18550811 ->
18550470 (<.01%)
instructions in affected programs: 233908 -> 233567 (-0.15%)
helped: 182 / HURT: 25
total cycles in shared programs:
835910983 ->
835889167 (<.01%)
cycles in affected programs:
38764359 ->
38742543 (-0.06%)
helped: 207/ HURT: 94
total spills in shared programs: 4522 -> 4506 (-0.35%)
spills in affected programs: 324 -> 308 (-4.94%)
helped: 4 / HURT: 0
total fills in shared programs: 5296 -> 5280 (-0.30%)
fills in affected programs: 324 -> 308 (-4.94%)
helped: 4 / HURT: 0
LOST: 0
GAINED: 1
Broadwell
total instructions in shared programs:
18199130 ->
18197920 (<.01%)
instructions in affected programs: 214664 -> 213454 (-0.56%)
helped: 191 / HURT: 0
total cycles in shared programs:
935131908 ->
934870248 (-0.03%)
cycles in affected programs:
75770568 ->
75508908 (-0.35%)
helped: 203 / HURT: 84
total spills in shared programs: 13896 -> 13734 (-1.17%)
spills in affected programs: 162 -> 0
helped: 3 / HURT: 0
total fills in shared programs: 16989 -> 16761 (-1.34%)
fills in affected programs: 228 -> 0
helped: 3 / HURT: 0
Haswell
total instructions in shared programs:
16969502 ->
16969085 (<.01%)
instructions in affected programs: 185498 -> 185081 (-0.22%)
helped: 121 / HURT: 1
total cycles in shared programs:
925290863 ->
924806827 (-0.05%)
cycles in affected programs:
30200863 ->
29716827 (-1.60%)
helped: 100 / HURT: 85
total spills in shared programs: 13565 -> 13533 (-0.24%)
spills in affected programs: 736 -> 704 (-4.35%)
helped: 8 / HURT: 0
total fills in shared programs: 15468 -> 15436 (-0.21%)
fills in affected programs: 740 -> 708 (-4.32%)
helped: 8 / HURT: 0
LOST: 0
GAINED: 1
Ivy Bridge
total instructions in shared programs:
15839127 ->
15838947 (<.01%)
instructions in affected programs: 77776 -> 77596 (-0.23%)
helped: 58 / HURT: 0
total cycles in shared programs:
459852774 ->
459739770 (-0.02%)
cycles in affected programs:
11970210 ->
11857206 (-0.94%)
helped: 79 / HURT: 53
Sandy Bridge
total instructions in shared programs:
14106847 ->
14106831 (<.01%)
instructions in affected programs: 1611 -> 1595 (-0.99%)
helped: 10 / HURT: 0
total cycles in shared programs:
775004024 ->
775007516 (<.01%)
cycles in affected programs: 2530686 -> 2534178 (0.14%)
helped: 55 / HURT: 48
Iron Lake
total cycles in shared programs:
257753356 ->
257754900 (<.01%)
cycles in affected programs: 2977374 -> 2978918 (0.05%)
helped: 12 / HURT: 106
GM45
total cycles in shared programs:
169711382 ->
169712816 (<.01%)
cycles in affected programs: 2402070 -> 2403504 (0.06%)
helped: 12 / HURT: 57
Fossil-db results:
All Intel platforms had similar results. (DG2 shown)
Totals:
Instrs:
193884596 ->
193465896 (-0.22%); split: -0.25%, +0.03%
Cycles:
14050193354 ->
14048194826 (-0.01%); split: -0.34%, +0.33%
Spill count: 114944 -> 100449 (-12.61%); split: -13.59%, +0.98%
Fill count: 201525 -> 179534 (-10.91%); split: -11.22%, +0.31%
Scratch Memory Size:
10028032 -> 8468480 (-15.55%)
Totals from 16912 (2.59% of 653124) affected shaders:
Instrs:
34173709 ->
33755009 (-1.23%); split: -1.41%, +0.19%
Cycles:
2945969110 ->
2943970582 (-0.07%); split: -1.62%, +1.55%
Spill count: 97753 -> 83258 (-14.83%); split: -15.98%, +1.15%
Fill count: 176355 -> 154364 (-12.47%); split: -12.82%, +0.35%
Scratch Memory Size: 8619008 -> 7059456 (-18.09%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20176>
Pierre-Eric Pelloux-Prayer [Thu, 21 Sep 2023 07:42:53 +0000 (09:42 +0200)]
radeonsi: emit framebuffer state after allocating cmask
tex->cmask_base_address_reg and tex->cb_color_info are used in
si_emit_framebuffer_state so we have to re-emit the state when
they're modified.
It's not done in si_alloc_separate_cmask because it cannot
update framebuffer.dirty_cbufs.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9830
Cc: mesa-stable
Reviewed-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25317>
Emma Anholt [Wed, 20 Sep 2023 18:40:17 +0000 (11:40 -0700)]
ci/fastboot: Use a case insensitive match for a fastboot line.
Newer boards like the RB5 have a capital F, so this will make the script
more reusable for drm ci.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25311>
David Rosca [Tue, 19 Sep 2023 09:00:12 +0000 (11:00 +0200)]
radeonsi/vcn: Implement destroy_fence vfunc
Now that fences are correctly cleaned up in frontend, we can store
the fence reference in picture->fence again.
The encoder also needs to implement this vfunc because if a surface
from decoder is used directly as encode input it's now up to encoder
to destroy the fence.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9834
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25296>
David Rosca [Tue, 19 Sep 2023 08:53:21 +0000 (10:53 +0200)]
frontends/va: Destroy fences when destroying surface or context
It is valid to destroy VASurface after destroying VAContext, so we need
to destroy fences of all surfaces that are currently being tracked by a
context when deleting this context.
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25296>
David Rosca [Tue, 19 Sep 2023 08:51:10 +0000 (10:51 +0200)]
frontends/va: Track surfaces in context
This will be needed to correctly cleanup fences.
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25296>
Roman Stratiienko [Sat, 9 Sep 2023 10:57:29 +0000 (13:57 +0300)]
u_gralloc: Add a function that returns gralloc type
This is needed by some drivers to reject the fallback gralloc.
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25256>
Roman Stratiienko [Wed, 20 Sep 2023 21:06:15 +0000 (00:06 +0300)]
Revert "util: Add NONNULL macro"
We agreed in [1] not to use it since it has little value,
but making a code less readable.
[1]: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25256
This reverts commit
21dcde096f351f83a2df7aa9f42a7276b5454c81.
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25256>
Roman Stratiienko [Wed, 20 Sep 2023 21:01:19 +0000 (00:01 +0300)]
u_gralloc: Remove usage of NONNULL macro
We agreed in [1] not to use it since it has little value,
but making a code less readable.
[1]: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25256
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25256>
Roman Stratiienko [Fri, 15 Sep 2023 22:26:33 +0000 (01:26 +0300)]
u_gralloc: Remove inline modifiers from the functions
Suggested-by: Chia-I Wu <olvaffe@gmail.com>
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25256>
Eric Engestrom [Thu, 21 Sep 2023 09:25:02 +0000 (10:25 +0100)]
docs: drop outdated and redundant note about the minimum meson version
The documentation we've been keeping up to date is in `docs/meson.rst`.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25322>
Georg Lehmann [Fri, 8 Sep 2023 09:01:34 +0000 (11:01 +0200)]
aco: simplify masked swizzle dpp selection by removing or_mask first
and_mask and xor_mask alone can represent all patterns without or_mask
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25115>
Eric Engestrom [Fri, 1 Sep 2023 12:28:36 +0000 (13:28 +0100)]
ci: limit build jobs to 30min so that they can retry when they go wrong
Build jobs should never take more than 1-3 minutes.
These jobs are never slow, either they finish within reasonable time or
something has gone wrong and the job will never terminate, so we should
instead timeout and retry.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24995>
Karol Herbst [Tue, 19 Sep 2023 16:07:27 +0000 (18:07 +0200)]
rusticl/kernel: skip adding global id offsets if not used
This allows us to shrink the kernel input buffer quite significantly as
the offset is a vec aligned size_t3 value.
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25303>
Karol Herbst [Wed, 20 Sep 2023 10:46:13 +0000 (12:46 +0200)]
rusticl/mesa: fix `set_constant_buffer` when passing an empty buffer
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25303>
Jordan Justen [Thu, 13 Apr 2023 22:55:07 +0000 (15:55 -0700)]
intel/fs: Update SSBO & shared uniform block loads for Xe2
Note: lower_lsc_block_logical_send() most likely stills needs some
related updates.
Ref:
a358b97c586 ("intel/fs: optimize uniform SSBO & shared loads")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Jordan Justen [Thu, 2 Mar 2023 00:28:29 +0000 (16:28 -0800)]
intel/compiler: Update RT stack_id access for Xe2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Jordan Justen [Sat, 18 Feb 2023 00:08:26 +0000 (16:08 -0800)]
intel/compiler: Update ray-tracing intrinsic lowering for Xe2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Jordan Justen [Wed, 1 Feb 2023 18:32:38 +0000 (10:32 -0800)]
intel/compiler: Update lower_trace_ray_logical_send() for Xe2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Jordan Justen [Wed, 1 Feb 2023 18:32:10 +0000 (10:32 -0800)]
intel/compiler: Update emit_rt_lsc_fence() for Xe2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Jordan Justen [Tue, 19 Sep 2023 18:09:09 +0000 (11:09 -0700)]
intel/compiler: Update opt_split_sends() for Xe2 reg size
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Jordan Justen [Wed, 1 Feb 2023 00:01:26 +0000 (16:01 -0800)]
intel/compiler/fs: Support Xe2 reg size in assign_curb_setup
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Wed, 11 Jan 2023 08:20:36 +0000 (00:20 -0800)]
intel/xe2+: Round up size to reg_unit() in fs_reg_alloc::alloc_spill_reg().
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Tue, 11 Oct 2022 01:05:13 +0000 (18:05 -0700)]
intel/fs/xe2+: Fix calculation of spill message width for Xe2 regs.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Thu, 29 Sep 2022 00:37:18 +0000 (17:37 -0700)]
intel/fs/xe2+: Fix execution width of SHADER_OPCODE_GET_BUFFER_SIZE for SIMD16 EU.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Fri, 30 Sep 2022 01:04:56 +0000 (18:04 -0700)]
intel/fs/xe2+: Update regioning lowering offset alignment checks for Xe2 regs.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Thu, 11 Aug 2022 00:31:58 +0000 (17:31 -0700)]
intel/fs: Lower unsupported regioning with non-trivial 2D regions on FIXED_GRFs.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Caio Oliveira [Sun, 11 Sep 2022 08:01:17 +0000 (01:01 -0700)]
intel/fs/xe2+: Update TASK/MESH payload setup for Xe2 reg size.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Caio Oliveira [Sun, 11 Sep 2022 07:57:26 +0000 (00:57 -0700)]
intel/fs/xe2+: Update BS payload setup for Xe2 reg size.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Wed, 7 Sep 2022 21:11:05 +0000 (14:11 -0700)]
intel/fs/xe2+: Update TES payload setup for Xe2 reg size.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Wed, 7 Sep 2022 21:09:04 +0000 (14:09 -0700)]
intel/fs/xe2+: Update TCS payload setup for Xe2 reg size.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Thu, 8 Sep 2022 00:52:18 +0000 (17:52 -0700)]
intel/fs/xe2+: Update GS payload setup for Xe2 reg size.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Caio Oliveira [Fri, 2 Sep 2022 00:13:57 +0000 (17:13 -0700)]
intel/compiler/xe2: Account for reg_unit() in TES intrinsics
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Caio Oliveira [Wed, 7 Sep 2022 07:22:13 +0000 (00:22 -0700)]
intel/compiler/xe2: Account for reg_unit() in TCS intrinsics
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Wed, 24 Aug 2022 18:46:45 +0000 (11:46 -0700)]
intel/fs/xe2+: Fix payload layout of sampler messages for Xe2 reg size
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Ian Romanick [Tue, 23 Aug 2022 01:00:09 +0000 (18:00 -0700)]
intel/compiler/xe2: TXD is lowered to SIMD16 in SIMD32 mode
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Ian Romanick [Tue, 23 Aug 2022 00:35:53 +0000 (17:35 -0700)]
intel/compiler/xe2: Use SIMD16 for nir_intrinsic_image_size
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Ian Romanick [Mon, 1 Aug 2022 23:42:57 +0000 (16:42 -0700)]
intel/compiler/xe2: Update fs_visitor::setup_vs_payload to account for Xe2 reg size
[ Francisco Jerez: Simplify. ]
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Rohan Garg [Mon, 1 Aug 2022 14:45:30 +0000 (16:45 +0200)]
intel/compiler: Adjust barrier emission for Xe2+
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Wed, 3 Aug 2022 23:51:43 +0000 (16:51 -0700)]
intel/fs/xe2+: Scale BRW_MAX_MSG_LENGTH by native register size.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Rohan Garg [Fri, 22 Jul 2022 11:33:17 +0000 (13:33 +0200)]
intel/compiler: Adjust fence message lengths for new register width on Xe2+
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Rohan Garg [Fri, 22 Jul 2022 11:32:08 +0000 (13:32 +0200)]
intel/compiler: Adjust CS payload registers for new register width on Xe2+
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Thu, 21 Jul 2022 18:38:03 +0000 (11:38 -0700)]
intel/fs/xe2+: Round up fs_builder::vgrf() size calculation to HW register unit.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Sat, 23 Jul 2022 00:36:26 +0000 (17:36 -0700)]
intel/fs/xe2+: Update encoding of FB write message payload.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Tue, 19 Jul 2022 23:44:26 +0000 (16:44 -0700)]
intel/compiler/xe2+: Represent dispatch_grf_start_reg in native GRF units.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Sat, 23 Jul 2022 00:30:30 +0000 (17:30 -0700)]
intel/fs/xe2+: Allow increased SIMD width for various get_fpu_lowered_simd_width() restrictions.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Sat, 16 Jul 2022 02:11:04 +0000 (19:11 -0700)]
intel/eu/xe2+: Update validation of GRF region size to account for Xe2 reg size
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Sat, 23 Jul 2022 00:28:47 +0000 (17:28 -0700)]
intel/fs/xe2+: Scale MAX_SAMPLER_MESSAGE_SIZE by native register size.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Thu, 7 Jul 2022 21:43:05 +0000 (14:43 -0700)]
intel/fs/xe2+: Fixes for increased accumulator register width.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Thu, 7 Jul 2022 21:03:49 +0000 (14:03 -0700)]
intel/fs/xe2+: Fix grf_count in post-RA scheduling for updated register file size.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Thu, 7 Jul 2022 21:01:29 +0000 (14:01 -0700)]
intel/fs/xe2+: Fix payload node live range calculations for change in register size.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Thu, 7 Jul 2022 08:12:24 +0000 (01:12 -0700)]
intel/fs: Fix signedness of payload_node_count argument of calculate_payload_ranges().
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Thu, 7 Jul 2022 08:00:19 +0000 (01:00 -0700)]
intel/eu/xe2+: Fix encoding of various message descriptors for change in register size.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Wed, 29 Jun 2022 00:49:38 +0000 (17:49 -0700)]
intel/fs/ra/xe2: Scale up register allocation granularity by 2x on Xe2+ platforms.
v2: Fix spill register allocation. Switch to brw_reg::nr
representation in fake 256b units.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Tue, 22 Feb 2022 05:42:05 +0000 (21:42 -0800)]
intel/compiler: Make MAX_VGRF_SIZE macro depend on devinfo and update it for Xe2.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Sat, 19 Feb 2022 06:28:58 +0000 (22:28 -0800)]
intel/vec4/ra: Define REG_CLASS_COUNT constant specifying the number of register classes.
Rework:
* Jordan: 16=>20 following
d33aff783d9 ("intel/fs: add support for
sparse accesses")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Sat, 19 Feb 2022 06:25:58 +0000 (22:25 -0800)]
intel/fs/ra: Define REG_CLASS_COUNT constant specifying the number of register classes.
Rework:
* Jordan: 16=>20 following
d33aff783d9 ("intel/fs: add support for
sparse accesses")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Eric Engestrom [Wed, 20 Sep 2023 17:25:12 +0000 (18:25 +0100)]
docs: add another 23.1.x
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25310>
Eric Engestrom [Wed, 20 Sep 2023 17:24:06 +0000 (18:24 +0100)]
docs: update calendar for 23.1.8
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25310>
Eric Engestrom [Wed, 20 Sep 2023 17:24:00 +0000 (18:24 +0100)]
docs: add sha256sum for 23.1.8
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25310>
Eric Engestrom [Wed, 20 Sep 2023 17:15:21 +0000 (18:15 +0100)]
docs: add release notes for 23.1.8
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25310>