Stephen Boyd [Thu, 19 Sep 2019 22:31:59 +0000 (15:31 -0700)]
Merge branches 'clk-bulk-fix', 'clk-at91' and 'clk-sprd' into clk-next
- Make clk_bulk_get_all() return an 'id' corresponding to clock-names
* clk-bulk-fix:
clk: Make clk_bulk_get_all() return a valid "id"
* clk-at91:
clk: at91: allow 24 Mhz clock as input for PLL
clk: at91: select parent if main oscillator or bypass is enabled
clk: at91: fix update bit maps on CFG_MOR write
* clk-sprd:
clk: sprd: add missing kfree
Stephen Boyd [Thu, 19 Sep 2019 22:31:46 +0000 (15:31 -0700)]
Merge branches 'clk-cdce-regulator', 'clk-bcm', 'clk-evict-parent-cache' and 'clk-actions' into clk-next
- Add regulator support to the
cdce925 clk driver
- Add support for Raspberry Pi 4 bcm2711 SoCs
- Evict parents from parent cache when they're unregistered
* clk-cdce-regulator:
clk: clk-
cdce925: Add regulator support
dt-bindings: clock:
cdce925: Add regulator documentation
* clk-bcm:
clk: bcm2835: Mark PLLD_PER as CRITICAL
clk: bcm2835: Add BCM2711_CLOCK_EMMC2 support
clk: bcm2835: Introduce SoC specific clock registration
dt-bindings: bcm2835-cprman: Add bcm2711 support
* clk-evict-parent-cache:
clk: Evict unregistered clks from parent caches
* clk-actions:
clk: actions: Fix factor clk struct member access
Stephen Boyd [Thu, 19 Sep 2019 22:31:41 +0000 (15:31 -0700)]
Merge branches 'clk-renesas', 'clk-rockchip', 'clk-const' and 'clk-simplify' into clk-next
* clk-renesas:
clk: renesas: cpg-mssr: Set GENPD_FLAG_ALWAYS_ON for clock domain
clk: renesas: r9a06g032: Set GENPD_FLAG_ALWAYS_ON for clock domain
clk: renesas: mstp: Set GENPD_FLAG_ALWAYS_ON for clock domain
dt-bindings: clk: emev2: Rename bindings documentation file
clk: renesas: rcar-usb2-clock-sel: Use devm_platform_ioremap_resource() helper
* clk-rockchip:
clk: rockchip: Add clock controller for the rk3308
clk: rockchip: Add dt-binding header for rk3308
dt-bindings: Add bindings for rk3308 clock controller
clk: rockchip: Fix -Wunused-const-variable in rv1108 clk driver
* clk-const:
clk: spear: Make structure i2s_sclk_masks constant
* clk-simplify:
clk/ti: Use kmemdup rather than duplicating its implementation
clk: fix devm_platform_ioremap_resource.cocci warnings
Stephen Boyd [Thu, 19 Sep 2019 22:31:27 +0000 (15:31 -0700)]
Merge branches 'clk-init-destroy', 'clk-doc', 'clk-imx' and 'clk-allwinner' into clk-next
- Set clk_init_data pointer inside clk_hw to NULL after registration
* clk-init-destroy:
clk: Overwrite clk_hw::init with NULL during clk_register()
clk: sunxi: Don't call clk_hw_get_name() on a hw that isn't registered
clk: ti: Don't reference clk_init_data after registration
clk: qcom: Remove error prints from DFS registration
rtc: sun6i: Don't reference clk_init_data after registration
clk: zx296718: Don't reference clk_init_data after registration
clk: milbeaut: Don't reference clk_init_data after registration
clk: socfpga: deindent code to proper indentation
phy: ti: am654-serdes: Don't reference clk_init_data after registration
clk: sprd: Don't reference clk_init_data after registration
clk: socfpga: Don't reference clk_init_data after registration
clk: sirf: Don't reference clk_init_data after registration
clk: qcom: Don't reference clk_init_data after registration
clk: meson: axg-audio: Don't reference clk_init_data after registration
clk: lochnagar: Don't reference clk_init_data after registration
clk: actions: Don't reference clk_init_data after registration
* clk-doc:
clk: remove extra ---help--- tags in Kconfig
clk: add include guard to clk-conf.h
clk: Document of_parse_clkspec() some more
clk: Remove extraneous 'for' word in comments
* clk-imx: (32 commits)
clk: imx: imx8mn: fix pll mux bit
clk: imx: imx8mm: fix pll mux bit
clk: imx: clk-pll14xx: unbypass PLL by default
clk: imx: pll14xx: avoid glitch when set rate
clk: imx: imx8mn: fix audio pll setting
clk: imx8mn: Add necessary frequency support for ARM PLL table
clk: imx8mn: Add missing rate_count assignment for each PLL structure
clk: imx8mn: fix int pll clk gate
clk: imx8mn: Add GIC clock
clk: imx8mn: Fix incorrect parents
clk: imx8mm: Fix incorrect parents
clk: imx8mq: Fix sys3 pll references
clk: imx8mq: Unregister clks when of_clk_add_provider failed
clk: imx8mm: Unregister clks when of_clk_add_provider failed
clk: imx8mq: Mark AHB clock as critical
clk: imx8mn: Keep uart clocks on for early console
clk: imx: Remove unused function statement
clk: imx7ulp: Make sure earlycon's clock is enabled
clk: imx8mm: Switch to platform driver
clk: imx: imx8mm: fix audio pll setting
...
* clk-allwinner:
clk: sunxi-ng: h6: Allow I2S to change parent rate
clk: sunxi-ng: v3s: add Allwinner V3 support
clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks
dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU
clk: sunxi-ng: v3s: add the missing PLL_DDR1
Stephen Boyd [Thu, 19 Sep 2019 22:30:59 +0000 (15:30 -0700)]
Merge branches 'clk-qcom', 'clk-mtk', 'clk-armada', 'clk-ingenic' and 'clk-meson' into clk-next
- Support qcom SM8150 RPMh clks
- Set floor ops for qcom sd clks
- Support qcom QCS404 WCSS clks
- Support for Mediatek MT6779 SoCs
- Add CPU clock support for Armada 7K/8K (specifically AP806 and AP807)
* clk-qcom:
clk: qcom: rcg: Return failure for RCG update
clk: qcom: fix QCS404 TuringCC regmap
clk: qcom: clk-rpmh: Add support for SM8150
dt-bindings: clock: Document SM8150 rpmh-clock compatible
clk: qcom: clk-rpmh: Convert to parent data scheme
dt-bindings: clock: Document the parent clocks
clk: qcom: gcc: Use floor ops for SDCC clocks
clk: qcom: gcc-qcs404: Use floor ops for sdcc clks
clk: qcom: gcc-sdm845: Use floor ops for sdcc clks
clk: qcom: define probe by index API as common API
clk: qcom: Add WCSS gcc clock control for QCS404
clk: qcom: msm8916: Don't build by default
clk: qcom: gcc: Add global clock controller driver for SM8150
dt-bindings: clock: Document gcc bindings for SM8150
clk: qcom: clk-alpha-pll: Add support for Trion PLLs
clk: qcom: clk-alpha-pll: Remove post_div_table checks
clk: qcom: clk-alpha-pll: Remove unnecessary cast
* clk-mtk:
clk: mediatek: Runtime PM support for MT8183 mcucfg clock provider
clk: mediatek: Register clock gate with device
clk: mediatek: add pericfg clocks for MT8183
dt-bindings: clock: mediatek: add pericfg for MT8183
clk: mediatek: Add MT6779 clock support
clk: mediatek: Add dt-bindings for MT6779 clocks
dt-bindings: mediatek: bindings for MT6779 clk
clk: reset: Modify reset-controller driver
* clk-armada:
clk: mvebu: ap80x: add AP807 clock support
clk: mvebu: ap806: Prepare the introduction of AP807 clock support
clk: mvebu: ap806: add AP-DCLK (hclk) to system controller driver
clk: mvebu: ap806: be more explicit on what SaR is
clk: mvebu: ap80x-cpu: add AP807 CPU clock support
clk: mvebu: ap806-cpu: prepare mapping of AP807 CPU clock
dt-bindings: ap806: Document AP807 clock compatible
dt-bindings: ap80x: Document AP807 CPU clock compatible
clk: mvebu: ap806: Fix clock name for the cluster
clk: mvebu: add CPU clock driver for Armada 7K/8K
clk: mvebu: add helper file for Armada AP and CP clocks
dt-bindings: ap806: add the cluster clock node in the syscon file
* clk-ingenic:
clk: ingenic: Use CLK_OF_DECLARE_DRIVER macro
clk: ingenic/jz4740: Fix "pll half" divider not read/written properly
* clk-meson: (23 commits)
clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocks
clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clock
clk: meson: g12a: add support for SM1 GP1 PLL
dt-bindings: clk: meson: add sm1 periph clock controller bindings
clk: meson: axg-audio: add g12a reset support
dt-bindings: clock: meson: add resets to the audio clock controller
clk: meson: g12a: expose CPUB clock ID for G12B
clk: meson: g12a: add notifiers to handle cpu clock change
clk: meson: add g12a cpu dynamic divider driver
clk: core: introduce clk_hw_set_parent()
clk: meson: remove clk input helper
clk: meson: remove ee input bypass clocks
clk: meson: clk-regmap: migrate to new parent description method
clk: meson: meson8b: migrate to the new parent description method
clk: meson: axg: migrate to the new parent description method
clk: meson: gxbb: migrate to the new parent description method
clk: meson: g12a: migrate to the new parent description method
clk: meson: remove ao input bypass clocks
clk: meson: axg-aoclk: migrate to the new parent description method
clk: meson: gxbb-aoclk: migrate to the new parent description method
...
Stephen Boyd [Thu, 19 Sep 2019 22:30:40 +0000 (15:30 -0700)]
Merge branches 'clk-aspeed', 'clk-unused', 'clk-of-node-put', 'clk-const-bulk-data' and 'clk-debugfs' into clk-next
- Add SDIO gate to aspeed driver
- Support aspeed AST2600 SoC
- Add missing of_node_put() calls in various clk drivers
- Drop NULL checks in clk debugfs
- Add min/max rates to clk debugfs
* clk-aspeed:
clk: Add support for AST2600 SoC
clk: aspeed: Move structures to header
clk: aspeed: Add SDIO gate
* clk-unused:
clk: st: clkgen-pll: remove unused variable 'st_pll3200c32_407_a0'
clk: st: clkgen-fsyn: remove unused variable 'st_quadfs_fs660c32_ops'
clk: composite: Drop unused clk.h include
clk: Si5341/Si5340: remove redundant assignment to n_den
clk: qoriq: Fix -Wunused-const-variable
* clk-of-node-put:
clk: ti: dm814x: Add of_node_put() to prevent memory leak
clk: st: clk-flexgen: Add of_node_put() in st_of_flexgen_setup()
clk: davinci: pll: Add of_node_put() in of_davinci_pll_init()
clk: versatile: Add of_node_put() in cm_osc_setup()
* clk-const-bulk-data:
clk: Constify struct clk_bulk_data * where possible
* clk-debugfs:
clk: Drop !clk checks in debugfs dumping
clk: Use seq_puts() in possible_parent_show()
clk: Assert prepare_lock in clk_core_get_boundaries
clk: Add clk_min/max_rate entries in debugfs
Stephen Boyd [Mon, 26 Aug 2019 23:47:29 +0000 (16:47 -0700)]
clk: Drop !clk checks in debugfs dumping
These recursive functions have checks for !clk being passed in, but the
callers are always looping through lists and therefore the pointers
can't be NULL. Drop the checks to simplify the code.
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190826234729.145593-1-sboyd@kernel.org
Peng Fan [Mon, 9 Sep 2019 03:39:50 +0000 (03:39 +0000)]
clk: imx: imx8mn: fix pll mux bit
pll BYPASS bit should be kept inside pll driver for glitchless freq
setting following spec. If exposing the bit, that means pll driver and
clk driver has two paths to touch this bit, which is wrong.
So use EXT_BYPASS bit here.
And drop uneeded set parent, because EXT_BYPASS default is 0.
Suggested-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lkml.kernel.org/r/1568043491-20680-5-git-send-email-peng.fan@nxp.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Peng Fan [Mon, 9 Sep 2019 03:39:44 +0000 (03:39 +0000)]
clk: imx: imx8mm: fix pll mux bit
pll BYPASS bit should be kept inside pll driver for glitchless freq
setting following spec. If exposing the bit, that means pll driver and
clk driver has two paths to touch this bit, which is wrong.
So use EXT_BYPASS bit here.
And drop uneeded set parent, because EXT_BYPASS default is 0.
Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm")
Suggested-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lkml.kernel.org/r/1568043491-20680-4-git-send-email-peng.fan@nxp.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Peng Fan [Mon, 9 Sep 2019 03:39:39 +0000 (03:39 +0000)]
clk: imx: clk-pll14xx: unbypass PLL by default
When registering the PLL, unbypass the PLL.
The PLL has two bypass control bit, BYPASS and EXT_BYPASS.
we will expose EXT_BYPASS to clk driver for mux usage, and keep
BYPASS inside pll14xx usage. The PLL has a restriction that
when M/P change, need to RESET/BYPASS pll to avoid glitch, so
we could not expose BYPASS.
To make it easy for clk driver usage, unbypass PLL which does
not hurt current function.
Fixes: 8646d4dcc7fb ("clk: imx: Add PLLs driver for imx8mm soc")
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lkml.kernel.org/r/1568043491-20680-3-git-send-email-peng.fan@nxp.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Peng Fan [Mon, 9 Sep 2019 03:39:34 +0000 (03:39 +0000)]
clk: imx: pll14xx: avoid glitch when set rate
According to PLL1443XA and PLL1416X spec,
"When BYPASS is 0 and RESETB is changed from 0 to 1, FOUT starts to
output unstable clock until lock time passes. PLL1416X/PLL1443XA may
generate a glitch at FOUT."
So set BYPASS when RESETB is changed from 0 to 1 to avoid glitch.
In the end of set rate, BYPASS will be cleared.
When prepare clock, also need to take care to avoid glitch. So
we also follow Spec to set BYPASS before RESETB changed from 0 to 1.
And add a check if the RESETB is already 0, directly return 0;
Fixes: 8646d4dcc7fb ("clk: imx: Add PLLs driver for imx8mm soc")
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lkml.kernel.org/r/1568043491-20680-2-git-send-email-peng.fan@nxp.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Ben Peled [Mon, 5 Aug 2019 10:03:10 +0000 (12:03 +0200)]
clk: mvebu: ap80x: add AP807 clock support
Add driver support for AP807 clock.
Signed-off-by: Ben Peled <bpeled@marvell.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20190805100310.29048-9-miquel.raynal@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Ben Peled [Mon, 5 Aug 2019 10:03:09 +0000 (12:03 +0200)]
clk: mvebu: ap806: Prepare the introduction of AP807 clock support
Factor out the code that is only useful to AP806 so it will be easier
to support AP807. No functional changes.
Signed-off-by: Ben Peled <bpeled@marvell.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20190805100310.29048-8-miquel.raynal@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Omri Itach [Mon, 5 Aug 2019 10:03:08 +0000 (12:03 +0200)]
clk: mvebu: ap806: add AP-DCLK (hclk) to system controller driver
Add dynamic AP-DCLK clock (hclk) to system controller driver. AP-DCLK
is half the rate of DDR clock, so its derrived from Sample At Reset
configuration. The clock frequency is required for AP806 AXI monitor
profiling feature.
Signed-off-by: Omri Itach <omrii@marvell.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20190805100310.29048-7-miquel.raynal@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Miquel Raynal [Mon, 5 Aug 2019 10:03:07 +0000 (12:03 +0200)]
clk: mvebu: ap806: be more explicit on what SaR is
"SaR" means Sample at Reset. DIP switches can be changed on the board,
their states at reset time is available through a register read.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20190805100310.29048-6-miquel.raynal@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Ben Peled [Mon, 5 Aug 2019 10:03:06 +0000 (12:03 +0200)]
clk: mvebu: ap80x-cpu: add AP807 CPU clock support
Enhance the ap-cpu-clk driver to support both AP806 and AP807 CPU
clocks.
Signed-off-by: Ben Peled <bpeled@marvell.com>
[<miquel.raynal@bootlin.com>: use device data instead of conditions on
the compatible]
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20190805100310.29048-5-miquel.raynal@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Christine Gharzuzi [Mon, 5 Aug 2019 10:03:05 +0000 (12:03 +0200)]
clk: mvebu: ap806-cpu: prepare mapping of AP807 CPU clock
This patch allows same flow to be executed on chips with different
register mappings like AP806 and, in the future, AP807.
Note: this patch has no functional effect, and only prepares the
driver for additional chips to be supported by retrieving the right
device data depenging on the compatible property.
Signed-off-by: Christine Gharzuzi <chrisg@marvell.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20190805100310.29048-4-miquel.raynal@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Miquel Raynal [Mon, 5 Aug 2019 10:03:04 +0000 (12:03 +0200)]
dt-bindings: ap806: Document AP807 clock compatible
Add AP807 clock compatible to the bindings.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20190805100310.29048-3-miquel.raynal@bootlin.com
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Miquel Raynal [Mon, 5 Aug 2019 10:03:03 +0000 (12:03 +0200)]
dt-bindings: ap80x: Document AP807 CPU clock compatible
Add AP807 CPU clock compatible to the bindings.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20190805100310.29048-2-miquel.raynal@bootlin.com
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Chunyan Zhang [Thu, 5 Sep 2019 10:30:09 +0000 (18:30 +0800)]
clk: sprd: add missing kfree
The number of config registers for different pll clocks probably are not
same, so we have to use malloc, and should free the memory before return.
Fixes: 3e37b005580b ("clk: sprd: add adjustable pll support")
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Signed-off-by: Chunyan Zhang <zhang.lyra@gmail.com>
Link: https://lkml.kernel.org/r/20190905103009.27166-1-zhang.lyra@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Eugen Hristev [Wed, 11 Sep 2019 06:39:20 +0000 (06:39 +0000)]
clk: at91: allow 24 Mhz clock as input for PLL
The PLL input range needs to be able to allow 24 Mhz crystal as input
Update the range accordingly in plla characteristics struct
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Link: https://lkml.kernel.org/r/1568183622-7858-1-git-send-email-eugen.hristev@microchip.com
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Fixes: c561e41ce4d2 ("clk: at91: add sama5d2 PMC driver")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Bjorn Andersson [Fri, 13 Sep 2019 02:40:29 +0000 (19:40 -0700)]
clk: Make clk_bulk_get_all() return a valid "id"
The adreno driver expects the "id" field of the returned clk_bulk_data
to be filled in with strings from the clock-names property.
But due to the use of kmalloc_array() in of_clk_bulk_get_all() it
receives a list of bogus pointers instead.
Zero-initialize the "id" field and attempt to populate with strings from
the clock-names property to resolve both these issues.
Fixes: 616e45df7c4a ("clk: add new APIs to operate on all available clocks")
Fixes: 8e3e791d20d2 ("drm/msm: Use generic bulk clock function")
Cc: Dong Aisheng <aisheng.dong@nxp.com>
Cc: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lkml.kernel.org/r/20190913024029.2640-1-bjorn.andersson@linaro.org
Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Manivannan Sadhasivam [Mon, 16 Sep 2019 15:45:40 +0000 (21:15 +0530)]
clk: actions: Fix factor clk struct member access
Since the helper "owl_factor_helper_round_rate" is shared between factor
and composite clocks, using the factor clk specific helper function
like "hw_to_owl_factor" to access its members will create issues when
called from composite clk specific code. Hence, pass the "factor_hw"
struct pointer directly instead of fetching it using factor clk specific
helpers.
This issue has been observed when a composite clock like "sd0_clk" tried
to call "owl_factor_helper_round_rate" resulting in pointer dereferencing
error.
While we are at it, let's rename the "clk_val_best" function to
"owl_clk_val_best" since this is an owl SoCs specific helper.
Fixes: 4bb78fc9744a ("clk: actions: Add factor clock support")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190916154546.24982-2-manivannan.sadhasivam@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Taniya Das [Wed, 8 May 2019 18:24:53 +0000 (23:54 +0530)]
clk: qcom: rcg: Return failure for RCG update
In case of update config failure, return -EBUSY, so that consumers could
handle the failure gracefully.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lkml.kernel.org/r/1557339895-21952-2-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Lubomir Rintel [Thu, 22 Aug 2019 09:31:26 +0000 (11:31 +0200)]
clk: remove extra ---help--- tags in Kconfig
Sometimes an extraneous "---help---" follows "help". That is probably a
copy&paste error stemming from their inconsistent use. Remove those.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20190822093126.594013-1-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Masahiro Yamada [Tue, 20 Aug 2019 03:05:36 +0000 (12:05 +0900)]
clk: add include guard to clk-conf.h
Add a header include guard just in case.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Link: https://lkml.kernel.org/r/20190820030536.1181-1-yamada.masahiro@socionext.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Stephen Boyd [Wed, 28 Aug 2019 18:19:59 +0000 (11:19 -0700)]
clk: Evict unregistered clks from parent caches
We leave a dangling pointer in each clk_core::parents array that has an
unregistered clk as a potential parent when that clk_core pointer is
freed by clk{_hw}_unregister(). It is impossible for the true parent of
a clk to be set with clk_set_parent() once the dangling pointer is left
in the cache because we compare parent pointers in
clk_fetch_parent_index() instead of checking for a matching clk name or
clk_hw pointer.
Before commit
ede77858473a ("clk: Remove global clk traversal on fetch
parent index"), we would check clk_hw pointers, which has a higher
chance of being the same between registration and unregistration, but it
can still be allocated and freed by the clk provider. In fact, this has
been a long standing problem since commit
da0f0b2c3ad2 ("clk: Correct
lookup logic in clk_fetch_parent_index()") where we stopped trying to
compare clk names and skipped over entries in the cache that weren't
NULL.
There are good (performance) reasons to not do the global tree lookup in
cases where the cache holds dangling pointers to parents that have been
unregistered. Let's take the performance hit on the uncommon
registration path instead. Loop through all the clk_core::parents arrays
when a clk is unregistered and set the entry to NULL when the parent
cache entry and clk being unregistered are the same pointer. This will
fix this problem and avoid the overhead for the "normal" case.
Based on a patch by Bjorn Andersson.
Fixes: da0f0b2c3ad2 ("clk: Correct lookup logic in clk_fetch_parent_index()")
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190828181959.204401-1-sboyd@kernel.org
Weiyi Lu [Mon, 2 Sep 2019 09:00:58 +0000 (17:00 +0800)]
clk: mediatek: Runtime PM support for MT8183 mcucfg clock provider
Enable the runtime PM support and forward the struct device pointer for
registration of MT8183 mcucfg clocks.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Link: https://lkml.kernel.org/r/1567414859-3244-3-git-send-email-weiyi.lu@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Weiyi Lu [Mon, 2 Sep 2019 09:00:57 +0000 (17:00 +0800)]
clk: mediatek: Register clock gate with device
Allow those clocks under a power domain to do the runtime pm operation
by forwarding the struct device pointer from clock provider.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Link: https://lkml.kernel.org/r/1567414859-3244-2-git-send-email-weiyi.lu@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Chunfeng Yun [Wed, 28 Aug 2019 08:22:13 +0000 (16:22 +0800)]
clk: mediatek: add pericfg clocks for MT8183
Add pericfg clocks for MT8183, it's used when support USB
remote wakeup
Cc: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Link: https://lkml.kernel.org/r/1566980533-28282-2-git-send-email-chunfeng.yun@mediatek.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Chunfeng Yun [Wed, 28 Aug 2019 08:22:12 +0000 (16:22 +0800)]
dt-bindings: clock: mediatek: add pericfg for MT8183
This patch adds binding of pericfg for MT8183.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Link: https://lkml.kernel.org/r/1566980533-28282-1-git-send-email-chunfeng.yun@mediatek.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Stefan Wahren [Sun, 18 Aug 2019 16:23:44 +0000 (18:23 +0200)]
clk: bcm2835: Mark PLLD_PER as CRITICAL
The VPU firmware assume that the PLLD_PER isn't modified by the ARM core.
Otherwise this could cause firmware lookups. So mark the clock as critical
to avoid this.
Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
Stefan Wahren [Sun, 18 Aug 2019 16:23:43 +0000 (18:23 +0200)]
clk: bcm2835: Add BCM2711_CLOCK_EMMC2 support
The new BCM2711 supports an additional clock for the emmc2 block.
So add a new compatible and register this clock only for BCM2711.
Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
Stefan Wahren [Sun, 18 Aug 2019 16:23:42 +0000 (18:23 +0200)]
clk: bcm2835: Introduce SoC specific clock registration
In order to support SoC specific clocks (e.g. emmc2 for BCM2711), we
extend the description with a SoC support flag. This approach avoids long
and mostly redundant lists of clock IDs. Since PLLH is specific to
BCM2835, we register only rest of the clocks as common to all SoC.
Suggested-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
Stefan Wahren [Sun, 18 Aug 2019 16:23:41 +0000 (18:23 +0200)]
dt-bindings: bcm2835-cprman: Add bcm2711 support
The new BCM2711 supports an additional clock for the emmc2 block.
So we need an additional compatible.
Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
Eugen Hristev [Mon, 9 Sep 2019 15:30:34 +0000 (15:30 +0000)]
clk: at91: select parent if main oscillator or bypass is enabled
Selecting the right parent for the main clock is done using only
main oscillator enabled bit.
In case we have this oscillator bypassed by an external signal (no driving
on the XOUT line), we still use external clock, but with BYPASS bit set.
So, in this case we must select the same parent as before.
Create a macro that will select the right parent considering both bits from
the MOR register.
Use this macro when looking for the right parent.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Link: https://lkml.kernel.org/r/1568042692-11784-2-git-send-email-eugen.hristev@microchip.com
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Eugen Hristev [Mon, 9 Sep 2019 15:30:31 +0000 (15:30 +0000)]
clk: at91: fix update bit maps on CFG_MOR write
The regmap update bits call was not selecting the proper mask, considering
the bits which was updating.
Update the mask from call to also include OSCBYPASS.
Removed MOSCEN which was not updated.
Fixes: 1bdf02326b71 ("clk: at91: make use of syscon/regmap internally")
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Link: https://lkml.kernel.org/r/1568042692-11784-1-git-send-email-eugen.hristev@microchip.com
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
mtk01761 [Mon, 19 Aug 2019 09:21:41 +0000 (17:21 +0800)]
clk: mediatek: Add MT6779 clock support
Add MT6779 clock support, include topckgen, apmixedsys,
infracfg, and subsystem clocks.
Signed-off-by: mtk01761 <wendell.lin@mediatek.com>
Link: https://lkml.kernel.org/r/1566206502-4347-11-git-send-email-mars.cheng@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
mtk01761 [Mon, 19 Aug 2019 09:21:40 +0000 (17:21 +0800)]
clk: mediatek: Add dt-bindings for MT6779 clocks
Add MT6779 clock dt-bindings, include topckgen, apmixedsys,
infracfg, and subsystem clocks.
Signed-off-by: mtk01761 <wendell.lin@mediatek.com>
Link: https://lkml.kernel.org/r/1566206502-4347-10-git-send-email-mars.cheng@mediatek.com
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
mtk01761 [Mon, 19 Aug 2019 09:21:39 +0000 (17:21 +0800)]
dt-bindings: mediatek: bindings for MT6779 clk
This patch adds the binding documentation for
apmixedsys, audiosys, camsys, imgsys, ipesys,
infracfg, mfgcfg, mmsys, topckgen, vdecsys,
and vencsys for Mediatek MT6779.
Signed-off-by: mtk01761 <wendell.lin@mediatek.com>
Link: https://lkml.kernel.org/r/1566206502-4347-9-git-send-email-mars.cheng@mediatek.com
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Jorge Ramirez-Ortiz [Mon, 9 Sep 2019 08:54:30 +0000 (10:54 +0200)]
clk: qcom: fix QCS404 TuringCC regmap
The max register is 0x23004 as per the manual (the current
max_register that this commit is fixing is actually out of bounds).
Fixes: 892df0191b29 ("clk: qcom: Add QCS404 TuringCC")
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Link: https://lkml.kernel.org/r/20190909085430.8700-1-jorge.ramirez-ortiz@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Vinod Koul [Mon, 26 Aug 2019 17:31:20 +0000 (23:01 +0530)]
clk: qcom: clk-rpmh: Add support for SM8150
Add support for rpmh clocks found in SM8150
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lkml.kernel.org/r/20190826173120.2971-5-vkoul@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Vinod Koul [Mon, 26 Aug 2019 17:31:19 +0000 (23:01 +0530)]
dt-bindings: clock: Document SM8150 rpmh-clock compatible
Document the SM8150 rpmh-clock compatible for rpmh clock controller
found on SM8150 platforms.
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lkml.kernel.org/r/20190826173120.2971-4-vkoul@kernel.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Vinod Koul [Mon, 26 Aug 2019 17:31:18 +0000 (23:01 +0530)]
clk: qcom: clk-rpmh: Convert to parent data scheme
Convert the rpmh clock driver to use the new parent data scheme by
specifying the parent data for board clock.
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lkml.kernel.org/r/20190826173120.2971-3-vkoul@kernel.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Vinod Koul [Mon, 26 Aug 2019 17:31:17 +0000 (23:01 +0530)]
dt-bindings: clock: Document the parent clocks
With clock parent data scheme we must specify the parent clocks for the
rpmhcc nodes. So describe the parent clock for rpmhcc in the bindings.
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lkml.kernel.org/r/20190826173120.2971-2-vkoul@kernel.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Taniya Das [Mon, 9 Sep 2019 07:44:10 +0000 (13:14 +0530)]
clk: qcom: gcc: Use floor ops for SDCC clocks
Update global clock controller SDCC2/4 clocks to use the floor rcg ops,
so as to use the rounded down clock rates for these clocks.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lkml.kernel.org/r/20190909074410.18977-1-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Vinod Koul [Fri, 6 Sep 2019 04:56:59 +0000 (10:26 +0530)]
clk: qcom: gcc-qcs404: Use floor ops for sdcc clks
Update the gcc qcs404 clock driver to use floor ops for sdcc clocks. As
disuccsed in [1] it is good idea to use floor ops for sdcc clocks as we
dont want the clock rates to do round up.
[1]: https://lore.kernel.org/linux-arm-msm/
20190830195142.103564-1-swboyd@chromium.org/
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lkml.kernel.org/r/20190906045659.20621-1-vkoul@kernel.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Stephen Boyd [Fri, 30 Aug 2019 19:51:42 +0000 (12:51 -0700)]
clk: qcom: gcc-sdm845: Use floor ops for sdcc clks
Some MMC cards fail to enumerate properly when inserted into an MMC slot
on sdm845 devices. This is because the clk ops for qcom clks round the
frequency up to the nearest rate instead of down to the nearest rate.
For example, the MMC driver requests a frequency of 52MHz from
clk_set_rate() but the qcom implementation for these clks rounds 52MHz
up to the next supported frequency of 100MHz. The MMC driver could be
modified to request clk rate ranges but for now we can fix this in the
clk driver by changing the rounding policy for this clk to be round down
instead of round up.
Fixes: 06391eddb60a ("clk: qcom: Add Global Clock controller (GCC) driver for SDM845")
Reported-by: Douglas Anderson <dianders@chromium.org>
Cc: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lkml.kernel.org/r/20190830195142.103564-1-swboyd@chromium.org
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Joel Stanley [Sun, 25 Aug 2019 14:18:48 +0000 (23:48 +0930)]
clk: Add support for AST2600 SoC
The ast2600 is a new BMC SoC from ASPEED. It contains many more clocks
than the previous iterations, so support is broken out into it's own
driver.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://lkml.kernel.org/r/20190825141848.17346-3-joel@jms.id.au
[sboyd@kernel.org: Mark arrays const]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Joel Stanley [Sun, 25 Aug 2019 14:18:47 +0000 (23:48 +0930)]
clk: aspeed: Move structures to header
They will be reused by the ast2600 driver.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://lkml.kernel.org/r/20190825141848.17346-2-joel@jms.id.au
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Fuqian Huang [Wed, 3 Jul 2019 16:27:00 +0000 (00:27 +0800)]
clk/ti: Use kmemdup rather than duplicating its implementation
kmemdup is introduced to duplicate a region of memory in a neat way.
Rather than kmalloc/kzalloc + memcpy, which the programmer needs to
write the size twice (sometimes lead to mistakes), kmemdup improves
readability, leads to smaller code and also reduce the chances of mistakes.
Suggestion to use kmemdup rather than using kmalloc/kzalloc + memcpy.
Signed-off-by: Fuqian Huang <huangfq.daxian@gmail.com>
Link: https://lkml.kernel.org/r/20190703162700.32091-1-huangfq.daxian@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Phil Reid [Fri, 28 Jun 2019 03:19:10 +0000 (11:19 +0800)]
clk: clk-
cdce925: Add regulator support
The
cdce925 power supplies could be controllable on some platforms.
Enable them before communicating with the
cdce925.
Signed-off-by: Phil Reid <preid@electromag.com.au>
Link: https://lkml.kernel.org/r/1561691950-42154-3-git-send-email-preid@electromag.com.au
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Phil Reid [Fri, 28 Jun 2019 03:19:09 +0000 (11:19 +0800)]
dt-bindings: clock:
cdce925: Add regulator documentation
The
cdce925 has two separate supply pins. Document the bindings
for them.
Signed-off-by: Phil Reid <preid@electromag.com.au>
Link: https://lkml.kernel.org/r/1561691950-42154-2-git-send-email-preid@electromag.com.au
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
kbuild test robot [Thu, 8 Aug 2019 16:10:53 +0000 (18:10 +0200)]
clk: fix devm_platform_ioremap_resource.cocci warnings
drivers/clk/bcm/clk-bcm63xx-gate.c:174:1-9: WARNING: Use devm_platform_ioremap_resource for hw -> regs
Use devm_platform_ioremap_resource helper which wraps
platform_get_resource() and devm_ioremap_resource() together.
Generated by: scripts/coccinelle/api/devm_platform_ioremap_resource.cocci
Fixes: 1c099779c1e2 ("clk: add BCM63XX gated clock controller driver")
CC: Jonas Gorski <jonas.gorski@gmail.com>
Signed-off-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Julia Lawall <julia.lawall@lip6.fr>
Link: https://lkml.kernel.org/r/alpine.DEB.2.21.1908081809160.2995@hadrien
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Nishka Dasgupta [Tue, 13 Aug 2019 08:57:14 +0000 (14:27 +0530)]
clk: spear: Make structure i2s_sclk_masks constant
Static structure i2s_sclk_masks, having type aux_clk_masks, is only used
when it is passed as the sixth argument to function clk_register_aux().
However, clk_register_aux() is defined with its sixth argument as const.
Hence i2s_sclk_masks is not modified by clk_register_aux, which is also
the only usage of the former. Therefore make i2s_sclk_masks constant as
it is never modified.
Issue found with Coccinelle.
Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com>
Link: https://lkml.kernel.org/r/20190813085714.8079-1-nishkadg.linux@gmail.com
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
YueHaibing [Fri, 16 Aug 2019 13:55:23 +0000 (21:55 +0800)]
clk: st: clkgen-pll: remove unused variable 'st_pll3200c32_407_a0'
drivers/clk/st/clkgen-pll.c:64:37: warning:
st_pll3200c32_407_a0 defined but not used [-Wunused-const-variable=]
It is never used, so can be removed.
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lkml.kernel.org/r/20190816135523.73520-1-yuehaibing@huawei.com
Acked-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
YueHaibing [Fri, 16 Aug 2019 13:53:41 +0000 (21:53 +0800)]
clk: st: clkgen-fsyn: remove unused variable 'st_quadfs_fs660c32_ops'
drivers/clk/st/clkgen-fsyn.c:70:29: warning:
st_quadfs_fs660c32_ops defined but not used [-Wunused-const-variable=]
It is never used, so can be removed.
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lkml.kernel.org/r/20190816135341.52248-1-yuehaibing@huawei.com
Acked-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Stephen Boyd [Mon, 26 Aug 2019 21:20:42 +0000 (14:20 -0700)]
clk: Document of_parse_clkspec() some more
The return value of of_parse_clkspec() is peculiar. If the function is
called with a NULL argument for 'name' it will return -ENOENT, but if
it's called with a non-NULL argument for 'name' it will return -EINVAL.
This peculiarity is documented by commit
5c56dfe63b6e ("clk: Add comment
about __of_clk_get_by_name() error values").
Let's further document this function so that it's clear what the return
value is and how to use the arguments to parse clk specifiers.
Cc: Phil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190826212042.48642-1-sboyd@kernel.org
Reviewed-by: Phil Edworthy <phil.edworthy@renesas.com>
Stephen Boyd [Thu, 5 Sep 2019 18:40:11 +0000 (11:40 -0700)]
Merge tag 'v5.4-rockchip-clk1' of git://git./linux/kernel/git/mmind/linux-rockchip into clk-rockchip
Pull Rockchip clk driver updates from Heiko Stuebner:
- Removal of an unused variable vom rv1108
- Addition of clock driver for rk3308 arm64 soc
* tag 'v5.4-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: Add clock controller for the rk3308
clk: rockchip: Add dt-binding header for rk3308
dt-bindings: Add bindings for rk3308 clock controller
clk: rockchip: Fix -Wunused-const-variable in rv1108 clk driver
Finley Xiao [Tue, 3 Sep 2019 11:59:47 +0000 (19:59 +0800)]
clk: rockchip: Add clock controller for the rk3308
Add the clock tree definition for the new RK3308 SoC.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Finley Xiao [Tue, 3 Sep 2019 11:59:46 +0000 (19:59 +0800)]
clk: rockchip: Add dt-binding header for rk3308
Add the dt-bindings header for the rk3308, that gets shared between
the clock controller and the clock references in the dts.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Finley Xiao [Tue, 3 Sep 2019 11:59:45 +0000 (19:59 +0800)]
dt-bindings: Add bindings for rk3308 clock controller
Add devicetree bindings for Rockchip cru which found on
Rockchip SoCs.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Stephen Boyd [Wed, 4 Sep 2019 18:21:19 +0000 (11:21 -0700)]
Merge tag 'clk-renesas-for-v5.4-tag1' of git://git./linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Fix "always-on" Clock Domains on R-Car M1A, RZ/A1, RZ/A2, and RZ/N1
* tag 'clk-renesas-for-v5.4-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: cpg-mssr: Set GENPD_FLAG_ALWAYS_ON for clock domain
clk: renesas: r9a06g032: Set GENPD_FLAG_ALWAYS_ON for clock domain
clk: renesas: mstp: Set GENPD_FLAG_ALWAYS_ON for clock domain
dt-bindings: clk: emev2: Rename bindings documentation file
clk: renesas: rcar-usb2-clock-sel: Use devm_platform_ioremap_resource() helper
Stephen Boyd [Wed, 4 Sep 2019 18:14:51 +0000 (11:14 -0700)]
Merge tag 'sunxi-clk-for-5.4-1' of https://git./linux/kernel/git/sunxi/linux into clk-allwinner
Pull Allwinner clock changes from Maxime Ripard:
A few patches to enable the V3 SoC and fix the i2s clock for the H6.
* tag 'sunxi-clk-for-5.4-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: h6: Allow I2S to change parent rate
clk: sunxi-ng: v3s: add Allwinner V3 support
clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks
dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU
clk: sunxi-ng: v3s: add the missing PLL_DDR1
Stephen Boyd [Wed, 4 Sep 2019 18:00:15 +0000 (11:00 -0700)]
Merge tag 'clk-imx-5.4' of git://git./linux/kernel/git/shawnguo/linux into clk-imx
Pull i.MX clock changes from Shawn Guo:
- Add clock driver for i.MX8MN SoC
- Switch i.MX8MM clock driver to platform driver
- Add API for clk unregister when driver probe fail
- Add Hifi4 DSP related clocks for i.MX8QXP SoC
- Fix Audio PLL setting and parent clock for USB
- Misc i.MX8 clock driver improvements and corrections
* tag 'clk-imx-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (28 commits)
clk: imx: imx8mn: fix audio pll setting
clk: imx8mn: Add necessary frequency support for ARM PLL table
clk: imx8mn: Add missing rate_count assignment for each PLL structure
clk: imx8mn: fix int pll clk gate
clk: imx8mn: Add GIC clock
clk: imx8mn: Fix incorrect parents
clk: imx8mm: Fix incorrect parents
clk: imx8mq: Fix sys3 pll references
clk: imx8mq: Unregister clks when of_clk_add_provider failed
clk: imx8mm: Unregister clks when of_clk_add_provider failed
clk: imx8mq: Mark AHB clock as critical
clk: imx8mn: Keep uart clocks on for early console
clk: imx: Remove unused function statement
clk: imx7ulp: Make sure earlycon's clock is enabled
clk: imx8mm: Switch to platform driver
clk: imx: imx8mm: fix audio pll setting
clk: imx8mm: GPT1 clock mux option #5 should be sys_pll1_80m
clk: imx8mm: Fix typo of pwm3 clock's mux option #4
clk: imx: Remove unused clk based API
clk: imx8mq: set correct parent for usb ctrl clocks
...
Stephen Boyd [Wed, 4 Sep 2019 17:53:34 +0000 (10:53 -0700)]
Merge tag 'clk-meson-v5.4-2' of https://github.com/BayLibre/clk-meson into clk-meson
Pull second set of Amlogic clk driver updates from Jerome Brunet:
- Add g12a reset support to the axg audio clock controller
- Add sm1 support to the g12a clock controller
* tag 'clk-meson-v5.4-2' of https://github.com/BayLibre/clk-meson:
clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocks
clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clock
clk: meson: g12a: add support for SM1 GP1 PLL
dt-bindings: clk: meson: add sm1 periph clock controller bindings
clk: meson: axg-audio: add g12a reset support
dt-bindings: clock: meson: add resets to the audio clock controller
Neil Armstrong [Mon, 26 Aug 2019 07:25:38 +0000 (09:25 +0200)]
clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocks
The Amlogic SM1 can set a dedicated clock frequency for each CPU core by
having a dedicate tree for each core similar to the CPU0 tree.
Like the DSU tree, a supplementaty mux has been added to use the CPU0
frequency instead.
But since the cluster only has a single power rail and shares a single PLL,
it's not worth adding 3 unsused clock tree, so we add only the mux to
select the CPU0 clock frequency for each CPU1, CPU2 and CPU3 cores.
They are set read-only because the early boot stages sets them to select
the CPU0 input clock.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Neil Armstrong [Mon, 26 Aug 2019 07:25:37 +0000 (09:25 +0200)]
clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clock
The Amlogic SM1 DynamIQ Shared Unit has a dedicated clock tree similar to
the CPU clock tree with a supplementaty mux to select the CPU0 clock
instead.
Leave this as read-only since it's set up by the early boot stages.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Neil Armstrong [Mon, 26 Aug 2019 07:25:36 +0000 (09:25 +0200)]
clk: meson: g12a: add support for SM1 GP1 PLL
Add the new GP1 PLL for the Amlogic SM1 SoC, used to feed the new
DynamIQ Shared Unit of the ARM Cores Complex.
This also adds a dedicated set of clock and compatible for SM1.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Jerome Brunet [Mon, 26 Aug 2019 09:01:20 +0000 (11:01 +0200)]
Merge branch 'v5.4/dt' into v5.4/drivers
Neil Armstrong [Mon, 26 Aug 2019 07:25:35 +0000 (09:25 +0200)]
dt-bindings: clk: meson: add sm1 periph clock controller bindings
Update the documentation to support clock driver for the Amlogic SM1 SoC
and expose the GP1, DSU and the CPU 1, 2 & 3 clocks.
SM1 clock tree is very close, the main differences are :
- each CPU core can achieve a different frequency, albeit a common PLL
- a similar tree as the clock tree has been added for the DynamIQ Shared
Unit
- has a new GP1 PLL used for the DynamIQ Shared Unit
- SM1 has additional clocks like for CSI, NanoQ an other components
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Peng Fan [Tue, 20 Aug 2019 01:55:07 +0000 (01:55 +0000)]
clk: imx: imx8mn: fix audio pll setting
The AUDIO PLL max support 650M, so the original clk settings violate
spec. This patch makes the output
786432000 ->
393216000,
and
722534400 ->
361267200 to aligned with NXP vendor kernel without any
impact on audio functionality and go within 650MHz PLL limit.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Geert Uytterhoeven [Fri, 9 Aug 2019 13:44:51 +0000 (15:44 +0200)]
clk: renesas: cpg-mssr: Set GENPD_FLAG_ALWAYS_ON for clock domain
The CPG/MSSR Clock Domain driver does not implement the
generic_pm_domain.power_{on,off}() callbacks, as the domain itself
cannot be powered down. Hence the domain should be marked as always-on
by setting the GENPD_FLAG_ALWAYS_ON flag, to prevent the core PM Domain
code from considering it for power-off, and doing unnessary processing.
Note that this only affects RZ/A2 SoCs. On R-Car Gen2 and Gen3 SoCs,
the R-Car SYSC driver handles Clock Domain creation, and offloads only
device attachment/detachment to the CPG/MSSR driver.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Geert Uytterhoeven [Fri, 9 Aug 2019 13:43:07 +0000 (15:43 +0200)]
clk: renesas: r9a06g032: Set GENPD_FLAG_ALWAYS_ON for clock domain
The RZ/N1 Clock Domain driver does not implement the
generic_pm_domain.power_{on,off}() callbacks, as the domain itself
cannot be powered down. Hence the domain should be marked as always-on
by setting the GENPD_FLAG_ALWAYS_ON flag, to prevent the core PM Domain
code from considering it for power-off, and doing unnessary processing.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Geert Uytterhoeven [Fri, 9 Aug 2019 13:38:34 +0000 (15:38 +0200)]
clk: renesas: mstp: Set GENPD_FLAG_ALWAYS_ON for clock domain
The CPG/MSTP Clock Domain driver does not implement the
generic_pm_domain.power_{on,off}() callbacks, as the domain itself
cannot be powered down. Hence the domain should be marked as always-on
by setting the GENPD_FLAG_ALWAYS_ON flag, to prevent the core PM Domain
code from considering it for power-off, and doing unnessary processing.
This also gets rid of a boot warning when the Clock Domain contains an
IRQ-safe device, e.g. on RZ/A1:
sh_mtu2
fcff0000.timer: PM domain cpg_clocks will not be powered off
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Simon Horman [Wed, 21 Aug 2019 09:15:16 +0000 (11:15 +0200)]
dt-bindings: clk: emev2: Rename bindings documentation file
Rename the device tree clock bindings for Renesas EMMA Mobile EV2
from emev2-clock.txt to renesas,emev2-smu.txt.
This is part of an ongoing effort to name bindings documentation files for
Renesas IP blocks consistently, in line with the compat strings they
document.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Jernej Skrabec [Wed, 14 Aug 2019 06:08:48 +0000 (08:08 +0200)]
clk: sunxi-ng: h6: Allow I2S to change parent rate
I2S doesn't work if parent rate couldn't be change. Difference between
wanted and actual rate is too big.
Fix this by adding CLK_SET_RATE_PARENT flag to I2S clocks.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Jerome Brunet [Mon, 12 Aug 2019 12:32:53 +0000 (14:32 +0200)]
clk: meson: axg-audio: add g12a reset support
On the g12a, the register space dedicated to the audio clock also
provides some resets. Let the clock controller register a reset
provider as well for this SoC family.
the axg SoC family does not appear to provide this feature.
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Jerome Brunet [Tue, 20 Aug 2019 09:50:54 +0000 (11:50 +0200)]
Merge branch 'v5.4/dt' into v5.4/drivers
Jerome Brunet [Mon, 12 Aug 2019 12:32:52 +0000 (14:32 +0200)]
dt-bindings: clock: meson: add resets to the audio clock controller
Add the documentation and bindings for the resets provided by the g12a
audio clock controller
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Anson Huang [Sun, 18 Aug 2019 06:32:24 +0000 (02:32 -0400)]
clk: imx8mn: Add necessary frequency support for ARM PLL table
i.MX8MN supports CPU running at 1.5GHz/1.4GHz/1.2GHz, add missing
frequency for ARM PLL table.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Anson Huang [Sun, 18 Aug 2019 06:32:23 +0000 (02:32 -0400)]
clk: imx8mn: Add missing rate_count assignment for each PLL structure
Add .rate_count assignment which is necessary for searching required
PLL rate from the each PLL table.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Peng Fan [Wed, 14 Aug 2019 01:53:12 +0000 (09:53 +0800)]
clk: imx8mn: fix int pll clk gate
To Frac pll, the gate shift is 13, however to Int PLL the gate shift
is 11.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Leonard Crestez [Tue, 13 Aug 2019 17:05:31 +0000 (20:05 +0300)]
clk: imx8mn: Add GIC clock
This is enabled by default but if it's not explicitly defined and marked
as critical then its parent might get turned off.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Leonard Crestez [Tue, 13 Aug 2019 17:05:30 +0000 (20:05 +0300)]
clk: imx8mn: Fix incorrect parents
* Replace to audio_pll2_clk with audio_pll2_out
* Replace sys3_pll2_out with sys_pll3_out
* Replace sys1_pll_40m with sys_pll1_40m
* qspi parent[2] is sys_pll2_333m not sys_pll1_800m
Fixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver")
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Leonard Crestez [Tue, 13 Aug 2019 17:05:29 +0000 (20:05 +0300)]
clk: imx8mm: Fix incorrect parents
* There is no video_pll2 on imx8mm, replace with dummy
* Replace reference to sys_pll3_clk with sys_pll3_out
* qspi parent[2] is sys_pll2_333m not sys_pll1_800m
Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm")
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Leonard Crestez [Tue, 13 Aug 2019 17:05:28 +0000 (20:05 +0300)]
clk: imx8mq: Fix sys3 pll references
The "sys3_pll2_out" CLK was removed in refactoring so all references
need to be updated to "sys3_pll_out"
Fixes: e9dda4af685f ("clk: imx: Refactor entire sccg pll clk")
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Rishi Gupta [Sat, 17 Aug 2019 06:35:59 +0000 (12:05 +0530)]
clk: Remove extraneous 'for' word in comments
An extra 'for' word is grammatically incorrect in the comment
'verifying ops for multi-parent clks'. This commit removes
this extra for word.
Signed-off-by: Rishi Gupta <gupt21@gmail.com>
Link: https://lkml.kernel.org/r/1566023759-7880-1-git-send-email-gupt21@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Stephen Boyd [Thu, 15 Aug 2019 04:25:00 +0000 (21:25 -0700)]
clk: composite: Drop unused clk.h include
This include isn't used. Drop it.
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190815042500.9519-1-sboyd@kernel.org
Stephen Boyd [Wed, 31 Jul 2019 19:35:17 +0000 (12:35 -0700)]
clk: Overwrite clk_hw::init with NULL during clk_register()
We don't want clk provider drivers to use the init structure after clk
registration time, but we leave a dangling reference to it by means of
clk_hw::init. Let's overwrite the member with NULL during clk_register()
so that this can't be used anymore after registration time.
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Doug Anderson <dianders@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190731193517.237136-10-sboyd@kernel.org
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Stephen Boyd [Thu, 15 Aug 2019 04:10:37 +0000 (21:10 -0700)]
clk: sunxi: Don't call clk_hw_get_name() on a hw that isn't registered
The implementation of clk_hw_get_name() relies on the clk_core
associated with the clk_hw pointer existing. If of_clk_hw_register()
fails, there isn't a clk_core created yet, so calling clk_hw_get_name()
here fails. Extract the name first so we can print it later.
Fixes: 1d80c14248d6 ("clk: sunxi-ng: Add common infrastructure")
Cc: Maxime Ripard <maxime.ripard@bootlin.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Stephen Boyd [Thu, 15 Aug 2019 22:12:49 +0000 (15:12 -0700)]
clk: ti: Don't reference clk_init_data after registration
A future patch is going to change semantics of clk_register() so that
clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid
referencing this member here so that we don't run into NULL pointer
exceptions.
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Reported-by: "kernelci.org bot" <bot@kernelci.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190815221249.53235-1-sboyd@kernel.org
Stephen Boyd [Thu, 15 Aug 2019 16:00:20 +0000 (09:00 -0700)]
clk: qcom: Remove error prints from DFS registration
These aren't useful and they reference the init structure name. Let's
just drop them.
Cc: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190815160020.183334-5-sboyd@kernel.org
Acked-by: Taniya Das <tdas@codeaurora.org>
Stephen Boyd [Thu, 15 Aug 2019 16:00:19 +0000 (09:00 -0700)]
rtc: sun6i: Don't reference clk_init_data after registration
A future patch is going to change semantics of clk_register() so that
clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid
referencing this member here so that we don't run into NULL pointer
exceptions.
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: Maxime Ripard <maxime.ripard@bootlin.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Reported-by: "kernelci.org bot" <bot@kernelci.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190815160020.183334-4-sboyd@kernel.org
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Stephen Boyd [Thu, 15 Aug 2019 16:00:18 +0000 (09:00 -0700)]
clk: zx296718: Don't reference clk_init_data after registration
A future patch is going to change semantics of clk_register() so that
clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid
referencing this member here so that we don't run into NULL pointer
exceptions.
Cc: Jun Nie <jun.nie@linaro.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190815160020.183334-3-sboyd@kernel.org
Stephen Boyd [Thu, 15 Aug 2019 16:00:17 +0000 (09:00 -0700)]
clk: milbeaut: Don't reference clk_init_data after registration
A future patch is going to change semantics of clk_register() so that
clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid
referencing this member here so that we don't run into NULL pointer
exceptions.
Cc: Sugaya Taichi <sugaya.taichi@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190815160020.183334-2-sboyd@kernel.org
Stephen Boyd [Wed, 14 Aug 2019 00:24:02 +0000 (17:24 -0700)]
clk: socfpga: deindent code to proper indentation
This code is indented oddly, causing checkpatch to complain. Indent it
properly.
Cc: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190814002402.18154-1-sboyd@kernel.org
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Stephen Boyd [Wed, 31 Jul 2019 19:35:16 +0000 (12:35 -0700)]
phy: ti: am654-serdes: Don't reference clk_init_data after registration
A future patch is going to change semantics of clk_register() so that
clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid
referencing this member here so that we don't run into NULL pointer
exceptions.
Cc: Roger Quadros <rogerq@ti.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190731193517.237136-9-sboyd@kernel.org
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
Stephen Boyd [Wed, 31 Jul 2019 19:35:15 +0000 (12:35 -0700)]
clk: sprd: Don't reference clk_init_data after registration
A future patch is going to change semantics of clk_register() so that
clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid
referencing this member here so that we don't run into NULL pointer
exceptions.
Cc: Chunyan Zhang <zhang.chunyan@linaro.org>
Cc: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190731193517.237136-8-sboyd@kernel.org
Acked-by: Baolin Wang <baolin.wang@linaro.org>
Acked-by: Chunyan Zhang <zhang.chunyan@linaro.org>
Stephen Boyd [Wed, 31 Jul 2019 19:35:14 +0000 (12:35 -0700)]
clk: socfpga: Don't reference clk_init_data after registration
A future patch is going to change semantics of clk_register() so that
clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid
referencing this member here so that we don't run into NULL pointer
exceptions.
Cc: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190731193517.237136-7-sboyd@kernel.org
Acked-by: Dinh Nguyen <dinguyen@kernel.org>