platform/kernel/u-boot.git
21 months agoRevert "fdtdec: drop needlessly convoluted CONFIG_PHANDLE_CHECK_SEQ"
Simon Glass [Wed, 21 Dec 2022 23:08:28 +0000 (16:08 -0700)]
Revert "fdtdec: drop needlessly convoluted CONFIG_PHANDLE_CHECK_SEQ"

The fdt_path_offset() function is slow since it must scan the tree.
This substantial overhead now applies to all boards.

The original code may not be ideal but it is fit for purpose and is only
needed on a few boards.

Reverting this reduces time to set up driver model by about 30ms.

Before revert:

Accumulated time:
                47,170  dm_r
                53,237  dm_spl
               572,986  dm_f

Accumulated time:
                44,598  dm_r
                50,347  dm_spl
               549,133  dm_f

This reverts commit 26f981f295d00351b6f0c69b5317b254b2361cc0.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agorockchip: Enable bootstage on rockpro64
Simon Glass [Sat, 7 Jan 2023 21:57:30 +0000 (14:57 -0700)]
rockchip: Enable bootstage on rockpro64

This board is useful for benchmarking overall U-Boot performance. Enable
the bootstage feature so we get a report.

Since this returns to the boot rom before finishing executing
board_init_r() in SPL, add a few bootstage calls so that we can collect
timing from TPL.

For the stash region, use a portion of SRAM, 64KB below the stack top.
This allows the TPL image to be up to nearly 120KB (it is typically about
64KB). SPL normally runs from SDRAM at 0, so can use the same stash
region.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agotrace: Don't require TIMER_EARLY
Simon Glass [Wed, 21 Dec 2022 23:08:26 +0000 (16:08 -0700)]
trace: Don't require TIMER_EARLY

Some platforms cannot honour this and don't need trace before relocation.
Use 'imply' instead, so boards can disable this.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agotrace: Update trace-format generator for newer version
Simon Glass [Wed, 21 Dec 2022 23:08:25 +0000 (16:08 -0700)]
trace: Update trace-format generator for newer version

This now includes flags and the layout has changed slightly in recent
versions of Linux. Update the generator accordingly.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agotrace: Adjust flags in proftool
Simon Glass [Wed, 21 Dec 2022 23:08:24 +0000 (16:08 -0700)]
trace: Adjust flags in proftool

The flags in this tool don't match the comments or help. Also the variable
names are quite confusing. Update them for consistency.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agomkimage: Add a few more messages for FIT failures
Simon Glass [Wed, 21 Dec 2022 23:08:23 +0000 (16:08 -0700)]
mkimage: Add a few more messages for FIT failures

Add messages to make it clearer which part of the FIT creation is failing.
This can happen when an invalid 'algo' property is provided in the .its
file.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agotrace: Move trace pointer to data section
Simon Glass [Wed, 21 Dec 2022 23:08:22 +0000 (16:08 -0700)]
trace: Move trace pointer to data section

This can be written before relocation. Move it to the data section, since
accessing BSS before relocation is not permitted.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agofdt: Check for overlapping data and FDT
Simon Glass [Wed, 21 Dec 2022 23:08:21 +0000 (16:08 -0700)]
fdt: Check for overlapping data and FDT

If the FDT overlaps with the data region of the image, or with the stack,
it can become corrupted before relocation. Add a check for this, behind a
debug flag, as it can be very confusing and time-consuming to debug.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agofdt: Pass the device tree to fdtdec_prepare_fdt()
Simon Glass [Wed, 21 Dec 2022 23:08:20 +0000 (16:08 -0700)]
fdt: Pass the device tree to fdtdec_prepare_fdt()

This function uses gd->fdt_blob a lot and cannot be used to check any
other device tree. Use a parameter instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agofdt: Drop ifdefs in fdtdec_prepare_fdt()
Simon Glass [Wed, 21 Dec 2022 23:08:19 +0000 (16:08 -0700)]
fdt: Drop ifdefs in fdtdec_prepare_fdt()

This function is a bit messy with several #ifdefs. Convert them to use C
for the conditions.

Rewrite the function comment since most of it is stale.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agofdt: Avoid exporting fdtdec_prepare_fdt()
Simon Glass [Wed, 21 Dec 2022 23:08:18 +0000 (16:08 -0700)]
fdt: Avoid exporting fdtdec_prepare_fdt()

This function is not used outside this file. Make it static.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agotpm: Add a proper Kconfig option for crc8 in SPL
Simon Glass [Sat, 7 Jan 2023 21:57:20 +0000 (14:57 -0700)]
tpm: Add a proper Kconfig option for crc8 in SPL

The current approach is a bit of a hack and only works for the tpm
subsystem. Add a Kconfig so that crc8 can be enabled in SPL for other
purposes.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agoarm: Support trace on armv8
Simon Glass [Wed, 21 Dec 2022 23:08:16 +0000 (16:08 -0700)]
arm: Support trace on armv8

Use the notrace attribute so that timer functions can be used when
tracing. This is required to avoid infinite loops when recording a trace.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agotrace: Use notrace for short
Simon Glass [Wed, 21 Dec 2022 23:08:15 +0000 (16:08 -0700)]
trace: Use notrace for short

The attribute syntax is quite verbose. Use the macro provided for this
purpose.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agoMerge branch '2022-01-16-bootstd-updates'
Tom Rini [Tue, 17 Jan 2023 13:55:40 +0000 (08:55 -0500)]
Merge branch '2022-01-16-bootstd-updates'

To quote the author:
So far standard boot lacks a boot menu, although it is possible to create
a rudimentary one using the existing 'bootmenu' command.

Even then, this text-based menu offer only basic functionality and does
not take full advantage of the displays which are common on many devices.

This series provides a 'bootflow menu' command which allows the user to
select from the available bootflows. An attempt is made to show the name
of the available operating systems, by reading more information into the
bootflow. A logo can be read also, where supported, so that this can be
presented to the user when an option is highlighted.

Full use is made of TrueType fonts, if enabled. For cases where only a
serial console is available, it falls back to a simple text-based menu.

All of this is implementing using a new 'expo' construct, a collection of
scenes (like menu screens) which can be navigated by the user to view
information and select options. This is fairly general and should be able
to cope with a wider array of use cases, with less hacking of the menu
code, such as is currently needed for CMD_BOOTEFI_BOOTMGR.

Of course it would be possible to enhance the existing menu rather than
creating a new setup. Instead it seems better to make the existing menu
use expo, if code space permits. It avoids the event-loop problem and
should be more extensible, given its loosely coupled components and use of
IDs instead of pointers. Further motivation is provided in the
documentation.

For now the CLI keypress-decoding code is split out to be used by the new
menu. The key codes defined by menu.h are reused also.

This is of course just a starting point. Some ideas for future work are
included in the documentation.

21 months agoMerge https://source.denx.de/u-boot/custodians/u-boot-marvell
Tom Rini [Tue, 17 Jan 2023 13:10:56 +0000 (08:10 -0500)]
Merge https://source.denx.de/u-boot/custodians/u-boot-marvell

- kirkwood: Convert to DM Serial for various Kirkwood boards (Tony)
- orion-timer: Fix problem in early_init_done() (Stefan)

21 months agoarm: kirkwood: Convert to DM Serial for various Kirkwood boards
Tony Dinh [Fri, 30 Dec 2022 05:45:57 +0000 (21:45 -0800)]
arm: kirkwood: Convert to DM Serial for various Kirkwood boards

For Kirkwood boards, it is necessary to have early malloc in DRAM area
when Driver Model for Serial is enabled. Please see Michael's patch here:
https://lore.kernel.org/u-boot/20220817193809.1059688-20-michael@walle.cc/

This patch enables the early malloc in DRAM for all Kirkwood boards.
Note that this will work for boards that have either non-DM serial
and DM_SERIAL. Also, add the CONFIG_KIRKWOOD_COMMON option to enable
DM_SERIAL as a common option for boards that have been tested.

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
21 months agotimer: orion-timer: Fix problem in early_init_done()
Stefan Roese [Mon, 16 Jan 2023 08:01:48 +0000 (09:01 +0100)]
timer: orion-timer: Fix problem in early_init_done()

It was noticed that Clearfog is currently broken with this newly
introduced early_init_done() function. Apparently the timer is enabled
here when U-Boot is run but not configured - at least not correctly.
Resulting in a hangup in the timer reading functions.

To fix this, also read the value of the reload register and check it's
value with the one written to by U-Boot. Only if this matches, the
init has already been done.

Fixes: 5387b093cb79 ("timer: orion-timer: Fix problem with early static variable")
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Pali Rohár <pali@kernel.org>
Cc: Martin Rowe <martin.p.rowe@gmail.com>
Cc: Tony Dinh <mibodhi@gmail.com>
Cc: Pali Rohár <pali@kernel.org>
Cc: Michael Walle <michael@walle.cc>
21 months agoMerge tag 'u-boot-rockchip-20230117' of https://source.denx.de/u-boot/custodians...
Tom Rini [Tue, 17 Jan 2023 01:58:37 +0000 (20:58 -0500)]
Merge tag 'u-boot-rockchip-20230117' of https://source.denx.de/u-boot/custodians/u-boot-rockchip

- Add support for rv1126 soc and rv1126 neu2 io board;
- Add support for rk3399 pine64 pinephone pro board;
- dts sync from linux for rk3399 and px30;
- Add support for PX30 Ringneck SoM board;

21 months agoexpo: Add documentation
Simon Glass [Fri, 6 Jan 2023 14:52:43 +0000 (08:52 -0600)]
expo: Add documentation

Add some documentation for the expo feature.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agobootstd: Support setting a theme for the menu
Simon Glass [Fri, 6 Jan 2023 14:52:42 +0000 (08:52 -0600)]
bootstd: Support setting a theme for the menu

Allow a theme to be set. For now this is very simple, just a default font
size to use for all elements.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agobootstd: Add a test for the bootstd menu
Simon Glass [Fri, 6 Jan 2023 14:52:41 +0000 (08:52 -0600)]
bootstd: Add a test for the bootstd menu

Add a test which checks that two operating systems can be displayed in a
menu, allowing one to be selected.

Enable a few things on snow so that the unit tests build.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agobootstd: Support creating a boot menu
Simon Glass [Fri, 6 Jan 2023 14:52:40 +0000 (08:52 -0600)]
bootstd: Support creating a boot menu

Create an expo to handle the boot menu. For now this is quite simple, with
just a header, some menu items and a pointer to show the current one.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agoexpo: Add basic tests
Simon Glass [Fri, 6 Jan 2023 14:52:39 +0000 (08:52 -0600)]
expo: Add basic tests

Add some tests for the expo, including setting up and rendering an expo.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agoexpo: Add support for scene menus
Simon Glass [Fri, 6 Jan 2023 14:52:38 +0000 (08:52 -0600)]
expo: Add support for scene menus

A menu is a key part of the expo design. It consists of a number of items
which the user can select from.

Add the initial implementation of this.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agoexpo: Add support for scenes
Simon Glass [Fri, 6 Jan 2023 14:52:37 +0000 (08:52 -0600)]
expo: Add support for scenes

A scene is a single screen within an expo. It is possible to move between
scenes but only one can be displayed at once.

Add a basic implementation.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agoexpo: Add basic implementation
Simon Glass [Fri, 6 Jan 2023 14:52:36 +0000 (08:52 -0600)]
expo: Add basic implementation

An expo is a way of presenting and collecting information from the
user. It consists of a collection of 'scenes' of which only one is
presented at a time. An expo is typically used to show a boot menu
and allow settings to be changed.

One created, the same expo can be automatically presented in graphical
form using a vidconsole, or in text form on a serial console.

Add an initial implementation of the expo itself. Supports for scenes
and objects is provided later.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agomenu: Factor out menu-keypress decoding
Simon Glass [Fri, 6 Jan 2023 14:52:35 +0000 (08:52 -0600)]
menu: Factor out menu-keypress decoding

Move this code into a separate function so that it can be used in the new
VBE menu.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agobootstd: Allow reading a logo for the OS
Simon Glass [Fri, 6 Jan 2023 14:52:34 +0000 (08:52 -0600)]
bootstd: Allow reading a logo for the OS

Some operating systems provide a logo in bmp format. Read this in if
present so it can be displayed in the menu.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agobootstd: Read the Operating System name for distro/scripts
Simon Glass [Fri, 6 Jan 2023 14:52:33 +0000 (08:52 -0600)]
bootstd: Read the Operating System name for distro/scripts

Add the concept of an OS name to the bootflow. This typically includes the
OS name, version and kernel version.

Implement this for the distro and script bootmeths so that it works with
Armbian and older version of Fedora.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agovideo: Add font functions to the vidconsole API
Simon Glass [Fri, 6 Jan 2023 14:52:32 +0000 (08:52 -0600)]
video: Add font functions to the vidconsole API

Support for fonts currently depends on the type of vidconsole in use. Add
two new methods to enumerate fonts and to set the font.

Fix a few other method comments while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agovideo: Fix unchnaged typo
Simon Glass [Fri, 6 Jan 2023 14:52:31 +0000 (08:52 -0600)]
video: Fix unchnaged typo

Fix this typo in the header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
21 months agovideo: truetype: Rename the metrics function
Simon Glass [Fri, 6 Jan 2023 14:52:30 +0000 (08:52 -0600)]
video: truetype: Rename the metrics function

This should really have a 'truetype' prefix. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agovideo: Enable VIDEO_ANSI by default only with EFI
Simon Glass [Fri, 6 Jan 2023 14:52:29 +0000 (08:52 -0600)]
video: Enable VIDEO_ANSI by default only with EFI

This is not generally needed unless EFI_LOADER is used. Adjust the default
setting to reduce the size of the U-Boot build.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agoimage: Move common image code to image_board and command
Simon Glass [Fri, 6 Jan 2023 14:52:28 +0000 (08:52 -0600)]
image: Move common image code to image_board and command

We should use the cmd/ directory for commands rather than for common code
used elsewhere in U-Boot. Move the common 'source' code into
image-board.c to achieve this.

The image_source_script() function needs to call run_command_list()  so
seems to belong better in the command library. Move and rename it.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agoimage: Add a function to find a script in an image
Simon Glass [Fri, 6 Jan 2023 14:52:27 +0000 (08:52 -0600)]
image: Add a function to find a script in an image

Split this functionality out of the 'source' command so it can be used
from another place. For now leave it where it is, but a future patch will
move it out of cmd/

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agomenu: Make use of CLI character processing
Simon Glass [Fri, 6 Jan 2023 14:52:26 +0000 (08:52 -0600)]
menu: Make use of CLI character processing

Avoid duplicating some of the escape-sequence processing here and use the
CLI function instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agomenu: Use a switch statement
Simon Glass [Fri, 6 Jan 2023 14:52:25 +0000 (08:52 -0600)]
menu: Use a switch statement

Convert the long line of if() statements to a switch() since this makes
better use of the C language.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agomenu: Update bootmenu_loop() to return the code
Simon Glass [Fri, 6 Jan 2023 14:52:24 +0000 (08:52 -0600)]
menu: Update bootmenu_loop() to return the code

Use the return value to save having to pass around a pointer. This also
resolves any ambiguity about what *key contains when the function is
called.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agomenu: Update bootmenu_autoboot_loop() to return the code
Simon Glass [Fri, 6 Jan 2023 14:52:23 +0000 (08:52 -0600)]
menu: Update bootmenu_autoboot_loop() to return the code

Use the return value to save having to pass around a pointer. This also
resolves any ambiguity about what *key contains when the function is
called.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agomenu: Rename KEY_... to BKEY_...
Simon Glass [Fri, 6 Jan 2023 14:52:22 +0000 (08:52 -0600)]
menu: Rename KEY_... to BKEY_...

This enum values conflict with linux/input.h so rename them.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agobootmenu: Add a few comments
Simon Glass [Fri, 6 Jan 2023 14:52:21 +0000 (08:52 -0600)]
bootmenu: Add a few comments

The behaviour of these two functions is completely undocumented. Add some
notes so the poor, suffering dev can figure out what is going on.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agocli: Move readline character-processing to a state machine
Simon Glass [Fri, 6 Jan 2023 14:52:20 +0000 (08:52 -0600)]
cli: Move readline character-processing to a state machine

The current cread_line() function is very long. It handles the escape
processing inline. The menu command does similar processing but at the
character level, so there is some duplication.

Split the character processing into a new function cli_ch_process() which
processes individual characters and returns the resulting input character,
taking account of escape sequences. It requires the caller to set up and
maintain its state.

Update cread_line() to use this new function.

The only intended functional change is that an invalid escape sequence
does not add invalid/control characters into the input buffer, but instead
discards these.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agosandbox: Enable mmc command and legacy images
Simon Glass [Fri, 6 Jan 2023 14:52:19 +0000 (08:52 -0600)]
sandbox: Enable mmc command and legacy images

The mmc command is useful for testing mmc disk images in sandbox, so
enable it. We also need to enable legacy images so that we can run tests
which use them.

Disable it for a few avb tests since MMC is not implemented there yet.

Signed-off-by: Simon Glass <sjg@chromium.org>
21 months agorockchip: add support for PX30 Ringneck SoM on Haikou Devkit
Quentin Schulz [Mon, 9 Jan 2023 10:36:45 +0000 (11:36 +0100)]
rockchip: add support for PX30 Ringneck SoM on Haikou Devkit

The PX30-µQ7 (Ringneck) is a system-on-module featuring the Rockchip
PX30 in a micro Qseven-compatible form-factor.

PX30-µQ7 features:
        * CPU: quad-core Cortex-A35
        * DRAM: 2GB dual-channel
        * eMMC: onboard eMMC
        * SD/MMC
        * TI DP83825I 10/100Mbps PHY
        * USB:
                * USB2.0 dual role port
                * 3x USB2.0 host via onboard USB2.0 hub
        * Display: MIPI-DSI
        * Camera: MIPI-CSI
        * onboard 2.4GHz WiFi + Bluetooth module
        * Companion Controller: on-board additional microcontroller
  (STM32 Cortex-M0 or ATtiny):
                * RTC
                * fan controller
                * CAN (only STM32)

The non-U-Boot DTS files are imported from Linux v6.2-rc2.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
21 months agoarm64: dts: rockchip: sync px30 DTSI with Linux kernel v6.1
Quentin Schulz [Mon, 9 Jan 2023 10:36:44 +0000 (11:36 +0100)]
arm64: dts: rockchip: sync px30 DTSI with Linux kernel v6.1

Sync the px30 dtsi from Linux kernel v6.1.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
21 months agorockchip: px30: insert u-boot, spl-boot-device into U-Boot device tree
Quentin Schulz [Mon, 9 Jan 2023 10:36:43 +0000 (11:36 +0100)]
rockchip: px30: insert u-boot, spl-boot-device into U-Boot device tree

It is possible to boot U-Boot proper from a different storage medium
than the one used by the BOOTROM to load the SPL. This information is
stored in the u-boot,spl-boot-device Device Tree property and is
accessible from U-Boot proper so that it has knowledge at runtime where
it was loaded from.

Let's add support for this feature for px30.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
21 months agorockchip: px30: list possible SPL boot devices
Quentin Schulz [Mon, 9 Jan 2023 10:36:42 +0000 (11:36 +0100)]
rockchip: px30: list possible SPL boot devices

BOOTROM sets a bit in a CPU register so that the software can know from
where the first stage bootloader was booted. One use case for this is to
specify the default loading medium for U-Boot proper to match the one
used by the BOOTROM to load the SPL (same-as-spl in
u-boot,spl-boot-order).

Let's create the mapping between BOOTROM value and Device Tree node
names for MMC devices.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
21 months agorockchip: px30: fix CFG_IRAM_BASE
Quentin Schulz [Mon, 9 Jan 2023 10:36:41 +0000 (11:36 +0100)]
rockchip: px30: fix CFG_IRAM_BASE

The IRAM on PX30 (or Int_MEM in datasheet) starts at 0xff0e0000 and not
0xff020000 as rightfully stated in the FIXME comment.

Let's fix it so that BROM_BOOTSOURCE_ID_ADDR points to the correct
address for PX30.

Fixes: 46281a76bee3 ("rockchip: add core px30 headers")
Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
21 months agorockchip: px30: fix possibly unused grf and cru variables
Quentin Schulz [Mon, 9 Jan 2023 10:36:40 +0000 (11:36 +0100)]
rockchip: px30: fix possibly unused grf and cru variables

The grf and cru are only used when no UART base is provided by the user
(defaults to UART2) or for UART1, UART3 and UART5 to be used for the
debug UART. Therefore, let's surround those variable definitions with
the proper checks.

This wasn't an issue before support for UART0 was added, because all
cases were using cru and grf. UART0 only uses pmucru so there's a need
to not define those variables anymore.

Fixes: d0af506625ff ("rockchip: px30: support debug uart on UART0")
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
21 months agorockchip: Add initial support for the PINE64 Pinephone Pro
Peter Robinson [Sat, 31 Dec 2022 09:24:00 +0000 (09:24 +0000)]
rockchip: Add initial support for the PINE64 Pinephone Pro

The Pinephone Pro is another device by PINE64. It's closely related
to the Pinebook Pro of which this initial support is derived from.

Specification:
- A variant of the Rockchip RK3399
- A 6 inch 720*1440 DSI display
- Front and rear cameras
- Type-C interface with alt mode display (DP 1.2) and PD charging
- 4GB LPDDR4 RAM
- 128GB eMMC
- mSD card slot
- An AP6255 module for 802.11ac WiFi and Bluetooth 5
- Quectel EG25-G 4G/LTE modem

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
21 months agoarm64: dts: rk3399: Add upstream Pinephone Pro dts
Peter Robinson [Sat, 31 Dec 2022 09:23:59 +0000 (09:23 +0000)]
arm64: dts: rk3399: Add upstream Pinephone Pro dts

Initial support for the PinePhone Pro has now landed upstream in
Linux 6.1 RC1 so sync the dts from 6.2-rc1 for initial support.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
21 months agoboard: rockchip: Add Edgeble Neu2 IO Board
Jagan Teki [Wed, 14 Dec 2022 17:51:11 +0000 (23:21 +0530)]
board: rockchip: Add Edgeble Neu2 IO Board

Neural Compute Module 2(Neu2) IO board is an industrial form factor
IO board from Edgeble AI.

General features:
- microSD slot
- MIPI DSI connector
- 2x USB Host
- 1x USB OTG
- Ethernet
- mini PCIe
- Onboard PoE
- RS485, RS232, CAN
- Micro Phone array
- Speaker
- RTC battery slot
- 40-pin expansion

Neu2 needs to mount on top of this IO board in order to create complete
Edgeble Neural Compute Module 2(Neu2) IO platform.

Add support for it.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
21 months agoARM: dts: rockchip: Add rv1126-u-boot.dtsi
Jagan Teki [Wed, 14 Dec 2022 17:51:10 +0000 (23:21 +0530)]
ARM: dts: rockchip: Add rv1126-u-boot.dtsi

Add u-boot,dm-spl and u-boot,dm-pre-reloc related properties
for Rockchip RV1126 SoC.

Both eMMC and SD boot are tested in Edgeble Neu2 SoM.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
21 months agoARM: dts: rockchip: rv1126: Add Edgeble Neural Compute Module 2(Neu2) IO
Jagan Teki [Wed, 14 Dec 2022 17:51:09 +0000 (23:21 +0530)]
ARM: dts: rockchip: rv1126: Add Edgeble Neural Compute Module 2(Neu2) IO

Neural Compute Module 2(Neu2) IO board is an industrial form factor
evaluation board from Edgeble AI.

General features:
- microSD slot
- MIPI DSI connector
- 2x USB Host
- 1x USB OTG
- Ethernet
- mini PCIe
- Onboard PoE
- RS485, RS232, CAN
- Micro Phone array
- Speaker
- RTC battery slot
- 40-pin expansion

Neu2 needs to mount on top of this IO board in order to create complete
Edgeble Neural Compute Module 2(Neu2) IO platform.

Add support for it.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
21 months agoARM: dts: rockchip: rv1126: Add Edgeble Neural Compute Module 2(Neu2)
Jagan Teki [Wed, 14 Dec 2022 17:51:08 +0000 (23:21 +0530)]
ARM: dts: rockchip: rv1126: Add Edgeble Neural Compute Module 2(Neu2)

Neural Compute Module 2(Neu2) is a 96boards SoM-CB compute module
based on Rockchip RV1126 from Edgeble AI.

General features:
- Rockchip RV1126
- 2/4GB LPDDR4
- 8/16/32GB eMMC
- 2x MIPI CSI2 FPC connector
- Fn-link 8223A-SR WiFi/BT

Industrial grade (-40 °C to +85 °C) version of the same class of module
called Neu2k powered with Rockchip RV1126K.

Neu2 needs to mount on top of Edgeble IO boards for creating complete
platform solutions.

Add support for it.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
21 months agorockchip: mkimage: Add rv1126 support
Jagan Teki [Wed, 14 Dec 2022 17:51:07 +0000 (23:21 +0530)]
rockchip: mkimage: Add rv1126 support

Add support for rv1126 package header in mkimage tool.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
21 months agoarm: rockchip: rv1126: Set dram area unsecure for SPL
Jagan Teki [Wed, 14 Dec 2022 17:51:06 +0000 (23:21 +0530)]
arm: rockchip: rv1126: Set dram area unsecure for SPL

Unsecure the dram area so that MMC, USB, and SFC controllers
can able to read data from dram.

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
21 months agoarm: rockchip: Add RV1126 arch core support
Jagan Teki [Wed, 14 Dec 2022 17:51:05 +0000 (23:21 +0530)]
arm: rockchip: Add RV1126 arch core support

Rockchip RV1126 is a high-performance vision processor SoC
for IPC/CVR, especially for AI related application.

Add arch core support for it.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I22fde40ec375e3c6aba39808abf252edc45d4b04

21 months agoARM: dts: rockchip: Add Rockchip RV1126 SoC
Jagan Teki [Wed, 14 Dec 2022 17:51:04 +0000 (23:21 +0530)]
ARM: dts: rockchip: Add Rockchip RV1126 SoC

RV1126 is a high-performance vision processor SoC for IPC/CVR,
especially for AI related application.

It is based on quad-core ARM Cortex-A7 32-bit core which integrates
NEON and FPU. There is a 32KB I-cache and 32KB D-cache for each core
and 512KB unified L2 cache. It has build-in NPU supports INT8/INT16
hybrid operation and computing power is up to 2.0TOPs.

This patch add basic core dtsi support.

Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
21 months agoARM: dts: rockchip: Add Rockchip RV1126 pinctrl
Jagan Teki [Wed, 14 Dec 2022 17:51:03 +0000 (23:21 +0530)]
ARM: dts: rockchip: Add Rockchip RV1126 pinctrl

Add pinctrl definitions for Rockchip RV1126.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
21 months agoarm: rockchip: Add grf header for rv1126
Jagan Teki [Wed, 14 Dec 2022 17:51:02 +0000 (23:21 +0530)]
arm: rockchip: Add grf header for rv1126

Add GRF header for Rockchip RV1126.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
21 months agodt-bindings: power: Add power-domain header for rv1126
Jagan Teki [Wed, 14 Dec 2022 17:51:01 +0000 (23:21 +0530)]
dt-bindings: power: Add power-domain header for rv1126

Add power-domain header for RV1126 SoC from description in TRM.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
21 months agoclk: rockchip: Add rv1126 clk support
Jagan Teki [Wed, 14 Dec 2022 17:51:00 +0000 (23:21 +0530)]
clk: rockchip: Add rv1126 clk support

Add clock driver support for Rockchip RV1126 SoC.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
21 months agodt-bindings: clk: Add dt-binding header for RV1126
Jagan Teki [Wed, 14 Dec 2022 17:50:59 +0000 (23:20 +0530)]
dt-bindings: clk: Add dt-binding header for RV1126

Add the dt-bindings header for the Rockchip RV1126, that gets shared
between the clock controller and the clock references in the dts.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
21 months agoarch: rockchip: Add cru header for rv1126
Jagan Teki [Wed, 14 Dec 2022 17:50:58 +0000 (23:20 +0530)]
arch: rockchip: Add cru header for rv1126

Add clock and reset unit header include for rv1126.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
21 months agopinctrl: rockchip: Add rv1126 support
Jagan Teki [Wed, 14 Dec 2022 17:50:57 +0000 (23:20 +0530)]
pinctrl: rockchip: Add rv1126 support

Add pinctrl driver for Rockchip RV1126.

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
21 months agopinctrl: rockchip: Add pinctrl route types
Jagan Teki [Wed, 14 Dec 2022 17:50:56 +0000 (23:20 +0530)]
pinctrl: rockchip: Add pinctrl route types

Some pins in rockchip are routed via Top GRF and PMU GRF
instead of direct regmap.

Add support to handle all these routing paths so that the
SoC pinctrl drivers will use them accordingly.

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
21 months agoram: rockchip: Add rv1126 lpddr4 support
Jagan Teki [Wed, 14 Dec 2022 17:50:55 +0000 (23:20 +0530)]
ram: rockchip: Add rv1126 lpddr4 support

Add LPDDR4 detection timings and support for RV1126.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
21 months agoram: rockchip: rv1126: Control ddr init prints via DEBUG
Jagan Teki [Wed, 14 Dec 2022 17:50:54 +0000 (23:20 +0530)]
ram: rockchip: rv1126: Control ddr init prints via DEBUG

Control the ddr init print messages via RAM_ROCKCHIP_DEBUG
instead of printing by default.

This gives an option to configs to enable these prints or
not.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
21 months agoram: rockchip: Add rv1126 ddr driver support
Jagan Teki [Wed, 14 Dec 2022 17:50:53 +0000 (23:20 +0530)]
ram: rockchip: Add rv1126 ddr driver support

Add DDR driver for Rockchip RV1126 SoC.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
21 months agoram: rockchip: Add rv1126 ddr loader params
Jagan Teki [Wed, 14 Dec 2022 17:50:52 +0000 (23:20 +0530)]
ram: rockchip: Add rv1126 ddr loader params

Add DDR loader parameters for Rockchip RV1126 SoC.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
21 months agoram: rockchip: Add rv1126 ddr3 support
Jagan Teki [Wed, 14 Dec 2022 17:50:51 +0000 (23:20 +0530)]
ram: rockchip: Add rv1126 ddr3 support

Add DDR3 detection timings for Rockchip RV1126 SoC.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
21 months agoram: rockchip: Update ddr pctl regs for px30
Jagan Teki [Wed, 14 Dec 2022 17:50:50 +0000 (23:20 +0530)]
ram: rockchip: Update ddr pctl regs for px30

Add full ddr pctl registers and bit masks for px30.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
21 months agoram: rockchip: Compute ddr capacity based on grf split
Jagan Teki [Wed, 14 Dec 2022 17:50:49 +0000 (23:20 +0530)]
ram: rockchip: Compute ddr capacity based on grf split

DDR chip capacity is computed based on GRF split in some
Rockchip SoC's like PX30 and RV1126.

Add split argument in ddr print info so-that the respective
ddr driver will pass the grf split.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
21 months agoram: rockchip: Add common ddr type configs
Jagan Teki [Wed, 14 Dec 2022 17:50:48 +0000 (23:20 +0530)]
ram: rockchip: Add common ddr type configs

We have common ddr types in rockchip or in general. So use
the common ddr type names instead of per Rockchip SoC to
avoid confusion.

The respective ddr type names will use on the associated
ddr SoC driver as these drivers are built per SoC at a time.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
21 months agoram: Mark ram-uclass depend on TPL_DM or SPL_DM
Jagan Teki [Wed, 14 Dec 2022 17:50:47 +0000 (23:20 +0530)]
ram: Mark ram-uclass depend on TPL_DM or SPL_DM

ram-uclass is building irrespective of whether TPL_DM
or SPL_DM is enabled. So control the ram uclass build
based on TPL/SPL_DM.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
21 months agoconfigs: roc-pc-rk3399: Enable rockchip efuse support
Christopher Obbard [Wed, 23 Nov 2022 13:59:02 +0000 (13:59 +0000)]
configs: roc-pc-rk3399: Enable rockchip efuse support

Enable efuse support which allows reading of the cpuid#, serial#
and also generates a unique mac address from the board's serial.

Signed-off-by: Christopher Obbard <chris.obbard@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
21 months agorockchip: mkimage: make RC4 key const
John Keeping [Fri, 18 Nov 2022 16:13:18 +0000 (16:13 +0000)]
rockchip: mkimage: make RC4 key const

This is read-only data, so mark it as such.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
21 months agorc4: mark key as const
John Keeping [Fri, 18 Nov 2022 16:13:17 +0000 (16:13 +0000)]
rc4: mark key as const

Key data is never written so the parameter can be const, which allows
putting fixed keys in .rodata.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
21 months agorockchip: puma-rk3399: sync DTS with Linux kernel next-20221114
Quentin Schulz [Tue, 15 Nov 2022 14:46:23 +0000 (15:46 +0100)]
rockchip: puma-rk3399: sync DTS with Linux kernel next-20221114

This synchronizes the Device Trees related to Puma RK3399 SoM with Linux
kernel next-20221114 to include two important changes pertaining to
eMMC and SD card instability.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
21 months agorockchip: clk: add watchdog clock to px30_clk_enable
Quentin Schulz [Mon, 14 Nov 2022 10:33:46 +0000 (11:33 +0100)]
rockchip: clk: add watchdog clock to px30_clk_enable

Add the PCLK_WDT_NS clock to px30_clk_enable so that the watchdog driver
can probe since it wants to enable this clock.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
21 months agorockchip: px30: make watchdog and tsadc trigger a first global reset
Quentin Schulz [Fri, 11 Nov 2022 11:25:48 +0000 (12:25 +0100)]
rockchip: px30: make watchdog and tsadc trigger a first global reset

By default, the PX30 is configured for watchdog and tsadc to trigger a
second global reset which is a more permissive reset than first global
reset.

From TRM part 1 "2.3 System Reset Solution":
glb_srstn_1 will reset the all logic, and
glb_srstn_2 will reset the all logic except GRF, SGRF and all GPIOs.

This enforces that the watchdog and tsadc trigger glb_srstn_1 as
similarly done for RK3399 in U-Boot (in SDRAM driver for some reason?),
TF-A and Coreboot.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
21 months agoMerge https://source.denx.de/u-boot/custodians/u-boot-sh
Tom Rini [Sun, 15 Jan 2023 15:31:17 +0000 (10:31 -0500)]
Merge https://source.denx.de/u-boot/custodians/u-boot-sh

21 months agoMerge https://source.denx.de/u-boot/custodians/u-boot-usb
Tom Rini [Sun, 15 Jan 2023 15:31:00 +0000 (10:31 -0500)]
Merge https://source.denx.de/u-boot/custodians/u-boot-usb

21 months agousb: gadget: dwc2_udc_otg: implement pullup()
Mattijs Korpershoek [Wed, 11 Jan 2023 08:19:27 +0000 (09:19 +0100)]
usb: gadget: dwc2_udc_otg: implement pullup()

Pullup is used by the usb framework in order to do software-controlled
usb_gadget_connect() and usb_gadget_disconnect().

Implement pullup() for dwc2 using the SOFT_DISCONNECT bit in the dctl
register:
* when pullup is on, clear SOFT_DISCONNECT
* when pullup is off, set SOFT_DISCONNECT

This is especially useful when a gadget disconnection is initiated but
no board_usb_cleanup() is called.

Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
21 months agousb: gadget: fastboot: detach usb just before rebooting
Dario Binacchi [Sat, 7 Jan 2023 16:48:07 +0000 (17:48 +0100)]
usb: gadget: fastboot: detach usb just before rebooting

The patch fixes the following error when updating a BSH SMM S2 board:
3:72>Start Cmd:FB[-t 8000]: ucmd nand write ${loadaddr} nanddtb ${filesize}
3:72>Okay (0.023s)
3:72>Start Cmd:FB: reboot
3:72>Fail Bulk(R):LIBUSB_ERROR_IO(0s)

The "fastboot reboot" command detaches the USB when it still needs to be
used. So let's detach the USB just before the reset.

CC: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Fixes: 5f7e01e9d5d800 ("usb: gadget: fastboot: detach usb on reboot commands")
Suggested-by: Michael Trimarchi <michael@amarulasolutions.com>
Co-developed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
21 months agousb: hub: allow to increase HUB_DEBOUNCE_TIMEOUT
Patrick Delaunay [Fri, 9 Sep 2022 09:45:23 +0000 (11:45 +0200)]
usb: hub: allow to increase HUB_DEBOUNCE_TIMEOUT

Add a new CONFIG_USB_HUB_DEBOUNCE_TIMEOUT to increase the
HUB_DEBOUNCE_TIMEOUT value, for example to 2s because some usb device
needs around 1.5s or more to make the hub port status to be
connected steadily after being powered off and powered on.

This 2s value is aligned with Linux driver and avoids to configure
"usb_pgood_delay" as a workaround for connection timeout on
some USB device; normally the env variable "usb_pgood_delay" is used
to delay the first query after power ON and thus the device answer,
but this variable not used to increase the connection timeout delay.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
21 months agoconfigs: r8a77980: Condor: Enable MMC support by default
Andrey Dolnikov [Thu, 22 Dec 2022 21:18:25 +0000 (22:18 +0100)]
configs: r8a77980: Condor: Enable MMC support by default

This enables MMC support, which is available
on Condor board, by default.

Signed-off-by: Andrey Dolnikov <andrey.dolnikov@cogentembedded.com>
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
21 months agoARM: renesas: condor: switch eMMC bus to 1V8
Hai Pham [Thu, 22 Dec 2022 21:18:01 +0000 (22:18 +0100)]
ARM: renesas: condor: switch eMMC bus to 1V8

The eMMC card has two supplies, VCC and VCCQ. The VCC supplies the NAND
array and the VCCQ supplies the bus. On Condor, the VCC is connected to
3.3V rail, while the VCCQ is connected to 1.8V rail. Adjust the pinmux
to match the bus, which is always operating in 1.8V mode.

Based on Linux commit 69efe4bbeda50745 ("arm64: dts: renesas: condor:
Switch eMMC bus to 1V8") from Wolfram Sang

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
21 months agoARM: dts: renesas: condor: Enable SPI NOR fast-read
Marek Vasut [Thu, 22 Dec 2022 21:17:20 +0000 (22:17 +0100)]
ARM: dts: renesas: condor: Enable SPI NOR fast-read

This board requires SPI NOR fast-read, otherwise the SPI NOR
access returns corrupted data. Enable the fast-read explicitly
in DT as it has been disabled in the MTD subsystem by commit
d008190920 ("mtd: spi-nor: Mask out fast read if not requested in DT")

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
21 months agoARM: renesas: ulcb: Set CONFIG_TEXT_BASE=0x0 on R-Car Gen3 ULCB
Marek Vasut [Thu, 22 Dec 2022 21:06:46 +0000 (22:06 +0100)]
ARM: renesas: ulcb: Set CONFIG_TEXT_BASE=0x0 on R-Car Gen3 ULCB

Since R-Car Gen3 already enables position independent build, also set
CONFIG_TEXT_BASE=0x0 to finalize the switch. This is possible since
534f0fbd65 ("arm64: Fix relocation of env_addr if POSITION_INDEPENDENT=y")
fixed current env_get_char() crash with CONFIG_TEXT_BASE=0x0 .

This change permits us to start U-Boot from any location in DRAM instead
of specific TEXT_BASE.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
21 months agoARM: renesas: condor: Set CONFIG_TEXT_BASE=0x0 on R-Car Gen3 Condor
Marek Vasut [Thu, 22 Dec 2022 21:07:08 +0000 (22:07 +0100)]
ARM: renesas: condor: Set CONFIG_TEXT_BASE=0x0 on R-Car Gen3 Condor

Since R-Car Gen3 already enables position independent build, also set
CONFIG_TEXT_BASE=0x0 to finalize the switch. This is possible since
534f0fbd65 ("arm64: Fix relocation of env_addr if POSITION_INDEPENDENT=y")
fixed current env_get_char() crash with CONFIG_TEXT_BASE=0x0 .

This change permits us to start U-Boot from any location in DRAM instead
of specific TEXT_BASE.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
21 months agoARM: renesas: Enable LTO on R-Car3 Falcon
Marek Vasut [Thu, 22 Dec 2022 21:13:15 +0000 (22:13 +0100)]
ARM: renesas: Enable LTO on R-Car3 Falcon

Enable LTO (link time optimization) to improve optimization
and reduce code size by cca. 30 kiB.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
21 months agoARM: renesas: Enable LTO on R-Car3 Draak
Marek Vasut [Thu, 22 Dec 2022 21:13:14 +0000 (22:13 +0100)]
ARM: renesas: Enable LTO on R-Car3 Draak

Enable LTO (link time optimization) to improve optimization
and reduce code size by cca. 29 kiB.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
21 months agoARM: renesas: Enable LTO on R-Car3 Ebisu
Marek Vasut [Thu, 22 Dec 2022 21:13:13 +0000 (22:13 +0100)]
ARM: renesas: Enable LTO on R-Car3 Ebisu

Enable LTO (link time optimization) to improve optimization
and reduce code size by cca. 34 kiB.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
21 months agoARM: renesas: Enable LTO on R-Car3 Condor
Marek Vasut [Thu, 22 Dec 2022 21:13:12 +0000 (22:13 +0100)]
ARM: renesas: Enable LTO on R-Car3 Condor

Enable LTO (link time optimization) to improve optimization
and reduce code size by cca. 32 kiB.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
21 months agoARM: renesas: Enable LTO on R-Car3 Eagle
Marek Vasut [Thu, 22 Dec 2022 21:13:11 +0000 (22:13 +0100)]
ARM: renesas: Enable LTO on R-Car3 Eagle

Enable LTO (link time optimization) to improve optimization
and reduce code size by cca. 32 kiB.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
21 months agoARM: renesas: Enable LTO on R-Car3 ULCB
Marek Vasut [Thu, 22 Dec 2022 21:13:10 +0000 (22:13 +0100)]
ARM: renesas: Enable LTO on R-Car3 ULCB

Enable LTO (link time optimization) to improve optimization
and reduce code size by cca. 31 kiB.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
21 months agoMerge tag 'u-boot-stm32-20230113' of https://source.denx.de/u-boot/custodians/u-boot-stm
Tom Rini [Fri, 13 Jan 2023 14:56:19 +0000 (09:56 -0500)]
Merge tag 'u-boot-stm32-20230113' of https://source.denx.de/u-boot/custodians/u-boot-stm

Add driver to manage onboard hub supplies
Add calibration support for stm32-adc
Linux kernel v6.1 DT synchronization for stm32mp151.dtsi
stm32mp157a-dk1-scmi-u-boot.dtsi update
Add support of OP-TEE and STM32MP13x in bsec driver
ECDSA various fixes for stm32mp