Tom Stellard [Sat, 20 Aug 2022 08:31:32 +0000 (01:31 -0700)]
Tom Stellard [Sat, 20 Aug 2022 08:25:11 +0000 (01:25 -0700)]
HowToReleaseLLVM: Add annual release schedule template
Reviewed By: ldionne, thieta
Differential Revision: https://reviews.llvm.org/D95114
Tom Stellard [Sat, 20 Aug 2022 08:22:00 +0000 (01:22 -0700)]
HowToReleaseLLVM: Add some more details about website updates
Reviewed By: thieta
Differential Revision: https://reviews.llvm.org/D131634
Tom Stellard [Sat, 20 Aug 2022 07:15:14 +0000 (00:15 -0700)]
workflows/llvm-project-tests: Workaround an issue with lldb builds on Windows
For some reason cmake started selecting a 32-bit version of python on
Windows instead of the 64-bit version when building windows. Explicitly
setting the default python to 3.10 fixes this problem.
Reviewed By: thieta
Differential Revision: https://reviews.llvm.org/D132280
Kazu Hirata [Sat, 20 Aug 2022 07:12:35 +0000 (00:12 -0700)]
Fix unused variable warnings
These warnings came up with gcc-11.3.0.
Michał Górny [Fri, 19 Aug 2022 14:22:55 +0000 (16:22 +0200)]
Reland "[lldb] [test] Disable new CommunicationTests on Windows"
This change was wrongly reverted and re-broke the Windows buildbot.
Sponsored by: The FreeBSD Foundation
Thomas [Sat, 20 Aug 2022 06:30:04 +0000 (08:30 +0200)]
[NFC][AMDGPU] Fix typo.
Fangrui Song [Sat, 20 Aug 2022 06:29:31 +0000 (23:29 -0700)]
[mlir][docs] Migrate away from deprecated llvm::Optional methods
Michał Górny [Fri, 12 Aug 2022 10:37:18 +0000 (12:37 +0200)]
[lldb] [gdb-remote] Include PID in vCont packets if multiprocess
Try to always send vCont packets and include the PID in them if running
multiprocess. This is necessary to ensure that with the upcoming full
multiprocess support always resumes the correct process without having
to resort to the legacy Hc packets.
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.llvm.org/D131758
Luo, Yuanke [Thu, 18 Aug 2022 01:50:55 +0000 (09:50 +0800)]
(Reland) [fastalloc] Support allocating specific register class in fastalloc
This reverts commit
853bb192c407f5d9e75a5fd55cc089151530cbd3.
Tom Stellard [Sat, 20 Aug 2022 04:51:00 +0000 (21:51 -0700)]
workflows/version-check: Fix check for release candidates
Reviewed By: thieta
Differential Revision: https://reviews.llvm.org/D131650
Kazu Hirata [Sat, 20 Aug 2022 04:40:48 +0000 (21:40 -0700)]
[lldb] Use Optional::value instead of Optional::getValue (NFC)
Kazu Hirata [Sat, 20 Aug 2022 04:40:47 +0000 (21:40 -0700)]
[lldb] Use Optional::transform instead of Optional::map (NFC)
Vitaly Buka [Sat, 20 Aug 2022 04:16:02 +0000 (21:16 -0700)]
[msan] Bump max allocation on aarch64
wanglei [Sat, 20 Aug 2022 04:06:45 +0000 (12:06 +0800)]
[MC][LoongArch] Make .reloc support arbitrary relocation types
Similar to D76746 (ARM), D76754 (AArch64), D77018 (RISCV) and
llvmorg-11-init-6967-g152d14da64c (x86)
Differential Revision: https://reviews.llvm.org/D132119
wanglei [Sat, 20 Aug 2022 02:13:29 +0000 (10:13 +0800)]
[LoongArch] Add some fixups and relocations
This patch only add %pc_hi20/%pc_lo12/%plt relocations in order
to be able to generate gnu ld linkable relocation file for the
`hello world` IR :
```
@.str = private unnamed_addr constant [14 x i8] c"Hello world!\0A\00", align 1
define dso_local signext i32 @main() nounwind {
entry:
%call = call signext i32 (ptr, ...) @printf(ptr noundef @.str)
ret i32 0
}
declare dso_local signext i32 @printf(ptr noundef, ...)
```
This patch also updates some test cases due to new modifiers introduced.
New test: test/MC/LoongArch/Relocations/relocations.s
Differential Revision: https://reviews.llvm.org/D132108
gonglingqin [Sat, 20 Aug 2022 02:20:30 +0000 (10:20 +0800)]
[LoongArch] Add codegen support for fsqrt
Reviewed By: xen0n, SixWeining
Differential Revision: https://reviews.llvm.org/D132198
Fangrui Song [Sat, 20 Aug 2022 02:08:28 +0000 (19:08 -0700)]
[docs] Remove lld/ELF release note about --package-metadata= which is in release/15.x
Lorenzo Albano [Sat, 20 Aug 2022 01:15:56 +0000 (18:15 -0700)]
[VP] Add splitting for VP_STRIDED_STORE and VP_STRIDED_LOAD
Following the comment's thread of D117235, I added checks for the widening + splitting case, which also causes a split with one of the resulting vectors to be empty. Due to the same issues described in that same thread, the `fixed-vectors-strided-store.ll` test is missing the widening + splitting case, while the same case in the `strided-vpload.ll` test requires to manually split the loaded vector.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D121784
Adrian Vogelsgesang [Sat, 20 Aug 2022 00:31:19 +0000 (17:31 -0700)]
[libc++][NFC][spaceship] Update status doc
Philip Reames [Fri, 19 Aug 2022 23:21:14 +0000 (16:21 -0700)]
[tti] Consolidate getOperandInfo without OperandValueProperties copies [nfc]
Austin Kerbow [Wed, 17 Aug 2022 17:00:06 +0000 (10:00 -0700)]
[AMDGPU] Add iglp_opt builtin and MFMA GEMM Opt strategy
Adds a builtin that serves as an optimization hint to apply specific optimized
DAG mutations during scheduling. This also disables any other mutations or
clustering that may interfere with the desired pipeline. The first optimization
strategy that is added here is designed to improve the performance of small gemm
kernels on gfx90a.
Reviewed By: jrbyrnes
Differential Revision: https://reviews.llvm.org/D132079
Alexander Yermolovich [Fri, 19 Aug 2022 22:27:55 +0000 (15:27 -0700)]
[DWARF][BOLT] Fix handling of converting range accesss from ofset to index.
Wasn't handling correctly creating DW_AT_rnglists_base in UnitDie when
converting access pattern for DW_AT_ranges from offset to index for DWARF5.
Reviewed By: rafauler
Differential Revision: https://reviews.llvm.org/D132087
Jonas Devlieghere [Fri, 19 Aug 2022 22:14:15 +0000 (15:14 -0700)]
[lldb] Support specifying a custom libcxx for the API tests
This patch combines D129166 (to always pick the just-built libc++) and
D132257 (to allow customizing the libc++ for testing). The common goal
is to avoid picking up an unexpected libc++ for testing.
Differential revision: https://reviews.llvm.org/D132263
LLVM GN Syncbot [Fri, 19 Aug 2022 21:56:27 +0000 (21:56 +0000)]
[gn build] Port
57c9780d60b1
Sam Clegg [Fri, 29 Jul 2022 17:16:57 +0000 (10:16 -0700)]
[lld][ELF] Rename SymbolTable::symbols() to SymbolTable::getSymbols(). NFC
This change renames this method match its original name and the name
used in the wasm linker.
Back in
d8f8abbd4a2823f223bd7bc56445541fb221b512 the ELF SymbolTable
method `getSymbols()` was replaced with `forEachSymbol`.
Then in
a2fc96441788fba1e4709d63677f34ed8e321dae `forEachSymbol` was
replaced with a `llvm::iterator_range`.
Then in
e9262edf0d11a907763098d8e101219ccd9c43e9 we came full circle
and the `llvm::iterator_range` was replaced with a `symbols()` accessor
that was identical the original `getSymbols()`.
`getSymbols` also matches the name used elsewhere in the ELF linker as
well as in both COFF and wasm backend (e.g. `InputFiles.h` and
`SyntheticSections.h`)
Differential Revision: https://reviews.llvm.org/D130787
Daniel Grumberg [Mon, 1 Aug 2022 13:55:08 +0000 (14:55 +0100)]
[clang][ExtractAPI] Record availability information on all platforms
Currently ExtractAPI only emits availability information for the
current platform. This makes it easy for clients to get all availability
information for a given symbol in one invocation as opposed to having to invoke
clang once per-platform and then merge the symbol-graphs.
Differential Revision: https://reviews.llvm.org/D130918
Nico Weber [Fri, 19 Aug 2022 21:53:36 +0000 (17:53 -0400)]
Revert "[NFC] Precommit test for D132255."
This reverts commit
01e3a376955864be6c20fe1134107eb4aa5f2e9c.
Breaks tests on mac and win, see comments on https://reviews.llvm.org/D132255
Guillaume Chatelet [Fri, 19 Aug 2022 21:51:40 +0000 (21:51 +0000)]
[libc][NFC] Move blockstore out of the CPP folder
Philip Reames [Fri, 19 Aug 2022 21:39:19 +0000 (14:39 -0700)]
[RISCV] Add test coverage for 64 bit splat constants
Guillaume Chatelet [Fri, 19 Aug 2022 21:39:02 +0000 (21:39 +0000)]
[libc][NFC] Use STL case for bitset and simplify implementation
eahcmrh [Fri, 19 Aug 2022 20:26:38 +0000 (22:26 +0200)]
[clang-tidy] Fix for bugprone-sizeof-expression PR57167
This addresses a change in behavior of the bugprone-sizeof-expression
checker after upstream commit
15f3cd6bfc6, which cleaned up
ElaboratedType sugaring in the AST. This restores (mostly) the
beahvior of the checker prior to that commit, which may or may not have
been consistent with the intent of the checker, but at least gave a
tolerable level of what users would consider false positives.
Bug: https://github.com/llvm/llvm-project/issues/57167
Reviewed By: mizvekov, aaron.ballman
Differential Revision: https://reviews.llvm.org/D131926
Change-Id: Ibe5aad77ad00977134aa7fa67efbbd6bd725fd79
Guillaume Chatelet [Fri, 19 Aug 2022 21:10:12 +0000 (21:10 +0000)]
[reland][libc][NFC] Use STL case for bit
Eli Friedman [Fri, 19 Aug 2022 21:19:24 +0000 (14:19 -0700)]
Fix reverse-iteration buildbot.
A couple of instances of iterating over maps snuck in while the bot was
down; fix them to use maps with deterministic iteration.
Guillaume Chatelet [Fri, 19 Aug 2022 21:17:48 +0000 (21:17 +0000)]
Revert "[libc][NFC] Use STL case for bit"
This reverts commit
7ba14b8611df1172d92d60bf19870e98a92e7a3a.
Guillaume Chatelet [Fri, 19 Aug 2022 21:10:12 +0000 (21:10 +0000)]
[libc][NFC] Use STL case for bit
Craig Topper [Fri, 19 Aug 2022 18:42:40 +0000 (11:42 -0700)]
[RISCV] Move xori creation for scalar setccs to lowering.
This patch enables expansion or custom lowering for some integer
condition codes so that any xori that is needed is created before
the last DAG combine to enable optimization.
I've seen cases where we end up with
(or (xori (setcc), 1), (xori (setcc), 1)) which we would ideally
convert to (xori (and (setcc), (setcc)), 1). This patch doesn't
accomplish that yet, but it should allow us to add DAG
combines as follow ups. Example https://godbolt.org/z/Y4qnvsq1b
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D131729
Peter Klausler [Fri, 19 Aug 2022 20:33:50 +0000 (13:33 -0700)]
[flang] Add a placeholder argument for a format descriptor on IO calls
Author: vdonaldson
Differential Revision: https://reviews.llvm.org/D132259
Arthur Eubanks [Mon, 15 Aug 2022 21:48:00 +0000 (14:48 -0700)]
[llvm-reduce] Move most debugging output behind --verbose
This should cut down on the visual noise when reducing. Still keep output when we run a pass or when we successfully reduce.
Notably, this also suppresses redirecting the test output to stdout/stderr.
Reviewed By: regehr
Differential Revision: https://reviews.llvm.org/D131922
Mingming Liu [Wed, 3 Aug 2022 06:21:52 +0000 (23:21 -0700)]
[AArch64] Change aarch64_neon_pmull{,64} intrinsic ISel through a new
SDNode.
How:
1) Add AArch64ISD::PMULL SDNode, and extend aarch64_neon_pmull intrinsic
tablegen pattern for this SDNode.
2) For aarch64_neon_pmull64, canonicalize i64 operands to v1i64 vectors
during legalization.
3) For {aarch64_neon_pmull, aarch64_neon_pmull64}, combine intrinsic to
SDNode.
Why
1) Adding the SDNode makes it easier to canonicalize i64 inputs (required by
aarch64_neon_pmull64) to vector inputs. Vector inputs carries lane
information, which helps dag-combiner to combine nodes (e.g. rewrite to a
better node to prepare for instruction selection) and instruction-selection
to emit instructions that use higher-half inputs in place
(i.e., no need to move lane 1 content to lane 0).
2) Using the SDNode for aarch64_neon_pmull64 is NFC, yet without this we
have to move the definition of {PMULLv1i64, PMULLv2i64} out of its
current group of records without gains.
Test cases are commented with what is being tested in
`aarch64-pmull2.ll` and `pmull-ldr-merge.ll` under directory
`llvm/test/CodeGen/AArch64`.
Differential Revision: https://reviews.llvm.org/D131047
Mingming Liu [Wed, 3 Aug 2022 06:10:50 +0000 (23:10 -0700)]
[NFC][AArch64] Precommit test to optimize instruction selection for aarch64_neon_pmull64 intrinsic.
Differential Revision: https://reviews.llvm.org/D131045
Siva Chandra Reddy [Fri, 19 Aug 2022 08:15:50 +0000 (08:15 +0000)]
[libc] Install startup files with the install-libc target.
Differential Revision: https://reviews.llvm.org/D132212
Martin Storsjö [Wed, 6 Jul 2022 21:51:19 +0000 (00:51 +0300)]
[libcxx] [test] Fix the transitive_includes test on Windows
Look for both kinds of slashes in include paths output from the
compiler.
Use "diff -w" to do a whitespace insensitive comparison, to ignore
differences in line endings (the python script writes to stdout
in text mode, with crlf newlines).
Differential Revision: https://reviews.llvm.org/D129428
Philip Reames [Fri, 19 Aug 2022 20:07:12 +0000 (13:07 -0700)]
[RISCV] Add cost model coverage of store of constant [nfc]
Wei Yi Tee [Fri, 19 Aug 2022 13:37:33 +0000 (13:37 +0000)]
[clang][dataflow] Mark `getDeclCtx` function in dataflow `Environment` `const`.
Differential Revision: https://reviews.llvm.org/D132229
Rainer Orth [Fri, 19 Aug 2022 19:59:57 +0000 (21:59 +0200)]
Reland "[mlir][test] Fix IR/AttributeTest.cpp compilation on Solaris"
The `IR/AttributeTest.cpp` test fails to compile on Solaris:
```
/vol/llvm/src/llvm-project/local/mlir/unittests/IR/AttributeTest.cpp:223:36: error: no matching function for call to 'allocate'
AttrT::get(type, "resource", UnmanagedAsmResourceBlob::allocate(data));
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/vol/llvm/src/llvm-project/local/mlir/unittests/IR/AttributeTest.cpp:237:3: note: in instantiation of function template specialization 'checkNativeAccess<mlir::detail::DenseResourceElementsAttrBase<int8_t>, char>' requested here
checkNativeAccess<AttrT, T>(builder.getContext(), llvm::makeArrayRef(data),
^
/vol/llvm/src/llvm-project/local/mlir/unittests/IR/AttributeTest.cpp:258:3: note: in instantiation of function template specialization 'checkNativeIntAccess<mlir::detail::DenseResourceElementsAttrBase<int8_t>, char>' requested here
checkNativeIntAccess<DenseI8ResourceElementsAttr, int8_t>(builder, 8);
^
/vol/llvm/src/llvm-project/local/mlir/include/mlir/IR/AsmState.h:221:3: note: candidate template ignored: requirement '!std::is_same<char, char>::value' was not satisfied [with T = char]
allocate(ArrayRef<T> data, bool dataIsMutable = false) {
^
/vol/llvm/src/llvm-project/local/mlir/include/mlir/IR/AsmState.h:214:26: note: candidate function not viable: requires at least 2 arguments, but 1 was provided
static AsmResourceBlob allocate(ArrayRef<char> data, size_t align,
^
```
Because `char` is `signed` by default on Solaris and `int8_t` is
`char`. `std::is_same<int8_t, char>` is `true` unlike elsewhere, rejecting
the one-arg `allocate` overload.
Fixed by renaming the two overloads to avoid the ambiguity.
Tested on `amd64-pc-solaris2.11` ,`sparcv9-sun-solaris2.11`, and
`x86_64-pc-linux-gnu`.
Differential Revision: https://reviews.llvm.org/D131148
Philip Reames [Fri, 19 Aug 2022 19:52:56 +0000 (12:52 -0700)]
[RISCV] Factor out getVectorImmCost cost after 0e7ed3 [nfc]
Aaron Ballman [Fri, 19 Aug 2022 19:51:53 +0000 (15:51 -0400)]
Update coding standards for constexpr if statements; NFC
We currently suggest that users not use an else clause after a return
statement in a prior if branch. e.g.,
if (foo)
return 1;
else // Should remove this else clause
return 10;
however, this suggestion is incorrect for a constexpr if statement
because one of the two branches will be a discarded statement and thus
can impact template instantiation behavior. This updates the coding
standard to make it clear that it's okay to have a return after an else
in a constexpr if statement.
I think this is an NFC change to the intent of the rule, which is why
I've not started an RFC for the changes.
Differential Revision: https://reviews.llvm.org/D132232
Nick Desaulniers [Fri, 19 Aug 2022 19:40:24 +0000 (12:40 -0700)]
[MachineVerifier] add checks for INLINEASM_BR
Test for a case we observed after the initial implementation of D129997
landed, in which case we observed a crash while building the ppc64le
Linux kernel. In that case, we had one block with two exits, both to the
same successor. Removing one of the exits corrupted the
successor/predecessor lists.
So when we have an INLINEASM_BR, check a few things for each indirect
target:
1. that it exists.
2. that it is listed in our successors.
3. that its predecessor list contains the parent MBB of INLINEASM_BR.
This would have caught the regression discovered after D129997 landed,
after the pass that was problematic (early-tailduplication) rather than
getting a stack trace in a later pass (regalloc) that doesn't understand
the anomaly and crashes.
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D130290
Erich Keane [Fri, 19 Aug 2022 19:37:04 +0000 (12:37 -0700)]
Revert "Re-apply "Deferred Concept Instantiation Implementation"""
This reverts commit
d483730d8c3fa2e0d4192b2f3c61c761b124e6ad.
This allegedly breaks a significant part of facebooks internal build.
Reverting while we wait for them to provide a reproducer of this from
@wlei.
Alex Bradbury [Fri, 19 Aug 2022 17:16:24 +0000 (18:16 +0100)]
[clang][RISCV] Fix incorrect ABI lowering for inherited structs under hard-float ABIs
The hard float ABIs have a rule that if a flattened struct contains
either a single fp value, or an int+fp, or fp+fp then it may be passed
in a pair of registers (if sufficient GPRs+FPRs are available).
detectFPCCEligibleStruct and the helper it calls,
detectFPCCEligibleStructHelper examine the type of the argument/return
value to determine if it complies with the requirements for this ABI
rule.
As reported in bug #57084, this logic produces incorrect results for C++
structs that inherit from other structs. This is because only the fields
of the struct were examined, but enumerating RD->fields misses any
fields in inherited C++ structs. This patch corrects that issue by
adding appropriate logic to enumerate any included base structs.
Differential Revision: https://reviews.llvm.org/D131677
Bill Wendling [Thu, 18 Aug 2022 21:52:49 +0000 (14:52 -0700)]
[X86][AArch64][NFC] Simplify querying used argument registers
Registers used for arguments are listed as "live-ins" into the starting
basic block. This means we don't have to go through a potentially
expensive search through all possible argument registers when we only
care about used argument registers.
Differential Revision: https://reviews.llvm.org/D132181
jeff [Thu, 28 Jul 2022 18:09:14 +0000 (11:09 -0700)]
[InferAddressSpaces] [AMDGPU] Add inference for flat_atomic intrinsics
Certain address space dependent optimizations, like SeperateConstOffsetFromGEP, assume agreement between the address space of the recursive uses and the address space of the def. If this assumption is invalid, then optimizations may or may not be correct depending on properties of an address space for a given target, the address spaces of recursive uses, and the optimization being done.
This patch infers the previous address space for flat_atomic ptr arguments. As a result, the address spaces of the uses in flat_atomic cases will agree with the address space in recursive defs. If this results in non-flat address space, then isel may infer a different intrinsic. For example, if the result is a flat_atomic using global address space, then it will be lowered to the corresponding global_atomic intrinsic.
Change-Id: Ifcd981709dc2ea94d4acbcb84efe7176593ec8c7
Denis Antrushin [Fri, 19 Aug 2022 17:58:04 +0000 (00:58 +0700)]
[NFC] Precommit test for D132255.
Michael Buch [Fri, 19 Aug 2022 18:31:14 +0000 (19:31 +0100)]
Revert "[lldb] [gdb-remote] Include PID in vCont packets if multiprocess" - Part 2
This reverts commit
ccb9d4d4addc2fb2aa94cf776d43d8be35365272.
Reverts the associated tests
Simon Pilgrim [Fri, 19 Aug 2022 18:07:02 +0000 (19:07 +0100)]
[X86] Fix znver1 256-bit ALU/Logic/Blend uop counts
ymm instructions are double pumped on znver1 - noticed while trying to review size-latency costkinds numbers for D132216
Matches AMD 17h SOG / Agner / uops.info
Mats Petersson [Fri, 19 Aug 2022 12:34:48 +0000 (13:34 +0100)]
[Flang]Fix another way to crash SimplifyIntrinsics
Under some conditions, the defining op may be NULL, so
accept that rahter than try to use it and crash!
Adds test to prevent regression
Fixes github issue #57201
Reviewed By: vzakhari
Differential Revision: https://reviews.llvm.org/D132238
Chris Bieneman [Fri, 19 Aug 2022 22:21:49 +0000 (17:21 -0500)]
[NFC] Fix warning in asserts build
When asserts are enabled a warning for implicit conversion from 64-bit to
32-bit integer occurs here.
Philip Reames [Fri, 19 Aug 2022 17:37:39 +0000 (10:37 -0700)]
[RISCV] Correct costs for vector ceil/floor/trunc/round
Add vector costs for ceil/floor/trunc/round. As can be seen in the tests, the prior default costs were a significant under estimate of the actual code generated.
These costs are computed by simply generating code with the current backend, and then counting the number of instructions. I discount one vsetvli, and ignore the return.
Differential Revision: https://reviews.llvm.org/D131967
Michael Buch [Fri, 19 Aug 2022 17:05:04 +0000 (18:05 +0100)]
Revert "[lldb] [gdb-remote] Include PID in vCont packets if multiprocess"
This reverts commit
ccb9d4d4addc2fb2aa94cf776d43d8be35365272.
https://reviews.llvm.org/D131758
Differential Revision: https://reviews.llvm.org/D132250
Saleem Abdulrasool [Fri, 5 Aug 2022 16:52:03 +0000 (16:52 +0000)]
MC: make section classification a bit more thorough
This does *NOT* change the emitted section flags in any way. This only
impacts the internal classification of sections.
Extend the section classification in LLVM for ELF targets. This has one
important change: we now classify sections as text by default rather
than readonly. This matches the behaviour for GAS better.
Ensure that any section that has a writable attribute set is not treated
as readonly. We also special case any section named `.debug_` which is
reserved for DWARF as metadata. In the case none of the attributes are
set (or because no attributes were provided), consult the section name
for classification. We match the well known names and classify the
section accordingly. Any remaining section is now classified as text.
This change allows us to classify sections in the MC layer more
precisely which is needed for subsequent changes for handling target
specific behaviour.
Differential Revision: https://reviews.llvm.org/D131270
Reviewed By: @echristo
Simon Pilgrim [Fri, 19 Aug 2022 16:37:26 +0000 (17:37 +0100)]
Fix MSVC "not all control paths return a value" warning
Sanjay Patel [Fri, 19 Aug 2022 16:21:11 +0000 (12:21 -0400)]
[EarlyCSE][ConstantFolding] do not constant fold atan2(+/-0.0, +/-0.0)
These may raise an error (set errno) as discussed in the post-commit
comments for D127964, so we can't fold away the call and potentially
alter that behavior.
Adrian Prantl [Fri, 19 Aug 2022 16:22:19 +0000 (09:22 -0700)]
Revert "[lldb] [test] Add synchronization to TestContinue"
This reverts commit
7aadecae404b8d47aabdd874e9018a76fd4d1ffa.
I'm reverting this commit because it appears to break the green dragon
incremental LLDB bot.
https://reviews.llvm.org/D131758
See LLDB Incremental buildbot: https://green.lab.llvm.org/green/view/LLDB/job/lldb-cmake/46215/execution/node/70/log/
Adrian Prantl [Fri, 19 Aug 2022 16:21:55 +0000 (09:21 -0700)]
Revert "[lldb] [test] Disable new CommunicationTests on Windows"
This reverts commit
d38985a36be8b0165787f8893b3d2b0f831d1e83.
because I'm also reverting D131758.
Sanjay Patel [Fri, 19 Aug 2022 16:18:21 +0000 (12:18 -0400)]
[EarlyCSE][ConstantFolding] add tests for atan2 with zero args; NFC
Adrian Prantl [Fri, 19 Aug 2022 01:38:52 +0000 (18:38 -0700)]
Fix UB in DIExpression::appendOffset()
The absolute value of 0x8000000000000000 does not fit into an int64_t
and UBSan tells us that by crashing.
rdar://
98799670
Differential Revision: https://reviews.llvm.org/D132194
Craig Topper [Fri, 19 Aug 2022 15:59:49 +0000 (08:59 -0700)]
[RISCV] Use Triple::isRISCV/isRISCV32/isRISCV64 helps in some places. NFC
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D132197
isuckatcs [Fri, 19 Aug 2022 15:50:49 +0000 (17:50 +0200)]
[analyzer][NFC] Be more descriptive when we replay without inlining
This patch adds a ProgramPointTag to the EpsilonPoint created
before we replay a call without inlining.
Differential Revision: https://reviews.llvm.org/D132246
Denis Fatkulin [Fri, 19 Aug 2022 16:00:54 +0000 (19:00 +0300)]
[clang][index] Index unresolved member expression as reference
Unresolved member expressions aren't indexed as references.
Example code:
```
struct Foo {
template <typename T> void bar(T t);
};
template <typename T> void test(Foo F, T t) {
F.bar(t); // Not indexed
}
```
Reviewed By: hokein
Differential Revision: https://reviews.llvm.org/D131091
Craig Topper [Fri, 19 Aug 2022 15:53:43 +0000 (08:53 -0700)]
[RISCV] Add passthru operand to RISCVISD::SETCC_VL.
Use it to the fix a bug in the fceil/ffloor lowerings. We were
setting the passthru to IMPLICIT_DEF before and using a mask
agnostic policy. This means where the incoming bits in
the mask were 0 they could be anything in the outgoing mask. We
want those bits in the outgoing mask to be 0. This means we need to
pass the input mask as the passthru.
This generates worse code because we are unable to allocate the
v0 register to the output due to an earlyclobber constraint. We
probably need a special TIED pseudoinstruction and probably custom
isel since you can't use V0 twice in the input pattern.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D132058
Craig Topper [Fri, 19 Aug 2022 15:15:55 +0000 (08:15 -0700)]
[RISCV] Prefer vnsrl.wi v8, v8, 0 over vnsrl.wx v8, v8, x0.
I have a couple data points that some microarchitectures prefer
the immediate 0 over x0. Does anyone know of microarchitectures
where the opposite is true?
Unfortunately, this is different than the vncvt.x.x.w alias
from the spec. Perhaps the alias was poorly chosen if x0 isn't
as optimal as immediate 0 on all microarchitectures.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D132041
Alexey Bataev [Mon, 15 Aug 2022 17:26:45 +0000 (10:26 -0700)]
[SLP]Delay vectorization of postponable values for instructions with no users.
SLP vectorizer tries to find the reductions starting the operands of the
instructions with no-users/void returns/etc. But such operands can be
postponable instructions, like Cmp, InsertElement or InsertValue. Such
operands still must be postponed, vectorizer should not try to vectorize
them immediately.
Differential Revision: https://reviews.llvm.org/D131965
Guillaume Chatelet [Thu, 18 Aug 2022 09:39:47 +0000 (09:39 +0000)]
[reland][NFC][libc] rearrange aarch64 memset code to better match new implementation
Differential Revision: https://reviews.llvm.org/D132121
Christopher Bate [Tue, 16 Aug 2022 23:02:18 +0000 (17:02 -0600)]
[mlir][Affine] Add affine.delinearize_index operation
This change adds a new AffineDelinearizeIndexOp to the affine dialect.
The operation accepts an index type as well as a basis (array of index
values) representing how the index should be decomposed into a
multi-index. The decomposition obeys a canonical semantic that treats
the final basis element as "fastest varying" and the first basis element
as "slowest varying". A naive lowering of the operation using a sequence
of AffineApplyOps is given.
RFC was discussed on discourse here: https://discourse.llvm.org/t/rfc-tensor-extracting-slices-from-tensor-collapse-shape/64034
Reviewed By: bondhugula, nicolasvasilache
Differential Revision: https://reviews.llvm.org/D131997
Alexey Bataev [Thu, 2 Jun 2022 14:26:33 +0000 (07:26 -0700)]
[SLP]Cost for a constant buildvector.
In many cases constant buildvector results in a vector load from a
constant/data pool. Need to consider this cost too.
Differential Revision: https://reviews.llvm.org/D126885
Guillaume Chatelet [Fri, 19 Aug 2022 15:02:16 +0000 (15:02 +0000)]
Revert "[NFC][libc] rearrange aarch64 memset code to better match new implementation"
This reverts commit
4d931b6e1e7e6003fa6c68aec9223b06e31c982d.
Wei Yi Tee [Tue, 16 Aug 2022 12:34:42 +0000 (12:34 +0000)]
[clang][dataflow] Debug string for value kinds.
Differential Revision: https://reviews.llvm.org/D131891
Sam McCall [Fri, 19 Aug 2022 13:53:50 +0000 (15:53 +0200)]
[pseudo] Start rules are `_ := start-symbol EOF`, improve recovery.
Previously we were calling glrRecover() ad-hoc at the end of input.
Two main problems with this:
- glrRecover() on two separate code paths is inelegant
- We may have to recover several times in succession (e.g. to exit from
nested scopes), so we need a loop at end-of-file
Having an actual shift action for an EOF terminal allows us to handle
both concerns in the main shift/recover/reduce loop.
This revealed a recovery design bug where recovery could enter a loop by
repeatedly choosing the same parent to identically recover from.
Addressed this by allowing each node to be used as a recovery base once.
Differential Revision: https://reviews.llvm.org/D130550
Guillaume Chatelet [Thu, 18 Aug 2022 09:39:47 +0000 (09:39 +0000)]
[NFC][libc] rearrange aarch64 memset code to better match new implementation
Differential Revision: https://reviews.llvm.org/D132121
Muhammad Usman Shahid [Fri, 19 Aug 2022 14:46:29 +0000 (10:46 -0400)]
Missing tautological compare warnings due to unary operators
The patch mainly focuses on the no warnings for -Wtautological-compare.
It work fine for the positive numbers but doesn't for the negative
numbers. This is because the warning explicitly checks for an
IntegerLiteral AST node, but -1 is represented by a UnaryOperator with
an IntegerLiteral sub-Expr.
Fixes #42918
Differential Revision: https://reviews.llvm.org/D130510
Alexey Bataev [Fri, 19 Aug 2022 12:13:25 +0000 (05:13 -0700)]
[COST][NFC]Introduce OperandValueKind in getMemoryOpCost, NFC.
Added OperandValueKind OpdInfo parameter to getMemoryOpCost functions to
better estimate cost with immediate values.
Part of D126885.
Michał Górny [Fri, 19 Aug 2022 14:22:55 +0000 (16:22 +0200)]
[lldb] [test] Disable new CommunicationTests on Windows
Sponsored by: The FreeBSD Foundation
Timm Bäder [Fri, 19 Aug 2022 14:13:46 +0000 (16:13 +0200)]
[clang][Interp] Rename Integral::T to Integral::ReprT
Just 'T' is a bit generic and causes confusion.
David Sherwood [Fri, 19 Aug 2022 11:11:27 +0000 (12:11 +0100)]
[SVE][LoopVectorize][NFC] Tidy up some tests
Whilst writing a patch to add extra tail-folding RUN lines to
existing tests I noticed a few areas where they can be
cleaned up a little:
1. scalable-reductions.ll: fmin_fast does not mark fcmp as fast.
2. sve-inductions-unusual-types.ll: remove direct references to
SSA variable names.
3. sve-strict-fadd-cost.ll: don't force vector width so we see
costs for different VFs in one go. This will be important for
the follow-on patch.
4. sve-vector-reverse.ll,vector-reverse-mask4.ll: add noalias
keyword to simplify IR.
4. sve-widen-gep.ll,sve-widen-phi.ll: regenerate using script.
These changes will make the subsequent patch adding RUN lines much
easier to review!
Differential Revision: https://reviews.llvm.org/D132219
Simon Tatham [Fri, 19 Aug 2022 14:07:55 +0000 (15:07 +0100)]
[libcxxabi] Fix alignment of pointers returned by fallback_malloc
This aligns the ``heap[]`` array in ``fallback_malloc.cpp`` to ensure
that it can be safely cast to ``heap_node*``, and also adjusts the
allocation algorithm to ensure that every allocated block has the
alignment requested by ``__attribute__((aligned))``, by putting the
block's ``heap_node`` header 4 bytes before an aligned address.
Patch originally by Eric Fiselier: this is an updated version of
D12669, which was never landed.
Reviewed By: ldionne, #libc_abi
Differential Revision: https://reviews.llvm.org/D129842
Timm Bäder [Tue, 9 Aug 2022 06:08:48 +0000 (08:08 +0200)]
[clang][Interp] Implement inv and neg unary operations
Implement negating and inverting values. Also implement
IntegralToBoolean casts so the operations are easier to test.
Differential Revision: https://reviews.llvm.org/D132098
Max Kazantsev [Fri, 19 Aug 2022 13:51:57 +0000 (20:51 +0700)]
[Test] Add test for miscompile described in PR57247
Max Kazantsev [Fri, 19 Aug 2022 13:51:06 +0000 (20:51 +0700)]
Revert "[SCEV] Prove condition invariance via context"
This reverts commit
a3d1fb3b59b473e4f262a05f187de6474b7721e7.
Reverting until investigation of https://github.com/llvm/llvm-project/issues/57247
has concluded.
Ellis Hoag [Fri, 19 Aug 2022 13:46:22 +0000 (06:46 -0700)]
Revert "Revert "[compiler-rt] Fix check for cross-compiling""
This reverts commit
18f6b05e0a5a4197bac787f5522669576c134869.
This is a reland of https://reviews.llvm.org/D132130 which I incorrectly
thought had broken the builds.
Differential Revision: https://reviews.llvm.org/D132230
Haojian Wu [Fri, 19 Aug 2022 13:53:16 +0000 (15:53 +0200)]
[pseudo] NFC, remove redundant ;
Michał Górny [Fri, 19 Aug 2022 13:49:35 +0000 (15:49 +0200)]
[lldb] [test] Add synchronization to TestContinue
Sponsored by: The FreeBSD Foundation
Michał Górny [Fri, 19 Aug 2022 10:30:50 +0000 (12:30 +0200)]
[lldb] [Core] Harmonize Communication::Read() returns w/ thread
Harmonize the status and error values of Communication::Read() when
running with and without read thread. Prior to this change, Read()
would return eConnectionStatusSuccess if read thread was enabled
and the read timed out or reached end-of-file, rather than
the respective states that are returned if read thread was disabled.
Now, it correctly returns eConnectionStatusTimedOut
and eConnectionStatusEndOfFile, and sets the error respectively.
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.llvm.org/D132217
Nikolas Klauser [Fri, 19 Aug 2022 11:08:01 +0000 (13:08 +0200)]
[libc++][NFC] Rename the constexpr macros
This was discussed on Discord with the consensus that we should rename the macros.
Reviewed By: ldionne, Mordante, var-const, avogelsgesang, jloser, #libc
Spies: libcxx-commits
Differential Revision: https://reviews.llvm.org/D131498
Sam McCall [Wed, 13 Jul 2022 14:27:36 +0000 (16:27 +0200)]
[Sema] Tweak diagnostic logic so suppress-in-header logic works in tools too.
Certain idioms are ignored by -Wunused in header files only.
The current "is a header" check assumes that if headers are the main file, we're
building a PCH or a module or something. However in tools we may be parsing the
header in its own right, but still want to treat it as a header.
Fixes https://github.com/clangd/vscode-clangd/issues/360
Differential Revision: https://reviews.llvm.org/D129642
Sam McCall [Fri, 19 Aug 2022 13:15:37 +0000 (15:15 +0200)]
[pseudo] Changes omitted from previous commit
Sam McCall [Fri, 19 Aug 2022 13:00:59 +0000 (15:00 +0200)]
[pseudo] Perform unconstrained reduction prior to recovery.
Our GLR uses lookahead: only perform reductions that might be consumed by the
shift immediately following. However when shift fails and so reduce is followed
by recovery instead, this restriction is incorrect and leads to missing heads.
In turn this means certain recovery strategies can't be made to work. e.g.
```
ns := NAMESPACE { namespace-body } [recover=Skip]
ns-body := namespace_opt
```
When `namespace { namespace {` is parsed, we can recover the inner `ns` (using
the `Skip` strategy to ignore the missing `}`). However this `namespace` will
not be reduced to a `namespace-body` as EOF is not in the follow-set, and so we
are unable to recover the outer `ns`.
This patch fixes this by tracking which heads were produced by constrained
reduce, and discarding and rebuilding them before performing recovery.
This is a prerequisite for the `Skip` strategy mentioned above, though there are
some other limitations we need to address too.
Reviewed By: hokein
Differential Revision: https://reviews.llvm.org/D130523
Sam McCall [Fri, 19 Aug 2022 12:51:36 +0000 (14:51 +0200)]
[clangd] Support hover on __func__ etc (PredefinedExpr)
Expose these as variables as that's what the standard calls them (and D131175).
To make this work, we also fix a bug in SelectionTree: PredefinedExpr has
an implicit/invisible StringLiteral, and SelectionTree should not traverse
implicit things.
Reviewed By: ckandeler
Differential Revision: https://reviews.llvm.org/D132135
Kristof Beyls [Thu, 18 Aug 2022 12:58:05 +0000 (14:58 +0200)]
Add guidance for what to put in community calendar invites
Differential Revision: https://reviews.llvm.org/D132134
Stefan Pintilie [Tue, 16 Aug 2022 16:08:33 +0000 (11:08 -0500)]
[PowerPC] Fix bugs in sign-/zero-extension elimination
This patch fixes the following two bugs in `PPCInstrInfo::isSignOrZeroExtended` helper, which is used from sign-/zero-extension elimination in PPCMIPeephole pass.
- Registers defined by load with update (e.g. LBZU) were identified as already sign or zero-extended. But it is true only for the first def (loaded value) and not for the second def (i.e. updated pointer).
- Registers defined by ORIS/XORIS were identified as already sign-extended. But, it is not true for sign extension depending on the immediate (while it is ok for zero extension).
To handle the first case, the parameter for the helpers is changed from `MachineInstr` to a register number to distinguish first and second defs. Also, this patch moves the initialization of PPCMIPeepholePass to allow mir test case.
Reviewed By: nemanjai
Differential Revision: https://reviews.llvm.org/D40554