Gert Wollny [Sat, 21 Nov 2020 15:20:01 +0000 (16:20 +0100)]
r600/sfn: Add lowering pass to convert load_interpolated to load for POS
the values are loaded directly from a register and the specification of
parycentrics is only in the way.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7715>
Gert Wollny [Mon, 23 Nov 2020 17:49:08 +0000 (18:49 +0100)]
r600/sfn: fix component loading from fixed buffer ID
Fixes:
18e97817148eb376274a8749c03b45c2f817c139
r600/sfn: Use load_ubo_vec4 lowering pass
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7715>
Boris Brezillon [Thu, 26 Nov 2020 14:35:20 +0000 (15:35 +0100)]
panfrost: Update the resource layout when doing a tile -> linear conversion
If we don't do that the stride in texture/framebuffer descriptors
is wrong, leading to page faults when those buffers are accessed.
Fixes:
00360cd5c85e ("panfrost: Calculate the row stride at resource creation time")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7797>
Iago Toral Quiroga [Thu, 26 Nov 2020 09:44:30 +0000 (10:44 +0100)]
v3dv: extend the list of formats supported by the TFU unit
Also, update the hardware version assert check to match what we are
really requiring for Vulkan.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7788>
Iago Toral Quiroga [Wed, 25 Nov 2020 13:16:19 +0000 (14:16 +0100)]
v3dv: batch buffer to image copies with the texel buffer path if possible
When copying multiple regions that have the same image subresource we are
effectively copying various rects across the same layer range, so we can
batch together all the rects to copy for each layer in a single job.
This allows us to significantly reduce CPU overhead when recording the
command, as we need to produce less jobs and allocate less descriptor
sets. It also offers smaller gains in execution time due to the reduced
job count.
A stress test where we copy 10 subrects of an image in a loop 100 time,
choosing regions that will involve the texel buffer path, we get these
results:
| Recording Time | Execution Time |
----------|----------------|----------------|
master | 3.021s | 0.112s |
----------|----------------|----------------|
patch | 0.163s | 0.080s |
----------|----------------|----------------|
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7782>
Iago Toral Quiroga [Thu, 26 Nov 2020 07:02:36 +0000 (08:02 +0100)]
v3dv: fix leak in the buffer to image copy via texel buffer
Fixes:
ba69c36ada5 ("v3dv: add a buffer to image copy path using a texel buffer")
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7782>
Marek Olšák [Mon, 9 Nov 2020 22:52:45 +0000 (17:52 -0500)]
radeonsi: implement GS fast launch for indexed triangle strips
This increases performance for indexed triangle strips up to +100%.
In practice, it's limited by memory bandwidth and compute power,
so 256-bit memory bus and a lot of CUs are recommended.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7681>
Bas Nieuwenhuizen [Mon, 19 Oct 2020 00:53:39 +0000 (02:53 +0200)]
radv: Fix a hang on CB change by adding flushes.
This workaround fixes a hang while loading a renderdoc trace for me.
Since the workload does 1 mip per cmdbuffer it is quite hard to confirm
what exactly the conditions for the hang are but this is the most
restrictive set I found and it corresponds to a workaround in AMDVLK as
well.
CC: mesa-stable
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7210>
Erik Faye-Lund [Thu, 26 Nov 2020 18:26:23 +0000 (19:26 +0100)]
docs: document new zink-flag
We forgot to document this previously, so let's add it now.
Fixes:
feb9462bb19 ("zink: Added inbuilt debug logging from the VK_LAYER_LUNARG_standard_validation layer.")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7802>
Rhys Perry [Mon, 14 Sep 2020 18:51:41 +0000 (19:51 +0100)]
nir: make intrinsic order in nir_print consistent
Make it consistent with nir_intrinsics.py, the unlabelled indices just
before it and the intrinsic builders.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6587>
Rhys Perry [Thu, 3 Sep 2020 18:44:00 +0000 (19:44 +0100)]
radv: use intrinsic builders
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6587>
Rhys Perry [Thu, 3 Sep 2020 16:20:17 +0000 (17:20 +0100)]
nir: use intrinsic builders
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6587>
Rhys Perry [Mon, 7 Sep 2020 13:17:14 +0000 (14:17 +0100)]
glsl_to_nir: use intrinsic builders
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6587>
Rhys Perry [Mon, 7 Sep 2020 13:16:57 +0000 (14:16 +0100)]
spirv: use intrinsic builders
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6587>
Rhys Perry [Mon, 7 Sep 2020 12:55:38 +0000 (13:55 +0100)]
nir: add generated intrinsic builders
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6587>
Rhys Perry [Mon, 14 Sep 2020 18:56:48 +0000 (19:56 +0100)]
nir: move nir_load_system_value() to nir_builder.h
To make review easier.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6587>
Rhys Perry [Mon, 14 Sep 2020 18:57:25 +0000 (19:57 +0100)]
nir: remove useless nir_builder_opcodes.h include
This is included earlier in the file.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6587>
Rhys Perry [Mon, 7 Sep 2020 12:35:41 +0000 (13:35 +0100)]
nir: add destination bit-size information to more intrinsics
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6587>
Rhys Perry [Mon, 7 Sep 2020 12:25:59 +0000 (13:25 +0100)]
nir: add bit_size_src for when the destination bit size matches a source
If bit_size_src is not -1, then it's the index of the source the
destination bit size can be expected to match. This will be useful for
generating intrinsic builders
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6587>
Rhys Perry [Tue, 24 Nov 2020 12:51:59 +0000 (12:51 +0000)]
nir: use a single canonical list of intrinsic indices
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6587>
Rhys Perry [Thu, 10 Sep 2020 10:58:04 +0000 (11:58 +0100)]
nir: fix sampler_lod_parameters_pan indices
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Fixes:
deaebc82a73 "nir: Add load_sampler_lod_paramaters_pan intrinsic"
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6587>
Danylo Piliaiev [Thu, 26 Nov 2020 12:05:59 +0000 (14:05 +0200)]
freedreno/a6xx: Fix typo in height alignment calculation in a6xx layout
Fixes KHR-GL31.texture_size_promotion.functional
Fixes:
e49748521ec9182e8d2eec823182cc463709123f
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7792>
Danylo Piliaiev [Thu, 19 Nov 2020 09:27:33 +0000 (11:27 +0200)]
freedreno/a6xx: add support for dual-source blending
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7708>
Rhys Perry [Thu, 13 Feb 2020 15:09:53 +0000 (15:09 +0000)]
nir/lower_non_uniform: improve code with the same texture, sampler indices
NIR can't CSE the read_first_invocation intrinsics, so we can end up
creating iand(read_first_invocation(a) == a, read_first_invocation(a) == a)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3813>
Lionel Landwerlin [Thu, 26 Nov 2020 14:37:01 +0000 (16:37 +0200)]
anv: fix descriptor pool leak in VMA object
Quoting the spec :
"When a pool is destroyed, all descriptor sets allocated from the
pool are implicitly freed and become invalid. Descriptor sets
allocated from a given pool do not need to be freed before
destroying that descriptor pool."
This implies we might leak nodes allocated in the vma object.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
0a6d2593b8b63d ("anv: Allocate descriptor buffers from the BO cache")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7796>
Timur Kristóf [Wed, 5 Feb 2020 11:14:00 +0000 (12:14 +0100)]
aco/optimizer: Propagate scc_needed label through p_wqm.
Without this, RA is confused and adds a bunch of unnecessary moves.
Fossil-db results (Navi 10):
Totals from 7658 (5.55% of 137887) affected shaders:
SGPRs: 752488 -> 752392 (-0.01%)
CodeSize:
74046720 ->
73924368 (-0.17%); split: -0.17%, +0.00%
Instrs:
14293916 ->
14263350 (-0.21%); split: -0.21%, +0.00%
Cycles:
1455556728 ->
1438466536 (-1.17%); split: -1.17%, +0.00%
VMEM: 1096736 -> 1094962 (-0.16%); split: +0.03%, -0.19%
SMEM: 448436 -> 448418 (-0.00%); split: +0.00%, -0.01%
SClause: 485501 -> 485495 (-0.00%); split: -0.00%, +0.00%
Copies: 1383769 -> 1353029 (-2.22%); split: -2.22%, +0.00%
Branches: 568247 -> 568451 (+0.04%); split: -0.01%, +0.05%
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7677>
Timur Kristóf [Wed, 18 Nov 2020 20:28:09 +0000 (21:28 +0100)]
aco/optimizer: Only set scc_needed when it is actually needed.
Not every p_cbranch uses the SCC, but our optimizer thought so.
Fixes:
8a32f57fff56b3b94f1b5589feba38016f39427c
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7677>
Andrii Simiklit [Thu, 29 Oct 2020 15:05:19 +0000 (17:05 +0200)]
glsl: avoid an out-of-bound access while setting up a location for variable
It fixes the following valgrind issue:
==141996== Invalid read of size 4
==141996== at 0x61F8806: gl_nir_link_uniforms (gl_nir_link_uniforms.c:1788)
==141996== by 0x60F17AA: gl_nir_link_glsl (gl_nir_linker.c:672)
==141996== by 0x5C1AEDF: st_link_nir (st_glsl_to_nir.cpp:739)
==141996== by 0x5C15574: st_link_shader (st_glsl_to_ir.cpp:172)
==141996== by 0x5C673B0: _mesa_glsl_link_shader (ir_to_mesa.cpp:3117)
==141996== by 0x5E7B61C: link_program (shaderapi.c:1311)
==141996== by 0x5E7B61C: link_program_error (shaderapi.c:1419)
==141996== by 0x5E7CF8A: _mesa_LinkProgram (shaderapi.c:1911)
==141996== by 0x4923D13: stub_glLinkProgram (piglit-dispatch-gen.c:33956)
==141996== by 0x1142C0: link_and_use_shaders (shader_runner.c:1636)
==141996== by 0x1205A6: init_test (shader_runner.c:5347)
==141996== by 0x121555: piglit_init (shader_runner.c:5725)
==141996== by 0x4991C84: run_test (piglit_fbo_framework.c:50)
It can be reproduced on `iris` using the following piglit test:
instance-matching-shader-storage-blocks-align-qualifier-mismatch.shader_test
Closes: #3818
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Fixes:
47c35823 ("glsl: fix up location setting for variables pointing to a UBO's base")
Signed-off-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7376>
Michel Zou [Wed, 25 Nov 2020 14:46:36 +0000 (15:46 +0100)]
glsl: Drop mingw -O1 workaround for GCC>=7.3
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7770>
Vinson Lee [Sun, 22 Nov 2020 06:05:38 +0000 (22:05 -0800)]
scons: Fix build with llvm-12.
This patch fixes these SCons build errors.
/usr/bin/ld: build/linux-x86_64-debug/gallium/auxiliary/libgallium.a(lp_bld_misc.os): in function `llvm::InitializeNativeTarget()':
llvm/Support/TargetSelect.h:118: undefined reference to `LLVMInitializeX86TargetInfo'
/usr/bin/ld: llvm/Support/TargetSelect.h:119: undefined reference to `LLVMInitializeX86Target'
/usr/bin/ld: llvm/Support/TargetSelect.h:120: undefined reference to `LLVMInitializeX86TargetMC'
/usr/bin/ld: build/linux-x86_64-debug/gallium/auxiliary/libgallium.a(lp_bld_misc.os): in function `llvm::InitializeNativeTargetAsmPrinter()':
llvm/Support/TargetSelect.h:132: undefined reference to `LLVMInitializeX86AsmPrinter'
/usr/bin/ld: build/linux-x86_64-debug/gallium/auxiliary/libgallium.a(lp_bld_misc.os): in function `llvm::InitializeNativeTargetDisassembler()':
llvm/Support/TargetSelect.h:156: undefined reference to `LLVMInitializeX86Disassembler'
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7722>
Samuel Pitoiset [Thu, 26 Nov 2020 11:03:55 +0000 (12:03 +0100)]
radv/winsys: fix the sysmem submission path for GFX6
Oops.
Fixes:
cba6ec309ab ("radv: Fix -Wshadow warnings")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7790>
James Park [Thu, 26 Nov 2020 10:05:22 +0000 (02:05 -0800)]
radv: Const aco_compiler_statistic_info usage
Necessary for upcoming const correctness change to aco struct.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7787>
Samuel Pitoiset [Thu, 26 Nov 2020 11:27:10 +0000 (12:27 +0100)]
radv: fix missing initialization of the predication value
It's expected to be 0.
Fixes:
62d9ca696e0 ("radv: use 32-bit predication for conditional rendering on GFX10.3+")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7789>
Alejandro Piñeiro [Tue, 24 Nov 2020 21:25:21 +0000 (22:25 +0100)]
v3dv: remove non-conformant warning
The driver is now Vulkan 1.0 conformant.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7758>
Alejandro Piñeiro [Tue, 24 Nov 2020 21:24:21 +0000 (22:24 +0100)]
docs/features: update list of v3dv supported features
We have been implementing some features without updating the file, and
we even had some that were supported for a while.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
v2: include VK_KHR_wayland_surface as !7303 got merged
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7758>
Pierre-Eric Pelloux-Prayer [Tue, 24 Nov 2020 10:13:48 +0000 (11:13 +0100)]
ac: use bigger storage for ac_arg::arg_index / ac_shader_args::arg_count
AC_MAX_ARGS is now 384 so uint8_t isn't enough.
Fixes:
6f130342658 ("ac/llvm: prepare for passing VS->TCS IO via VGPRs")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7750>
Pierre-Eric Pelloux-Prayer [Mon, 23 Nov 2020 12:48:42 +0000 (13:48 +0100)]
radeonsi/gfx10: flush gfx cs on ngg -> legacy transition
with a sequence like this:
glClear(STENCIL)
glBeginTransformFeedback()
...
glEndTransformFeedback()
glClear(STENCIL)
The second clear sometimes may produce an unexpected result.
Calling si_flush_gfx_cs() when doing ngg -> legacy transition seems to be a
valid workaround (both for the synthetic reproducer and the real Blender bug).
Using flush flags or events (BOTTOM_OF_PIPE_TS, RESET_TO_LOWEST_VGT) didn't help.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2941
Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7750>
James Park [Sat, 31 Oct 2020 23:18:34 +0000 (16:18 -0700)]
util,radv: Cross-platform monotonic condition variable
cnd_t operates on REALTIME clock, and isn't suitable for MONOTONIC use.
Clone the API, and implement using a monotonic clock.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7138>
James Park [Tue, 3 Nov 2020 18:03:13 +0000 (10:03 -0800)]
util/os_time: Safe os_time_get_nano for Windows
Avoid small possibility of reading torn write on 32-bit platforms.
If frequency caching is desired, it's probably better to initialize from
C++ and extern "C" instead. It's not a tremendous optimization though.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7138>
James Park [Wed, 12 Aug 2020 02:28:09 +0000 (19:28 -0700)]
c11/threads: Remove Windows XP support
Enable and remove EMULATED_THREADS_USE_NATIVE_CV. Delete legacy code.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7138>
James Park [Wed, 12 Aug 2020 02:26:39 +0000 (19:26 -0700)]
c11/threads: Remove Win32 null checks
Nonsensical to pass null. glibc doesn't check, and neither should we.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7138>
James Park [Wed, 12 Aug 2020 02:24:12 +0000 (19:24 -0700)]
c11/threads: Fix Win32 timed functions
mtx_timedlock and cnd_timedwait now use relative milliseconds.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7138>
Thong Thai [Mon, 21 Sep 2020 17:56:05 +0000 (13:56 -0400)]
frontends/va/postproc: Convert destination when deinterlacing
When the VAAPI deinterlacing filter is chained with other VAAPI
post-processing filters, the image might get deinterlaced multiple
times, as the filters after the deinterlacing filter might still see an
interlaced buffer.
Signed-off-by: Thong Thai <thong.thai@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6803>
Thong Thai [Mon, 21 Sep 2020 17:53:16 +0000 (13:53 -0400)]
frontends/va/postproc: Use the actual image height when blitting
Updates the height of the blitting parameter to use the actual image
height instead of the buffer height, otherwise when scaling, garbage
lines are shown in the output.
Signed-off-by: Thong Thai <thong.thai@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6803>
Caio Marcelo de Oliveira Filho [Tue, 24 Nov 2020 06:04:51 +0000 (21:04 -0900)]
intel/disasm: Don't rely on FALLTHROUGHTs to print unsupported SFID
The code works but is a bit fragile if we ever add a case that has a
less strict requirement (a smaller gen) than the case above. To avoid
having to reason about this, refactor code to use a variable to
indicate whether the SFID is supported or not.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7742>
Boris Brezillon [Sat, 21 Nov 2020 15:03:32 +0000 (16:03 +0100)]
panfrost: Fix stride calculation for Z32_S8X24/X32_S8X24 formats
Z32_S8X24 variants are actually stored in 2 planes (one per component),
we have to adjust the bytes_per_pixel value accordingly.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Sat, 21 Nov 2020 14:58:41 +0000 (15:58 +0100)]
panfrost: Calculate the row stride at resource creation time
So we don't have to calculate it again when we create a texture or
framebuffer descriptor.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Sat, 21 Nov 2020 14:52:28 +0000 (15:52 +0100)]
panfrost: Fix panfrost_needs_explicit_stride() for block-based formats
The expected stride calculation does not take the block width into
account, thus creating an expected line stride that's bigger than
required. Fix that by dividing the width by the block width.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Sat, 21 Nov 2020 14:44:10 +0000 (15:44 +0100)]
panfrost: Expose panfrost_block_dim()
So we can use it from pan_resource.c to retrieve the tile size based on
a modifier.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Tue, 17 Nov 2020 08:32:40 +0000 (09:32 +0100)]
panfrost: Enable MSAA on bifrost when deqp debug option is set
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Thu, 19 Nov 2020 09:12:53 +0000 (10:12 +0100)]
panfrost: Unconditionally align strides on 64 bytes for linear resources
If we don't do that we end up with DATA_INVALID faults when accessing
3D textures on Bifrost.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Thu, 19 Nov 2020 09:38:09 +0000 (10:38 +0100)]
panfrost: Set the layer stride
Needed for 3D textures.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Thu, 19 Nov 2020 09:35:55 +0000 (10:35 +0100)]
panfrost: Add two helpers to calculate the surface pointer and strides
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Thu, 19 Nov 2020 09:14:42 +0000 (10:14 +0100)]
panfrost: Clarify bit 2:28 meaning in the Midgard texture descriptor
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Wed, 18 Nov 2020 14:22:59 +0000 (15:22 +0100)]
panfrost: Add a minus(1) modifier to the Levels field
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Tue, 17 Nov 2020 11:14:02 +0000 (12:14 +0100)]
panfrost: Increase blit shader BO size on Bifrost
Otherwise we hit 'offset + program->compiled.size < total_size' assert.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Tue, 17 Nov 2020 16:27:40 +0000 (17:27 +0100)]
pan/bi: LOD is a 8.8 fixed point
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Tue, 17 Nov 2020 10:25:41 +0000 (11:25 +0100)]
pan/bi: Always emit a LOD/CUBE word for FETCH instructions
There's no flag/mode to reflect when a LOD is zero on FETCH instructions,
we have to emit the LOD/CUBE word unconditionally.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Tue, 17 Nov 2020 10:23:35 +0000 (11:23 +0100)]
pan/bi: Only update LOD mode on TEX operations
If we don't add this check we clobber fetch mode when a 0 LOD is
specified on a txf instruction.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Tue, 17 Nov 2020 10:20:35 +0000 (11:20 +0100)]
panfrost: Set sample_count when packing bifrost texture descriptors
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Tue, 17 Nov 2020 18:09:26 +0000 (19:09 +0100)]
panfrost: Set depth for 3D textures on Bifrost
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Tue, 17 Nov 2020 18:18:42 +0000 (19:18 +0100)]
panfrost: Fix decoding of texture payloads
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Tue, 17 Nov 2020 10:19:43 +0000 (11:19 +0100)]
panfrost: Get rid of the Sample Count enum
Sample count just needs a log2 modifier. While at it, rename the
"Multisample count" field "Sample count" to be consistent with
other descriptors.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Tue, 17 Nov 2020 19:44:52 +0000 (20:44 +0100)]
panfrost: Stop forcing depth to nr_samples
Those are two different things, and the fact that Midgard use the same
offset in the texture descriptor for both things is just an
implementation detail.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Alyssa Rosenzweig [Mon, 9 Nov 2020 19:31:01 +0000 (14:31 -0500)]
panfrost: Fix RAW8/16/32 component replication
Fixes dEQP-GLES3.functional.fbo.msaa.4_samples.r32f
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Alyssa Rosenzweig [Mon, 9 Nov 2020 19:43:36 +0000 (14:43 -0500)]
panfrost: Account for sample count in tib offsets
I don't know if we have tests for MRT + MSAA but that would hit this.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Tue, 17 Nov 2020 11:12:08 +0000 (12:12 +0100)]
nir: Fix LOD source type for txf_ms instructions
txf_ms takes an integer LOD, not a float.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Rhys Perry [Thu, 12 Nov 2020 14:32:57 +0000 (14:32 +0000)]
aco/ngg: fix division-by-zero in assertion
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7576>
Rhys Perry [Thu, 12 Nov 2020 14:21:00 +0000 (14:21 +0000)]
aco: fix GS with no outputs
With NGG, ngg_gs_known_vtxcnt[0] would be false and ngg_gs_finale() would
assert.
With legacy GS, I don't know why the assertion was there.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7576>
Rhys Perry [Wed, 18 Nov 2020 19:13:19 +0000 (19:13 +0000)]
radv/llvm,aco/ngg: fix large shift exponent in ngg_gs_vertex_lds_addr
When vertices_out=0, we will try to shift 1u by UINT32_MAX.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7576>
Alyssa Rosenzweig [Fri, 13 Nov 2020 22:34:25 +0000 (17:34 -0500)]
pan/bi: Implement shader-db stats
v2: Drop register tracking since it was wrong, and meaningful accounting
is tricky for Bifrost (which wants round robin RA for at least some
registers)... we'll cross that bridge when we get there, possibly
preferring a "max liveness" estimate to the raw RA output.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7615>
Alyssa Rosenzweig [Tue, 24 Nov 2020 19:53:55 +0000 (14:53 -0500)]
pan/bi: Ensure TEXC src0 is not marked SSA
Prevents attempts to spill tied TEXC src/dest, resulting in a crash,
seen in shaders/tesseract/229.shader_test
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7615>
Boris Brezillon [Tue, 17 Nov 2020 20:48:27 +0000 (21:48 +0100)]
pan/bi: Emit a combine even if we only pass one staging reg to TEXC
We need that to account for potential swizzling on the source reg.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7615>
Alyssa Rosenzweig [Tue, 24 Nov 2020 18:56:52 +0000 (13:56 -0500)]
pan/bi: Fix off-by-one in RA
Could result in trying to allocate R64 which is clearly wrong.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7615>
Alyssa Rosenzweig [Fri, 13 Nov 2020 22:09:27 +0000 (17:09 -0500)]
pan/bi: Fix varying writemask handling
Allows shaders/supertuxkart/1.shader_test and
shaders/unity/24-Tree.shader_test to compile.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7615>
Alyssa Rosenzweig [Fri, 13 Nov 2020 22:04:43 +0000 (17:04 -0500)]
pan/bi: Implement sampler1D
Enough to get shaders/humus-celshading/1.shader_test compiling, no idea
if it actually works but it looks reasonable.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7615>
Alyssa Rosenzweig [Fri, 13 Nov 2020 22:34:17 +0000 (17:34 -0500)]
pan/mdg: Fix shader-db counter
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7615>
Alyssa Rosenzweig [Tue, 24 Nov 2020 18:57:12 +0000 (13:57 -0500)]
panfrost: Enable indirect uniform indexing
It works fine, and without it, the lowering bloats GLES2 shaders (by a
factor of 20x for one shader on t-rex!)
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7615>
Alyssa Rosenzweig [Fri, 13 Nov 2020 21:59:16 +0000 (16:59 -0500)]
panfrost: Add PAN_GPU_ID debug option
I'd like to run shader-db locally without turning on the Bifrost
machine. I'm lazy, it's just for debug builds, ok? 😇
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7615>
Rhys Perry [Tue, 24 Nov 2020 14:53:04 +0000 (14:53 +0000)]
nir/unsigned_upper_bound: decrement num_sources_left before recursing
Otherwise, search_phi_bcsel() will be called with a buf_size that is
slightly lower than it has to be.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7748>
Rhys Perry [Tue, 24 Nov 2020 10:52:56 +0000 (10:52 +0000)]
nir/unsigned_upper_bound: fix buffer overflow in search_phi_bcsel
It should only recurse if there's enough space to add the phi sources.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes:
72ac3f60261 ("nir: add nir_unsigned_upper_bound and nir_addition_might_overflow")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7748>
Rhys Perry [Tue, 24 Nov 2020 20:40:56 +0000 (20:40 +0000)]
aco: fix v_mul_hi_u32_u24 format
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes:
57c152af9ce ("aco: select v_mul_{hi}_u32_u24 for 24-bit multiplications")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3874
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7759>
Erik Faye-Lund [Tue, 24 Nov 2020 22:35:08 +0000 (23:35 +0100)]
Revert "util: Add helpers for various one-time-init patters"
This reverts commit
bda4d6e0d01116db59a0a03b0c703a7af6e11949.
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7760>
Erik Faye-Lund [Tue, 24 Nov 2020 22:34:59 +0000 (23:34 +0100)]
Revert "nir: Use get_once() helper for one-time init's"
This reverts commit
c9062df1d57df19a56288c1749d4b6d22d7c1418.
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7760>
Erik Faye-Lund [Tue, 24 Nov 2020 22:34:51 +0000 (23:34 +0100)]
Revert "freedreno/ir3: Use get_once() for one-time init"
This reverts commit
b4ad27a986e1c6899cbf23355c3e9c6de345a323.
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7760>
Erik Faye-Lund [Tue, 24 Nov 2020 22:34:46 +0000 (23:34 +0100)]
Revert "gallium/hud: Use do_once for one-time init"
This reverts commit
2e81ec5e009e3fbeef3fe1a76f2dfee428b7c160.
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7760>
Erik Faye-Lund [Tue, 24 Nov 2020 22:34:39 +0000 (23:34 +0100)]
Revert "mesa/st: Use do_once for one-time init"
This reverts commit
bcb2981e145f0c2a54a637e20b6c55eaf316c04f.
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7760>
Erik Faye-Lund [Tue, 24 Nov 2020 22:34:33 +0000 (23:34 +0100)]
Revert "util: Fix helgrind complaint about one-time init"
This reverts commit
f8c7a43f33d4647c16c4892d56706a14e5d6bf17.
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7760>
Erik Faye-Lund [Tue, 24 Nov 2020 22:34:24 +0000 (23:34 +0100)]
Revert "mesa: Fix helgrind complaint about one-time init"
This reverts commit
f7102ac376a23a394786085a2b0dffa94c13150c.
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7760>
Erik Faye-Lund [Tue, 24 Nov 2020 22:33:14 +0000 (23:33 +0100)]
Revert "gallium/trace: Fix helgrind complaint about one-time init"
This reverts commit
1aa055539f32fcb3c78d908d1635bb3a3d517bc2.
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7760>
Erik Faye-Lund [Tue, 24 Nov 2020 22:33:06 +0000 (23:33 +0100)]
Revert "tgsi: Fix helgrind complaint about one-time init"
This reverts commit
d91fe7d1c65179e64a6ca294135ac1bad2b16fb9.
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7760>
Samuel Pitoiset [Mon, 23 Nov 2020 10:59:55 +0000 (11:59 +0100)]
radv: always use 32-bit predication on compute queues
It seems that only gfx queue doesn't support it, except on GFX10.3
which supports all queues.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7732>
Samuel Pitoiset [Mon, 23 Nov 2020 10:57:49 +0000 (11:57 +0100)]
radv: use 32-bit predication for conditional rendering on GFX10.3+
It's now supported.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7732>
Samuel Pitoiset [Mon, 23 Nov 2020 10:51:25 +0000 (11:51 +0100)]
ac: add gpu_info::has_32bit_predication
32-bit predication is now supported with GFX10.3.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7732>
Ella-0 [Fri, 20 Nov 2020 08:57:07 +0000 (08:57 +0000)]
v3dv: Wayland WSI support
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7303>
Jason Ekstrand [Fri, 7 Aug 2020 03:17:17 +0000 (22:17 -0500)]
intel/rt: Implement push constants as global memory reads
They're not really "push" anymore but that's because there is no such
thing as push constants in bindless shaders on Intel. They should be
fast enough, though. There is some room for debate here as to whether
we want to do the pull in NIR or push it into the back-end. The
advantage of doing it in the back-end is that it'd be easier to use
MOV_INDIRECT for indirect push constant access rather than falling back
to a dataport message.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
Jason Ekstrand [Thu, 6 Aug 2020 21:42:14 +0000 (16:42 -0500)]
intel/rt: Add support for hit attributes
For triangle geometry, the hit attributes are always two floats which
contain the barycentric coordinates of the hit. For procedural
geometry, they're an arbitrary blob of data passed from the intersection
shader to the hit shaders. In our implementation, we stash that data
right after the HW RayQuery in the ray stack.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
Jason Ekstrand [Thu, 6 Aug 2020 21:31:05 +0000 (16:31 -0500)]
intel/rt: Add a helper to create the raygen trampoline shader
Unlike graphics and compute pipelines, Vulkan ray-tracing pipelines do
not have a single entrypoint. Instead, the raygen shader is specified
as a one-element shader binding table in the vkCmdTraceRay call. This
means that raygen shaders have to be bindless shaders just like any
other ray tracing shader. To launch them, we have a tiny compute shader
that acts as a trampoline and sets up the hotzone and uses btd_spawn to
fire off the raygen shader.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
Jason Ekstrand [Thu, 6 Aug 2020 21:22:15 +0000 (16:22 -0500)]
intel/rt: Add lowering for combined intersection/any-hit shaders
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
Jason Ekstrand [Thu, 6 Aug 2020 21:09:55 +0000 (16:09 -0500)]
intel/rt: Add lowering for ray-walk intrinsics in any-hit shaders
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
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