Henrik Nordström [Sun, 10 Nov 2013 17:26:56 +0000 (10:26 -0700)]
sandbox: block driver using host file/device as backing store
Provide a way to use any host file or device as a block device in U-Boot.
This can be used to provide filesystem access within U-Boot to an ext2
image file on the host, for example.
The support is plumbed into the filesystem and partition interfaces.
We don't want to print a message in the driver every time we find a missing
device. Pass the information back to the caller where a message can be printed
if desired.
Signed-off-by: Henrik Nordström <henrik@henriknordstrom.net>
Signed-off-by: Simon Glass <sjg@chromium.org>
- Removed change to part.c get_device_and_partition()
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 10 Nov 2013 17:26:47 +0000 (10:26 -0700)]
Add crc8 routine
Add an implementation of the CRC8 algorithm. This is required by the TPM
emulation, but is probably useful to U-Boot in general.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Albert ARIBAUD [Wed, 8 Jan 2014 19:48:26 +0000 (20:48 +0100)]
Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'
Lubomir Popov [Thu, 19 Dec 2013 15:14:02 +0000 (17:14 +0200)]
ARM: omap5_uevm: Enable 8-bit eMMC access
All prerequisites are already available, so why not enable 8-bit
access - it is a matter of a define in the board file only.
Signed-off-by: Lubomir Popov <l-popov@ti.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Chin Liang See [Wed, 18 Dec 2013 17:16:01 +0000 (11:16 -0600)]
mmc/dwmmc: Using calloc instead malloc
To enhance the SDMMC DesignWare driver to use calloc instead of
malloc. This will avoid the incident that uninitialized members
of mmc structure are later used for NULL comparison.
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Mischa Jonker <mjonker@synopsys.com>
Cc: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Andy Fleming <afleming@freescale.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Lad, Prabhakar [Tue, 3 Dec 2013 06:47:34 +0000 (12:17 +0530)]
include/mmc.h: Remove declaration for spl_mmc_load()
The spl_mmc_load() was removed while converting to
CONFIG_SPL_FRAMEWORK usage the definition was removed
but the declaration was missed. This patch removes this
declaration.
Signed-off-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Nobuhiro Iwamatsu [Wed, 8 Jan 2014 05:57:30 +0000 (14:57 +0900)]
sh: sh2: Change CONFIG_SYS_HZ to CONFIG_SH_CMT_CLK_FREQ
CONFIG_SYS_HZ of SH2 is not used as frequency of base timer. This is the
correct clock of CMT.
This changes from CONFIG_SYS_HZ to CONFIG_SH_CMT_CLK_FREQ, in order to use
CONFIG_SYS_HZ as clock of CMT.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Nobuhiro Iwamatsu [Wed, 8 Jan 2014 05:10:10 +0000 (14:10 +0900)]
sh: sh4: remove CONFIG_SH4 definition from board config
CONFIG_SH4 was already defined in arch/sh/sh4/config.mk.
This removes CONFIG_SH4 from board config files of SH4.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Nobuhiro Iwamatsu [Wed, 8 Jan 2014 05:09:32 +0000 (14:09 +0900)]
sh: sh4: Add CONFIG_SH4 definition to config.mk of SH4
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Nobuhiro Iwamatsu [Wed, 8 Jan 2014 04:51:07 +0000 (13:51 +0900)]
sh: sh3: remove CONFIG_SH3 definition from board config
CONFIG_SH3 was already defined in arch/sh/sh3/config.mk.
This removes CONFIG_SH3 from board config files of SH3.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Nobuhiro Iwamatsu [Wed, 8 Jan 2014 04:46:11 +0000 (13:46 +0900)]
sh: sh3: Add CONFIG_SH3 definition to config.mk of SH3
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Nobuhiro Iwamatsu [Wed, 8 Jan 2014 04:48:51 +0000 (13:48 +0900)]
sh: sh2: remove CONFIG_SH2 definition from board config
CONFIG_SH2 was already defined in arch/sh/sh2/config.mk.
This removes CONFIG_SH2 from board config files of SH2.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Nobuhiro Iwamatsu [Wed, 8 Jan 2014 04:46:06 +0000 (13:46 +0900)]
sh: sh2: Add CONFIG_SH2 definition to config.mk of SH2
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Masahiro Yamada [Mon, 6 Jan 2014 06:43:35 +0000 (15:43 +0900)]
sh: delete redundant CONFIG_SH definition
CONFIG_SH is defined in arch/sh/config.mk.
It is not necessary to define it in each board
header config header file.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Mugunthan V N [Tue, 7 Jan 2014 14:27:38 +0000 (19:57 +0530)]
ARM: dra7_evm: read mac address properly from e-fuse
Byte offset of Ethernet mac address read from e-fuse are wrong so DHCP is
not working on some boards, modifying the offset to read properly.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Nikita Kiryanov [Tue, 31 Dec 2013 10:55:15 +0000 (12:55 +0200)]
arm: omap: cm_t35: enable gpio bank 5 clocks explicitly
Following commit "arm: omap3: Enable clocks for peripherals only if they are
used" (
f33b9bd3984fb11e1d8566a866adc5957b1e1c9d) it is now necessary to enable
clocks for GPIO banks explicitly. On cm_t35, GPIO bank 5 is necessary for
scf0403 lcd support.
Enable GPIO bank 5 clocks.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Jeroen Hofstee [Sat, 21 Dec 2013 17:06:33 +0000 (18:06 +0100)]
ARM: twister: add missing gpio clock init
Commit
f33b9bd3984fb11e1d8566a866adc5957b1e1c9d breaks boards
which do not explicitly enable the gpio clocks. This causes
the twister spl to hang, since it uses the no longer enabled
gpio 55. Add CONFIG_OMAP3_GPIO_2 to unbrick the board.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tapani Utriainen <tapani@technexion.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Acked-by: Stefano Babic <sbabic@denx.de>
Jeroen Hofstee [Sat, 21 Dec 2013 17:03:09 +0000 (18:03 +0100)]
ARM: tam3517-common: fix nand spl boot
commit
f9095aac793aa8917ab9b915c5d449e6dc8d3d30, "mtd: nand:
omap: add CONFIG_NAND_OMAP_ECCSCHEME for selection of ecc-scheme"
removed CONFIG_SPL_NAND_SOFTECC from the tam3517 common config,
causing the spl nand boot to fail. Add it back, so derived
boards boot again.
Cc: Pekon Gupta <pekon@ti.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Raphael Assenat <raph@8d.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tapani Utriainen <tapani@technexion.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Acked-by: Stefano Babic <sbabic@denx.de>
Tom Rini [Fri, 20 Dec 2013 16:19:33 +0000 (11:19 -0500)]
TI:omap3: Drop omap3_zoom2
The omap3_zoom2 board has not been updated for a correct CONFIG_SYS_HZ
and Tom Rix's email has long been bouncing.
Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Wed, 18 Dec 2013 19:43:08 +0000 (14:43 -0500)]
cam_enc_4xx: Set CONFIG_SYS_NAND_MAX_OOBFREE / CONFIG_SYS_NAND_MAX_ECCPOS
With the changes to make OOBFREE/ECCPOS configurable but default to
larger, we need to set these config options for the space savings they
provide.
Cc: Scott Wood <scottwood@freescale.com>
Cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Mon, 6 Jan 2014 19:07:08 +0000 (14:07 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Tom Rini [Mon, 6 Jan 2014 18:48:36 +0000 (13:48 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-onenand
Holger Brunck [Mon, 7 Oct 2013 13:10:03 +0000 (15:10 +0200)]
arm/km: fix i2c mux define for km_kirkwood_128m16 target
Due to the i2c mux rework in u-boot we now have only to specify the
busnumber and not the whole mux configuration.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Acked-by: Heiko Schocher <hs@denx.de>
Karlheinz Jerg [Wed, 18 Sep 2013 07:32:48 +0000 (09:32 +0200)]
arm/km: add support for km_kirkwood_128m16 board
The board is similar to the standard km_kirkwood board. From a
u-boot point of view, the only difference is an increased
256 MiB DRAM (128M16). A board based on this design is for
example the SUP12.
Signed-off-by: Karlheinz Jerg <karlheinz.jerg@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Luka Perkov [Thu, 31 Oct 2013 03:05:05 +0000 (04:05 +0100)]
kirkwood: ib62x0: use device tree and update config
Signed-off-by: Luka Perkov <luka@openwrt.org>
CC: Prafulla Wadaskar <prafulla@marvell.com>
Acked-By: Prafulla Wadaskar <prafulla@marvell.com>
Albert ARIBAUD [Mon, 6 Jan 2014 08:32:42 +0000 (09:32 +0100)]
Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'
Albert ARIBAUD [Mon, 6 Jan 2014 07:49:58 +0000 (08:49 +0100)]
Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
Conflicts:
include/micrel.h
The conflict above was trivial, caused by four lines being
added in both branches with different whitepace.
Sergey Alyoshin [Tue, 17 Dec 2013 19:24:54 +0000 (23:24 +0400)]
arm: mx5: Add fuse supply enable in fsl_iim
Enable fuse supply before fuse programming and disable after.
Signed-off-by: Sergey Alyoshin <alyoshin.s@gmail.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Otavio Salvador [Mon, 16 Dec 2013 22:44:05 +0000 (20:44 -0200)]
ARM: mx6: Allow enablement of FEC Anatop based clock for all MX6
The enable_fec_anatop_clock method should be available for all MX6
variant as it is not MX6 SoloLite specific. This moves the code out of
the #ifdef/#endif and we make it conditional to CONFIG_FEC_MXC
instead.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
Otavio Salvador [Mon, 16 Dec 2013 22:44:04 +0000 (20:44 -0200)]
ARM: mx6: Change the FDT loading address to avoid overlaping
This patch fixes allow for the DeviceTree and initrd relocation fixing
the boot of FSL 3.10.9-1.0.0-alpha kernel.
This changes following boards:
- mx6sabreauto
- mx6sabresd
- wandboard
- udoo
- nitrogen6x
- cgtqmx6eval
The reasoning, as explained by Hui Liu, is:
,----
| The FDT blob will be placed at DDR physical addr: 0x11000000. When Linux kernel
| Boot up, it will decompress the compressed kernel image and place the decompressed
| kernel image at the low end of the DDR memory and start running from it. If the
| decompressed kernel image is bigger for example than 16M, it may over written the
| fdt blob which u-boot loaded to the DDR memory @0x11000000 with fdt_addr=0x11000000
|
| To expand the fdt_addr from 0x11000000 to 0x18000000, which can avoid the override
| Since we will not likely have one kernel image larger than 128MB.
`----
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
Otavio Salvador [Mon, 16 Dec 2013 22:44:03 +0000 (20:44 -0200)]
mx28evk: Extend environment to easy write of NAND system
This adds following new targets:
- update_nand_kernel
- update_nand_fdt
- update_nand_filesystem
and to avoid confusion, the 'update_nand_full' has been renamed to
'update_nand_firmware_full'.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Otavio Salvador [Mon, 16 Dec 2013 22:44:02 +0000 (20:44 -0200)]
mx28evk: Add 'nandboot' environment command
This reads the kernel, ftd and boot into ubifs filesystem. While on
that, the SD firmware filename definition has been moved next to the
other SD related commands.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Otavio Salvador [Mon, 16 Dec 2013 22:44:01 +0000 (20:44 -0200)]
mx28evk: Use 512k for fdt partition to align it
Using 512k for fdt partition allow it to be aligned with the other
small partitions and 512k erase block size.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
Otavio Salvador [Mon, 16 Dec 2013 22:44:00 +0000 (20:44 -0200)]
imx: Easy enabling of SION per-pin using MUX_MODE_SION helper macro
The macro allows easy setting in per-pin, as for example:
,----
| imx_iomux_v3_setup_pad(MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_MODE_SION);
`----
The IOMUX_CONFIG_SION allows for reading PAD value from PSR register.
The following quote from the datasheet:
,----
| ...
| 28.4.2.2 GPIO Write Mode
| The programming sequence for driving output signals should be as follows:
| 1. Configure IOMUX to select GPIO mode (Via IOMUXC), also enable SION if need
| to read loopback pad value through PSR
| 2. Configure GPIO direction register to output (GPIO_GDIR[GDIR] set to 1b).
| 3. Write value to data register (GPIO_DR).
| ...
`----
This fixes the gpio_get_value to properly work when a GPIO is set for
output and has no conflicts.
Thanks for Benoît Thébaudeau <benoit.thebaudeau@advansee.com>, Fabio
Estevam <fabio.estevam@freescale.com> and Eric Bénard
<eric@eukrea.com> for helping to properly trace this down.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
Prabhakar Kushwaha [Thu, 26 Dec 2013 07:10:55 +0000 (12:40 +0530)]
board/t1040qds: Enable memory reset control
Define QIXIS_RST_FORCE_MEM to reset on-board DDR-DIMM before start
accessing it.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Shaohui Xie [Thu, 19 Dec 2013 05:38:11 +0000 (13:38 +0800)]
powerpc/b4860/pbl: fix rcw cfg
The BOOT_LOC setting in rcw cfg is wrong, set it to Memory complex 1.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Shaohui Xie [Wed, 18 Dec 2013 07:09:57 +0000 (15:09 +0800)]
powerpc/t4240: enable NAND boot support
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Scott Wood [Wed, 18 Dec 2013 04:11:07 +0000 (22:11 -0600)]
powerpc/cms700: limit NAND data structure size
This fixes a build break due to excessively large NAND data structures.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Shengzhou Liu [Wed, 18 Dec 2013 02:27:55 +0000 (10:27 +0800)]
powerpc/t208x: fix macro CONFIG_SYS_FSL_NUM_USB_CTRLS
CONFIG_SYS_FSL_NUM_USB_CTRLS is no longer used,
update it to new CONFIG_USB_MAX_CONTROLLER_COUNT.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
York Sun [Tue, 17 Dec 2013 19:21:09 +0000 (11:21 -0800)]
powerpc/B4860QDS: Define new nand_ecclayout structure macros
Define CONFIG_SYS_NAND_MAX_ECCPOS and CONFIG_SYS_NAND_MAX_OOBFREE to
reduce the image size, by taking advantage of the new nand_ecclayout
structure.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Prabhakar Kushwaha <prabhakar@freescale.com>
CC: Scott Wood <scottwood@freescale.com>
York Sun [Tue, 17 Dec 2013 19:21:08 +0000 (11:21 -0800)]
powerpc/P1022DS: Define new nand_ecclayout structure macros
Define CONFIG_SYS_NAND_MAX_ECCPOS and CONFIG_SYS_NAND_MAX_OOBFREE to
reduce the image size, by taking advantage of the new nand_ecclayout
structure.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Prabhakar Kushwaha <prabhakar@freescale.com>
CC: Scott Wood <scottwood@freescale.com>
Priyanka Jain [Tue, 17 Dec 2013 08:55:52 +0000 (14:25 +0530)]
powerpc/mpc85xx: Add support for single source clocking
Single-source clocking is new feature introduced in T1040.
In this mode, a single differential clock is supplied to the
DIFF_SYSCLK_P/N inputs to the processor, which in turn is
used to supply clocks to the sysclock, ddrclock and usbclock.
So, both ddrclock and syclock are driven by same differential
sysclock in single-source clocking mode whereas in normal clocking
mode, generally separate DDRCLK and SYSCLK pins provides
reference clock for sysclock and ddrclock
DDR_REFCLK_SEL rcw bit is used to determine DDR clock source
-If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in
normal clocking mode by DDR_Reference clock
-If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in
single source clocking mode by DIFF_SYSCLK
Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Prabhakar Kushwaha [Thu, 12 Dec 2013 06:39:01 +0000 (12:09 +0530)]
board/t1040qds: Relax IFC FPGA timings
Current IFC-FPGA TCH(Chip Select hold time with respect to WE deassertion)
is 0 i.e. 0 ns hold time on writes. This may not work on higher clock
freqencies.
So, Increase TCH as 0x8 i.e. 8 ip_clk.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Prabhakar Kushwaha [Wed, 11 Dec 2013 07:12:11 +0000 (12:42 +0530)]
board/freescale:Remove use of CONFIG_SPL_NAND_MINIMAL
CONFIG_SPL_NAND_MINIMAL should not be used as it was defined for temporary
review purpose.
So, use CONFIG_SPL_NAND_BOOT config.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Prabhakar Kushwaha [Tue, 10 Dec 2013 07:43:10 +0000 (13:13 +0530)]
board/t1040qds: Fix typo in t1040_pbi.cfg file
T1040QDS has 256KB SRAM. Comment is showing wrong information.
So update the comment.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Fabio Estevam [Thu, 26 Dec 2013 16:51:35 +0000 (14:51 -0200)]
mx6: soc: Disable VDDPU regulator
As U-boot does not use GPU/VPU peripherals, shutdown the VDDPU regulator
in order to save power.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Fabio Estevam [Thu, 26 Dec 2013 16:51:34 +0000 (14:51 -0200)]
mx6: soc: Add the required LDO ramp up delay
When changing LDO voltages we need to wait for the required amount of time
for the voltage to settle.
Also, as the timer is still not available when arch_cpu_init() is called, we
need to call it later at board_postclk_init() phase.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Fabio Estevam [Thu, 26 Dec 2013 16:51:33 +0000 (14:51 -0200)]
mx6: soc: Introduce set_ldo_voltage()
Introduce set_ldo_voltage() so that all three LDO regulators can be configured.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Fabio Estevam [Thu, 26 Dec 2013 16:51:32 +0000 (14:51 -0200)]
mx6: soc: Set the VDDSOC at 1.175 V
mx6 datasheet specifies that the minimum VDDSOC at 792 MHz is 1.15 V.
Add a 25 mV margin and set it to 1.175V.
This also matches the VDDSOC voltages for 792MHz operation that the kernel configures:
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-mx6/cpu_op-mx6.c?h=imx_3.0.35_4.1.0
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Fabio Estevam [Thu, 26 Dec 2013 16:51:31 +0000 (14:51 -0200)]
mx6: soc: Clear the LDO ramp values up prior to setting the LDO voltages
Since ROM may modify the LDO ramp up time according to fuse setting,
it is safer to reset the ramp up field to its default value of 00:
00: 64 cycles of 24MHz clock;
01: 128 cycles of 24MHz clock;
02: 256 cycles of 24MHz clock;
03: 512 cycles of 24MHz clock;
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Fabio Estevam [Thu, 26 Dec 2013 16:51:30 +0000 (14:51 -0200)]
mx6: soc: Staticize set_vddsoc()
set_vddsoc() is not used anywhere else, so make it static.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Fabio Estevam [Mon, 23 Dec 2013 15:07:18 +0000 (13:07 -0200)]
mx6sabre_common.h: Add CONFIG_CMD_FUSE support
Add CONFIG_CMD_FUSE option, so that the fuse API can be used.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Fabio Estevam [Mon, 23 Dec 2013 15:07:17 +0000 (13:07 -0200)]
doc: README.fuse: Add an example on how to use the fuse API on mx6q
When using the fuse API in U-boot user must calculate the 'bank' and 'word'
values.
Provide a real example on how to calculate such values for the mx6q.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Marek Vasut [Thu, 26 Dec 2013 00:01:24 +0000 (01:01 +0100)]
mtd: onenand: Fix unaligned access
Fix unaligned access in OneNAND core. The problem is that the ffchars[] array
is an array of "unsigned char", but in onenand_write_ops_nolock() can be passed
to the memcpy_16() function. The memcpy_16() function will treat the buffer as
an array of "unsigned short", thus triggering unaligned access if the compiler
decided ffchars[] to be not aligned.
I managed to trigger the problem with regular ELDK 5.4 GCC compiler.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@ti.com>
Piotr Wilczek [Mon, 30 Dec 2013 08:40:40 +0000 (09:40 +0100)]
board:trats2: fix default partitions and mmc env
This patch add uuid disk to defualt partions necessary to
restore gpt partitions and fixes mmcdev environmental variable.
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Piotr Wilczek [Wed, 18 Dec 2013 14:43:37 +0000 (15:43 +0100)]
board:trats1:trats2: fix adapter number
This fix is necessary after increased by one the number
of adapters in s3c24x0 driver.
Tested on Trats and Trats2.
Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Rajeshwari Birje [Thu, 26 Dec 2013 04:14:27 +0000 (09:44 +0530)]
SPL: EXYNOS: Prepare for variable size SPL support
When variable size SPL is used, the BL1 expects the SPL to be
encapsulated differently: instead of putting the checksum at a fixed
offset in the SPL blob, prepend the blob with a header including the
size and the checksum.
The enhancements include
- adding a command line option, '--vs' to indicate the need for the
variable size encapsulation
- padding the fixed size encapsulated blob with 0xff instead of random
memory contents
- do not silently truncate the input file, report error instead
- no need to explicitly closing files/freeing memory, this all happens
on exit; removing cleanups it makes code clearer
- profuse commenting
- modify Makefile to allow enabling the new feature per board
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Rajeshwari Birje [Thu, 26 Dec 2013 04:14:26 +0000 (09:44 +0530)]
Config: Add initial config for SMDK5420
Adding initial config for SMDK5420 to build and boot U-Boot
over Exynos based SMDK5420.
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Rajeshwari Birje [Thu, 26 Dec 2013 04:14:25 +0000 (09:44 +0530)]
DTS: Add dts support for SMDK5420
This patch adds dts support for SMDK5420.
exynos5.dtsi created is a common file which has the nodes common
to both 5420 and 5250.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Rajeshwari Birje [Thu, 26 Dec 2013 04:14:24 +0000 (09:44 +0530)]
Exynos5420: Add base patch for SMDK5420
Adding the base patch for Exynos based SMDK5420.
This shall enable compilation and basic boot support for
SMDK5420.
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Rajeshwari Birje [Thu, 26 Dec 2013 04:14:23 +0000 (09:44 +0530)]
Exynos5420: Add support for 5420 in pinmux and gpio
Adds code in pinmux and gpio framework to support Exynos5420.
Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Rajeshwari Birje [Thu, 26 Dec 2013 04:14:22 +0000 (09:44 +0530)]
Exynos5420: Add DDR3 initialization for 5420
This patch intends to add DDR3 initialization code for Exynos5420.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Rajeshwari Birje [Thu, 26 Dec 2013 04:14:21 +0000 (09:44 +0530)]
Exynos5420: Add clock initialization for 5420
This patch adds code for clock initialization and clock settings
of various IP's and controllers, required for Exynos5420
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Rajeshwari Birje [Thu, 26 Dec 2013 04:14:20 +0000 (09:44 +0530)]
EXYNOS5420: Add dmc and phy_control register structure
Add dmc and phy_control register structure for 5420.
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Rajeshwari Birje [Thu, 26 Dec 2013 04:14:19 +0000 (09:44 +0530)]
EXYNOS5420: Add power register structure.
Add structure for power register for Exynos5420
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Rajeshwari Birje [Thu, 26 Dec 2013 04:14:18 +0000 (09:44 +0530)]
Exynos5420: Add base addresses for 5420
Adds base addresses of various IPs and controllers required for
Exynos5420.
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Rajeshwari Birje [Thu, 26 Dec 2013 04:14:17 +0000 (09:44 +0530)]
EXYNOS5: Create a common board file
Create a common board.c file for all functions which are common across
all EXYNOS5 platforms.
exynos_init function is provided for platform specific code.
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Tom Rini [Fri, 20 Dec 2013 16:24:07 +0000 (11:24 -0500)]
PowerPC: Drop linkstation_HGLAN support
With changes to the rtl8169 ethernet to improve cache support, we have
needed additional cache functions for mpc8245. As the board maintainer
has been unresponsive, remove this board.
Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Tom Rini <trini@ti.com>
Łukasz Majewski [Wed, 11 Dec 2013 06:15:42 +0000 (07:15 +0100)]
ARM: Samsung: Change GONI and Universal_C210 maintainers.
Update boards.cfg entries for Samsung's GONI and Universal_C210 maintainers
entry.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
Tom Rini [Thu, 19 Dec 2013 19:22:12 +0000 (14:22 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-spi
Stefano Babic [Thu, 19 Dec 2013 10:04:33 +0000 (11:04 +0100)]
MX6: fix sata compilation for i.MX6
Commit
164d98466103a46b7c881149e92ec2a28a6375be breaks
board with SATA support, because sata is not compiled.
Signed-off-by: Stefano Babic <sbabic@denx.de>
Poddar, Sourav [Thu, 14 Nov 2013 15:31:15 +0000 (21:01 +0530)]
driver: mtd: sf_ops: claim bus while doing memcpy
claim spi bus while doing memory copy, this will set up
the spi controller device control register before doing
a memory read.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Tested-by: Yebio Mesfin <ymesfin@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Poddar, Sourav [Thu, 14 Nov 2013 15:31:14 +0000 (21:01 +0530)]
config: dra7_evm: Add Bank Address Register(BAR) config
Add config to support bank address register.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Tested-by: Yebio Mesfin <ymesfin@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Lokesh Vutla [Tue, 10 Dec 2013 09:32:24 +0000 (15:02 +0530)]
ARM: AM43xx: Add Maintainer
Adding Maintainer for AM43xx.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Lokesh Vutla [Tue, 10 Dec 2013 09:32:23 +0000 (15:02 +0530)]
ARM: AM43xx: GP_EVM: Add support for DDR3
GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH).
Adding details for the same.
Below is the brief description of DDR3 init sequence(SW leveling):
-> Enable VTT regulator
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program leveling registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Lokesh Vutla [Tue, 10 Dec 2013 09:32:22 +0000 (15:02 +0530)]
ARM: AM43xx: EPOS_EVM: Add support for LPDDR2
AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A)
Adding LPDDR2 init sequence and register details for the same.
Below is the brief description of LPDDR2 init sequence:
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
-> Wait till initialization is complete and the configure MR registers.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Lokesh Vutla [Tue, 10 Dec 2013 09:32:21 +0000 (15:02 +0530)]
ARM: AM33xx+: Update ioregs to pass different values
Currently same value is programmed for all ioregs. This is not
the case for all SoC's like AM4372. So adding a structure for ioregs
and updating in all board files. And also return from config_cmd_ctrl()
and config_ddr_data() functions if data is not passed.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[trini: Fixup dxr2, cm_t335, adapt pcm051 rev3]
Signed-off-by: Tom Rini <trini@ti.com>
Lokesh Vutla [Tue, 10 Dec 2013 09:32:20 +0000 (15:02 +0530)]
ARM: AM43xx: clocks: Update DPLL details
Updating the Multiplier and Dividers value for all DPLLs.
Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value
returned the MPU DPLL is locked.
At different OPPs follwoing are the MPU locked frequencies.
OPP50 300MHz
OPP100 600MHz
OPP120 720MHz
OPPTB 800MHz
OPPNT 1000MHz
According to the latest DM following is the OPP table dependencies:
VDD_CORE VDD_MPU
OPP50 OPP50
OPP50 OPP100
OPP100 OPP50
OPP100 OPP100
OPP100 OPP120
So at different OPPs of MPU it is safest to lock CORE at OPP_NOM.
Following are the DPLL locking frequencies at OPP NOM:
Core locks at 1000MHz
Per locks at 960MHz
LPDDR2 locks at 266MHz
DDR3 locks at 400MHz
Touching AM33xx files also to get DPLL values specific to board but no
functionality difference.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Lokesh Vutla [Tue, 10 Dec 2013 09:32:19 +0000 (15:02 +0530)]
ARM: AM43xx: mux: Update mux data
Updating the mux data for UART, adding data for i2c0 and mmc.
And also updating pad_signals structure.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Lokesh Vutla [Tue, 10 Dec 2013 09:32:18 +0000 (15:02 +0530)]
ARM: AM43xx: Update Current Booting devices list
Current Booting devices list is different from that of AM33xx.
Updating the same.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Lokesh Vutla [Tue, 10 Dec 2013 09:32:17 +0000 (15:02 +0530)]
ARM: AM43xx: Select clk source for Timer2
Selecting the Master osc clk as Timer2 clock source.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Sekhar Nori [Tue, 10 Dec 2013 09:32:16 +0000 (15:02 +0530)]
ARM: AM43XX: Add CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG support
CONFIG_ENV_VARS_UBOOT_CONFIG, CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG and
CONFIG_BOARD_LATE_INIT is already set. Adding support to detect the
board. These variables are used by findfdt.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Sekhar Nori [Tue, 10 Dec 2013 09:32:15 +0000 (15:02 +0530)]
ARM: AM43XX: board: add support for reading onboard EEPROM
Add support for reading onboard EEPROM to enable
board detection.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Lokesh Vutla [Tue, 10 Dec 2013 09:32:14 +0000 (15:02 +0530)]
ARM: AM43xx: Add extra ENV settings
Add Extra env settings.
This is derived from am335x Extra ENV settings.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Lokesh Vutla [Tue, 10 Dec 2013 09:32:13 +0000 (15:02 +0530)]
ARM: AM43xx: Add L2 Support
AM4372 uses PL310 L2 Cache. Enable the configs for the same.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Lokesh Vutla [Tue, 10 Dec 2013 09:32:12 +0000 (15:02 +0530)]
ARM: AM43xx: Adapt to ti_armv7_common.h config file
Use ti_armv7_common.h config file to inclde the common
configs.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Lokesh Vutla [Tue, 10 Dec 2013 09:32:11 +0000 (15:02 +0530)]
ARM: AM43xx: Update the base addresses of modules
PRCM, timer base addresses and offsets are different from
AM33xx. Updating the same.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Stefan Roese [Tue, 17 Dec 2013 13:14:06 +0000 (14:14 +0100)]
arm: omap3: Fix beagleboard SPL boot hangup (GPIO clocks not enabled)
Patch
f33b9bd3
[arm: omap3: Enable clocks for peripherals only if they are used]
breaks SPL booting on Beagleboard. Since some gpio input's are
read to detect the board revision. But with this patch above, the
clocks to the GPIO subsystems are not enabled per default any more.
The GPIO banks need to be configured specifically now.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Tom Rini [Wed, 18 Dec 2013 23:45:39 +0000 (18:45 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-nand-flash
Albert ARIBAUD [Wed, 18 Dec 2013 21:19:02 +0000 (22:19 +0100)]
Merge remote-tracking branch 'u-boot-pxa/master' into 'u-boot-arm/master'
Albert ARIBAUD [Wed, 18 Dec 2013 20:45:34 +0000 (21:45 +0100)]
Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master'
Tom Rini [Wed, 18 Dec 2013 20:06:43 +0000 (15:06 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-usb
Marek Vasut [Mon, 4 Nov 2013 19:50:21 +0000 (20:50 +0100)]
ARM: pxa: Fix CONFIG_SYS_HZ on PXA
The PXA incorrectly uses CONFIG_SYS_HZ, which should be 1000 across
U-Boot. Fix this.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Marek Vasut [Sat, 14 Dec 2013 01:04:52 +0000 (02:04 +0100)]
usb: ehci: Fix register access
Fix the register access in EHCI HCD. We need to use address of the register
as an ehci_writel() argument.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Marek Vasut [Sat, 14 Dec 2013 01:03:11 +0000 (02:03 +0100)]
usb: ehci: Do not de-init uninited controllers
In case the controller is not initialized, we shall not de-initialize it.
As the control structure will not be filled, we will produce a null ptr
dereference if the controller is not inited.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Marek Vasut [Fri, 13 Dec 2013 22:36:33 +0000 (23:36 +0100)]
usb: ehci-pci: Clarify and cleanup the EHCI controller detection
The detection function of the EHCI PCI controller was really cryptic,
add a beefy comment and clean the portion of the code up a bit. No
change in the logic of the code.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Lukasz Majewski [Mon, 9 Dec 2013 15:20:16 +0000 (16:20 +0100)]
ARM: trats: dfu: Enable default Poll Timeout for Trats board
Provide default Poll Timeout value for Trats board.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Lukasz Majewski [Mon, 9 Dec 2013 15:20:15 +0000 (16:20 +0100)]
usb: f_dfu: cosmetic: Code cleanup
Code cleanup for dfu_bind_config function
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Lukasz Majewski [Mon, 9 Dec 2013 15:20:14 +0000 (16:20 +0100)]
usb: dfu: f_dfu: Provide infrastructure to adjust DFU's Poll Timeout value
It is necessary to deter the host from sending subsequent DFU_GETSTATUS
request in the case of e.g. writing the buffer to medium.
Here the timeout is increased when we fill up the whole buffer. This delay
allows eMMC memory to perform its internal operations.
Otherwise we end up with HOST's error regarding GET_STATUS receive timeout.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Lukasz Majewski [Mon, 9 Dec 2013 15:20:13 +0000 (16:20 +0100)]
dfu: Export allocated dfu buffer size
The method for exporting size of allocated buffer is provided.
It is afterwards used by USB's dfu function code.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>