Matt Arsenault [Thu, 7 Jun 2018 19:42:27 +0000 (19:42 +0000)]
DAG: Avoid bitcast/ext/build_vector combine
This avoids regressions in a future AMDGPU change
to make v4i16/v4f16 legal. For these types, build_vector
is implemented as bitcasted operations on v2i32. This
combine was creating v4i16s out of what would have been
already been a v2i32 build_vector, creating a mess
of nodes that never get cleaned up.
I'm not sure this is the right condition to check.
I initially tried just checking for the legality of the
new build_vector. This works for my case, but breaks dozens
of x86 tests. A Mips test seems to show some improvement
or at least a neutral change. I don't want to think
about how long it would take to analyze the set of
different x86 vector operations impacted.
Test included in future commit.
llvm-svn: 334218
Alexander Shaposhnikov [Thu, 7 Jun 2018 19:41:42 +0000 (19:41 +0000)]
[llvm-objcopy] Remove unused field from Object
The class Object contains std::shared_ptr<MemoryBuffer> OwnedData
which is not used anywhere. Besides avoiding two stage initialization
the motivation to remove it comes from the plan to add (currently missing) support
for static libraries.
NFC.
Test plan: make check-all
Differential revision: https://reviews.llvm.org/D47855
llvm-svn: 334217
Vitaly Buka [Thu, 7 Jun 2018 19:17:46 +0000 (19:17 +0000)]
Introducing single for loop into clang_proto_fuzzer
Summary:
Created a new protobuf and protobuf-to-C++ "converter" that wraps the entire C++ code in a single for loop.
- Slightly changed cxx_proto.proto -> cxx_loop_proto.proto
- Made some changes to proto_to_cxx files to handle the new kind of protobuf
- Created ExampleClangLoopProtoFuzzer to test new protobuf and "converter"
Patch by Emmett Neyman
Reviewers: kcc, vitalybuka, morehouse
Reviewed By: vitalybuka, morehouse
Subscribers: mgorny, llvm-commits, cfe-commits
Differential Revision: https://reviews.llvm.org/D47843
llvm-svn: 334216
Alexander Polyakov [Thu, 7 Jun 2018 19:09:01 +0000 (19:09 +0000)]
[lldb-mi] Re-implement MI -exec-next command.
Summary: Now -exec-next command uses SB API for stepping over.
Reviewers: aprantl, clayborg, stella.stamenova, labath
Reviewed By: aprantl, clayborg, labath
Subscribers: labath, ki.stfu, lldb-commits
Differential Revision: https://reviews.llvm.org/D47797
llvm-svn: 334215
Douglas Yung [Thu, 7 Jun 2018 18:51:47 +0000 (18:51 +0000)]
Silence a -Wconstant-logical-operand warning.
llvm-svn: 334214
Petr Hosek [Thu, 7 Jun 2018 18:41:35 +0000 (18:41 +0000)]
[Fuzzer] Update the header path for fdio/spawn.h on Fuchsia
The path now includes lib/ prefix.
Differential Revision: https://reviews.llvm.org/D47866
llvm-svn: 334213
Petr Hosek [Thu, 7 Jun 2018 18:27:27 +0000 (18:27 +0000)]
[CMake] Filter out -z,defs when building custom libc++
-z,defs is incompatible with sanitizers so we need to filter it out
from the linker flags before passing them to the libc++ build.
Differential Revision: https://reviews.llvm.org/D47865
llvm-svn: 334212
Sanjay Patel [Thu, 7 Jun 2018 18:21:24 +0000 (18:21 +0000)]
[TargetLibraryInfo] add mappings from LLVM sin/cos intrinsics to SVML calls
These weren't included in D19544 - probably just an oversight.
D40044 made it more likely that we'll have LLVM math intrinsics rather
than libcalls, so this bug was more easily exposed.
As the tests/code show, we already have the complete mappings for pow/exp/log.
I don't have any experience with SVML, so I don't know if anything else is
missing. It's also not clear to me that we should be doing this transform in
IR rather than DAG/isel, but that's a separate issue.
Differential Revision: https://reviews.llvm.org/D47610
llvm-svn: 334211
Stella Stamenova [Thu, 7 Jun 2018 17:49:22 +0000 (17:49 +0000)]
[lit, windows] Disable a number of tests that are failing on Windows
Summary: They all correspond to bugs that are already logged and I've added the appropriate (or most appropriate) bug numbers. This leaves only a handful of failing tests.
Reviewers: asmith, zturner, labath
Reviewed By: zturner
Subscribers: eraman, llvm-commits
Differential Revision: https://reviews.llvm.org/D47892
llvm-svn: 334210
Daniil Fukalov [Thu, 7 Jun 2018 17:30:58 +0000 (17:30 +0000)]
[LSR] Check yet more intrinsic pointer operands
the patch fixes another assertion in isLegalUse()
Differential Revision: https://reviews.llvm.org/D47794
llvm-svn: 334209
Craig Topper [Thu, 7 Jun 2018 17:28:03 +0000 (17:28 +0000)]
[X86] Add back builtins for _mm_slli_si128/_mm_srli_si128 and similar intrinsics.
We still lower them to native shuffle IR, but we do it in CGBuiltin.cpp now. This allows us to check the target feature and ensure the immediate fits in 8 bits.
This also improves our -O0 codegen slightly because we're able to see the zeroinitializer in the shuffle. It looks like it got lost behind a store+load previously.
llvm-svn: 334208
David Carlier [Thu, 7 Jun 2018 16:33:48 +0000 (16:33 +0000)]
[docs] add various sanitisers support for FreeBSD/OpenBSD
since couple of months, supports had been enabled for FreeBSD and OpenBSD.
Reviewers: thakis, spatel, dim
Reviewed By: dim
Differential Revision: https://reviews.llvm.org/D47322
llvm-svn: 334207
Roman Lebedev [Thu, 7 Jun 2018 16:18:26 +0000 (16:18 +0000)]
[NFC][InstSimplify] Add more tests for shl nuw C, %x -> C fold.
Follow-up for rL334200.
For these, KnownBits will be needed.
llvm-svn: 334206
Jonas Devlieghere [Thu, 7 Jun 2018 16:10:42 +0000 (16:10 +0000)]
[Platform] Accept arbitrary kext variants
When loading kexts in PlatformDarwinKernel, we use the BundleID as the
filename to to create shared modules. In GetSharedModule we call
ExamineKextForMatchingUUID for any BundleID it finds that is a match, to
see if the UUID is also a match. Until now we were using
Host::ResolveExecutableInBundle which calls a CoreFoundation API to
obtain the executable. However, it's possible that the executable has a
variant suffix (e.g. foo_development) and these files were ignored.
This patch replaces that call with logic that looks for all the binaries
in the bundle. Because of the way ExamineKextForMatchingUUID works, it's
fine to try to load executables that are not valid and we can just
iterate over the list until we found a match.
Differential revision: https://reviews.llvm.org/D47539
llvm-svn: 334205
Simon Pilgrim [Thu, 7 Jun 2018 16:08:40 +0000 (16:08 +0000)]
[X86][SSE] Updated comment - combineVectorSignBitsTruncation handles PACKSS and PACKUS. NFCI.
llvm-svn: 334204
Alex Bradbury [Thu, 7 Jun 2018 15:35:47 +0000 (15:35 +0000)]
[RISCV] AsmParser support for the li pseudo instruction
The implementation follows the MIPS backend and expands the pseudo instruction
directly during asm parsing. As the result, only real MC instructions are
emitted to the MCStreamer. The actual expansion to real instructions is
similar to the expansion performed by the GNU Assembler.
This patch supersedes D41949.
Differential Revision: https://reviews.llvm.org/D46118
Patch by Mario Werner.
llvm-svn: 334203
Alex Bradbury [Thu, 7 Jun 2018 15:29:09 +0000 (15:29 +0000)]
[AVR] Fix build after r334078
r334078 added MCSubtargetInfo to fixupNeedsRelaxation and applyFixup. This
patch makes the necessary adjustment for the AVR target.
llvm-svn: 334202
Simon Pilgrim [Thu, 7 Jun 2018 14:53:32 +0000 (14:53 +0000)]
[X86][SSE] Simplify combineVectorTruncationWithPACKUS. NFCI.
Move code only used by combineVectorTruncationWithPACKUS out of combineVectorTruncation.
llvm-svn: 334201
Roman Lebedev [Thu, 7 Jun 2018 14:18:38 +0000 (14:18 +0000)]
[NFC][InstSimplify] Add tests for shl nuw C, %x -> C fold.
%r = shl nuw i8 C, %x
As per langref: If the nuw keyword is present, then the shift produces
a poison value if it shifts out any non-zero bits.
Thus, if the sign bit is set on C, then %x can only be 0,
which means that %r can only be C.
https://rise4fun.com/Alive/WMk
Was mentioned in D47428 review.
llvm-svn: 334200
Sanjay Patel [Thu, 7 Jun 2018 14:11:18 +0000 (14:11 +0000)]
[x86] add tests for backwards propagate mask bug (PR37060, PR37667); NFC
llvm-svn: 334199
Pavel Labath [Thu, 7 Jun 2018 14:03:30 +0000 (14:03 +0000)]
DIERef: move trivial constructors into the header
This enables more inlining/optimization opportunities for a fairly
critical class.
NFCI
llvm-svn: 334198
Guillaume Chatelet [Thu, 7 Jun 2018 14:00:29 +0000 (14:00 +0000)]
[llvm-exegesis] Make BenchmarkRunner handle multiple configurations.
Summary: BenchmarkRunner subclasses can now create many configurations - although this patch still generates one.
Reviewers: courbet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D47877
llvm-svn: 334197
Paul Semel [Thu, 7 Jun 2018 13:30:55 +0000 (13:30 +0000)]
[llvm-objdump] Add -R option
This option prints dynamic relocation entries of the given file
Differential Revision: https://reviews.llvm.org/D47493
llvm-svn: 334196
Hiroshi Inoue [Thu, 7 Jun 2018 13:21:14 +0000 (13:21 +0000)]
[PowerPC] avoid unprofitable Repl32 flag in BitPermutationSelector
BitPermutationSelector sets Repl32 flag for bit groups which can be (potentially) benefit from 32-bit rotate-and-mask instructions with bit replication, i.e. rlwinm/rlwimi copies lower 32 bits into upper 32 bits on 64-bit PowerPC before rotation.
However, enforcing 32-bit instruction sometimes results in redundant generated code.
For example, the following simple code is compiled into rotldi + rlwimi while it can be compiled into only rldimi instruction if Repl32 flag is not set on the bit group for (a & 0xFFFFFFFF).
uint64_t func(uint64_t a, uint64_t b) {
return (a & 0xFFFFFFFF) | (b << 32) ;
}
To avoid such problem, this patch checks the potential benefit of Repl32 flag before setting it. If a bit group does not require rotation (i.e. RLAmt == 0) and won't be merged into another group, we do not benefit from Repl32 flag on this group.
Differential Revision: https://reviews.llvm.org/D47867
llvm-svn: 334195
Petar Jovanovic [Thu, 7 Jun 2018 13:06:06 +0000 (13:06 +0000)]
[Mips] Silencing warnings in instruction info (NFC)
isORCopyInst and isReadOrWriteToDSPReg functions were producing warning
that some statements my fall through.
Patch by Nikola Prica.
Differential Revision: https://reviews.llvm.org/D47876
llvm-svn: 334194
Simon Pilgrim [Thu, 7 Jun 2018 13:01:42 +0000 (13:01 +0000)]
[X86][SSE] Simplify combineVectorTruncationWithPACKSS to reduce code duplication
Simplify combineVectorTruncationWithPACKSS to just a SIGN_EXTEND_INREG followed by using the existing truncateVectorWithPACK instead of duplicating code.
llvm-svn: 334193
Sam McCall [Thu, 7 Jun 2018 12:49:17 +0000 (12:49 +0000)]
[clangd] Code completion: drop explicit injected names/operators, ignore Sema priority
Summary:
Now we have most of Sema's code completion signals incorporated in Quality,
which will allow us to give consistent ranking to sema/index results.
Therefore we can/should stop using Sema priority as an explicit signal.
This fixes some issues like namespaces always having a terrible score.
The most important missing signals are:
- Really dumb/rarely useful completions like:
SomeStruct().^SomeStruct
SomeStruct().^operator=
SomeStruct().~SomeStruct()
We already filter out destructors, this patch adds injected names and
operators to that list.
- type matching the expression context.
Ilya has a plan to add this in a way that's compatible with indexes
(design doc should be shared real soon now!)
Reviewers: ioeric
Subscribers: ilya-biryukov, MaskRay, jkorous, cfe-commits
Differential Revision: https://reviews.llvm.org/D47871
llvm-svn: 334192
Hiroshi Inoue [Thu, 7 Jun 2018 12:49:12 +0000 (12:49 +0000)]
[PowerPC] fix trivial typos in comment, NFC
llvm-svn: 334191
Pavel Labath [Thu, 7 Jun 2018 12:26:18 +0000 (12:26 +0000)]
DebugNamesDWARFIndex: Add type lookup suport
This implements just one of the GetTypes overloads. The other is not
testable from lldb-test so I'm leaving it unimplemented until I figure
out what to do with testing.
llvm-svn: 334190
Matt Arsenault [Thu, 7 Jun 2018 12:16:31 +0000 (12:16 +0000)]
AMDGPU: Fix not including v2f64 in SReg_128
Fixes assertion with calls returning v2f64.
llvm-svn: 334189
Simon Pilgrim [Thu, 7 Jun 2018 11:22:52 +0000 (11:22 +0000)]
[X86][SSE] Add extra trunc(shl) test cases
The existing trunc_shl_17_v8i16_v8i32 test case should (but doesn't) fold to zero, I've added 2 new test cases:
- trunc_shl_16_v8i16_v8i32 which folds to zero (this is actually testing the target faux shuffle combine)
- trunc_shl_15_v8i16_v8i32 which should perform the full shl + truncate
llvm-svn: 334188
Florian Hahn [Thu, 7 Jun 2018 11:09:05 +0000 (11:09 +0000)]
[Mem2Reg] Avoid replacing load with itself in promoteSingleBlockAlloca.
We do the same thing in rewriteSingleStoreAlloca.
Fixes PR37632.
Reviewers: chandlerc, davide, efriedma
Reviewed By: davide
Differential Revision: https://reviews.llvm.org/D47825
llvm-svn: 334187
Pavel Labath [Thu, 7 Jun 2018 10:56:16 +0000 (10:56 +0000)]
DebugNamesDWARFIndex: add namespace lookup support
llvm-svn: 334186
Pavel Labath [Thu, 7 Jun 2018 10:35:28 +0000 (10:35 +0000)]
DebugNamesDWARFIndex: Add support for partial indexes
Summary:
It possible that a single module has indexed and non-indexed compile
units. In this case, we can use the fast indexed lookup for the first
ones and fall back to the manual index for the others.
This patch implements this functionality by adding a units_to_avoid
argument to the ManualDWARFIndex constructor. Any units present in that
list will be ignored for the purposes of manual index. Individual
DebugNamesDWARFIndex then always consult both the manual fallback index
as well as the index in the .debug_names section.
Reviewers: JDevlieghere, clayborg
Subscribers: aprantl, lldb-commits
Differential Revision: https://reviews.llvm.org/D47832
llvm-svn: 334185
Matt Arsenault [Thu, 7 Jun 2018 10:15:20 +0000 (10:15 +0000)]
AMDGPU: Use scalar operations for f16 fabs/fneg patterns
Fixes unnecessary differences between subtargets.
llvm-svn: 334184
Simon Pilgrim [Thu, 7 Jun 2018 10:13:09 +0000 (10:13 +0000)]
[X86] Regenerate rotate tests
Add 32-bit tests to show missed SHLD/SHRD cases
llvm-svn: 334183
Paul Semel [Thu, 7 Jun 2018 10:05:25 +0000 (10:05 +0000)]
[llvm-strip] Expose --strip-unneeded option
Differential Revision: https://reviews.llvm.org/D47818
llvm-svn: 334182
Pavel Labath [Thu, 7 Jun 2018 10:04:44 +0000 (10:04 +0000)]
DebugNamesDWARFIndex: Add ability to lookup variables
Summary:
This patch adds the ability to lookup variables to the DWARF v5 index
class.
During review we discovered an inconsistency between how the existing
two indexes handle looking up qualified names of the variables:
- manual index would return a value if the input string exactly matched
the demangled name of some variable.
- apple index ignored the context and returned any variable with the
same base name.
So, this patch also rectifies that situation:
- it removes all context handling from the index classes. The
GetGlobalVariables functions now just take a base name. For manual
index, this meant we can stop putting demangled names into the
variable index (this matches the behavior for functions).
- context extraction is put into SymbolFileDWARF, so that it is common
to all indexes.
- additional filtering based on the context is also done in
SymbolFileDWARF. This is done via a simple substring search, which is
not ideal, but it matches what we are doing for functions (cf.
Module::LookupInfo::Prune).
Reviewers: clayborg, JDevlieghere
Subscribers: aprantl, lldb-commits
Differential Revision: https://reviews.llvm.org/D47781
llvm-svn: 334181
Matt Arsenault [Thu, 7 Jun 2018 09:54:49 +0000 (09:54 +0000)]
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
Krasimir Georgiev [Thu, 7 Jun 2018 09:46:24 +0000 (09:46 +0000)]
[clang-format] Consider tok::hashhash in python-style comments
Summary: We were missing the case when python-style comments in text protos start with `##`.
Subscribers: cfe-commits
Differential Revision: https://reviews.llvm.org/D47870
llvm-svn: 334179
Clement Courbet [Thu, 7 Jun 2018 09:26:33 +0000 (09:26 +0000)]
[X86][NFC] Fix harmless typo in BtVer2 model.
See D46356 for context.
llvm-svn: 334178
David Carlier [Thu, 7 Jun 2018 08:58:34 +0000 (08:58 +0000)]
[LLDB] Unit tests / typo fix
removing unnecessary comma.
llvm-svn: 334177
Haojian Wu [Thu, 7 Jun 2018 08:49:55 +0000 (08:49 +0000)]
[clangd] Fix using the incorrect Index for go-to-definition.
Reviewers: sammccall
Subscribers: ilya-biryukov, ioeric, MaskRay, jkorous, cfe-commits
Differential Revision: https://reviews.llvm.org/D47869
llvm-svn: 334176
Tomasz Krupa [Thu, 7 Jun 2018 08:48:45 +0000 (08:48 +0000)]
[X86] Block UndefRegUpdate
Summary: Prevent folding of operations with memory loads when one of the sources has undefined register update.
Reviewers: craig.topper
Subscribers: llvm-commits, mike.dvoretsky, ashlykov
Differential Revision: https://reviews.llvm.org/D47621
llvm-svn: 334175
Gabor Buella [Thu, 7 Jun 2018 08:48:36 +0000 (08:48 +0000)]
[CodeGen] Improve diagnostics related to target attributes
Summary:
When requirement imposed by __target__ attributes on functions
are not satisfied, prefer printing those requirements, which
are explicitly mentioned in the attributes.
This makes such messages more useful, e.g. printing avx512f instead of avx2
in the following scenario:
```
$ cat foo.c
static inline void __attribute__((__always_inline__, __target__("avx512f")))
x(void)
{
}
int main(void)
{
x();
}
$ clang foo.c
foo.c:7:2: error: always_inline function 'x' requires target feature 'avx2', but would be inlined into function 'main' that is compiled without support for 'avx2'
x();
^
1 error generated.
```
bugzilla: https://bugs.llvm.org/show_bug.cgi?id=37338
Reviewers: craig.topper, echristo, dblaikie
Reviewed By: craig.topper, echristo
Differential Revision: https://reviews.llvm.org/D46541
llvm-svn: 334174
Max Kazantsev [Thu, 7 Jun 2018 08:47:19 +0000 (08:47 +0000)]
[NFC] Use variable instead of accessing pair many times
llvm-svn: 334173
Philip Pfaffe [Thu, 7 Jun 2018 08:32:13 +0000 (08:32 +0000)]
Run clang-format
llvm-svn: 334172
Tomasz Krupa [Thu, 7 Jun 2018 08:20:28 +0000 (08:20 +0000)]
Test commit access.
Added a bunch of periods after comments.
llvm-svn: 334171
Sam McCall [Thu, 7 Jun 2018 08:16:36 +0000 (08:16 +0000)]
[clangd] fix unintended fallthrough in scope-based scoring
llvm-svn: 334170
Guillaume Chatelet [Thu, 7 Jun 2018 08:11:54 +0000 (08:11 +0000)]
[llvm-exegesis] Add a Configuration object for Benchmark.
Summary: This is the first step to have the BenchmarkRunner create and measure many different configurations (different initial values for instance).
Reviewers: courbet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D47826
llvm-svn: 334169
Kamil Rytarowski [Thu, 7 Jun 2018 07:55:20 +0000 (07:55 +0000)]
Disable recursive interceptors in signal(3)/MSan
Summary:
signal(3) on NetBSD calls internally sigaction(2).
Without disabling the recursive interceptor, there are
false positives about uninitialized memory reads inside libc.
This change fixes execution of such programs as sh(1) and
vmstat(1) in the NetBSD userland.
Sponsored by <The NetBSD Foundation>
Reviewers: eugenis, vitalybuka, joerg
Reviewed By: vitalybuka
Subscribers: llvm-commits, #sanitizers
Tags: #sanitizers
Differential Revision: https://reviews.llvm.org/D47650
llvm-svn: 334168
Guillaume Chatelet [Thu, 7 Jun 2018 07:51:16 +0000 (07:51 +0000)]
[llvm-exegesis] Improve error reporting.
Summary: BenchmarkResult IO functions now return an Error or Expected so caller can deal take proper action.
Reviewers: courbet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D47868
llvm-svn: 334167
Philip Pfaffe [Thu, 7 Jun 2018 07:50:55 +0000 (07:50 +0000)]
Fix a missing lambda return type that tripped the builders
llvm-svn: 334166
Guillaume Chatelet [Thu, 7 Jun 2018 07:40:40 +0000 (07:40 +0000)]
[llvm-exegesis] Serializes instruction's operand in BenchmarkResult's key.
Summary: Follow up patch to https://reviews.llvm.org/D47764.
Reviewers: courbet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D47785
llvm-svn: 334165
Clement Courbet [Thu, 7 Jun 2018 07:37:49 +0000 (07:37 +0000)]
[X86][NFC] Fix harmless typos in BDW/ZnVer1 sched models.
See D46356 for context.
llvm-svn: 334164
Karl-Johan Karlsson [Thu, 7 Jun 2018 07:20:33 +0000 (07:20 +0000)]
[BranchFolding] Fix live-in's when hoisting code
Summary:
When the branch folder hoist code into a predecessor it adjust live-in's
in the blocks it hoist code from. However it fail to handle hoisted code
that contain a defed register that originally is live-in in the block
through a super register.
This is fixed by replacing the live-in handling code with calls to
utility functions in LivePhysRegs.
Reviewers: kparzysz, gberry, MatzeB, uweigand, aprantl
Reviewed By: kparzysz
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D47529
llvm-svn: 334163
Sam McCall [Thu, 7 Jun 2018 06:55:59 +0000 (06:55 +0000)]
[clangd] Make workspace/symbols actually rank its results.
Summary: The index doesn't actually return results in ranked order.
Reviewers: hokein
Subscribers: ilya-biryukov, ioeric, MaskRay, jkorous, cfe-commits
Differential Revision: https://reviews.llvm.org/D47821
llvm-svn: 334162
Jonas Paulsson [Thu, 7 Jun 2018 05:59:07 +0000 (05:59 +0000)]
[SystemZ] Build Load And Test from scratch in convertToLoadAndTest.
This is needed to get CC operand in right place, as expected by the
SchedModel.
Review: Ulrich Weigand
https://reviews.llvm.org/D47820
llvm-svn: 334161
Richard Trieu [Thu, 7 Jun 2018 03:20:30 +0000 (03:20 +0000)]
Change return value of trivial visibility check.
Previous, if no Decl's were checked, visibility was set to false. Switch it
so that in cases of no Decl's, return true. These are the Decl's after being
filtered. Also remove an unreachable return statement since it is directly
after another return statement.
llvm-svn: 334160
Craig Topper [Thu, 7 Jun 2018 02:46:02 +0000 (02:46 +0000)]
[X86] Add back _mask, _maskz, and _mask3 builtins for some 512-bit fmadd/fmsub/fmaddsub/fmsubadd builtins.
Summary:
We recently switch to using a selects in the intrinsics header files for FMA instructions. But the 512-bit versions support flavors with rounding mode which must be an Integer Constant Expression. This has forced those intrinsics to be implemented as macros. As it stands now the mask and mask3 intrinsics evaluate one of their macro arguments twice. If that argument itself is another intrinsic macro, we can end up over expanding macros. Or if its something we can CSE later it would show up multiple times when it shouldn't.
I tried adding __extension__ around the macro and making it an expression statement and declaring a local variable. But whatever name you choose for the local variable can never be used as the name of an input to the macro in user code. If that happens you would end up with the same name on the LHS and RHS of an assignment after expansion. We might be safe if we use __ in front of the variable names because those names are reserved and user code shouldn't use that, but I wasn't sure I wanted to make that claim.
The other option which I've chosen here, is to add back _mask, _maskz, and _mask3 flavors of the builtin which we will expand in CGBuiltin.cpp to replicate the argument as needed and insert any fneg needed on the third operand to make a subtract. The _maskz isn't truly necessary if we have an unmasked version or if we use the masked version with a -1 mask and wrap a select around it. But I've chosen to make things more uniform.
I separated out the scalar builtin handling to avoid too many things going on in EmitX86FMAExpr. It was different enough due to the extract and insert that the minor duplication of the CreateCall was probably worth it.
Reviewers: tkrupa, RKSimon, spatel, GBuella
Reviewed By: tkrupa
Subscribers: cfe-commits
Differential Revision: https://reviews.llvm.org/D47724
llvm-svn: 334159
Kostya Serebryany [Thu, 7 Jun 2018 01:40:20 +0000 (01:40 +0000)]
[libFuzzer] make the corpus elements aware of their data flow traces
llvm-svn: 334158
Sam Clegg [Thu, 7 Jun 2018 01:27:07 +0000 (01:27 +0000)]
[WebAssembly] Add --export-all flag
This causes all symbols to be exported in the final wasm binary
even if they were not compiled with default visibility.
This feature is useful for the emscripten toolchain that has a
corresponding EXPORT_ALL feature which allows the JS code to
interact with all C function.
Differential Revision: https://reviews.llvm.org/D47806
llvm-svn: 334157
Kostya Serebryany [Thu, 7 Jun 2018 01:18:43 +0000 (01:18 +0000)]
[libFuzzer] simplify a test, hopefully to fix the bot
llvm-svn: 334156
Han Shen [Thu, 7 Jun 2018 00:55:54 +0000 (00:55 +0000)]
ClangTidy fix - 'clang::Sema::checkAllowedCUDAInitializer' has a definition with different parameter names.
llvm-svn: 334155
Bob Haarman [Thu, 7 Jun 2018 00:50:03 +0000 (00:50 +0000)]
[COFF] report file containing unsupported relocation
Summary:
When reporting an unsupported relocation type, let's also report the
file we encountered it in to aid diagnosis.
Reviewers: ruiu, rnk
Reviewed By: rnk
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45911
llvm-svn: 334154
Sunil Srivastava [Thu, 7 Jun 2018 00:42:59 +0000 (00:42 +0000)]
Change the wording of RTTI errors to make them more generic.
An attempt to use dynamic_cast while rtti is disabled, used to emit the error:
cannot use dynamic_cast with -fno-rtti
and a similar one for typeid.
This patch changes that to:
use of dynamic_cast requires -frtti
Differential Revision: https://reviews.llvm.org/D47291
llvm-svn: 334153
Vitaly Buka [Thu, 7 Jun 2018 00:26:06 +0000 (00:26 +0000)]
[sanitizer] Don't use internal_unlink on Windows
llvm-svn: 334152
Richard Trieu [Thu, 7 Jun 2018 00:20:58 +0000 (00:20 +0000)]
[ODRHash] Adjust info stored for FunctionTemplateDecl.
Avoid storing information for definitions since those can be out-of-line and
vary between modules even when the declarations are the same.
llvm-svn: 334151
Michael Zolotukhin [Thu, 7 Jun 2018 00:19:29 +0000 (00:19 +0000)]
SpeculativeExecution Pass: Set PreserveCFG to avoid unnecessary analyses invalidation.
The pass doesn't touch CFG in any way, only moves instructions between
blocks.
llvm-svn: 334150
Peter Collingbourne [Thu, 7 Jun 2018 00:06:41 +0000 (00:06 +0000)]
Add definition for ELF dynamic tag DT_SYMTAB_SHNDX.
DT_SYMTAB_SHNDX is defined in generic-abi:
http://www.sco.com/developers/gabi/latest/ch5.dynamic.html
Patch by Rahul Chaudhry!
Differential Revision: https://reviews.llvm.org/D47803
llvm-svn: 334149
Rui Ueyama [Thu, 7 Jun 2018 00:04:47 +0000 (00:04 +0000)]
Expand the file comment for the error handlers.
Differential Revision: https://reviews.llvm.org/D47790
llvm-svn: 334148
Peter Collingbourne [Thu, 7 Jun 2018 00:02:07 +0000 (00:02 +0000)]
llvm-readobj: fix printing number of relocations in Android packed format.
With '-elf-output-style=GNU -relocations', a header containing the number
of entries is printed before all the relocation entries in the section.
For Android packed format, we need to perform the unpacking first before
we can get the actual number of relocations in the section.
Patch by Rahul Chaudhry!
Differential Revision: https://reviews.llvm.org/D47800
llvm-svn: 334147
Kostya Serebryany [Wed, 6 Jun 2018 23:24:41 +0000 (23:24 +0000)]
[libFuzzer] remove an experimental flag -use_feature_frequency
llvm-svn: 334146
Shoaib Meenai [Wed, 6 Jun 2018 23:09:02 +0000 (23:09 +0000)]
[Driver] Stop passing -fseh-exceptions for x86_64-windows-msvc
-fseh-exceptions is only meaningful for MinGW targets, and that driver
already has logic to pass either -fdwarf-exceptions or -fseh-exceptions
as appropriate. -fseh-exceptions is just a no-op for MSVC triples, and
passing it to cc1 causes unnecessary confusion.
Differential Revision: https://reviews.llvm.org/D47850
llvm-svn: 334145
Petr Hosek [Wed, 6 Jun 2018 22:59:14 +0000 (22:59 +0000)]
[Fuzzer] Use private libc++ even for Fuchsia
On Fuchsia, we use libc++ compiled with ASan for our ASan built
executable which means we cannot use the same libc++ for libFuzzer when
building fuzz targets, instead we'll link a custom internal libc++ into
Fuchsia's build of libFuzzer like we already do on Linux.
Differential Revision: https://reviews.llvm.org/D47835
llvm-svn: 334144
Artem Belevich [Wed, 6 Jun 2018 22:37:25 +0000 (22:37 +0000)]
[CUDA] Check initializers of instantiated template variables.
We were already performing checks on non-template variables,
but the checks on templated ones were missing.
Differential Revision: https://reviews.llvm.org/D45231
llvm-svn: 334143
Stanislav Mekhanoshin [Wed, 6 Jun 2018 22:22:32 +0000 (22:22 +0000)]
[AMDGPU] Improve reciprocal handling
When denormals are supported we are producing a full division for
1.0f / x. That still can be replaced by the faster version:
bool c = fabs(x) > 0x1.0p+96f;
float s = c ? 0x1.0p-32f : 1.0f;
x *= s;
return s * v_rcp_f32(x)
in case if requested accuracy is 2.5ulp or less. The same version
is used if denormals are not supported for non 1.0 numerators, where
just v_rcp_f32 is then used for 1.0 numerator.
The optimization of 1/x is extended to the case -1/x, which is the
same except for the resulting sign bit.
OpenCL conformance passed with both enabled and disabled denorms.
Differential Revision: https://reviews.llvm.org/D47805
llvm-svn: 334142
Teresa Johnson [Wed, 6 Jun 2018 22:22:13 +0000 (22:22 +0000)]
[ThinLTO/lld] Document constant bool ModuleSummaryIndex parameter (NFC)
Makes this consistent with other ModuleSummaryIndex constructor calls.
llvm-svn: 334141
Teresa Johnson [Wed, 6 Jun 2018 22:22:01 +0000 (22:22 +0000)]
[ThinLTO] Rename index IsAnalysis flag to HaveGVs (NFC)
With the upcoming patch to add summary parsing support, IsAnalysis would
be true in contexts where we are not performing module summary analysis.
Rename to the more specific and approprate HaveGVs, which is essentially
what this flag is indicating.
llvm-svn: 334140
Petr Hosek [Wed, 6 Jun 2018 22:10:12 +0000 (22:10 +0000)]
[CMake] Passthrough additional flags to custom libcxx CMake build
This is needed when we're cross-compiling compiler-rt.
Differential Revision: https://reviews.llvm.org/D47834
llvm-svn: 334139
Vitaly Buka [Wed, 6 Jun 2018 22:05:48 +0000 (22:05 +0000)]
[sanitizer] Replace deprecated mktemp with mkstemp
llvm-svn: 334138
Sanjay Patel [Wed, 6 Jun 2018 21:58:12 +0000 (21:58 +0000)]
[InstCombine] fold another shifty abs pattern to cmp+sel (PR36036)
The bug report:
https://bugs.llvm.org/show_bug.cgi?id=36036
...requests a DAG change for this, but an IR canonicalization
probably handles most cases. If we still want to match this
pattern in the backend, there's a proposal for that too:
D47831
Alive proofs including nsw/nuw cases that were first noted in:
D46988
https://rise4fun.com/Alive/Kmp
This patch is largely copied from the existing code that was
initially added with:
D40984
...but I didn't see much gain from trying to share code.
llvm-svn: 334137
Petr Hosek [Wed, 6 Jun 2018 21:43:37 +0000 (21:43 +0000)]
[CMake] Pass additional CMake tools to external projects
This is needed when the external projects try to use other tools
besides just the compiler and the linker.
Differential Revision: https://reviews.llvm.org/D47833
llvm-svn: 334136
Han Shen [Wed, 6 Jun 2018 21:43:34 +0000 (21:43 +0000)]
Correct aligment computation for shared object symbols.
The original computation for shared object symbol alignment is wrong when
st_value equals 0. It is very unusual for dso symbols to have st_value equal 0.
But when it happens, it causes obscure run time bugs.
Differential Revision: https://reviews.llvm.org/D47602
llvm-svn: 334135
Michael Kruse [Wed, 6 Jun 2018 21:37:35 +0000 (21:37 +0000)]
[OpTree] Introduce shortcut for computing the def->target mapping. NFCI.
In case the schedule has not changed and the operand tree root uses a
value defined in an ancestor loop, the def-to-target mapping is trivial.
For instance, the SCoP
for (int i < 0; i < N; i+=1) {
DefStmt:
D = ...;
for (int j < 0; j < N; j+=1) {
TargetStmt:
use(D);
}
}
has DefStmt-to-TargetStmt mapping of
{ DefStmt[i] -> TargetStmt[i,j] }
This should apply on the majority of def-to-target mappings.
This patch detects this case and directly constructs the expected
mapping. It assumes that the mapping never crosses the loop header
DefStmt is in, which ForwardOpTree does not support at the moment
anyway.
Differential Revision: https://reviews.llvm.org/D47752
llvm-svn: 334134
Sanjay Patel [Wed, 6 Jun 2018 21:32:42 +0000 (21:32 +0000)]
[InstCombine] add tests for another abs() pattern (PR36036); NFC
llvm-svn: 334133
Matt Arsenault [Wed, 6 Jun 2018 21:28:11 +0000 (21:28 +0000)]
AMDGPU: Custom lower v2f16 fneg/fabs with illegal f16
Fixes terrible code on targets without f16 support. The
legalization creates a mess that is difficult to recover
from. Also should avoid randomly breaking these tests
multiple times in sequence in future commits.
Some regressions in cases where it happens to be better
to pull the source modifier after the conversion.
llvm-svn: 334132
Alexander Shaposhnikov [Wed, 6 Jun 2018 21:23:19 +0000 (21:23 +0000)]
[llvm-strip] Expose --discard-all option
Expose objcopy's --discard-all option in llvm-strip.
Test plan: make check-all
Differential revision: https://reviews.llvm.org/D47750
llvm-svn: 334131
Vitaly Buka [Wed, 6 Jun 2018 20:53:43 +0000 (20:53 +0000)]
[sanitizer] Cleanup ReadFileToVector and ReadFileToBuffer
Summary:
Added unit-test.
Fixed behavior of max_len argument.
Call read syscall with all available buffer, not just a page.
Reviewers: eugenis
Subscribers: kubamracek, mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D46618
llvm-svn: 334130
Rui Ueyama [Wed, 6 Jun 2018 20:46:08 +0000 (20:46 +0000)]
Remove an unrelated file accidentally submitted as part of r334095.
llvm-svn: 334129
Yaxun Liu [Wed, 6 Jun 2018 19:44:10 +0000 (19:44 +0000)]
[HIP] Fix unbundling
HIP uses clang-offload-bundler to bundle intermediate files for host
and different gpu archs together. When a file is unbundled,
clang-offload-bundler should be called only once, and the objects
for host and different gpu archs should be passed to the next
jobs. This is because Driver maintains CachedResults which maps
triple-arch string to output files for each job.
This patch fixes a bug in Driver::BuildJobsForActionNoCache which
uses incorrect key for CachedResults for HIP which causes
clang-offload-bundler being called mutiple times and incorrect
output files being used.
It only affects HIP.
Differential Revision: https://reviews.llvm.org/D47555
llvm-svn: 334128
Roman Lebedev [Wed, 6 Jun 2018 19:38:27 +0000 (19:38 +0000)]
[InstCombine] PR37603: low bit mask canonicalization
Summary:
This is [[ https://bugs.llvm.org/show_bug.cgi?id=37603 | PR37603 ]].
https://godbolt.org/g/VCMNpS
https://rise4fun.com/Alive/idM
When doing bit manipulations, it is quite common to calculate some bit mask,
and apply it to some value via `and`.
The typical C code looks like:
```
int mask_signed_add(int nbits) {
return (1 << nbits) - 1;
}
```
which is translated into (with `-O3`)
```
define dso_local i32 @mask_signed_add(int)(i32) local_unnamed_addr #0 {
%2 = shl i32 1, %0
%3 = add nsw i32 %2, -1
ret i32 %3
}
```
But there is a second, less readable variant:
```
int mask_signed_xor(int nbits) {
return ~(-(1 << nbits));
}
```
which is translated into (with `-O3`)
```
define dso_local i32 @mask_signed_xor(int)(i32) local_unnamed_addr #0 {
%2 = shl i32 -1, %0
%3 = xor i32 %2, -1
ret i32 %3
}
```
Since we created such a mask, it is quite likely that we will use it in `and` next.
And then we may get rid of `not` op by folding into `andn`.
But now that i have actually looked:
https://godbolt.org/g/VTUDmU
_some_ backend changes will be needed too.
We clearly loose `bzhi` recognition.
Reviewers: spatel, craig.topper, RKSimon
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D47428
llvm-svn: 334127
Roman Lebedev [Wed, 6 Jun 2018 19:38:21 +0000 (19:38 +0000)]
[InstCombine][NFC] PR37603: low bit mask canonicalization tests
Differential Revision: https://reviews.llvm.org/D47427
llvm-svn: 334126
Roman Lebedev [Wed, 6 Jun 2018 19:38:16 +0000 (19:38 +0000)]
[X86] Emit BZHI when mask is ~(-1 << nbits))
Summary:
In D47428, i propose to choose the `~(-(1 << nbits))` as the canonical form of low-bit-mask formation.
As it is seen from these tests, there is a reason for that.
AArch64 currently better handles `~(-(1 << nbits))`, but not the more traditional `(1 << nbits) - 1` (sic!).
The other way around for X86.
It would be much better to canonicalize.
This patch is completely monkey-typing.
I don't really understand how this works :)
I have based it on `// x & (-1 >> (32 - y))` pattern.
Also, when we only have `BMI`, i wonder if we could use `BEXTR` with `start=0` ?
Related links:
https://bugs.llvm.org/show_bug.cgi?id=36419
https://bugs.llvm.org/show_bug.cgi?id=37603
https://bugs.llvm.org/show_bug.cgi?id=37610
https://rise4fun.com/Alive/idM
Reviewers: craig.topper, spatel, RKSimon, javed.absar
Reviewed By: craig.topper
Subscribers: kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D47453
llvm-svn: 334125
Roman Lebedev [Wed, 6 Jun 2018 19:38:10 +0000 (19:38 +0000)]
[NFC][X86][AArch64] Reorganize/cleanup BZHI test patterns
Summary:
In D47428, i propose to choose the `~(-(1 << nbits))` as the canonical form of low-bit-mask formation.
As it is seen from these tests, there is a reason for that.
AArch64 currently better handles `~(-(1 << nbits))`, but not the more traditional `(1 << nbits) - 1` (sic!).
The other way around for X86.
It would be much better to canonicalize.
It would seem that there is too much tests, but this is most of all the auto-generated possible variants
of C code that one would expect for BZHI to be formed, and then manually cleaned up a bit.
So this should be pretty representable, which somewhat good coverage...
Related links:
https://bugs.llvm.org/show_bug.cgi?id=36419
https://bugs.llvm.org/show_bug.cgi?id=37603
https://bugs.llvm.org/show_bug.cgi?id=37610
https://rise4fun.com/Alive/idM
Reviewers: javed.absar, craig.topper, RKSimon, spatel
Reviewed By: RKSimon
Subscribers: kristof.beyls, llvm-commits, RKSimon, craig.topper, spatel
Differential Revision: https://reviews.llvm.org/D47452
llvm-svn: 334124
Krzysztof Parzyszek [Wed, 6 Jun 2018 19:34:40 +0000 (19:34 +0000)]
[Hexagon] Implement vector-pair zero as V6_vsubw_dv
llvm-svn: 334123
Simon Pilgrim [Wed, 6 Jun 2018 19:31:39 +0000 (19:31 +0000)]
Fix MSVC 'not all control paths return a value' warning. NFCI.
llvm-svn: 334122
Craig Topper [Wed, 6 Jun 2018 19:15:15 +0000 (19:15 +0000)]
[X86] Properly disassemble gather/scatter instructions where xmm4/ymm4/zmm4 are used as the index.
These encodings correspond to the cases in the normal encoding scheme where there is no index and our modrm reading code initially decodes it as such. The VSIB handling code tried to compensate for this, but failed to add the base needed to make later code do the right thing.
Fixes PR37712.
llvm-svn: 334121
Craig Topper [Wed, 6 Jun 2018 19:15:12 +0000 (19:15 +0000)]
[X86] Rename vy512mem->vy512xmem and vz256xmem->vz256mem.
The index size is represented by the letter after the 'v'. The number represents the memory size. If an 'x' appears after the number its means the index register can be from VR128X/VR256X instead of VR128/VR256.
As vy512mem uses a VR256X index it should have an x.
And vz256mem uses a VR512 index so it shouldn't have an x.
I admit these names kind of suck and are confusing.
llvm-svn: 334120
Simon Pilgrim [Wed, 6 Jun 2018 19:06:09 +0000 (19:06 +0000)]
[X86][BtVer2] Add support for all vector instructions that should match the dependency-breaking 'zero-idiom'
As detailed on Agner's Microarchitecture doc (21.8 AMD Bobcat and Jaguar pipeline - Dependency-breaking instructions), all these instructions are dependency breaking and zero the destination register.
llvm-svn: 334119