Bernhard Rosenkränzer [Wed, 10 Feb 2016 16:19:46 +0000 (17:19 +0100)]
freedreno/ir3: Get rid of nested functions
This allows building Freedreno with clang
Signed-off-by: Bernhard Rosenkränzer <bero@linaro.org>
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Chris Forbes [Tue, 18 Nov 2014 08:49:53 +0000 (21:49 +1300)]
i965/blorp: Fix hiz ops on MSAA surfaces
Two things were broken here:
- The depth/stencil surface dimensions were broken for MSAA.
- Sample count was programmed incorrectly.
Result was the depth resolve didn't work correctly on MSAA surfaces, and
so sampling the surface later produced garbage.
Fixes the new piglit test arb_texture_multisample-sample-depth, and
various artifacts in 'tesseract' with msaa=4 glineardepth=0.
Fixes freedesktop bug #76396.
Not observed any piglit regressions on Haswell.
v2: Just set brw_hiz_op_params::dst.num_samples rather than adding a
helper function (Ken).
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
v3: moved the alignment needed for hiz+msaa to brw_blorp.cpp, as
suggested by Chad Versace (Alejandro Piñeiro on behalf of Chris
Forbes)
Signed-off-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
Tested-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Topi Pohjolainen [Sun, 3 Jan 2016 13:06:09 +0000 (15:06 +0200)]
i965/gen8: Remove dead assertion
The assertion is inside a condition mandating num_samples > 1 and
therefore the first half of the constraint is always met. The
second half in turn would only be applicable for single sampled
case and moreover it is trying to falsely check against surface
type instead of format.
Subsequent patches will introduce proper support for the lossless
compression and dropping this here makes the patches a little
simpler.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
Topi Pohjolainen [Mon, 7 Dec 2015 19:58:33 +0000 (21:58 +0200)]
i965: Use constant pointer when checking for compression
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
Brian Paul [Wed, 10 Feb 2016 03:09:26 +0000 (20:09 -0700)]
mesa: fix trivial comment typo in dlist.c
Kenneth Graunke [Thu, 14 Jan 2016 04:33:17 +0000 (20:33 -0800)]
i965/vec4: Drop support for ATTR as an instruction destination.
This is no longer necessary...and it doesn't make much sense to
have inputs as destinations.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Thu, 14 Jan 2016 04:33:16 +0000 (20:33 -0800)]
i965/vec4/gs: Stop munging the ATTR containing gl_PointSize.
gl_PointSize is delivered in the .w component of the VUE header, while
the language expects it to be a float (and thus in the .x component).
Previously, we emitted MOVs to copy it over to the .x component.
But this is silly - we can just use a .wwww swizzle and access it
without copying anything or clobbering the value stored at .x
(which admittedly is useless).
Removes the last use of ATTR destinations.
v2: Use BRW_SWIZZLE_WWWW, not SWIZZLE_WWWW (caught by GCC).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Thu, 14 Jan 2016 04:33:15 +0000 (20:33 -0800)]
i965: Apply VS attribute workarounds in NIR.
This patch re-implements the pre-Haswell VS attribute workarounds.
Instead of emitting shader code in the vec4 backend, we now simply
call a NIR pass to emit the necessary code.
This simplifies the vec4 backend. Beyond deleting code, it removes
the primary use of ATTR as a destination. It also eliminates the
requirement that the vec4 VS backend express the ATTR file in terms
of VERT_ATTRIB_* locations, giving us a bit more flexibility.
This approach is a little different: rather than munging the attributes
at the top, we emit code to fix them up when they're accessed. However,
we run the optimizer afterwards, so CSE should eliminate the redundant
math. It may even be able to fuse it with other calculations based on
the input value.
shader-db does not handle non-default NOS settings, so I have no
statistics about this patch.
Note that the scalar backend does not implement VS attribute
workarounds, as they are unnecessary on hardware which allows SIMD8 VS.
v2: Do one multiply for FIXED rescaling and select components from
either the original or scaled copy, rather than multiplying each
component separately (suggested by Matt Turner).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Brian Paul [Tue, 9 Feb 2016 21:44:54 +0000 (14:44 -0700)]
st/mesa: clarify some texture target code in st_cb_drawpix.c
Use st->internal_target instead of PIPE_TEXTURE_2D when choosing the
texture format. Probably no real difference, but let's be consistent.
Simplify a test when determining whether we need normalized texcoords.
Add a new assertion.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Brian Paul [Tue, 9 Feb 2016 21:35:31 +0000 (14:35 -0700)]
st/mesa: fix bitmap texture target code and simplify tex sampler state
Bitmaps may be drawn with a PIPE_TEXTURE_2D or PIPE_TEXTURE_RECT resource
as determined at context creation by checking if PIPE_CAP_NPOT_TEXTURES is
supported. But many places in the bitmap code were hard-coded to use
PIPE_TEXTURE_2D. Use st->internal_target instead.
I think an older NV chip is the only case where a gallium driver does not
support NPOT textures. Bitmap drawing was probably broken for that GPU.
Also, we only need one sampler state with texcoord normalization set up
according to st->internal_target.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Brian Paul [Tue, 9 Feb 2016 21:20:41 +0000 (14:20 -0700)]
st/mesa: use MAX3() macro, as we do for sampler view code below
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Brian Paul [Tue, 9 Feb 2016 21:19:25 +0000 (14:19 -0700)]
st/mesa: move some st_cb_drawpixels.c code, add comments
Nanley Chery [Sat, 6 Feb 2016 00:25:28 +0000 (16:25 -0800)]
mesa/readpix: Dedent former _mesa_readpixels() if block
Formatting patch split out for easy reviewing.
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Nanley Chery [Sat, 6 Feb 2016 00:25:01 +0000 (16:25 -0800)]
mesa/readpix: Don't clip in _mesa_readpixels()
The clipping is performed higher up in the call-chain.
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Nanley Chery [Sat, 6 Feb 2016 00:21:33 +0000 (16:21 -0800)]
mesa/readpix: Clip ReadPixels() area to the ReadBuffer's
The fast path for Intel's ReadPixels() unintentionally omits clipping
the specified area to a valid one. Rather than clip in various
corner-cases, perform this operation in the API validation stage.
The bug in intel_readpixels_tiled_memcpy() showed itself when the winsys
ReadBuffer's height was smaller than the one specified by ReadPixels().
yoffset became negative, which was an invalid input for tiled_to_linear().
v2: Move clipping to validation stage (Jason)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92193
Reported-by: Marta Löfstedt <marta.lofstedt@intel.com>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Nanley Chery [Sat, 6 Feb 2016 00:20:01 +0000 (16:20 -0800)]
mesa/image: Make _mesa_clip_readpixels() work with renderbuffers
v2: Use gl_renderbuffer::{Width,Height} (Jason)
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Jason Ekstrand [Tue, 3 Nov 2015 02:39:17 +0000 (18:39 -0800)]
i965/vec4: Plumb separate surfaces and samplers through from NIR
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Tue, 3 Nov 2015 02:28:49 +0000 (18:28 -0800)]
i965/vec4: Separate the sampler from the surface in generate_tex
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Sat, 6 Feb 2016 02:24:02 +0000 (18:24 -0800)]
i965/fs: Plumb separate surfaces and samplers through from NIR
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Mon, 2 Nov 2015 23:24:05 +0000 (15:24 -0800)]
i965/fs: Separate the sampler from the surface in generate_tex
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Sat, 6 Feb 2016 02:39:13 +0000 (18:39 -0800)]
i965/fs: Add an enum for keeping track of texture instruciton sources
These logical texture instructions can have a *lot* of sources. It's much
safer if we have symbolic names for them.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Tue, 3 Nov 2015 01:58:29 +0000 (17:58 -0800)]
nir: Separate texture from sampler in nir_tex_instr
This commit adds the capability to NIR to support separate textures and
samplers. As it currently stands, glsl_to_nir only sets the texture deref
and leaves the sampler deref alone as it did before and nir_lower_samplers
assumes this. Backends can still assume that they are combined and only
look at only at the texture index. Or, if they wish, they can assume that
they are separate because nir_lower_samplers, tgsi_to_nir, and prog_to_nir
all set both texture and sampler index whenever a sampler is required (the
two indices are the same in this case).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Sat, 6 Feb 2016 17:05:10 +0000 (09:05 -0800)]
nir/tex_instr: Rename sampler to texture
We're about to separate the two concepts. When we do, the sampler will
become optional. Doing a rename first makes the separation a bit more
safe because drivers that depend on GLSL or TGSI behaviour will be fine to
just use the texture index all the time.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Tue, 9 Feb 2016 18:48:42 +0000 (10:48 -0800)]
nir: Add some braces around loops and ifs
Kenneth Graunke [Tue, 5 Jan 2016 09:53:57 +0000 (01:53 -0800)]
i965: Explicitly write the "TR DS Cache Disable" bit at TCS EOT.
Bit 0 of the Patch Header is "TR DS Cache Disable". Setting that bit
disables the DS Cache for tessellator-output topologies resulting in
stitch-transition regions (but leaves it enabled for other cases).
We probably shouldn't leave this to chance - the URB could contain
garbage - which could result in the cache randomly being turned on
or off.
This patch makes the final EOT write 0 to the first DWord (which
only contains this one bit). This ensures the cache is always on.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Rob Clark [Thu, 21 Jan 2016 20:15:56 +0000 (15:15 -0500)]
freedreno/ir3: use const_index helpers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Thu, 21 Jan 2016 19:12:58 +0000 (14:12 -0500)]
nir: use const_index helpers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Rob Clark [Thu, 21 Jan 2016 18:49:07 +0000 (13:49 -0500)]
ptn: use const_index helpers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Rob Clark [Thu, 21 Jan 2016 18:36:37 +0000 (13:36 -0500)]
ttn: use const_index helpers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Rob Clark [Thu, 21 Jan 2016 18:32:37 +0000 (13:32 -0500)]
ttn: small logic cleanup
The only case where dim!=NULL is where op==load_ubo. But using
op==load_ubo is less confusing.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Thu, 21 Jan 2016 18:32:09 +0000 (13:32 -0500)]
gtn: use const_index helpers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Rob Clark [Wed, 13 Jan 2016 23:43:14 +0000 (18:43 -0500)]
nir: const_index helpers
Direct access to intr->const_index[n], where different slots have
different meanings, is somewhat confusing.
Instead, let's put some extra info in nir_intrinsic_infos[] about which
slots map to what, and add some get/set helpers. The helpers validate
that the field being accessed (base/writemask/etc) is applicable for the
intrinsic opc, for some extra safety. And nir_print can use this to
dump out decoded const_index fields.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Tue, 9 Feb 2016 10:12:07 +0000 (02:12 -0800)]
glsl: Disallow transform feedback varyings with compute shaders.
If the only stage is MESA_SHADER_COMPUTE, we should complain that
there's nothing coming out of the geometry shader stage just as
we would if the first stage were MESA_SHADER_FRAGMENT.
Also, it's valid for tessellation shaders to be the stage producing
transform feedback varyings, so mention those in the compiler error.
Found by inspection.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Marek Olšák [Fri, 5 Feb 2016 21:49:12 +0000 (22:49 +0100)]
radeonsi: enable denorms for 64-bit and 16-bit floats
This fixes FP16 conversion instructions for VI, which has 16-bit floats,
but not SI & CI, which can't disable denorms for those instructions.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 6 Feb 2016 16:13:07 +0000 (17:13 +0100)]
gallium: pass the robust buffer access context flag to drivers
radeonsi will not do bounds checking for loads if this is not set.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 6 Jan 2016 20:21:07 +0000 (21:21 +0100)]
gallium/radeon: add a function for adding llvm function attributes
This will be used for setting the new InitialPSInputAddr attribute.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 28 Jan 2016 01:26:59 +0000 (02:26 +0100)]
radeonsi: compile geometry shaders immediately
they have only 1 variant
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 28 Jan 2016 00:29:25 +0000 (01:29 +0100)]
radeonsi: split out code for deleting si_shader
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 26 Jan 2016 16:07:29 +0000 (17:07 +0100)]
radeonsi: move code writing tess factors into a separate function
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 26 Jan 2016 22:32:23 +0000 (23:32 +0100)]
radeonsi: make LLVM IR dumping less messy
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 26 Jan 2016 21:39:24 +0000 (22:39 +0100)]
radeonsi: move a few r600_can_dump_shader calls to where they're needed
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 26 Jan 2016 16:27:54 +0000 (17:27 +0100)]
radeonsi: remove useless code that handles dx10_clamp_mode
"enable-no-nans-fp-math" is a wrong string and there was a disagreement
about fixing it.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 26 Jan 2016 21:16:55 +0000 (22:16 +0100)]
radeonsi: dump SPI_PS_INPUT values along with shader stats
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 6 Jan 2016 15:03:38 +0000 (16:03 +0100)]
radeonsi: read SPI_PS_INPUT_ADDR from LLVM if it returns it
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 9 Jan 2016 13:33:38 +0000 (14:33 +0100)]
radeonsi: don't force gl_SampleMaskIn to 1 for smoothing
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 1 Jan 2016 23:41:43 +0000 (00:41 +0100)]
radeonsi: split PS input interpolation code into its own function
This will be used by the fragment shader prolog.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 3 Jan 2016 18:00:29 +0000 (19:00 +0100)]
radeonsi: implement forcing per-sample_interpolation using the shader key only
It was partly a state and partly emulated by shader code, but since we want
to do this in a fragment shader prolog, we need to put it into the shader
key, which will be used to generate the prolog.
This also removes the spi_ps_input states and moves the registers
to the PS state.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 2 Jan 2016 02:18:03 +0000 (03:18 +0100)]
radeonsi: remove si_shader::ps_input_interpolate
tgsi_shader_info has this too.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 2 Jan 2016 01:54:29 +0000 (02:54 +0100)]
radeonsi: move BCOLOR PS input locations after all other inputs
BCOLOR inputs were immediately after COLOR inputs. Thus, all following inputs
were offset by 1 if color_two_side was enabled, and not offset if it was not
enabled, which is a variation that's problematic if we want to have 1 variant
per shader and the variant doesn't care about color_two_side (that should be
handled by other bytecode attached at the beginning).
Instead, move BCOLOR inputs after all other inputs, so BCOLOR0 is at location
"num_inputs" if it's present. BCOLOR1 is next.
This also allows removing si_shader::nparam and
si_shader::ps_input_param_offset, which are useless now.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 2 Jan 2016 01:25:51 +0000 (02:25 +0100)]
radeonsi: move SPI_PS_INPUT_CNTL value computation to a separate function
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 1 Jan 2016 18:44:16 +0000 (19:44 +0100)]
radeonsi: generate a color_two_side variant only if the shader reads colors
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 27 Dec 2015 19:10:33 +0000 (20:10 +0100)]
radeonsi: move si_shader_context initialization into a separate function
This will be re-used later.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 30 Jan 2016 15:43:53 +0000 (16:43 +0100)]
st/mesa: remove st_is_program_native
The default scenario sets GL_TRUE too.
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Marek Olšák [Sat, 30 Jan 2016 15:34:20 +0000 (16:34 +0100)]
st/mesa: unify destroy_program_variants cases for TCS, TES, GS
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Marek Olšák [Sat, 30 Jan 2016 15:24:29 +0000 (16:24 +0100)]
st/mesa: unify get_variant functions for TCS, TES, GS
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Marek Olšák [Sat, 30 Jan 2016 14:10:11 +0000 (15:10 +0100)]
st/mesa: unify variants and delete functions for TCS, TES, GS
no difference between those
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Brian Paul [Tue, 9 Feb 2016 16:58:39 +0000 (09:58 -0700)]
mesa: fix incorrect viewport position when GL_CLIP_ORIGIN = GL_LOWER_LEFT
Ilia Mirkin found/fixed the mistake.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93813
Cc: "11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Brian Paul [Tue, 9 Feb 2016 00:50:23 +0000 (17:50 -0700)]
mesa: rewrite save_CallLists() code
When glCallLists() is compiled into a display list, preserve the call
as a single glCallLists rather than 'n' glCallList calls. This will
matter for an upcoming display list optimization project.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Brian Paul [Mon, 8 Feb 2016 22:30:39 +0000 (15:30 -0700)]
mesa: add missing error check in _mesa_CallLists()
Generate GL_INVALID_VALUE if n < 0. Return early if n==0 or lists==NULL.
v2: fix formatting, also check for lists==NULL.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Brian Paul [Mon, 8 Feb 2016 18:29:07 +0000 (11:29 -0700)]
mesa: whitespace clean-ups in dlist.h
And remove 'extern' qualifiers.
Brian Paul [Mon, 8 Feb 2016 16:59:40 +0000 (09:59 -0700)]
st/mesa: don't allocate bitmap drawing state until needed
Most apps don't use glBitmap so don't allocate the bitmap cache or
gallium state objects/shaders/etc until the first call to st_Bitmap().
v2: simplify a conditional, per Gustaw Smolarczyk.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Brian Paul [Wed, 3 Feb 2016 00:24:34 +0000 (17:24 -0700)]
st/mesa: move the setup_bitmap_vertex_data() code into draw_bitmap_quad()
Now all the code to setup the vertex data and draw it is in one place.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Brian Paul [Wed, 3 Feb 2016 00:12:46 +0000 (17:12 -0700)]
st/mesa: refactor some bitmap drawing code
Move setup/restoration of rendering state into helper functions.
This makes the draw_bitmap_quad() function much more concise.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Ilia Mirkin [Fri, 5 Feb 2016 02:55:13 +0000 (21:55 -0500)]
mesa: remove hack to fix up GL_ANY_SAMPLES_PASSED results
Both st/mesa and i965 should return a true/false result now, and the
only other driver implementing queries (radeon) doesn't support
ARB_occlusion_query2 which added that pname.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Ilia Mirkin [Fri, 5 Feb 2016 02:51:58 +0000 (21:51 -0500)]
st/mesa: make use of the occlusion predicate query
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Ilia Mirkin [Thu, 4 Feb 2016 17:48:29 +0000 (12:48 -0500)]
nv50: add PIPE_QUERY_OCCLUSION_PREDICATE support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Ilia Mirkin [Thu, 4 Feb 2016 17:48:06 +0000 (12:48 -0500)]
nv30: add PIPE_QUERY_OCCLUSION_PREDICATE support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Thu, 4 Feb 2016 17:47:42 +0000 (12:47 -0500)]
ilo: add PIPE_QUERY_OCCLUSION_PREDICATE support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Nicolai Hähnle [Thu, 21 Jan 2016 21:10:11 +0000 (16:10 -0500)]
draw: use util_pstipple_* function for stipple pattern textures and samplers
This reduces code duplication.
Suggested-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Nicolai Hähnle [Thu, 21 Jan 2016 21:03:17 +0000 (16:03 -0500)]
draw: use util_pstipple_create_fragment_shader
This reduces code duplication. It also adds support for drivers where the
fragment position is a system value.
Suggested-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Marek Olšák [Sun, 7 Feb 2016 19:25:01 +0000 (20:25 +0100)]
winsys/radeon: fix a wrong NUM_TILE_PIPES value from the kernel
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94019
Tested-by: Nick Sarnie <commendsarnex@gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Timothy Arceri [Tue, 2 Feb 2016 00:53:57 +0000 (11:53 +1100)]
nir: remove unused nir_variable fields
These are used in GLSL IR to removed unused varyings and match
transform feedback variables. There is no need to use these in NIR.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Fri, 29 Jan 2016 23:50:12 +0000 (10:50 +1100)]
glsl: remove unrequired forward declaration
This was added in
2548092ad80156a4 although I don't see why as it
was already in the linker.h header.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Fri, 22 Jan 2016 22:08:23 +0000 (09:08 +1100)]
glsl: clean up and fix bug in varying linking rules
The existing code was very hard to follow and has been the source
of at least 3 bugs in the past year.
The existing code also has a bug for SSO where if we have a
multi-stage SSO for example a tes -> gs program, if we try to use
transform feedback with gs the existing code would look for the
transform feedback varyings in the tes stage and fail as it can't
find them.
V2: Add more code comments, always try to remove unused inputs
to the first stage.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Wed, 27 Jan 2016 05:16:01 +0000 (16:16 +1100)]
glsl: simplify ES Vertex/Fragment shader requirements
We really just needed to skip the existing ES < 3.1 check if we have
a compute shader, all other scenarios are already covered.
* No shaders is a link error.
* Geom or Tess without Vertex is a link error which means we always
require a Vertex shader and hence a Fragment shader.
* Finally a Compute shader linked with any other stage is a link error.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Wed, 27 Jan 2016 04:42:58 +0000 (15:42 +1100)]
glsl: simplify required stages for linking rules
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Wed, 27 Jan 2016 04:34:53 +0000 (15:34 +1100)]
glsl: small tidy up now that link_shaders() exits early with 0 shaders
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Mon, 25 Jan 2016 10:56:18 +0000 (21:56 +1100)]
glsl: don't attempt to link empty program
Previously an empty program would go through the entire
link_shaders() function and we would have to be careful
not to cause a segfault.
In core profile also now set link_status to false by
generating an error, it was previously set to true.
From Section 7.3 (PROGRAM OBJECTS) of the OpenGL 4.5 spec:
"Linking can fail for a variety of reasons as specified in the
OpenGL Shading Language Specification, as well as any of the
following reasons:
- No shader objects are attached to program."
V2: Only generate an error in core profile and add spec quote (Ian)
V3: generate error in ES too, remove previous check which was only
applying the rule to GL 4.5/ES 3.1 and above. My understand is that
this spec change is clarifying previously undefined behaviour and
therefore should be applied retrospectively. The ES CTS tests for
this are in ES 2 I suspect it was passing because it would have
generated an error for not having both a vertex and fragment shader.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Tue, 2 Feb 2016 00:44:18 +0000 (16:44 -0800)]
nir: Recognize open-coded bitfield_reverse.
Helps 11 shaders in UnrealEngine4 demos.
I seriously hope they would have given us bitfieldReverse() if we
exposed GL 4.0 (but we do expose ARB_gpu_shader5, so why not use that
anyway?).
instructions in affected programs: 4875 -> 4633 (-4.96%)
cycles in affected programs: 270516 -> 244516 (-9.61%)
I suspect there's a *lot* of room to improve nir_search/opt_algebraic's
handling of this. We'd actually like to match, e.g., step2 by matching
step1 once and then doing a pointer comparison for the second instance
of step1, but unfortunately we generate an enormous tuple for instead.
The .text size increases by 6.5% and the .data by 17.5%.
text data bss dec hex filename
22957 45224 0 68181 10a55 nir_libnir_la-nir_opt_algebraic.o
24461 53160 0 77621 12f35 nir_libnir_la-nir_opt_algebraic.o
I'd be happy to remove this if Unreal4 uses bitfieldReverse() if it is
in a GL 4.0 context once we expose GL 4.0.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Matt Turner [Tue, 2 Feb 2016 00:35:41 +0000 (16:35 -0800)]
nir: Handle large unsigned values in opt_algebraic.
The next patch adds an algebraic rule that uses the constant 0xff00ff00.
Without this change, the build fails with
return hex(struct.unpack('I', struct.pack('i', self.value))[0])
struct.error: 'i' format requires -
2147483648 <= number <=
2147483647
The hex() function handles integers of any size, and assigning a
negative value to an unsigned does what we want in C. The pack/unpack is
unnecessary (and as we see, buggy).
Reviewed-by: Dylan Baker <baker.dylan.c@gmail.com>
Matt Turner [Thu, 4 Feb 2016 20:04:42 +0000 (12:04 -0800)]
nir: Do opt_algebraic in reverse order.
Walking the SSA definitions in order means that we consider the smallest
algebraic optimizations before larger optimizations. So if a smaller
rule is part of a larger rule, the smaller one will happen first,
preventing the larger one from happening.
instructions in affected programs: 32721 -> 32611 (-0.34%)
helped: 106
In programs whose nir_optimize loop count changes (129 of them):
before: 1164 optimization loops
after: 1071 optimization loops
Of the 129 affected, 16 programs' optimization loop counts increased.
Prevents regressions and annoyances in the next commits.
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Matt Turner [Thu, 4 Feb 2016 20:00:15 +0000 (12:00 -0800)]
nir: Recognize product of open-coded pow()s.
Prevents regressions in the next commit.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Matt Turner [Tue, 2 Feb 2016 00:34:46 +0000 (16:34 -0800)]
nir: Add opt_algebraic rules for xor with zero.
instructions in affected programs: 668 -> 664 (-0.60%)
helped: 4
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Timothy Arceri [Fri, 5 Feb 2016 02:08:19 +0000 (13:08 +1100)]
glsl: validate arrays of arrays on empty type delclarations
Fixes:
dEQP-GLES31.functional.shaders.arrays_of_arrays.invalid.empty_declaration_without_var_name_fragment
dEQP-GLES31.functional.shaders.arrays_of_arrays.invalid.empty_declaration_without_var_name_vertex
Reviewed-by: Dave Airlie <airlied@redhat.com>
Kenneth Graunke [Fri, 22 Jan 2016 00:37:20 +0000 (16:37 -0800)]
i965: Use nir_lower_load_const_to_scalar().
I don't know why, but we never hooked up this pass Eric wrote.
Otherwise, you can end up with stupid scalarized code such as:
vec4 ssa_7 = load_const (0.0, 0.0, 0.0, 0.0)
vec4 ssa_8 = ...
vec1 ssa_9 = feq ssa_8, ssa_7
vec1 ssa_10 = feq ssa_8.y, ssa_7.y
vec1 ssa_11 = feq ssa_8, ssa_7.z
vec1 ssa_12 = feq ssa_8.y, ssa_7.w
ssa_8.xyxy == <0, 0, 0, 0> should only take two feq instructions.
shader-db on Skylake:
total instructions in shared programs: 9121153 -> 9120749 (-0.00%)
instructions in affected programs: 32421 -> 32017 (-1.25%)
helped: 277
HURT: 69
total cycles in shared programs:
69003364 ->
69000912 (-0.00%)
cycles in affected programs: 899186 -> 896734 (-0.27%)
helped: 313
HURT: 403
This also prevents regressions when disabling channel expressions.
v2: Don't call opt_cse afterwards (requested by Matt). It should
happen in the optimization loop below anyway.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Timothy Arceri [Fri, 5 Feb 2016 22:38:55 +0000 (09:38 +1100)]
mesa: remove now unused sampler index handing code
Reviewed-by: Dave Airlie <airlied@redhat.com>
Timothy Arceri [Fri, 5 Feb 2016 22:30:00 +0000 (09:30 +1100)]
mesa: compute sampler index in ir_to_mesa rather than using UniformHash
The aim of this is to work towards removing UniformHash from the program
struct so that we don't need to hold onto it in memory and pass it around
outside the linker.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Kenneth Graunke [Thu, 4 Feb 2016 16:10:02 +0000 (08:10 -0800)]
i965: Don't add barrier deps for FB write messages.
There are never render target reads, so there are no scheduling hazards.
Giving the extra flexibility to the scheduler makes it possible to do
FB writes as soon as their sources are available, reducing register
pressure. It also makes it possible to do the payload setup for more
than one FB write message at a time, which could better hide latency.
shader-db results on Skylake:
total instructions in shared programs: 9110254 -> 9110211 (-0.00%)
instructions in affected programs: 2898 -> 2855 (-1.48%)
helped: 3
HURT: 0
LOST: 0
GAINED: 1
A reduction in instruction counts is surprising, but legitimate:
the three shaders helped were spilling, and reducing register
pressure allowed us to issue fewer spills/fills.
total cycles in shared programs:
69035108 ->
68928820 (-0.15%)
cycles in affected programs: 4412402 -> 4306114 (-2.41%)
helped: 4457
HURT: 213
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Dave Airlie [Thu, 4 Feb 2016 07:38:54 +0000 (17:38 +1000)]
st/mesa: enable AoA for gallium drivers reporting GLSL 1.30
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 5 Feb 2016 02:00:38 +0000 (12:00 +1000)]
st/mesa: add atomic AoA support
reuse the sampler deref handling code to do the same
thing for atomics.
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 5 Feb 2016 03:34:29 +0000 (13:34 +1000)]
mesa: drop unused nonconst sampler functions.
Since we fixed the glsl->tgsi conversion we no longer need
this function.
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 4 Feb 2016 06:48:18 +0000 (16:48 +1000)]
st/mesa: handle indirect samplers in arrays/structs properly (v4.1)
The state tracker never handled this properly, and it finally
annoyed me for the second time so I decided to fix it properly.
This is inspired by the NIR sampler lowering code and I only realised
NIR seems to do its deref ordering different to GLSL at the last
minute, once I got that things got much easier.
it fixes a bunch of tests in
tests/spec/arb_gpu_shader5/execution/sampler_array_indexing/
v2: fix AoA tests when forced on.
I was right I didn't need all that code, fixing the AoA code
meant cleaning up a chunk of code I didn't like in the array
handling.
v3: start generalising the code a bit more for atomics.
v3.1: use UniformRemapTable
v4: handle uniforms differently using the param_index,
and go back to UniformStorage
fix issues identified by Timothy with deref handling.
v4.1: squash const fix and move handling 1D const out
of recursive function.
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 8 Feb 2016 01:09:29 +0000 (11:09 +1000)]
glsl/ir: add param index to variable.
We have a requirement to store the index into the mesa parameterlist
for uniforms. Up until now we've overwritten var->data.location with
this info. However this then stops us accessing UniformStorage,
which is needed to do proper dereferencing.
Add a new variable to ir_variable to store this value in, and change
the two uses to use it correctly.
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Francisco Jerez [Thu, 14 Jan 2016 20:20:46 +0000 (12:20 -0800)]
i965: Rename define for the PIPE_CONTROL DC flush bit.
Its previous name was somewhat misleading, this really behaves like a
RW cache flush rather than an invalidation.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Thu, 14 Jan 2016 20:17:01 +0000 (12:17 -0800)]
i965: Invalidate state cache before L3 partitioning set-up.
The state cache is also L3-backed so it seems sensible to make sure
it's clean as we do for other RO caches before repartitioning the L3.
This wasn't part of my original L3 partitioning code because I was
able to reproduce hangs on Gen7 hardware when the state cache
invalidation happened asynchronously with previous 3D rendering, which
should no longer be possible after the previous change.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Thu, 14 Jan 2016 19:22:46 +0000 (11:22 -0800)]
i965: Fix cache pollution race during L3 partitioning set-up.
We need to split the stalling flush from the RO cache invalidation
into a different PIPE_CONTROL command to make sure that the top of the
pipe invalidation happens after any previous rendering is complete.
Otherwise it's possible for previous rendering to pollute the L3 cache
in the short window of time between RO invalidation and the completion
of the stalling flush. Fixes rendering artifacts on Unigine Heaven,
Metro Last Light Redux and Metro 2033 Redux.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93540
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93599
Tested-by: Darius Spitznagel <d.spitznagel@goodbytez.de>
Tested-by: Martin Peres <martin.peres@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Sun, 7 Feb 2016 02:43:45 +0000 (18:43 -0800)]
i965/fs: Don't emit unnecessary SEL instruction from emit_image_atomic().
The SEL instruction with predication mode NONE emitted when the atomic
operation doesn't need to be predicated is a no-op and might rely on
undocumented hardware behaviour. Noticed by chance while looking at
the assembly output.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Matt Turner [Mon, 8 Feb 2016 23:32:12 +0000 (15:32 -0800)]
i965/vec4: Update vec4 unit tests for commit
01dacc83ff.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94050
Brian Paul [Mon, 8 Feb 2016 17:52:02 +0000 (10:52 -0700)]
dri/common: include debug_output.h to silence warning
Brian Paul [Mon, 8 Feb 2016 16:29:38 +0000 (09:29 -0700)]
tgsi: minor whitespace fixes in tgsi_scan.c
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>