Kristian H. Kristensen [Wed, 13 Feb 2019 20:02:39 +0000 (12:02 -0800)]
.mailmap: Add a few more alises for myself
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Samuel Pitoiset [Wed, 13 Feb 2019 17:51:23 +0000 (18:51 +0100)]
radv/winsys: fix BO list creation when RADV_DEBUG=allbos is set
Fixes:
50fd253bd6e ("radv/winsys: Add priority handling during submit.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Kristian H. Kristensen [Tue, 12 Feb 2019 18:17:55 +0000 (10:17 -0800)]
freedreno/a6xx: Fix point coord
Use ir3_next_varying() for iterating through varyings and unset the
global point coord invert bit.
Fixes:
dEQP-GLES3.functional.shaders.builtin_variable.pointcoord
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Kristian H. Kristensen [Tue, 12 Feb 2019 05:51:09 +0000 (21:51 -0800)]
freedreno/a6xx: Front facing needs UNK3 bit
We need to set UNK3 in GRAS_CNTL and RB_RENDER_CONTROL0 for the value
to be reliably delivered.
Fixes:
dEQP-GLES3.functional.shaders.builtin_variable.frontfacing
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Kristian H. Kristensen [Tue, 12 Feb 2019 05:50:21 +0000 (21:50 -0800)]
freedreno/a6xx: Update headers
This pulls in changes for compute shaders and a6xx ssbo/image support.
FACENESS bit moved from position 1 to 2 and there's a global invert
bit for point coord.
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Kristian H. Kristensen [Mon, 11 Feb 2019 23:09:21 +0000 (15:09 -0800)]
freedreno/a6xx: Clean up mixed use of swap and swizzle for texture state
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Rob Clark [Wed, 13 Feb 2019 18:54:05 +0000 (13:54 -0500)]
freedreno/a6xx: small compiler warning fix
Signed-off-by: Rob Clark <robdclark@gmail.com>
Dylan Baker [Tue, 12 Feb 2019 22:03:21 +0000 (14:03 -0800)]
get-pick-list: Add --pretty=medium to the arguments for Cc patches
Because none of them have been picked up for 19.0 due to this bug
being reintroduced.
v2: - Fix fixes tags
Fixes:
e6b3a3b2014413366110f6deeced8095e7262b1d
("bin/get-pick-list.sh: handle "typod" usecase.")
Fixes:
fac10169bbad2da918ef07a62c01e0b321508cfe
("bin/get-pick-list.sh: prefix output with "[stable] "")
Reviewed-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Eric Engestrom [Wed, 13 Feb 2019 14:25:45 +0000 (14:25 +0000)]
gitlab-ci: limit ninja to 4 threads max
I tried bumping the limit on make and scons instead, but that just
thrashed the runners, so let's not do that (sorry @daniels :]).
Instead, remove the automatic thread management from ninja and limit it
to 4 instead, in line with make and scons.
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Konstantin Kharlamov [Sun, 3 Feb 2019 18:36:32 +0000 (21:36 +0300)]
mapi: work around GCC LTO dropping assembly-defined functions
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109391
Signed-off-by: Konstantin Kharlamov <Hi-Angel@yandex.ru>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Caio Marcelo de Oliveira Filho [Mon, 11 Feb 2019 19:55:19 +0000 (11:55 -0800)]
nir: fix example in opt_peel_loop_initial_if description
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Karol Herbst [Tue, 12 Feb 2019 19:59:35 +0000 (20:59 +0100)]
nir/opt_if: don't mark progress if nothing changes
if we have something like this:
loop {
...
if x {
break;
} else {
continue;
}
}
opt_if_loop_last_continue returns true marking progress allthough nothing
changes.
Fixes:
5921a19d4b0c6 "nir: add if opt opt_if_loop_last_continue()"
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Oscar Blumberg [Tue, 12 Feb 2019 20:52:51 +0000 (21:52 +0100)]
radeonsi: Fix guardband computation for large render targets
Stop using 12.12 quantization for viewports that are not contained in
the lower 4k corner of the render target as the hardware needs to keep
both absolute and relative coordinates representable.
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Chia-I Wu [Thu, 7 Feb 2019 23:11:57 +0000 (15:11 -0800)]
egl: fix KHR_partial_update without EXT_buffer_age
EGL_BUFFER_AGE_EXT can be queried without EXT_buffer_age.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Kenneth Graunke [Fri, 8 Feb 2019 05:58:57 +0000 (21:58 -0800)]
mesa: Advertise EXT_float_blend in ES 3.0+ contexts.
This extension simply drops a draw time restriction:
"Furthermore, an INVALID_OPERATION error is generated by
DrawArrays and the other drawing commands defined in section
2.8.3 (10.5 in ES 3.1) if blending is enabled (see below) and
any draw buffer has 32-bit floating-point format components."
We never correctly enforced this restriction anyway, so we were
basically already implementing it. We just need to advertise it
for our behavior to be correct.
The extension requires EXT_color_buffer_float, but we already enable
that via dummy_true. So we can dummy_true this one as well.
Found while debugging WebGL conformance tests. Does not fix any.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Alok Hota [Wed, 30 Jan 2019 16:43:40 +0000 (10:43 -0600)]
gallium/swr: Param defaults for unhandled PIPE_CAPs
Without using this function, we fail the -Wswitch flag when compiling
the default debugoptimized mode in Meson
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Juan A. Suarez Romero [Tue, 12 Feb 2019 18:19:13 +0000 (19:19 +0100)]
anv/cmd_buffer: check for NULL framebuffer
This can happen when we record a VkCmdDraw in a secondary buffer that
was created inheriting from the primary buffer, but with the framebuffer
set to NULL in the VkCommandBufferInheritanceInfo.
Vulkan 1.1.81 spec says that "the application must ensure (using scissor
if neccesary) that all rendering is contained in the render area [...]
[which] must be contained within the framebuffer dimesions".
While this should be done by the application, commit
465e5a86 added the
clamp to the framebuffer size, in case of application does not do it.
But this requires to know the framebuffer dimensions.
If we do not have a framebuffer at that moment, the best compromise we
can do is to just apply the scissor as it is, and let the application to
ensure the rendering is contained in the render area.
v2: do not clamp to framebuffer if there isn't a framebuffer
v3 (Jason):
- clamp earlier in the conditional
- clamp to render area if command buffer is primary
v4: clamp also x and y to render area (Jason)
v5: rename used variables (Jason)
Fixes:
465e5a86 ("anv: Clamp scissors to the framebuffer boundary")
CC: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Marek Olšák [Sat, 9 Feb 2019 01:20:41 +0000 (20:20 -0500)]
radeonsi: use MEM instead of MEM_GRBM in COPY_DATA.DST_SEL
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 7 Feb 2019 05:02:33 +0000 (00:02 -0500)]
radeonsi: add AMD_DEBUG env var as an alternative to R600_DEBUG
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Samuel Pitoiset [Tue, 12 Feb 2019 08:01:50 +0000 (09:01 +0100)]
radv: fix using LOAD_CONTEXT_REG with old GFX ME firmwares on GFX8
This fixes a critical issue.
Cc: <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109575
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 5 Feb 2019 19:22:01 +0000 (20:22 +0100)]
radv: add support for push constants inlining when possible
This removes some scalar loads from shaders, but it increases
the number of SET_SH_REG packets. This is currently basic but
it could be improved if needed. Inlining dynamic offsets might
also help.
Original idea from Dave Airlie.
29077 shaders in 15096 tests
Totals:
SGPRS: 1321325 -> 1357101 (2.71 %)
VGPRS: 936000 -> 932576 (-0.37 %)
Spilled SGPRs: 24804 -> 24791 (-0.05 %)
Code Size:
49827960 ->
49642232 (-0.37 %) bytes
Max Waves: 242007 -> 242700 (0.29 %)
Totals from affected shaders:
SGPRS: 290989 -> 326765 (12.29 %)
VGPRS: 244680 -> 241256 (-1.40 %)
Spilled SGPRs: 1442 -> 1429 (-0.90 %)
Code Size: 8126688 -> 7940960 (-2.29 %) bytes
Max Waves: 80952 -> 81645 (0.86 %)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 5 Feb 2019 19:22:00 +0000 (20:22 +0100)]
radv: keep track of the number of remaining user SGPRs
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 5 Feb 2019 19:21:59 +0000 (20:21 +0100)]
radv: gather if shaders load dynamic offsets separately
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 5 Feb 2019 19:21:58 +0000 (20:21 +0100)]
radv: gather more info about push constants
This is needed in order to inline some push constants when possible.
This also adds a new helper for initializing the pass.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Mon, 11 Feb 2019 09:17:52 +0000 (10:17 +0100)]
radv: fix compiler issues with GCC 9
"The C standard says that compound literals which occur inside of
the body of a function have automatic storage duration associated
with the enclosing block. Older GCC releases were putting such
compound literals into the scope of the whole function, so their
lifetime actually ended at the end of containing function. This
has been fixed in GCC 9. Code that relied on this extended lifetime
needs to be fixed, move the compound literals to whatever scope
they need to accessible in."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109543
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Gustaw Smolarczyk <wielkiegie@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tapani Pälli [Mon, 11 Feb 2019 08:12:45 +0000 (10:12 +0200)]
i965: add P0x formats and propagate required scaling factors
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Lin Johnson <johnson.lin@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tapani Pälli [Mon, 11 Feb 2019 08:06:09 +0000 (10:06 +0200)]
intel/compiler: add scale_factors to sampler_prog_key_data
Patch propagates given scale_factors to lowering options.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tapani Pälli [Mon, 11 Feb 2019 08:01:35 +0000 (10:01 +0200)]
dri: add P010, P012, P016 for 10bit/12bit/16bit YUV420 formats
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Lin Johnson <johnson.lin@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tapani Pälli [Mon, 11 Feb 2019 07:25:18 +0000 (09:25 +0200)]
nir: add option to use scaling factor when sampling planes YUV lowering
Patch adds nir_lower_tex_options as parameter to sample_plane so that
we don't need to extend nir_tex_instr for this.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Mon, 11 Feb 2019 03:53:40 +0000 (19:53 -0800)]
i965: Use info->textures_used instead of prog->SamplersUsed.
prog->SamplersUsed is set by the linker when validating resource limits,
while info->textures_used is gathered after NIR optimizations, which may
have eliminated some unused surfaces.
This may let us skip some work.
Reviewed-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Mon, 11 Feb 2019 03:50:37 +0000 (19:50 -0800)]
i965: Drop unnecessary 'and' with prog->SamplerUnits
textures_used_by_txf is a subset of textures_used which is a subset
of prog->SamplerUnits. This should do nothing.
Reviewed-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Sun, 13 Jan 2019 18:39:41 +0000 (10:39 -0800)]
nir: Gather texture bitmasks in gl_nir_lower_samplers_as_deref.
Eric and I would like a bitmask of which samplers are used, similar to
prog->SamplersUsed, but available in NIR. The linker uses SamplersUsed
for resource limit checking, but later optimizations may eliminate more
samplers. So instead of propagating it through, we gather a new one.
While there, we also gather the existing textures_used_by_txf bitmask.
Gathering these bitfields in nir_shader_gather_info is awkward at best.
The main reason is that it introduces an ordering dependency between the
two passes. If gathering runs before lower_samplers_as_deref, it can't
look at var->data.binding. If the driver doesn't use the full lowering
to texture_index/texture_array_size (like radeonsi), then the gathering
can't use those fields. Gathering might be run early /and/ late, first
to get varying info, and later to update it after variant lowering. At
this point, should gathering work on pre-lowered or post-lowered code?
Pre-lowered is also harder due to the presence of structure types.
Just doing the gathering when we do the lowering alleviates these
ordering problems. This fixes ordering issues in i965 and makes the
txf info gathering work for radeonsi (though they don't use it).
Reviewed-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Wed, 6 Feb 2019 07:24:51 +0000 (23:24 -0800)]
nir: Use sampler derefs in drawpixels and bitmap lowering.
Reviewed-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Wed, 6 Feb 2019 03:02:44 +0000 (19:02 -0800)]
program: Make prog_to_nir create texture/sampler derefs.
Until now, prog_to_nir has been setting texture_index and sampler_index
directly. This is different than GLSL shaders, which create variable
dereferences and rely on lowering passes to reach this final form.
radeonsi uses variable dereferences for samplers rather than
texture_index and sampler_index, so it doesn't even make sense to set
them there. By moving to derefs, we ensure that both GLSL and ARB
programs produce the same final form that the driver desires.
Reviewed-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Wed, 6 Feb 2019 03:24:16 +0000 (19:24 -0800)]
st/nir: Use sampler derefs in built-in shaders.
Reviewed-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Wed, 6 Feb 2019 08:06:33 +0000 (00:06 -0800)]
st/nir: Lower sampler derefs for builtin shaders.
Reviewed-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Wed, 6 Feb 2019 08:03:49 +0000 (00:03 -0800)]
st/nir: Pull sampler lowering into a helper function.
This will make it easier to reuse across GLSL / ARB / built-ins.
Reviewed-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Wed, 6 Feb 2019 03:15:46 +0000 (19:15 -0800)]
i965: Call nir_lower_samplers for ARB programs.
An upcoming patch will start building derefs in prog_to_nir, at which
point we'll need to lower them to indexes.
This gets both GLSL and non-GLSL shaders using the same paths.
Reviewed-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Wed, 6 Feb 2019 10:05:01 +0000 (02:05 -0800)]
glsl: Don't look at sampler uniform storage for internal vars
Passes like nir_lower_drawpixels add additional sampler variables,
and set an explicit binding which never changes. These extra samplers
don't have proper uniform storage associated with them, and there is no
way to update bindings via the API. So, for any 'hidden' variables,
just trust that there's an explicit binding set.
Reviewed-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Wed, 6 Feb 2019 03:08:04 +0000 (19:08 -0800)]
glsl: Allow gl_nir_lower_samplers*() without a gl_shader_program
I would like to be able to run gl_nir_lower_samplers() to turn texture
and sampler variable dereferences into indexes and offsets, even for
ARB programs, and built-in shaders. This would make sampler handling
more consistent across the various types of shaders.
For GLSL programs, the gl_nir_lower_samplers_as_deref() pass looks up
the variable bindings in the shader program's uniform storage. But
ARB programs and built-in shaders don't have a gl_shader_program, and
uniform storage doesn't exist. In this case, we simply skip that
lookup, and trust var->data.binding to be set correctly by whoever
created the shader.
Reviewed-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Mon, 11 Feb 2019 06:49:20 +0000 (22:49 -0800)]
st/mesa: Limit GL_MAX_[NATIVE_]PROGRAM_PARAMETERS_ARB to 2048
Piglit's vp-max-array test creates a vertex program containing a uniform
array sized to the value of GL_MAX_NATIVE_PROGRAM_PARAMETERS_ARB. Mesa
will then add additional state-var parameters for things like the MVP
matrix.
radeonsi currently exposes a value of 4096, derived from constant buffer
upload size. This means the array will have 4096 elements, and the
extra MVP state-vars would get a prog_src_register::Index of over 4096.
Unfortunately, prog_src_register::Index is a signed 13-bit integer, so
values beyond 4096 end up turning into negative numbers. Negative
source indexes are only valid for relative addressing, so this ends up
generating illegal IR.
In prog_to_nir, this would cause an out of bounds array access.
st_mesa_to_tgsi checks for a negative value, assumes it's bogus,
and remaps it to parameter 0 in order to get something in-range.
This isn't right - instead of reading the MVP matrix, it would read
the first element of the vertex program's large array. But the test
only checks that the program compiles, so we never noticed that it
was broken.
This patch limits the size of the program limits, with the understanding
that we may need to generate additional state-vars internally. i965 has
exposed 1024 for this limit for years, so I don't expect lowering it to
2048 will cause any practical problems for radeonsi or other drivers.
Fixes vp-max-array with prog_to_nir.c.
Cc: "19.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Francisco Jerez [Fri, 18 Jan 2019 20:51:57 +0000 (12:51 -0800)]
intel/dump_gpu: Disambiguate between BOs from different GEM handle spaces.
This fixes a rather astonishing problem that came up while debugging
an issue in the Vulkan CTS. Apparently the Vulkan CTS framework has
the tendency to create multiple VkDevices, each one with a separate
DRM device FD and therefore a disjoint GEM buffer object handle space.
Because the intel_dump_gpu tool wasn't making any distinction between
buffers from the different handle spaces, it was confusing the
instruction state pools from both devices, which happened to have the
exact same GEM handle and PPGTT virtual address, but completely
different shader contents. This was causing the simulator to believe
that the vertex pipeline was executing a fragment shader, which didn't
end up well.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Kristian H. Kristensen [Fri, 8 Feb 2019 23:07:22 +0000 (15:07 -0800)]
freedreno/a6xx: Fall back to masked RGBA blits for depth/stencil
The blitter doesn't seem to have a write mask, so for depth only and
stencil only blits to Z24S8 we cast the Z24S8 buffer to an RGBA UNORM8
buffer and fall back to pipeline blits with corresponding write mask.
Fixes
dEQP-GLES3.functional.fbo.blit.depth_stencil.depth24_stencil8_stencil_only
dEQP-GLES3.functional.fbo.invalidate.sub.unbind_blit_depth
dEQP-GLES3.functional.fbo.invalidate.sub.unbind_blit_msaa_depth
dEQP-GLES3.functional.fbo.invalidate.whole.unbind_blit_depth
dEQP-GLES3.functional.fbo.invalidate.whole.unbind_blit_msaa_depth
dEQP-GLES3.functional.fbo.msaa.2_samples.stencil_index8
dEQP-GLES3.functional.fbo.msaa.4_samples.stencil_index8
Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Kristian H. Kristensen [Sat, 9 Feb 2019 00:27:25 +0000 (16:27 -0800)]
freedreno/a6xx: Add format argument to fd6_tex_swiz()
We need to allow overriding the format with that of the image or
sampler view, so we can't take it from the resource in fd6_tex_swiz().
Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Kristian H. Kristensen [Thu, 7 Feb 2019 23:35:07 +0000 (15:35 -0800)]
freedreno/a6xx: Support y-inverted blits
The src coordinates are s24.8. For an inverted blit that ends at y=0
we need to program -1 for sy2, so we need to handle negative values
correctly.
Fixes
dEQP-GLES3.functional.fbo.blit.rect.nearest_consistency_mag_reverse_dst_y
dEQP-GLES3.functional.fbo.blit.rect.nearest_consistency_min_reverse_dst_y
dEQP-GLES3.functional.fbo.blit.rect.nearest_consistency_min_reverse_src_y
dEQP-GLES3.functional.fbo.invalidate.sub.unbind_blit_color
dEQP-GLES3.functional.fbo.invalidate.whole.unbind_blit_color
Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Kristian H. Kristensen [Sat, 2 Feb 2019 01:15:45 +0000 (17:15 -0800)]
freedreno/a6xx: Support some depth/stencil blits on blitter
We can rewrite almost all depth stencil blits to various red-only
blits. The exception is depth-only or stencil-only blits into z24s8
combined depth stencil buffer. We can fall back for depth-only, but
stencil-only remains broken.
Fixes
dEQP-GLES3.functional.fbo.blit.depth_stencil.depth24_stencil8_basic
dEQP-GLES3.functional.fbo.blit.depth_stencil.depth24_stencil8_scale
dEQP-GLES3.functional.fbo.blit.depth_stencil.depth32f_stencil8_basic
dEQP-GLES3.functional.fbo.blit.depth_stencil.depth32f_stencil8_scale
dEQP-GLES3.functional.fbo.blit.depth_stencil.depth32f_stencil8_stencil_only
Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Kristian H. Kristensen [Fri, 1 Feb 2019 23:28:00 +0000 (15:28 -0800)]
freedreno/a6xx: Move blit check so as to restore comment
The explanation for the compressed format check is broken across two
comments:
/* We can blit if both or neither formats are compressed formats... */
/* ... but only if they're the same compression format. */
but the ok_format() checks were inserted between, breaking up the flow
of the sentence.
Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Kristian H. Kristensen [Fri, 1 Feb 2019 23:20:05 +0000 (15:20 -0800)]
freedreno: Don't tell the blitter what it can't do
Call ctx->blit() and let it reject blits it can't do instead of giving
up on stencil blits and blits u_blitter can't do.
Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Kristian H. Kristensen [Fri, 1 Feb 2019 22:44:17 +0000 (14:44 -0800)]
freedreno: Consolidate u_blitter functions in freedreno_blitter.c
Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Kristian H. Kristensen [Fri, 1 Feb 2019 22:01:15 +0000 (14:01 -0800)]
freedreno/a6xx: Combine emit_blit and fd6_blit
Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Kristian H. Kristensen [Thu, 31 Jan 2019 23:00:34 +0000 (15:00 -0800)]
freedreno/a6xx: Use the right resource for separate stencil stride
Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Kristian H. Kristensen [Thu, 24 Jan 2019 19:38:51 +0000 (11:38 -0800)]
freedreno: Log number of draw for sysmem passes
Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Kristian H. Kristensen [Thu, 7 Feb 2019 19:40:29 +0000 (11:40 -0800)]
freedreno/a6xx: Drop render condition check in blitter
We already check earlier in the call chain in fd_blit().
glBlitFramebuffer always sets render_condition_enable and thus we
would never try the blitter path for that.
Now that we get all of dEQP-GLES3.functional.fbo.blit.conversion.*
down this path, it turs out that the
fail_if(info->mask != util_format_get_mask(info->src.format));
fail_if(info->mask != util_format_get_mask(info->dst.format));
conditions weren't accurate. util_format_get_mask() returns
PIPE_MASK_RGBA for any format with any color channels, while
info->mask is the exact set of channels to blit. So we reject things
we could blit - for example, PIPE_FORMAT_R16G16_FLOAT where info->mask
is RG while util_format_get_mask() returns RGBA - and accept things we
can't. It turns out that the blitter is happy to blit different
number of channels, but fails to blit formats with different numerical
formats and srgb formats.
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Kristian H. Kristensen [Mon, 11 Feb 2019 18:31:18 +0000 (10:31 -0800)]
freedreno/a6xx: regen headers
Update for a6xx.xml.h to incorporate a few new bits and changes to
blit src rect coordinate types.
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Leo Liu [Fri, 8 Feb 2019 14:48:23 +0000 (09:48 -0500)]
st/va/vp9: set max reference as default of VP9 reference number
If there is no information about number of render targets
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
Leo Liu [Fri, 8 Feb 2019 13:56:53 +0000 (08:56 -0500)]
st/va: fix the incorrect max profiles report
Add "PIPE_VIDEO_PROFILE_MAX" to enum, so it will make sure here will
be correct when adding more profiles in the future.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109107
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
Guttula, Suresh [Mon, 11 Feb 2019 11:12:52 +0000 (06:12 -0500)]
st/va:Add support for indirect manner by returning VA_STATUS_ERROR_OPERATION_FAILED
Based on VA Spec,DeriveImage() returns VA_STATUS_ERROR_OPERATION_FAILED if driver
dont have support for internal surface formats.Currently vaDeriveImage()
failed for non-contiguous planes and operation failed error string is
required to support indirect manner i.e. vaCreateImage()+vaPutImage()
incase vaDeriveImage() failed with VA_STATUS_ERROR_OPERATION_FAILED.
This patch will notify to the client as operation failed with proper
error sting,so that client will fallback to vaCreateImage()+vaPutImage().
v2: updated commit message based on VA spec.
Signed-off-by: suresh guttula <suresh.guttula@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Marek Olšák [Mon, 4 Feb 2019 21:30:32 +0000 (16:30 -0500)]
winsys/amdgpu: cs_check_space sets the minimum IB size for future IBs
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 4 Feb 2019 21:23:39 +0000 (16:23 -0500)]
winsys/amdgpu: clean up IB buffer size computation
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 4 Feb 2019 21:15:12 +0000 (16:15 -0500)]
winsys/amdgpu: remove occurence of INDIRECT_BUFFER_CONST
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 4 Feb 2019 20:27:27 +0000 (15:27 -0500)]
winsys/amdgpu: use a separate fence list for syncobjs
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 4 Feb 2019 19:55:03 +0000 (14:55 -0500)]
winsys/amdgpu: unify fence list code
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 4 Feb 2019 20:12:17 +0000 (15:12 -0500)]
winsys/amdgpu: don't drop manually added fence dependencies
wow, it's hard to believe that fence and syncobjs dependencies were ignored.
Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 1 Feb 2019 22:10:46 +0000 (17:10 -0500)]
radeonsi: fix EXPLICIT_FLUSH for flush offsets > 0
Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 1 Feb 2019 22:10:46 +0000 (17:10 -0500)]
gallium/u_threaded: fix EXPLICIT_FLUSH for flush offsets > 0
Cc: 18.3 19.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Jason Ekstrand [Mon, 11 Feb 2019 04:23:01 +0000 (22:23 -0600)]
nir/deref: Rematerialize parents in rematerialize_derefs_in_use_blocks
When nir_rematerialize_derefs_in_use_blocks_impl was first written, I
attempted to optimize things a bit by not bothering to re-materialize
the sources of deref instructions figuring that the final caller would
take care of that. However, in the case of more complex deref chains
where the first link or two lives in block A and then another link and
the load/store_deref intrinsic live in block B it doesn't work. The
code in rematerialize_deref_in_block looks at the tail of the chain,
sees that it's already in block B and skips it, not realizing that part
of the chain also lives in block A.
The easy solution here is to just rematerialize deref sources of deref
instructions as well. This may potentially lead to a few more deref
instructions being created by the conditions required for that to
actually happen are fairly unlikely and, thanks to the caching, it's all
linear time regardless.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109603
Fixes:
7d1d1208c2b "nir: Add a small pass to rematerialize derefs per-block"
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Jason Ekstrand [Wed, 6 Feb 2019 20:27:34 +0000 (14:27 -0600)]
intel/fs: Use enumerated array assignments in fb read TXF setup
It's more clear and means we don't have to update the array every time
we add an optional texture instruction argument
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Michel Dänzer [Fri, 8 Feb 2019 09:14:58 +0000 (10:14 +0100)]
gitlab-ci: Re-use docker image from the main repo in forked repos
Instead of generating it from scratch in each forked repo. This should
save time, energy and storage. (The xserver & xf86-video-amdgpu CI
scripts do basically the same)
v2:
* Hardcode "mesa" instead of using $CI_PROJECT_NAME, to avoid breakage
if the project name is changed after forking (Eric Engestrom)
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Ilia Mirkin [Sun, 10 Feb 2019 03:36:49 +0000 (22:36 -0500)]
nvc0: we have 16k-sized framebuffers, fix default scissors
For some reason we don't use view volume clipping by default, and use
scissors instead. These scissors were set to an 8k max fb size, while
the driver advertises 16k-sized framebuffers.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>
Alyssa Rosenzweig [Fri, 8 Feb 2019 02:28:12 +0000 (02:28 +0000)]
panfrost: Specify supported draw modes per-context
Midgard has native support for QUADS and POLYGONS; Bifrost seemingly
does not. Thus, Midgard generally skips prim_convert whereas Bifrost
needs the pass; this patch allows the setting of allowed primitives to
occur on a per-context basis (for runtime hardware selection).
v2: Use (POLYGONS + 1) instead of LINES_ADJACENCY.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Robert Foss <robert.foss@collabora.com>
Dave Airlie [Fri, 8 Feb 2019 04:27:09 +0000 (14:27 +1000)]
radv: remove alloc parameter from pipeline init
clang points out this isn't used.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Dave Airlie [Fri, 8 Feb 2019 05:25:49 +0000 (15:25 +1000)]
radv/llvm: initialise passes member.
Fixes coverity warning
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Dave Airlie [Fri, 8 Feb 2019 05:23:46 +0000 (15:23 +1000)]
glsl: glsl to nir fix uninit class member.
The constructor should init this to NULL
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Alyssa Rosenzweig [Sat, 9 Feb 2019 01:14:34 +0000 (01:14 +0000)]
panfrost: Elucidate texture op scheduling comment
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Sat, 9 Feb 2019 01:13:23 +0000 (01:13 +0000)]
panfrost: Remove speculative if 0'd format bit code
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Fri, 8 Feb 2019 02:21:46 +0000 (02:21 +0000)]
panfrost: Remove if 0'd dead code
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Thu, 7 Feb 2019 06:00:11 +0000 (06:00 +0000)]
panfrost: Add kernel-agnostic resource management
Various methods relating to resource management were previously marked
as kernel-specific, forcing them to stay downstream in the vendor
overlay and eventually be duplicated for DRM code. This patch adds back
this code in kernel-neutral space, allowing for code sharing and
minimising the diff to downstream.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Thu, 7 Feb 2019 04:56:13 +0000 (04:56 +0000)]
panfrost: Don't hardcode number of nir_ssa_defs
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Thu, 7 Feb 2019 03:39:25 +0000 (03:39 +0000)]
panfrost: Clean-up one-argument passing quirk
Most Midgard instructions take two-arguments logically; there are always
two arguments at the assembly level. For the few instructions that take
only a single argument, generally the second argument slot is unused,
with a zero inline constant occupying the space. fmov/imov are the
exception, where the first argument is filled with r24 and the logical
argument is in the second slot.
Previously, these constraints were handled by a delicate, buggy series
of hacks. This commit removes these hacks. Instead, we look at the
logical number of arguments (from NIR), switching between two argument
and one-argument-one-zero style. We then introduce a quirk for the
flipped style, which applies to fmov/imov.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Karol Herbst [Sat, 9 Feb 2019 00:22:27 +0000 (01:22 +0100)]
glsl_type: initialize offset and location to -1 for glsl_struct_field
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Fri, 8 Feb 2019 23:57:19 +0000 (15:57 -0800)]
nouveau: Silence unhandled cap warnings
Nouveau apparently uses the u_screen helper but prints a warning in the
default case, so running any GL program would start grumbling.
Fixes:
8fa54bc5490 gallium: Add a PIPE_CAP_NIR_COMPACT_ARRAYS capability bit.
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Caio Marcelo de Oliveira Filho [Thu, 7 Feb 2019 21:44:33 +0000 (13:44 -0800)]
intel/compiler: use 0 as sampler in emit_mcs_fetch
The sampler will be ignored since the underlying 'ld_mcs' operation
won't use it, so just fill the field with 0 instead of the texture to
make it clearer that's the case.
This will also avoid is_high_sampler() to kick in unnecessarily, in
case we are using the operation for a texture with index >= 16.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Eric Engestrom [Sun, 25 Nov 2018 11:23:26 +0000 (11:23 +0000)]
wsi: query the ICD's max dimensions instead of hard-coding them
anv and radv both happened to already return 2^14 for these, but
querying the ICD is safer and will help if vdreno (or whatever it's
called) doesn't have the same max.
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Ian Romanick [Fri, 18 Jan 2019 01:53:40 +0000 (17:53 -0800)]
nir: Convert a bcsel with only phi node sources to a phi node
v2: Remove the original ALU instruciton after all of its readers are
modified to read the new ALU instruction.
v3: Fix an issue where a bcsel that may not be executed on a loop
iteration due to a break statement is converted to a phi (and therefore
incorrectly "executed"). Noticed by Tim.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109216
Fixes:
8fb8ebfbb05 ("intel/compiler: More peephole select")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Ian Romanick [Fri, 18 Jan 2019 01:34:47 +0000 (17:34 -0800)]
nir: Split ALU instructions in loops that read phis
A single shader in Unigine Superposition is affected by this change.
A single iadd is moved to the end of a loop. This iadd is involved in
a complex set of logic to terminate the loop, and an extra mov
instruction is inserted. This shader really needs the optimization
suggested by bugzilla #94747, and I expect that to make this tiny
regression go away.
All Gen7+ platforms had similar results. (Skylake shown)
total instructions in shared programs:
15047543 ->
15047545 (<.01%)
instructions in affected programs: 565 -> 567 (0.35%)
helped: 0
HURT: 2
total cycles in shared programs:
369977253 ->
369978253 (<.01%)
cycles in affected programs: 127910 -> 128910 (0.78%)
helped: 0
HURT: 2
v2: Skip nir_op_vec{2,3,4} and nir_op_[fi]mov instructions to avoid
infinite optimization loops. Remove the original ALU instruciton after
all of its readers are modified to read the new ALU instruction.
v3: Extend to the more general case. The if the prev-block value from
the phi is not undef, this means the ALU instruction has to be
duplicated in both the prev-block and the continue-block.
Fixes:
8fb8ebfbb05 ("intel/compiler: More peephole select")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Ian Romanick [Mon, 14 Jan 2019 23:12:36 +0000 (15:12 -0800)]
nir: Select phi nodes using prev_block instead of continue_block
This simplifies some changes coming later.
Fixes:
8fb8ebfbb05 ("intel/compiler: More peephole select")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Ian Romanick [Mon, 14 Jan 2019 19:36:23 +0000 (11:36 -0800)]
nir: Refactor code that checks phi nodes in opt_peel_loop_initial_if
This will be used in a couple more places soon.
The function name is... horribly long. Neither Matt nor I could think
of any thing that was shorter and still more descriptive than
"is_phi_foo". I'm willing to entertain suggestions.
Fixes:
8fb8ebfbb05 ("intel/compiler: More peephole select")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Ian Romanick [Wed, 16 Jan 2019 19:34:35 +0000 (11:34 -0800)]
nir: Document some fields of nir_loop_terminator
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Ian Romanick [Fri, 25 Jan 2019 01:18:01 +0000 (17:18 -0800)]
intel/compiler: Silence warning about value that may be used uninitialized
For some reason, this warning only occurs for me in release builds.
In file included from src/intel/compiler/brw_nir_lower_mem_access_bit_sizes.c:25:0:
src/intel/compiler/brw_nir_lower_mem_access_bit_sizes.c: In function ‘brw_nir_lower_mem_access_bit_sizes’:
src/compiler/nir/nir_builder.h:501:26: warning: ‘src_swiz[2]’ may be used uninitialized in this function [-Wmaybe-uninitialized]
alu_src.swizzle[i] = swiz[i];
~~~~~~~~~~~~~~~~~~~^~~~~~~~~
src/intel/compiler/brw_nir_lower_mem_access_bit_sizes.c:225:16: note: ‘src_swiz[2]’ was declared here
unsigned src_swiz[4];
^~~~~~~~
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Ian Romanick [Thu, 24 Jan 2019 22:37:16 +0000 (14:37 -0800)]
nir: Silence zillions of unused parameter warnings in release builds
Fixes:
cd56d79b59f "nir: check NIR_SKIP to skip passes by name"
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Eric Engestrom [Fri, 8 Feb 2019 17:43:55 +0000 (17:43 +0000)]
gitlab-ci: workaround docker bug for users with uppercase characters
CI_REGISTRY_IMAGE == lower($CI_REGISTRY/$CI_PROJECT_PATH)
Suggested-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Andrii Simiklit [Tue, 2 Oct 2018 16:16:01 +0000 (19:16 +0300)]
i965: consider a 'base level' when calculating width0, height0, depth0
I guess that when we calculating the width0, height0, depth0
to use for function 'intel_miptree_create' we need to consider
the 'base level' like it is done in the 'intel_miptree_create_for_teximage'
function.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107987
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Sun, 9 Dec 2018 23:23:51 +0000 (10:23 +1100)]
nir: rewrite varying component packing
There are a number of reasons for the rewrite.
1. Adding support for packing tess patch varyings in a sane way.
2. Making use of qsort allowing the code to be much easier to
follow.
3. Fixes a bug where different interp types caused component
packing to be skipped for all varyings in some scenarios.
4. Allows us to add a crude live range analysis for deciding
which components should be packed together. This support can
optionally be added in a future patch.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Timothy Arceri [Sun, 9 Dec 2018 22:42:42 +0000 (09:42 +1100)]
nir: add is_packing_supported_for_type() helper
This will be used in the following patches to determine if we
support packing the components of a varying.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Timothy Arceri [Wed, 6 Feb 2019 01:27:39 +0000 (12:27 +1100)]
nir: add glsl_type_is_32bit() helper
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Timothy Arceri [Sun, 2 Dec 2018 23:42:40 +0000 (10:42 +1100)]
nir: add support for marking used patches when packing varyings
This adds support needed for marking the varyings as used but we
don't actually support packing patches in this patch.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Timothy Arceri [Wed, 6 Feb 2019 09:37:14 +0000 (20:37 +1100)]
st/glsl_to_nir: call nir_remove_dead_variables() after lowing local indirects
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Timothy Arceri [Wed, 6 Feb 2019 01:18:52 +0000 (12:18 +1100)]
util: move BITFIELD macros to util/macros.h
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Karol Herbst [Wed, 16 Jan 2019 14:17:31 +0000 (15:17 +0100)]
st/mesa: require RGBA2, RGB4, and RGBA4 to be renderable
If the driver does not support rendering to these formats but does
support texturing, we can end up in incompatibilities between textures
and renderbuffers that are then copied to.
Fixes KHR-GL45.copy_image.functional on nvc0
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
Karol Herbst [Fri, 25 Aug 2017 17:22:03 +0000 (19:22 +0200)]
gallium: add PIPE_CAP_MAX_VARYINGS
Some NVIDIA hardware can accept 128 fragment shader input components,
but only have up to 124 varying-interpolated input components. We add a
new cap to express this cleanly. For most drivers, this will have the
same value as PIPE_SHADER_CAP_MAX_INPUTS for the fragment shader.
Fixes KHR-GL45.limits.max_fragment_input_components
Signed-off-by: Karol Herbst <karolherbst@gmail.com>
[imirkin: rebased, improved docs/commit message]
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Rob Clark <robdclark@gmail.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: 19.0 <mesa-stable@lists.freedesktop.org>