Sean Nyekjaer [Fri, 24 Nov 2017 13:01:28 +0000 (14:01 +0100)]
arm: mvebu: fix boot from UART when in fallback mode
It's the first 8 bits of the bootrom error register that
contain the boot error/fallback error code. Let's check that
and continue to boot from UART.
Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
Signed-off-by: Stefan Roese <sr@denx.de>
Sean Nyekjaer [Fri, 24 Nov 2017 13:00:48 +0000 (14:00 +0100)]
arm: mvebu: add nand pins
Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
Signed-off-by: Stefan Roese <sr@denx.de>
Sean Nyekjaer [Wed, 22 Nov 2017 12:39:08 +0000 (13:39 +0100)]
fix: nand: pxa3xx: fix defined but not used warnings
bbt_mirror_descr and bbt_main_descr is defined but not used
when compiling without CONFIG_SYS_NAND_USE_FLASH_BBT set.
Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
Signed-off-by: Stefan Roese <sr@denx.de>
Tom Rini [Wed, 29 Nov 2017 13:26:07 +0000 (08:26 -0500)]
Merge tag 'xilinx-for-v2018.01' of git://denx.de/git/u-boot-microblaze
Xilinx changes for v2018.1
Zynq:
- Add support for Syzygy and cc108 boards
- Add support for mini u-boot configurations (cse)
- dts updates
- config/defconfig updates in connection to Kconfig changes
- Fix psu_init handling
ZynqMP:
- SPL fixes
- Remove slcr.c
- Fixing r5 startup sequence
- Add support for external pmufw
- Add support for new ZynqMP chips
- dts updates
- Add support for zcu102 rev1.0 board
Drivers:
- nand: Support external timing setting and board init
- ahci: Fix wording
- axi_emac: Wait for bit, non processor mode, readl/write conversion
- zynq_gem: Fix SGMII/PCS support
Siva Durga Prasad Paladugu [Thu, 23 Nov 2017 06:53:12 +0000 (12:23 +0530)]
net: xilinx_axi_emac: Use readl and writel for io ops
This patch uses readl and writel instead of in_be32 and
out_be32 for io ops as these internally uses readl,
writel for microblaze and for Zynq, ZynqMP there is
no need of endianness conversion and readl, writel
should work straightaway. This patch starts supporting
the driver for Zynq and ZynqMP platforms.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Thu, 23 Nov 2017 07:26:55 +0000 (12:56 +0530)]
net: zynq_gem: Dont enable SGMII and PCS selection
Dont enable SGMII and PCS selection if internal PCS/PMA
is not used, by getting the info about internal/external
PCS/PMA usage from dt property "is-internal-phy".
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 23 Nov 2017 07:25:41 +0000 (08:25 +0100)]
arm: zynq: Change Zynq/ZynqMP Kconfig description
Use more accurate description for Xilinx Zynq and ZynqMP based platforms.
With using driver model there shouldn't be a need to create separate
Kconfig config options.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Jean-Francois Dagenais [Thu, 23 Mar 2017 11:39:14 +0000 (07:39 -0400)]
tools: zynqmpimage: adjust ug1085 reference to v1.4 of the document
The chapter in which the table explaining the image format changed
chapter as the document evolved. This should help people track the
info down faster.
Signed-off-by: Jean-Francois Dagenais <jeff.dagenais@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Joe Hershberger [Tue, 7 Nov 2017 02:16:10 +0000 (18:16 -0800)]
mtd: nand: zynq: Add support for the NAND lock/unlock operation
Zynq NAND driver is not support for NAND lock or unlock operation.
Hence, accidentally write into the critical NAND region might cause
data corruption to occur.
This commit is to add NAND lock/unlock command into NAND SMC register
set for NAND lock/unlock operaion.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Keng Soon Cheah <keng.soon.cheah@ni.com>
Cc: Chen Yee Chew <chen.yee.chew@ni.com>
Cc: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Scott Wood <oss@buserror.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Wilson Lee [Wed, 15 Nov 2017 09:14:35 +0000 (01:14 -0800)]
mtd: zynq: nand: Move board_nand_init() function to board.c
Putting board_nand_init() function inside NAND driver was not appropriate
due to it doesn't allow board vendor to customise their NAND
initialization code such as adding NAND lock/unlock code.
This commit was to move the board_nand_init() function from NAND driver
to board.c file. This allow customization of board_nand_init() function.
Signed-off-by: Wilson Lee <wilson.lee@ni.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Keng Soon Cheah <keng.soon.cheah@ni.com>
Cc: Chen Yee Chew <chen.yee.chew@ni.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Cc: Scott Wood <oss@buserror.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 10 Nov 2017 11:41:10 +0000 (12:41 +0100)]
arm: zynq: Add ps7_init for cc108
After some generic cleanup adding ps7_init* to repository
is not big pain now.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 10 Nov 2017 12:01:10 +0000 (13:01 +0100)]
arm: zynq: Show information about silicon version
Show information about silicon in bootlog.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 10 Nov 2017 12:03:50 +0000 (13:03 +0100)]
arm: zynq: Do not show information from checkboard twice
There is no reason to show information about board twice.
Remove boardinfo late calls.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 10 Nov 2017 12:28:07 +0000 (13:28 +0100)]
arm: zynq: Use unsigned type with comparison with ARRAY_SIZE
Sparse is return warning about this:
arch/arm/mach-zynq/slcr.c: In function 'zynq_slcr_get_mio_pin_status':
arch/arm/mach-zynq/slcr.c:185:16: warning: comparison between signed and
unsigned integer expressions [-Wsign-compare]
for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) {
^
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 10 Nov 2017 10:00:42 +0000 (11:00 +0100)]
arm: zynq: Convert all board to use arch ps7_init code
Use generic implementation. It will also reduce config data size for
converted boards.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 10 Nov 2017 10:03:47 +0000 (11:03 +0100)]
arm: zynq: Add support for EMIT_WRITE operation
Add proper support for EMIT_WRITE operation which is write only.
Do not use EMIT_MASKWRITE which is read-modify-write.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 10 Nov 2017 10:06:02 +0000 (11:06 +0100)]
arm: zynq: Add ps7GetSiliconVersion() to ps7_spl_init
Unfortunately camelcase is coming from ps7_init* format.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 10 Nov 2017 08:47:28 +0000 (09:47 +0100)]
arm: zynq: Move common ps7_init* initialization to arch code
This patch is based on work done in topic board where the first address
word also storing operation which should be done. This is reducing size
of configuration data.
This patch is not breaking an option to copy default ps7_init_gpl* files
from hdf file but it is doing preparation for ps7_init* consolidation.
The patch is also marking ps7_config as weak function.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 10 Nov 2017 08:51:17 +0000 (09:51 +0100)]
arm: zynq: Get rid of ps7_reset_apu() for syzygy board
There is no reason to call separate function.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 8 Nov 2017 15:14:47 +0000 (16:14 +0100)]
arm: zynq: Move ps7_* to separate file
Extract ps7_* from spl code to prepare for extension.
And also return value.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 10 Nov 2017 08:09:48 +0000 (09:09 +0100)]
arm: zynq: Remove ps7_debug code
SPL is not calling this code that's why it is dead code and can be
removed.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 10 Nov 2017 08:26:40 +0000 (09:26 +0100)]
arm: zynq: Enable debug uart on zc706
Enable debug uart by default.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 8 Nov 2017 15:10:35 +0000 (16:10 +0100)]
arm: zynq: Add missing ps7_post_config declaration
Add missing declaration to header.
Warning log:
arch/arm/mach-zynq/spl.c:94:12: warning: symbol 'ps7_post_config' was
not declared. Should it be static?
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Fri, 6 Jan 2017 10:57:15 +0000 (16:27 +0530)]
net: xilinx_axi_emac: Add support for non processor mode
Add support for non processor mode, this mode doesn't have
access to some of the registers and hence this patch
bypasses it and also length has to be calculated from
status instead of app4 in this mode.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tom Rini [Tue, 28 Nov 2017 21:54:30 +0000 (16:54 -0500)]
Merge git://git.denx.de/u-boot-mips
Tom Rini [Tue, 28 Nov 2017 21:54:09 +0000 (16:54 -0500)]
Merge git://git.denx.de/u-boot-uniphier
Paul Burton [Tue, 21 Nov 2017 22:31:07 +0000 (14:31 -0800)]
boston: Add u-boot.mcs make target
U-Boot is generally flashed to a MIPS Boston development board by means
of a .mcs file which Xilinx Vivado software can write to the flash
present on the board. As such we'd generally want to produce an mcs file
when building U-Boot to target the Boston board. Introduce a make target
for u-boot.mcs which generates it using the srec_cat tool available from
the SRecord project, and build it by default when srec_cat is present.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot@lists.denx.de
Paul Burton [Tue, 21 Nov 2017 20:35:31 +0000 (12:35 -0800)]
boston: Set CONFIG_SYS_LOAD_ADDR to 0x88000000
Generally we load Linux kernels on Boston boards in the form of FIT
images containing a compressed kernel binary. Linux is linked at
0x80100000 and so we need to decompress the kernel binary to that
address, however this is our default load address which means that
unless explicitly avoided we hit a decompression error as the
uncompressed kernel binary overwrites its compressed version from the
FIT image.
Avoid this by adjusting CONFIG_SYS_LOAD_ADDR to 0x88000000 (or
0xffffffff88000000 for MIPS64 builds) which avoids the address overlap
between compressed & uncompressed kernel binaries.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot@lists.denx.de
Paul Burton [Tue, 21 Nov 2017 19:18:39 +0000 (11:18 -0800)]
MIPS: Break out of cache loops for unimplemented caches
If we run on a CPU which doesn't implement a particular cache then we
would previously get stuck in an infinite loop, executing a cache op on
the first "line" of the missing cache & then incrementing the address by
0. This was being avoided for the L2 caches, but not for the L1s. Fix
this by generalising the check for a zero line size & avoiding the cache
op loop when this is the case.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot@lists.denx.de
Paul Burton [Tue, 21 Nov 2017 19:18:38 +0000 (11:18 -0800)]
MIPS: Clear instruction hazards in flush_cache()
When writing code, for example during relocation, we ensure that the
icache has a coherent view of the new instructions with a call to
flush_cache(). This handles the bulk of the work to ensure the new
instructions will execute as expected, however it does not ensure that
the CPU pipeline doesn't already contain instructions taken from a stale
view of the affected memory. This could theoretically be a problem for
relocation, but in practice typically isn't because we sync caches for
enough code after the entry point of the newly written code that by the
time the CPU pipeline might possibly fetch any of it we'll have long ago
written it back & invalidated any stale icache entries. This is however
a problem for shorter regions of code.
In preparation for later patches which write shorter segments of code,
ensure any instruction hazards are cleared by flush_cache() by
introducing & using a new instruction_hazard_barrier() function which
makes use of the jr.hb instruction to clear the hazard.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot@lists.denx.de
Paul Burton [Tue, 21 Nov 2017 19:18:37 +0000 (11:18 -0800)]
MIPS: Ensure cache ops complete in cache maintenance functions
A typical use of cache maintenance functions is to force writeback of
data which a device is about to read using DMA - for example a
descriptor or command structure. Such users of cache maintenance
functions require that operations on the cache have completed before
they proceed to instruct a device to read memory. This requires that we
place a completion barrier (ie. sync instruction) between the cache ops
and whatever write informs the device to perform DMA.
Whilst strictly speaking this isn't all users of the cache maintenance
functions & we could instead place the barriers in the drivers that
require them, it would be much more invasive to do so than to just have
the barrier be the default by placing it in the cache functions
themselves. The cost is low enough that it shouldn't matter to us in any
rare cases that we use the cache functions when not performing DMA.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot@lists.denx.de
Paul Burton [Mon, 30 Oct 2017 23:58:21 +0000 (16:58 -0700)]
Update Paul Burton's email address
MIPS is no longer a part of Imagination Technologies, and as such my
@imgtec.com email address will soon cease to function. This patch
updates occurrances of it with my new @mips.com email address, and adds
an entry in .mailmap such that git (& tools such as get_maintainer.pl
when examining history) will use the new address.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot@lists.denx.de
Paul Burton [Fri, 15 Sep 2017 18:35:54 +0000 (11:35 -0700)]
MIPS: Drop unused PTR_COUNT_SHIFT from u-boot.lds
The u-boot.lds linker script for MIPS defines a PTR_COUNT_SHIFT macro to
2 or 3 for 32 bit or 64 bit builds respectively. This macro is never
actually used though, so remove the dead code.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Paul Burton [Fri, 15 Sep 2017 18:34:31 +0000 (11:34 -0700)]
boston: Remove unused label in lowlevel_display
The lowlevel_display() function includes a "1:" label which is never
used. Remove it.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Paul Burton [Fri, 15 Sep 2017 18:33:53 +0000 (11:33 -0700)]
boston: Drop unused return value
The boston lowlevel_init() function zeroes the return register v0,
despite the function not being expected to return a value & that value
never being used.
Remove the redundant assignment to v0.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Masahiro Yamada [Mon, 27 Nov 2017 05:13:49 +0000 (14:13 +0900)]
ARM: uniphier: remove unused NAND CONFIG options
The Denali NAND driver does not use these options any more.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Fri, 24 Nov 2017 15:25:35 +0000 (00:25 +0900)]
ARM: dts: uniphier: Sync with Linux 4.15-rc1
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Fri, 24 Nov 2017 15:25:34 +0000 (00:25 +0900)]
gpio: uniphier: import dt-binginds header from Linux
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Fri, 24 Nov 2017 15:25:33 +0000 (00:25 +0900)]
ARM: uniphier: remove XIRQ pin settings
The XIRQ pins are now set up on the Linux side by the GPIO hogging.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Fri, 24 Nov 2017 15:25:32 +0000 (00:25 +0900)]
ARM: uniphier: remove IRQ settings
This work-around has been here in U-Boot because the AIDET and GPIO
drivers were missing in the upstream Linux. Both are now available
in Linus' tree:
- drivers/irqchip/irq-uniphier-aidet.c
- drivers/gpio/gpio-uniphier.c
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Fri, 24 Nov 2017 15:25:31 +0000 (00:25 +0900)]
ARM: uniphier: set CONFIG_LOGLEVEL to 6
Print out KERN_NOTICE or higher level log messages.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Tue, 21 Nov 2017 17:38:32 +0000 (02:38 +0900)]
mtd: nand: denali: sync with Linux 4.15-rc1
I largely reworked the Denali NAND controller driver in Linux.
This commit imports the improvements from Linux. The code is
almost synced with Linux 4.15-rc1.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Tue, 21 Nov 2017 17:38:31 +0000 (02:38 +0900)]
mtd: nand: introduce NAND_ROW_ADDR_3 flag
Several drivers check ->chipsize to see if the third row address cycle
is needed. Instead of embedding magic sizes such as 32MB, 128MB in
drivers, introduce a new flag NAND_ROW_ADDR_3 for clean-up. Since
nand_scan_ident() knows well about the device, it can handle this
properly. The flag is set if the row address bit width is greater
than 16.
Delete comments such as "One more address cycle for ..." because
intention is now clear enough from the code.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Wenyou Yang <wenyou.yang@microchip.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit:
14157f861437ebe2d624b0a845b91bbdf8ca9a2d]
Masahiro Yamada [Tue, 21 Nov 2017 17:38:30 +0000 (02:38 +0900)]
mtd: nand: add a shorthand to generate nand_ecc_caps structure
struct nand_ecc_caps was designed as flexible as possible to support
multiple stepsizes (like sunxi_nand.c).
So, we need to write multiple arrays even for the simplest case.
I guess many controllers support a single stepsize, so here is a
shorthand macro for the case.
It allows to describe like ...
NAND_ECC_CAPS_SINGLE(denali_pci_ecc_caps, denali_calc_ecc_bytes, 512, 8, 15);
... instead of
static const int denali_pci_ecc_strengths[] = {8, 15};
static const struct nand_ecc_step_info denali_pci_ecc_stepinfo = {
.stepsize = 512,
.strengths = denali_pci_ecc_strengths,
.nstrengths = ARRAY_SIZE(denali_pci_ecc_strengths),
};
static const struct nand_ecc_caps denali_pci_ecc_caps = {
.stepinfos = &denali_pci_ecc_stepinfo,
.nstepinfos = 1,
.calc_ecc_bytes = denali_calc_ecc_bytes,
};
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit:
a03c60178c181767ecfb26fb311a88742d228118]
Masahiro Yamada [Tue, 21 Nov 2017 17:38:29 +0000 (02:38 +0900)]
mtd: nand: add generic helpers to check, match, maximize ECC settings
Driver are responsible for setting up ECC parameters correctly.
Those include:
- Check if ECC parameters specified (usually by DT) are valid
- Meet the chip's ECC requirement
- Maximize ECC strength if NAND_ECC_MAXIMIZE flag is set
The logic can be generalized by factoring out common code.
This commit adds 3 helpers to the NAND framework:
nand_check_ecc_caps - Check if preset step_size and strength are valid
nand_match_ecc_req - Match the chip's requirement
nand_maximize_ecc - Maximize the ECC strength
To use the helpers above, a driver needs to provide:
- Data array of supported ECC step size and strength
- A hook that calculates ECC bytes from the combination of
step_size and strength.
By using those helpers, code duplication among drivers will be
reduced.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit:
2c8f8afa7f92acb07641bf95b940d384ed1d0294]
Boris Brezillon [Tue, 21 Nov 2017 17:38:28 +0000 (02:38 +0900)]
mtd: nand: Pass the CS line to ->setup_data_interface()
Some NAND controllers can assign different NAND timings to different
CS lines. Pass the CS line information to ->setup_data_interface() so
that the NAND controller driver knows which CS line is concerned by
the setup_data_interface() request.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit:
104e442a67cfba4d0cc982384761befb917fb6a1]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Tue, 21 Nov 2017 17:38:27 +0000 (02:38 +0900)]
mtd: nand: allow drivers to request minimum alignment for passed buffer
In some cases, nand_do_{read,write}_ops is passed with unaligned
ops->datbuf. Drivers using DMA will be unhappy about unaligned
buffer.
The new struct member, buf_align, represents the minimum alignment
the driver require for the buffer. If the buffer passed from the
upper MTD layer does not have enough alignment, nand_do_*_ops will
use bufpoi.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit:
477544c62a84d3bacd9f90ba75ffc16c04d78071]
Boris Brezillon [Tue, 21 Nov 2017 17:38:26 +0000 (02:38 +0900)]
mtd: nand: Wait for PAGEPROG to finish in drivers setting NAND_ECC_CUSTOM_PAGE_ACCESS
Drivers setting NAND_ECC_CUSTOM_PAGE_ACCESS are supposed to handle the
full read/write page sequence, and waiting for a page to actually be
programmed is part of this write-page sequence.
This is also what is done in ->write_oob_xxx() hooks, so let's do that in
->write_page_xxx() as well to make it consistent.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit:
41145649f4acb30249b636b945053db50c9331c5]
[masahiro:
There is no driver setting NAND_ECC_CUSTOM_PAGE_ACCESS in U-Boot.
No driver is affected by this change.]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Boris Brezillon [Tue, 21 Nov 2017 17:38:25 +0000 (02:38 +0900)]
mtd: nand: Drop the ->errstat() hook
The ->errstat() hook is no longer implemented NAND controller drivers.
Get rid of it before someone starts abusing it.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit:
7d135bcced20be2b50128432c5426a7278ec4f6d]
[masahiro: modify davinci_nand.c for U-Boot]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Boris Brezillon [Tue, 21 Nov 2017 17:38:24 +0000 (02:38 +0900)]
mtd: nand: Drop unused cached programming support
Cached programming is always skipped, so drop the associated code until
we decide to really support it.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit:
0b4773fd1649e0d418275557723a7ef54f769dc9]
[masahiro: modify davinci_nand.c for U-Boot]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Boris Brezillon [Tue, 21 Nov 2017 17:38:23 +0000 (02:38 +0900)]
mtd: add mtd_ooblayout_xxx() helper functions
In order to make the ecclayout definition completely dynamic we need to
rework the way the OOB layout are defined and iterated.
Create a few mtd_ooblayout_xxx() helpers to ease OOB bytes manipulation
and hide ecclayout internals to their users.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit:
75eb2cec251fda33c9bb716ecc372819abb9278a]
[masahiro:
cherry-pick more code from
adbbc3bc827eb1f43a932d783f09ba55c8ec8379]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Marc Gonzalez [Tue, 21 Nov 2017 17:38:22 +0000 (02:38 +0900)]
mtd: nand: Support controllers with custom page
If your controller already sends the required NAND commands when
reading or writing a page, then the framework is not supposed to
send READ0 and SEQIN/PAGEPROG respectively.
Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit:
3371d663bb4579f1b2003a92162edd6d90edd089]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Boris Brezillon [Tue, 21 Nov 2017 17:38:21 +0000 (02:38 +0900)]
mtd: nand: Add a few more timings to nand_sdr_timings
Add the tR_max, tBERS_max, tPROG_max and tCCS_min timings to the
nand_sdr_timings struct.
Assign default/safe values for the statically defined timings, and
extract them from the ONFI parameter table if the NAND is ONFI
compliant.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
[Linux commit:
204e7ecd47e26cc12d9e8e8a7e7a2eeb9573f0ba
Fixup commit:
6d29231000bbe0fb9e4893a9c68151ffdd3b5469]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Boris Brezillon [Tue, 21 Nov 2017 17:38:20 +0000 (02:38 +0900)]
mtd: nand: Fix data interface configuration logic
When changing from one data interface setting to another, one has to
ensure a specific sequence which is described in the ONFI spec.
One of these constraints is that the CE line has go high after a reset
before a command can be sent with the new data interface setting, which
is not guaranteed by the current implementation.
Rework the nand_reset() function and all the call sites to make sure the
CE line is asserted and released when required.
Also make sure to actually apply the new data interface setting on the
first die.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Fixes:
d8e725dd8311 ("mtd: nand: automate NAND timings selection")
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Tested-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
[Linux commit:
73f907fd5fa56b0066d199bdd7126bbd04f6cd7b]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Boris Brezillon [Tue, 21 Nov 2017 17:38:19 +0000 (02:38 +0900)]
mtd: nand: automate NAND timings selection
The NAND framework provides several helpers to query timing modes supported
by a NAND chip, but this implies that all NAND controller drivers have
to implement the same timings selection dance. Also currently NAND
devices can be resetted at arbitrary places which also resets the timing
for ONFI chips to timing mode 0.
Provide a common logic to select the best timings based on ONFI or
->onfi_timing_mode_default information. Hook this into nand_reset()
to make sure the new timing is applied each time during a reset.
NAND controller willing to support timings adjustment should just
implement the ->setup_data_interface() method.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
[Linux commit:
d8e725dd831186a3595036b2b1df9f68cbc6efa3]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Sascha Hauer [Tue, 21 Nov 2017 17:38:18 +0000 (02:38 +0900)]
mtd: nand: Expose data interface for ONFI mode 0
The nand layer will need ONFI mode 0 to use it as timing mode
before and right after reset.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit:
6e1f9708dbf3c50a8da93c1952a01a7a2acb5e66]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Sascha Hauer [Tue, 21 Nov 2017 17:38:17 +0000 (02:38 +0900)]
mtd: nand: convert ONFI mode into data interface
struct nand_data_interface is the designated type to pass to
the NAND drivers to configure the timing. To simplify further
patches convert the onfi_sdr_timings array from type struct
nand_sdr_timings nand_data_interface.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit:
b1dd3ca203fccd111926c3f6ac59bf903ec62b05]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Sascha Hauer [Tue, 21 Nov 2017 17:38:16 +0000 (02:38 +0900)]
mtd: nand: Introduce nand_data_interface
Currently we have no data structure to fully describe a NAND timing.
We only have struct nand_sdr_timings for NAND timings in SDR mode,
but nothing for DDR mode and also no container to store both types
of timing.
This patch adds struct nand_data_interface which stores the timing
type and a union of different timings. This can be used to pass to
drivers in order to configure the timing.
Add kerneldoc for struct nand_sdr_timings while touching it anyway.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit:
eee64b700e26b9bcc6fce024681c31f5e12271fc]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Sascha Hauer [Tue, 21 Nov 2017 17:38:15 +0000 (02:38 +0900)]
mtd: nand: Create a NAND reset function
When NAND devices are resetted some initialization may have to be done,
like for example they have to be configured for the timing mode that
shall be used. To get a common place where this initialization can be
implemented create a nand_reset() function. This currently only issues
a NAND_CMD_RESET to the NAND device. The places issuing this command
manually are replaced with a call to nand_reset().
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit:
2f94abfe35b210e7711af9202a3dcfc9e779219a]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Sascha Hauer [Tue, 21 Nov 2017 17:38:14 +0000 (02:38 +0900)]
mtd: nand: remove unnecessary 'extern' from function declarations
'extern' is not necessary for function declarations. To prevent
people from adding the keyword to new declarations remove the
existing ones.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[Linux commit:
79022591839f110f465cac0223e117b91d47d5db]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Boris Brezillon [Tue, 21 Nov 2017 17:38:13 +0000 (02:38 +0900)]
mtd: nand: Add an option to maximize the ECC strength
The generic NAND DT bindings allows one to tweak the ECC strength and
step size to their need. It can be used to lower the ECC strength to
match a bootloader/firmware config, but might also be used to get a better
reliability.
In the latter case, the user might want to use the maximum ECC strength
without having to explicitly calculate the exact value (this value not
only depends on the OOB size, but also on the NAND controller, and can
be tricky to extract).
Add a generic 'nand-ecc-maximize' DT property and the associated
NAND_ECC_MAXIMIZE flag, to let ECC controller drivers select the best
ECC strength and step-size on their own.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
[Linux commit:
ba78ee00e1ff84de9b3ad33edbd3ec599099ee82]
[masahiro: of_property_read_bool -> fdt_getprop for U-Boot]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Tue, 21 Nov 2017 17:38:12 +0000 (02:38 +0900)]
mtd: nand: add onfi_* stubs in case ONFI_DETECTION is disabled
Add stubs to the header in case CONFIG_SYS_NAND_ONFI_DETECTION is
disabled. This is much easier than adding around #ifdef to the
caller side.
Also, I removed the #ifdef around onfi_params. In Linux, onfi_params
and jedec_params are unified as union. It will be the right thing
to do.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Tue, 21 Nov 2017 17:38:11 +0000 (02:38 +0900)]
bitops: collect BIT macros to include/linux/bitops.h
Same macros are defined in various places. Collect them into
include/linux/bitops.h like Linux.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Tue, 28 Nov 2017 12:23:20 +0000 (21:23 +0900)]
ARM: openrd: set CONFIG_LOGLEVEL to 2
These boards are on the boundary of "u-boot-nodtb.bin exceeds file
size limit" error.
Reduce the log-level to save memory footprint.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Siva Durga Prasad Paladugu [Thu, 22 Jun 2017 05:44:55 +0000 (11:14 +0530)]
net: xilinx_axi_emac: Read dma address using fdtdec_get_addr
Read dma address using fdtdec_get_addr as it checks for
address cells and size cells and reads the address
properly. fdtdec_get_int always assume address is of int
size which goes wrong if using it on 64-bit architecture.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Fri, 6 Jan 2017 10:48:50 +0000 (16:18 +0530)]
net: xilinx_axi_emac: Use wait_for_bit instead of while loop
Use wait_for_bit instead while loop during init
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Michal Simek [Wed, 8 Nov 2017 14:48:57 +0000 (15:48 +0100)]
arm64: zynqmp: Add revision to identification string
It is good to see revision in boot log.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Shubhrajyoti Datta [Thu, 6 Apr 2017 06:58:14 +0000 (12:28 +0530)]
arm64: zynqmp: Enable watchdog by default
Enable watchdog in dts for zcu102.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 2 Nov 2017 11:45:10 +0000 (12:45 +0100)]
arm64: zynqmp: Add note about si5328 interrupt
Add comment about irq present on the board connected to PL.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Anurag Kumar Vulisha [Tue, 20 Jun 2017 10:55:16 +0000 (16:25 +0530)]
arm64: zynqmp: usb: Correct IOMMU node for making SMMU work with USB
This patch makes SMMU work by moving the iommus node under the dwc3 child
entry from parent node.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 2 Nov 2017 11:41:34 +0000 (12:41 +0100)]
arm64: zynqmp: Remove clock setting from dtsi
clock setting is handled via clk dtsi file.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Anurag Kumar Vulisha [Fri, 10 Mar 2017 13:48:17 +0000 (19:18 +0530)]
arm64: zynqmp: Uncomment snps,quirk-frame-length-adjustment flag in dwc3
This patch uncomments snps,quirk-frame-length-adjustment which has
the value to adjust the SOF/ITP generated from the controller.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Manish Narani [Wed, 18 Jan 2017 12:04:48 +0000 (17:34 +0530)]
arm64: zynqmp: Add USB OTG interrupts support in dt
This patch adds OTG interrupt support in device tree. It will add
an extra interrupt line number dedicated to OTG events. This will
enable OTG interrupts to serve in DWC3 OTG driver.
Signed-off-by: Manish Narani <mnarani@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Manish Narani [Mon, 27 Mar 2017 12:17:00 +0000 (17:47 +0530)]
arm64: zynqmp: Enabled CCI support for USB
This patch adds CCI support for USB when CCI is enabled in design.
This patch also adds 'reg' property for Xilinx USB 3.0 IP. The 'reg'
property is added in order to modify a register in that to enable
coherency in Hardware.
Also add address to unit name to avoid dtc warning
Signed-off-by: Manish Narani <mnarani@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Anurag Kumar Vulisha [Thu, 2 Mar 2017 09:10:51 +0000 (14:40 +0530)]
arm64: zynqmp: Add support reading SoC revision using nvmem driver in dwc3
This patch adds support for reading silicon revision using zynqmp nvmem
driver.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 5 Jul 2017 12:51:42 +0000 (14:51 +0200)]
arm64: zynqmp: Move nodes which have no reg property out of bus
Nodes without reg properties shouldn't be placed in amba node.
Move them out.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 2 Nov 2017 11:04:43 +0000 (12:04 +0100)]
arm64: zynqmp: dt: Add AMS node
The AMS includes an ADC as well as on-chip sensors that can be used to
sample external voltages and monitor on-die operating conditions, such as
temperature and supply voltage levels.
Signed-off-by: Rajnikant Bhojani <rajnikant.bhojani@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Manish Narani [Wed, 19 Jul 2017 15:46:33 +0000 (21:16 +0530)]
arm64: zynqmp: sdhci: set host quirk2 for no 1.8V support for 1.0 silicon
This patch sets host quirk2 bit field for No 1.8V supported in case of
1.0 silicon. The 1.0 silicon doesn't have support for UHS-I modes. This
property will ensure the SD runs on High Speed mode.
Signed-off-by: Manish Narani <mnarani@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Anurag Kumar Vulisha [Wed, 8 Feb 2017 11:39:10 +0000 (17:09 +0530)]
arm64: zynqmp: Use reset controller framework for asserting/de-asserting reset
This patch modifies the phy_zynqmp.c driver to use reset-controller
framework for asserting/de-asserting reset for High Speed modules.
Also fix documentation and dtsi.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Anurag Kumar Vulisha [Mon, 6 Feb 2017 16:10:34 +0000 (21:40 +0530)]
arm64: zynqmp: Add reset-controller support in serdes driver
This patch add the reset nodes in zynqmp.dtsi which are used by
reset-controller framework
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 17 Jan 2017 13:36:54 +0000 (14:36 +0100)]
arm64: zynqmp: Remove tx_termination_fix detection on silicon v1
Only silicon v1 requires this termination fix. With new nvmem soc
revision nvmem detection driver this can be autodetected at run time and
this flag is not needed.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Nava kishore Manne [Tue, 17 Jan 2017 11:27:24 +0000 (16:57 +0530)]
arm64: zynqmp: Add support for zynqmp nvmem firmware driver
Add support for zynqmp nvmem firmware driver.
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 2 Nov 2017 10:42:12 +0000 (11:42 +0100)]
arm64: zynqmp: Add support for zcu102 1.0 rev
1.0 rev is the latest rev. Describe information in eeprom.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 2 Nov 2017 10:51:59 +0000 (11:51 +0100)]
arm64: zynqmp: Update device tree for pinmux
Added pin control support in device tree for zynqmp.
Signed-off-by: Chirag Parekh <chirag.parekh@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 10 Feb 2017 13:11:54 +0000 (14:11 +0100)]
arm64: zynqmp: Remove local-mac-address from dtsi file
Generic dtsi file can't use the same mac address for all.
U-Boot read mac from eeprom in zcu102 case and for others random mac
address is generated.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 9 Feb 2017 13:38:36 +0000 (14:38 +0100)]
arm64: zynqmp: Use SPDX license with dc4
Just header change.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 5 Jul 2017 12:50:44 +0000 (14:50 +0200)]
arm64: zynqmp: Remove leading 0s from mtd table for spi flashes
dtc reports issues with it.
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dtb: Warning
(unit_address_format): Node
/amba/spi@
ff040000/spi0_flash0@0/spi0_flash0@
00000000 unit name should
not have leading 0s
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dtb: Warning
(unit_address_format): Node
/amba/spi@
ff050000/spi1_flash0@0/spi1_flash0@
00000000 unit name should
not have leading 0s
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dtb: Warning
(unit_address_format): Node
/amba/spi@
ff040000/spi0_flash0@0/spi0_flash0@
00000000 unit name should
not have leading 0s
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dtb: Warning
(unit_address_format): Node
/amba/spi@
ff050000/spi1_flash0@0/spi1_flash0@
00000000 unit name should
not have leading 0s
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 11 May 2017 08:15:15 +0000 (10:15 +0200)]
arm64: zynqmp: Add missing alias for gem0 for ep108
Add missing alias for gem0 for ep108 to have proper sequence number.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Bharat Kumar Gogada [Mon, 30 Jan 2017 06:36:02 +0000 (12:06 +0530)]
arm64: zynqmp: zcu102: Modifying GTR lane-0 to PCIe
- Enabling GTR lane-0 to PCIe
- Enabling PCIe node in device tree
Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Chirag Parekh [Wed, 25 Jan 2017 15:00:57 +0000 (07:00 -0800)]
arm64: zynqmp: Update device tree for gpio
Used defines rather than raw values for gpio configurations.
Signed-off-by: Chirag Parekh <chirag.parekh@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 2 Nov 2017 09:22:27 +0000 (10:22 +0100)]
arm64: zynqmp: Add revB string to compatible string
Some user space libraries reading platform compatible string and based
on that changing behavior. Mark revB board with revB string.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 2 Nov 2017 09:21:08 +0000 (10:21 +0100)]
arm64: zynqmp: Use revision in dts file description
Trivial change.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Jyotheeswar Reddy Mutthareddyvari [Mon, 2 Jan 2017 09:04:51 +0000 (14:34 +0530)]
arm64: zynqmp: PM: Specify power domains for DP related nodes
Currently DP power domain (pd_dp) is not attached to any of the DP nodes which is
causing genpd to trigger a power down request for DP domain, making all DP related
peripherals unusable. So assign power domains for all DP related nodes to enable
proper accounting of DP power domain usage.
Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Naga Sureshkumar Relli [Thu, 9 Mar 2017 14:30:13 +0000 (20:00 +0530)]
arm64: zynqmp: disable smmu
This patch disables the smmu and also removes the mmu-masters
Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Nava kishore Manne [Fri, 27 Jan 2017 12:50:14 +0000 (18:20 +0530)]
arm64: zynqmp: rtc: Add calibration
This patch adds the calibration property with required value,
calculated based on rtc input crystal oscillator frequency (32.768Khz).
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Anurag Kumar Vulisha [Tue, 4 Jul 2017 14:33:42 +0000 (20:03 +0530)]
arm64: zynqmp: Add SMMU support for SATA IP
AXI master interface in CEVA AHCI controller requires two unique
Write/Read ID tags per port. This is because, ahci controller uses
different AXI ID[3:0] bits for identifying non-data transfers(like
reading descriptors, updating PRD tables, etc) and data transfers
(like sending/receiving FIS).To make SMMU work with SATA we need to
add correct SMMU stream id for SATA. SMMU stream id for SATA is
determined based on the AXI ID[1:0] as shown below
SATA SMMU ID = <TBU number>, 0011, 00, 00, AXI ID[1:0]
Note: SATA in ZynqMp uses TBU1 so TBU number = 0x1, so
SMMU ID = 001, 0011, 00, 00, AXI ID[1:0]
Since we have four different AXI ID[3:0] (2 for port0 & 2 for port1
as said above) we get four different SMMU stream id's combinations
for SATA. These AXI ID can be configured using PAXIC register.
In this patch we assumed the below AXI ID values
Read ID/ Write ID for Non-Data Port0 transfers = 0
Read ID/ Write ID for Data Port0 transfers = 1
Read ID/ Write ID for Non-Data Port1 transfers = 2
Read ID/ Write ID for Data Port1 transfers = 3
Based on the above values,SMMU stream ID's for SATA will be 0x4c0 &
0x4c1 for PORT0, 0x4c2 & 0x4c3 for PORT1. These values needed to be
added to iommus dts property. This patch does the same.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Rob Herring [Wed, 22 Mar 2017 02:03:13 +0000 (21:03 -0500)]
arm64: dts: xilinx: fix PCI bus dtc warnings
dtc recently added PCI bus checks. Fix these warnings.
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 30 Aug 2017 06:06:11 +0000 (08:06 +0200)]
arm64: zynqmp: Add missing gpio property to dtsi
All gpio controllers should contain this property.
This property is not checked by the code that's why this issue wasn't
found earlier.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Hyun Kwon [Tue, 22 Aug 2017 01:54:29 +0000 (18:54 -0700)]
arm64: zynqmp: Update the GPU address size
The correct register size is 0x10000, otherwise
it overlaps with other register space.
Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Madhurkiran Harikrishnan [Fri, 17 Feb 2017 12:14:45 +0000 (04:14 -0800)]
arm64: zynqmp: Add clock name for GPU
This patch will add names to the clocks used by GPU.
Signed-off-by: Madhurkiran Harikrishnan <madhurki@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>