freedreno/rnn: add "addvariant" to schema

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6107>

freedreno/rnn: describe copyright element in schema

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6107>

freedreno/registers/adreno_pm4: fix validation errors

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6107>

freedreno/registers/a4xx: fix validation error

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6107>

freedreno/registers/a2xx: fix validation error

And bonus whitespace fix.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6107>

freedreno/rnn: add variants/varset to domain

We have already been using this to describe pm4 packets that are
specific to certain generations.

Maybe we should introduce a new "packet" element type instead.  But
first lets just get validation working with what we already use.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6107>

freedreno/rnn: relax Hexadecimal to HexOrNumber

We are already using non-hex offsets to describe pm4 packet payloads.
Let's just permit this in the schema, rather than updating all the xml
to use hex.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6107>

freedreno/rnn: add radix/align

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6107>

freedreno/rnn: add high/low/pos to registers

This was added recently in rnn, but the schema was not updated.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6107>

freedreno/rnn: add relaxed boolean type

In the schema, boolean means strictly "true" or "false".  But rnn
parsing code was looking for "yes"/"1"/"no"/"0".  So split the
difference, and add a relaxed boolean type, and update rnn to also
accept "true" or "false".

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6107>

freedreno/rnn: update schema for 'pos'

Ideally we'd like to express that *either* 'high' + 'low' OR 'pos' is
required, but it doesn't appear that this is possible.  But the rnn
parsing code should still enforce this.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6107>

freedreno/rnn: rename schema file

All of the xml references rules-ng.xsd, not rules-ng-ng.xsd

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6107>

freedreno/rnn: add error helper

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6107>

freedreno/rnn: split out helper to find files

So we can re-use it to locate the schema file.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6107>

freedreno/tools: check rnn parse status

Don't silently ignore issues.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6107>

ci: Build kernels and rootfs for x86 devices

For testing Mesa on LAVA devices with the amd64 architecture, build
kernels and rootfs in the same way as we do for arm64 and armhf.

Also add a few trivial jobs for a specific AMD Chromebook.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Rohan Garg <rohan.garg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5903>

ci: Split building of libdrm to its own script

As we are doing that in several places already and we'll need to build
in others as well.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Rohan Garg <rohan.garg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5903>

ci: Don't ship vk-build-programs after building dEQP

As it's not needed at runtime.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Rohan Garg <rohan.garg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5903>

ci: Fix URL for glslang

master-tot doesn't have that zip file any more, but the just made
release still does.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Rohan Garg <rohan.garg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5903>

ci: Print load stats after running dEQP

So we can get an idea if what are the bottlenecks when looking for
opportunities to speed things up.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Rohan Garg <rohan.garg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6101>

ci: Always print status code of HTTP uploads in tracie

I'm seeing occasional unexpected 403 errors when uploading artifacts.
Print the response in case MinIO is telling us why.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Rohan Garg <rohan.garg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6101>

freedreno: Add trace for CP_DRAW_INDIRECT_MULTI

Test the indirect count case. This is recorded with turnip.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6104>

freedreno/cffdec: Handle CP_DRAW_INDIRECT_MULTI like other draws

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6104>

freedreno/rnn: Support stripes in rnndec_decodereg

We'll need this for finding where INDIRECT/STRIDE are in
CP_DRAW_INDIRECT_MULTI, since they are in different locations in each
variant.

This is tricky because we need to bubble up success/failure to the upper
levels, and 0 could be a valid offset if the stripe is inside an array
or in a packet. Hence we refactor tryreg to return success/failure
separately, although I stopped short of modifying rnndec_decodereg
itself.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6104>

tu: Dump CP_DRAW_INDIRECT_MULTI draw BO's

These will be decoded by cffdump.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6104>

bifrost: Fix packing of ADD_FEXP2_FAST

This was being packed as 1-src and so the Src1 was not set up properly.
It only worked by accident.

Signed-off-by: Chris Forbes <chrisforbes@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6111>

bifrost: Honor src swizzle in special math ops

Most ops use the common handling in emit_alu in order to convert NIR
sources to bifrost sources, but the "special" math op lowering handrolls
the conversion (due to needing to reference the same source multiple
times).

Unfortunately, that handrolled lowering did not consider that there
might be a non-identity swizzle on the source. In this case we would
reference the wrong component of the source and generate garbage.

Fixes all but two of the remaining failures on G31 in:
  dEQP-GLES2.functional.shaders.operator.exponential.*highp*

The following tests are still broken due to some other issue:
  dEQP-GLES2.functional.shaders.operator.exponential.exp2.highp_float_fragment
  dEQP-GLES2.functional.shaders.operator.exponential.exp2.highp_vec2_fragment

Signed-off-by: Chris Forbes <chrisforbes@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6108>

prevent multiply defined symbols

Without this patch applied gcc@10.1.0 fails to compile with the following
error (note mesa@18.3.6 but the latest release also posseses this problem):

  ld: ../../../../src/gallium/auxiliary/.libs/libgallium.a(u_debug_symbol.o):/tmp/spack/spack-stage/spack-stage-mesa-18.3.6-be7kyg2dyxwktir3zrai27n6a6coadab/spack-src/src/galli um/auxiliary/util/u_debug_symbol.c:273: multiple definition of `symbols_hash'; ../../../../src/gallium/auxiliary/.libs/libgallium.a(u_debug_stack.o):/tmp/spa ck/spack-stage/spack-stage-mesa-18.3.6-be7kyg2dyxwktir3zrai27n6a6coadab/spack-src/src/gallium/auxiliary/util/u_debug_stack.c:49: first defined here
  collect2: error: ld returned 1 exit status
  make[4]: *** [libGL.la] Error 1
  make[4]: Leaving directory `/tmp/spack/spack-stage/spack-stage-mesa-18.3.6-be7kyg2dyxwktir3zrai27n6a6coadab/spack-src/src/gallium/targets/libgl-xlib'
  make[3]: *** [all-recursive] Error 1
  make[3]: Leaving directory `/tmp/spack/spack-stage/spack-stage-mesa-18.3.6-be7kyg2dyxwktir3zrai27n6a6coadab/spack-src/src/gallium'
  make[2]: *** [all-recursive] Error 1
  make[2]: Leaving directory `/tmp/spack/spack-stage/spack-stage-mesa-18.3.6-be7kyg2dyxwktir3zrai27n6a6coadab/spack-src/src'
  make[1]: *** [all] Error 2
  make[1]: Leaving directory `/tmp/spack/spack-stage/spack-stage-mesa-18.3.6-be7kyg2dyxwktir3zrai27n6a6coadab/spack-src/src'
  make: *** [all-recursive] Error 1

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3298
Cc: mesa-stable
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6053>

amd: enable displayable DCC for everything newer than Navi1x

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6100>

amd: add support for Navy Flounder

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6100>

amd: rename SIENNA -> SIENNA_CICHLID

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6100>

aco: create acq+rel barriers instead of acq/rel

NIR doesn't have atomic loads/stores, so we have to workaround that with
this for dEQP-VK.memory_model.* to pass.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4905>

aco: improve workgroup-scope and lower vmem/smem barriers

No fossil-db changes on Navi.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4905>

aco: improve sync_info for TCS output stores

Stop scheduling them as SSBO stores.

No fossil-db changes on Navi.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4905>

aco: use storage_scratch

fossil-db (Navi):
Totals from 9 (0.01% of 114665) affected shaders:
VMEM: 14456 -> 15312 (+5.92%)
VClause: 336 -> 327 (-2.68%)

Helps 9 Dark Souls 3 shaders a little.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4905>

aco: enable value numbering of s_buffer_load_*

fossil-db (Navi):
Totals from 33 (0.03% of 114665) affected shaders:
SGPRs: 2176 -> 2152 (-1.10%)
VGPRs: 1572 -> 1564 (-0.51%)
CodeSize: 115988 -> 115472 (-0.44%)
Instrs: 21459 -> 21385 (-0.34%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4905>

nir,radv/aco: add and use pass to lower make available/visible barriers

Lower them to ACCESS_COHERENT to simplify the backend and
probably give better performance than invalidating or writing back the
entire L0/L1 cache.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4905>

aco: consider intrinsic access in visit_{load,store}_image

radv_nir_lower_memory_model will use this.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4905>

radv/aco,aco: use scoped barriers

fossil-db (Navi):
Totals from 109 (0.08% of 132058) affected shaders:
SGPRs: 5416 -> 5424 (+0.15%)
CodeSize: 460500 -> 460508 (+0.00%); split: -0.07%, +0.07%
Instrs: 87278 -> 87272 (-0.01%); split: -0.09%, +0.09%
Cycles: 2241996 -> 2241852 (-0.01%); split: -0.04%, +0.04%
VMEM: 33868 -> 35539 (+4.93%); split: +5.14%, -0.20%
SMEM: 7183 -> 7184 (+0.01%); split: +0.36%, -0.35%
VClause: 1857 -> 1882 (+1.35%)
SClause: 2052 -> 2055 (+0.15%); split: -0.05%, +0.19%
Copies: 6377 -> 6380 (+0.05%); split: -0.02%, +0.06%
PreSGPRs: 3391 -> 3392 (+0.03%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4905>

aco: rework barriers and replace can_reorder

fossil-db (Navi):
Totals from 273 (0.21% of 132058) affected shaders:
CodeSize: 937472 -> 936556 (-0.10%)
Instrs: 158874 -> 158648 (-0.14%)
Cycles: 13563516 -> 13562612 (-0.01%)
VMEM: 85246 -> 85244 (-0.00%)
SMEM: 21407 -> 21310 (-0.45%); split: +0.05%, -0.50%
VClause: 9321 -> 9317 (-0.04%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4905>

aco: add missing add_to_hazard_query

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4905>

bifrost: Add support for nir_op_iabs

Signed-off-by: Chris Forbes <chrisforbes@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6098>

anv: fix descriptor set free

Once we start going through the free list of the descriptor set pool,
we might use a free entry larger than the descriptor set we want to
allocate. When we free that descriptor set, we use the size of the set
rather than the size of the entry that was picked. This leads to leaks
of some amount of descriptor set pool.

This fix saves the size of the entry in the descriptor set so we know
what amount of the pool needs to freed.

v2: Don't bother adding a new size field

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Cc: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3324
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6084>

nine: fix incorrect calculation of layer count for 3D textures

Volume textures don't have a concept of "layers"

v1: set last_layer to zero for 3D textures (Axel Davy)

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Axel Davy <davyaxel0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5808>

panfrost: Allow PIPE_TEXTURE_1D_ARRAY textures

Fixes a crash with wined3d.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6085>

i965: propagate error from gen_perf_begin_query to glBeginPerfQueryINTEL

Otherwise mesa will crash in glEndPerfQueryINTEL because OA BO is NULL.

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6094>

iris: propagate error from gen_perf_begin_query to glBeginPerfQueryINTEL

Otherwise mesa will crash in glEndPerfQueryINTEL because OA BO is NULL.

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6094>

freedreno/rnn: Return success when parsing addvariant

This was missed when I initially added addvariant.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6070>

freedreno/ci: add a2xx trace to CI job

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6070>

freedreno: deduplicate a2xx disasm

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6070>

freedreno: move a2xx disasm out of gallium

So that it can be reused by the decode tools.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6070>

freedreno: deduplicate a3xx+ disasm

Merge the extra tracking that is useful for generating stats from asm
(as opposed to ir), and for guestimating things like inputs and outputs
(mostly useful for r/e) into ir3's version and drop cffdec's version.

There is a small change in disasm output for the decode tools, in that
it no longer prints the used consts, but rather just the max accessed
const.  This is the more useful piece of information, and avoids making
the shared regmask type big enough to deal with the const reg file.
Additional error checking for invalid regids causes crashdec to bail
out sooner when decoding memory that *might* hold valid instructions.
Also, crashdec no longer prints stats, because stats aren't very useful
when trying to decode random instruction memory (which might or might
not be valid instructions).

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6070>

freedreno: drop shader_t

When this code was outside of the mesa tree, we needed our own enum.
Now we can use a common one, to simplify deduplicating the disasm
code.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6070>

freedreno/ir3: split out regmask

To unify the ir3 disasm code, we need to add in the regmask based
register tracking from cffdec's version of the disassembler.  Split
out regmask (or at least the part that doesn't depend on ir3) so
it can be shared.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6070>

freedreno: add CI for envytools tools

This also tunes `.freedreno-rules` a bit so that it isn't triggered by
various tools that don't effect the driver build.

The .gitlab-ci directory is kept separate from the toplevel one so that
updates to (for example) reference decode output do not trigger all the
other-driver jobs to run.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6070>

freedreno/afuc: warnings cleanup

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6070>

freedreno/decode: warnings cleanup

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6070>

freedreno/rnn: warnings cleanup

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6070>

freedreno: slurp in afuc

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6070>

freedreno: slurp in decode tools

cffdump, crashdec, etc

At this point there is some duplication with other files in-tree (ie.
a2xx and a3xx+ disassembly), which will be cleaned up in a later commit.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6070>

freedreno: slurp in rnn

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6070>

freedreno: slurp in rnndb

Pull in all of $envytools/rnndb (including display, etc) from envytools
commit 6ccdda33ac4d88e19d2a70e1b4edaaab5ec4b026

This changes the directory structure to match the organization in the
envytools tree.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6070>

freedreno: make gen_header.py check parent directory

With the next commit, the xml files will be no longer be all in the same
directory.  But checking up a single directory level to resolve import
will be sufficient.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6070>

radv: Fix host->host signalling with legacy timeline semaphores.

Fixes: 88d41367b8a "radv: Add timelines with a VK_KHR_timeline_semaphore impl."
Reviewed-by: Dave Airlie <airlied@redhat.com>
Tested-by: Andres Rodriguez <andresx7@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6097>

radv: cleanup locking around timeline waiting.

Just noticed in passing that this looked extra complicated,
Bas said it was for legacy design reasons, so clean it up.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6099>

bifrost: Add support for nir_op_imul

Unfortunately this doesn't map nicely to the existing instruction
classes, so we'll make a new one for now.

Signed-off-by: Chris Forbes <chrisforbes@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6091>

bifrost: Add support for nir_op_uge

Signed-off-by: Chris Forbes <chrisforbes@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6091>

bifrost: Add support for nir_op_ishl

Bifrost's bitwise ops include the shift capability. Previously we had
hardcoded the shift to zero in all cases.

There's room in future to emit slightly better code if a shift and a
bitwise operation can be folded together, but not going after that for
now.

This change also removes the separate BI_SHIFT instruction class as
BI_BITWISE can cover both cases.

Signed-off-by: Chris Forbes <chrisforbes@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6091>

bifrost: Add support for nir_op_inot

Signed-off-by: Chris Forbes <chrisforbes@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6091>

spirv: Handle most execution modes earlier

For convenience in e68871f6a44 ("spirv: Handle constants and types
before execution modes") we moved all execution mode parsing after the
constants and types, so that those using OpExecutionModeId could be
handled together.

Later in 84781e1f1d8 ("spirv/nir: keep track of SPV_KHR_float_controls
execution modes") we had to parse certain non-ID execution modes
before handling constants.

Instead of handling just the float controls related execution modes
early, handle all modes that don't need an ID.  This is a more
"natural" split and will allow other type handling to rely on
execution mode in the future.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6062>

bifrost: Add lowering for b2i32

Since the bool representation is 0/~0, we can convert to int
just by &1.

Signed-off-by: Chris Forbes <chrisforbes@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6079>

bifrost: Document d3d/gl comparison control bit

Signed-off-by: Chris Forbes <chrisforbes@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6079>

bifrost: Emit "d3d" variant of comparison instructions

The "d3d" variant uses ~0 as the true value. This is consistent
with NIR's nir_lower_bool_to_int32 pass.

Signed-off-by: Chris Forbes <chrisforbes@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6079>

bifrost: Lower x->bool conversions to != 0

Signed-off-by: Chris Forbes <chrisforbes@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6079>

tu: Enable resource dynamic indexing

This has actually worked since bindless support was merged.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6086>

ir3: Fix incorrect src flags for samp_tex

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6086>

ir3: Remove redundant samp_tex validation

It's already checked in ir3_validate. This way we don't have to fix it
up for bindless.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6086>

ir3: Validate bindless samp_tex correctly

It's full instead of half precision, because the maximum number of
textures/samplers is much larger.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6086>

tu: Fix descriptor update templates with input attachments

Found via
dEQP-VK.binding_model.descriptorset_random.sets4.noarray.ubolimitlow.sbolimitlow.sampledimglow.outimgonly.noiub.nouab.frag.ialimitlow.0

Fixes: 159a1300ceb ("turnip: input attachment descriptor set rework")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6087>

turnip: fix SP_HS_UNKNOWN_A831 value for A650

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5765>

turnip: use patchControlPoints for HS_INPUT_SIZE value

It should be calculated from patchControlPoints, not tcs_vertices_out.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5765>

turnip: move WFI out of draw state to fix a650 hangs

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5765>

freedreno/ir3: fix wrong local_primitive_id_start type

When changing the patch to use an offset instead of a bool, the type was
accidentally left as bool.

Fixes: f472c9844309 ("freedreno/ir3: add support for a650 tess shared storage")

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5765>

vulkan/wsi: Convert usage of -1 to UINT32_MAX.

The integers are unsigned so they do the same but this makes it
locally more clear what happened.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6071>

vulkan/wsi/x11: report device-group present rectangles with prime.

dEQP-VK.wsi.xlib.surface.query_devgroup_present_modes with prime
fail when 0 rectangles are reported. While I believe that test
tests this unintentionally (trying to test the VK_INCOMPLETE return),
I believe it makes sense to always return a rectangle.

In particular we require the data from the given rectangle for
presentation even if we use prime and given that prime is completely
transparent for the app it still counts as local from the perspective
as the application.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6071>

radv: call radv_nir_lower_ycbcr_textures after first optimizations

There might still be tex instructions with undef texture/sampler before
the first round of optimizations. No pipelinedb changes.

Fixes: 14a12b771d0a380defacafe5825362af77ff21bd ('spirv: Rework our handling of images and samplers')
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6083>

radv: link with ld_args_build_id

This is needed for radv_device_get_cache_uuid to work correctly.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6081>

v3d/compiler: request fragment shader clip lowering to be vulkan compatible.

Vulkan allows fragment shaders to read gl_ClipDistance[], in which case
the SPIR-V compiler will inject a compact array variable at
VARYING_SLOT_CLIP_DIST0. Request the lowering to always work in terms
of a compact array variable so we don't have to care about the API
in use.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6022>

v3d/compiler: handle compact varyings

We are going to need this in Vulkan because the SPIR-V compiler
defines clip distances as a single compact array of scalars, so
our compiler needs to know what to do with them.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6022>

nir/lower_clip: make the pass compatible with Vulkan semantics

Vulkan allows fragment shaders to read gl_ClipDistance[], in which
case the SPIR-V compiler inserts a single compact array variable for
VARYING_SLOW_CLIP_DIST0 and the lowering should not try to inject
its own variables, but instead work in terms of the existing one.
Vulkan drivers are expected to call this with use_clipdist_array set
to true to be consistent with this setup.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6022>

radv: Fix uninitialized variable in renderpass.

Fixes some dEQP-VK.renderpass2.* flakes. Valgrind:

Test case 'dEQP-VK.renderpass2.dedicated_allocation.attachment.8.724'..
==754520== Conditional jump or move depends on uninitialised value(s)
==754520==    at 0x575B21C: radv_layout_is_htile_compressed (radv_image.c:1690)
==754520==    by 0x572F470: radv_handle_depth_image_transition (radv_cmd_buffer.c:5855)
==754520==    by 0x572F2F2: radv_handle_image_transition (radv_cmd_buffer.c:6123)
==754520==    by 0x572EEC6: radv_handle_subpass_image_transition (radv_cmd_buffer.c:3385)
==754520==    by 0x572A104: radv_cmd_buffer_begin_subpass (radv_cmd_buffer.c:4843)
==754520==    by 0x572A007: radv_CmdBeginRenderPass (radv_cmd_buffer.c:4913)
==754520==    by 0x572A197: radv_CmdBeginRenderPass2 (radv_cmd_buffer.c:4921)

Why false?

A renderloop happens when the same attachment is both used as input
attachment and output (color, ds) attachment in a subpass. Of course
this doesn't happen outside of a renderpass and hence we can initialize
it to false at the start of the renderpass.

Fixes: 66131ceb8bc "radv: Pass through render loop detection to internal layout decisions."
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3074
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6068>

nir/lower_io: assert that offsets are used for shader_in

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6059>

etnaviv: do register setup only once

Register set setup should be done once at backend
initializaion, as ra_set_finalize is O(r^2*c^2).

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5996>

etnaviv: move shader_count to etna_compiler

Also fix data race on making the shader's id.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5996>

etnaviv: introduce struct etna_compiler

This struct will be used to for state saved across compiler
invocations.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5996>

tu: Enable vertex & fragment stores & atomics

Note that there are some extra tess fails, but they're probably
unrelated to the actual feature. There were also some xfails that were
created as part of an earlier attempt to enable the feature which were
fixed in the meantime, so remove them.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5738>

tu: Detect invalid-for-binning renderpass dependencies

This is all that was missing for stores & atomics.

Closes: #3196
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5738>

tu: Fix hangs for DS with no output

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5738>

tu: Fix empty blit scissor case

With vertexPipelineStoresAndAtomics enabled, fixes:
dEQP-VK.tessellation.invariance.one_minus_tess_coord_component.quads_fractional_even_spacing_cw_point_mode
dEQP-VK.tessellation.invariance.tess_coord_component_range.triangles_fractional_even_spacing_ccw_point_mode

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5738>

spirv: Also copy over binding information for atomic counters

I missed this if statement so atomic counters weren't getting bindings
and, when you have more than one of them, that meant they were all
getting combined into one.

Fixes: 3584cb09bc15 "spirv: Give atomic counters their own variable mode"
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6060>