Daniel Schürmann [Tue, 1 Feb 2022 11:21:15 +0000 (12:21 +0100)]
aco: make Preserve_WQM independent from block_kind_uses_discard_if
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14805>
Daniel Schürmann [Mon, 31 Jan 2022 14:11:22 +0000 (15:11 +0100)]
aco: remove block_kind_discard
This case doesn't seem to happen in practice.
No need to micro-optimize it.
This patch merges instruction selection for discard/discard_if.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14805>
Daniel Schürmann [Mon, 31 Jan 2022 13:26:50 +0000 (14:26 +0100)]
aco: emit nir_intrinsic_discard() as p_discard_if()
This simplifies the code and emits a slightly better
sequence in some cases.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14805>
Charles Baker [Mon, 29 Nov 2021 18:25:03 +0000 (07:25 +1300)]
mesa: align constant/uniform uploads to driver expected alignment
This fixed a problem for Zink where uniform buffer alignment varies by
GPU, e.g. 64 bytes for an RTX 2070 SUPER but 256 bytes for a GTX 1070
Ti.
Tested running Superposition on Windows 10 with Nvidia 1070 Ti with
496.13 driver. Without the fix Superposition soft locks on its splash
screen. With the fix Superposition runs through its benchmark.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14674>
Charles Baker [Fri, 21 Jan 2022 07:41:54 +0000 (20:41 +1300)]
zink: Fix MSVC RTC in zink_get_framebuffer_imageless()
The bit fields in zink_framebuffer_state cause a false positive with
MSVC's run-time checks enabled. setting state.num_attachments in
zink_get_framebuffer_imageless(). Writing some bits of num_attachments
involves reading bits from layers and samples that haven't been
initialized.
Fixed by assigning to num_attachments earlier in the function. Not
quite sure why that makes a difference but at a guess there's a
heuristic that considers assignment close to declaration as
initialization.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14566>
Mike Blumenkrantz [Fri, 4 Feb 2022 16:16:00 +0000 (11:16 -0500)]
zink: export PIPE_CAP_CULL_DISTANCE_NOCOMBINE
fixes:
KHR-GL46.cull_distance.functional
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14878>
Mike Blumenkrantz [Fri, 4 Feb 2022 16:15:08 +0000 (11:15 -0500)]
gallium: add PIPE_CAP_CULL_DISTANCE_NOCOMBINE
for drivers where separate cull distance variables are required, this
lets them avoid having to write yet another pass to undo gallium's mangling
of shader info
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14878>
Lionel Landwerlin [Fri, 4 Feb 2022 23:49:18 +0000 (01:49 +0200)]
anv: fix conditional render for vkCmdDrawIndirectByteCountEXT
We just forgot about conditional render for this entry point.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
2be89cbd826f9a ("anv: Implement vkCmdDrawIndirectByteCountEXT")
Tested-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14891>
Lionel Landwerlin [Tue, 8 Jun 2021 13:24:54 +0000 (16:24 +0300)]
anv: enable ray queries
Only on platforms that support it.
v3: Split out code setting up ray query shadow buffer (Caio)
Don't forget to setup ray query globals even when no shadow buffer
is used (Lionel)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>
Lionel Landwerlin [Mon, 21 Jun 2021 10:44:53 +0000 (13:44 +0300)]
intel/fs: lower ray query intrinsics
v2: Add helper for acceleration->root_node computation (Caio)
v3: Update comment on "done" bit (Caio)
Remove progress bool value for impl function (Caio)
Don't use nir_shader_instructions_pass to search the shader (Caio)
v4: Rename variable for if/else block (Caio)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>
Lionel Landwerlin [Tue, 11 Jan 2022 09:31:07 +0000 (11:31 +0200)]
intel/nir: document RT builder
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>
Lionel Landwerlin [Thu, 7 Oct 2021 13:25:21 +0000 (16:25 +0300)]
nir/lower_shader_calls: consider relocated constants as rematerializable
After all they're constants.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>
Lionel Landwerlin [Mon, 8 Nov 2021 13:00:46 +0000 (15:00 +0200)]
intel/nir/rt: add more helpers for ray queries
v2: Split stack_id helper in sync/async version (Caio)
Fixup a few bit field mistake (Caio)
Simplify some bitfield manipulations (Caio)
v3: Remove duplicated helper (Caio)
Simplify brw_nir_rt_set_dword_bit_at (Caio)
Comment brw_nir_rt_query_mark_init (Lionel)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>
Lionel Landwerlin [Mon, 8 Nov 2021 12:49:52 +0000 (14:49 +0200)]
intel/nir/rt: make RT manipulation helpers helper invocations ready
Since we need to be able to perform ray queries in helper invocations,
we need to have all the helpers properly tag their load/store
operations so that they operate in helper lanes.
v2: Switch from macros to inline functions (Caio)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>
Lionel Landwerlin [Mon, 8 Nov 2021 10:38:15 +0000 (12:38 +0200)]
intel/nir: document committed argument
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>
Lionel Landwerlin [Wed, 6 Oct 2021 09:19:08 +0000 (12:19 +0300)]
intel/fs: make trivial shader complete tracing operations with missing shaders
v2: Apply workaround only on < DG2-512-C0 & < DG2-128-B0
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>
Lionel Landwerlin [Mon, 8 Nov 2021 13:34:16 +0000 (15:34 +0200)]
intel/nir/rt: load bvh_level value off mem_hit structure
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>
Lionel Landwerlin [Wed, 6 Oct 2021 09:15:59 +0000 (12:15 +0300)]
intel: add a new intrinsic to get the shader stage from bindless shaders
We'll use this to apply ray tracing operations in our trivial return
shader based on the stage we're in.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>
Lionel Landwerlin [Fri, 22 Oct 2021 13:10:20 +0000 (16:10 +0300)]
nir/builder: add nir_ior_imm() helper
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>
Lionel Landwerlin [Mon, 14 Jun 2021 14:30:31 +0000 (17:30 +0300)]
intel/nir: use a single intel intrinsic to deal with ray traversal
In the future we'll want to reuse this intrinsic to deal with ray
queries. Ray queries will use a different global pointer and
programmatically change the control/level arguments of the trace send
instruction.
v2: Comment on barrier after sync trace instruction (Caio)
Generalize lsc helper (Caio)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>
Lionel Landwerlin [Tue, 18 Jan 2022 08:05:22 +0000 (10:05 +0200)]
intel/nir: fix shader call lowering
We're replacing a generic instruction by an intel specific one, we
need to remove the previous instruction.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
c5a42e401036 ("intel/fs: fix shader call lowering pass")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>
Lionel Landwerlin [Fri, 2 Jul 2021 09:47:38 +0000 (12:47 +0300)]
intel/fs: limit FS dispatch to SIMD16 when using ray queries
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>
Lionel Landwerlin [Tue, 26 Oct 2021 13:39:08 +0000 (16:39 +0300)]
intel/compiler: tracker number of ray queries in prog_data
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>
Lionel Landwerlin [Mon, 14 Jun 2021 19:25:38 +0000 (22:25 +0300)]
intel/fs: load more fields from BVH instance leafs
v2: Fixup mask (Caio)
Drop old comment (Caio)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>
Lionel Landwerlin [Thu, 3 Feb 2022 09:33:26 +0000 (11:33 +0200)]
intel/fs: don't set allow_sample_mask for CS intrinsics
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
77486db867bd ("intel/fs: Disable sample mask predication for scratch stores")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>
Lionel Landwerlin [Fri, 29 Oct 2021 15:07:51 +0000 (18:07 +0300)]
intel/fs: add support for ACCESS_ENABLE_HELPER
v2: Factor out fragment shader masking on send messages (Caio)
Update comments (Caio)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>
Lionel Landwerlin [Thu, 28 Oct 2021 09:05:16 +0000 (12:05 +0300)]
intel/fs: name sources for A64 opcodes
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>
Lionel Landwerlin [Mon, 21 Jun 2021 10:56:32 +0000 (13:56 +0300)]
intel/nir/rt: add a new number of SIMD lanes per DSS helper
v2: Add prefix brw_nir_rt (Caio)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>
Lionel Landwerlin [Fri, 18 Jun 2021 11:12:03 +0000 (14:12 +0300)]
intel/fs: add support for Eu/Thread/Lane id
This index will be used for accessing ray query data in memory.
v2: Drop a MOV (Caio)
v3: Rework back code emission (Caio)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>
Lionel Landwerlin [Fri, 18 Jun 2021 11:10:06 +0000 (14:10 +0300)]
intel/fs: rework dss_id opcode into generic opcode
We'll want different types of IDs based on topology. Let's make this
more flexible and also move the bit shifting code a layer above where
it's easier to do bitshifting operations, especially if you need to
stash things into temporary registers.
v2: Keep previous comment.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>
Lionel Landwerlin [Fri, 18 Jun 2021 08:52:31 +0000 (11:52 +0300)]
nir: change intel dss_id intrinsic to topology_id
This will allow to reuse the same intrinsic for various topology based
ID.
v2: fix intrinsic comment (Caio)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>
Lionel Landwerlin [Mon, 7 Feb 2022 20:33:55 +0000 (22:33 +0200)]
intel/ds: fix compilation with perfetto
Forgot to test with perfetto...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
9da3d714b87c ("anv: add dynamic rendering traces")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5992
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Tested-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14914>
Dylan Baker [Fri, 4 Feb 2022 18:47:17 +0000 (10:47 -0800)]
meson: add radv to meson devenv
I either rebased this out of the original PR, just failed to commit it
and then reset it.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14879>
Mike Blumenkrantz [Wed, 26 Jan 2022 20:14:43 +0000 (15:14 -0500)]
vk/sync: add asserts for timeline semaphore count matching
spec requires that the number of timeline waits/signals matches the
base number of waits/signals if there are any timeline semaphores
being processed by the submit, so asserting here is in line with what
validation will yield
failure to match these will also hang every driver I've tested, so asserting
here potentially saves some people their desktop session
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14741>
Mike Blumenkrantz [Thu, 3 Feb 2022 14:51:52 +0000 (09:51 -0500)]
zink: min/max blit region in coverage functions
these regions might not have the coords in the correct order, which will
cause them to fail intersection tests, resulting in clears that are never
applied
cc: mesa-stable
fixes:
GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_all_buffer_blit
GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_color_and_depth_blit
GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_color_and_stencil_blit
GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_linear_filter_color_blit
GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_magnifying_blit
GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_minifying_blit
GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_missing_buffers_blit
GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_nearest_filter_color_blit
GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_negative_dimensions_blit
GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_negative_height_blit
GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_negative_width_blit
GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_scissor_blit
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14867>
Mike Blumenkrantz [Tue, 1 Feb 2022 15:41:35 +0000 (10:41 -0500)]
zink: reject invalid draws
cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14859>
Mike Blumenkrantz [Mon, 31 Jan 2022 15:43:54 +0000 (10:43 -0500)]
zink: fix PIPE_CAP_TGSI_BALLOT export conditional
this requires VK_EXT_shader_subgroup_ballot
cc: mesa-stable
fixes (lavapipe):
KHR-GL46.shader_ballot_tests.ShaderBallotAvailability
KHR-GL46.shader_ballot_tests.ShaderBallotFunctionRead
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14858>
Mike Blumenkrantz [Fri, 28 Jan 2022 20:52:18 +0000 (15:52 -0500)]
zink: export PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
this is supported and has been for a while
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14858>
Pierre-Eric Pelloux-Prayer [Wed, 19 Jan 2022 10:38:28 +0000 (11:38 +0100)]
radeonsi/blit: relax conditions to use sdma copy for prime buffers
We don't need to check if it's imported: PIPE_BIND_DRI_PRIME is enough.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14615>
Pierre-Eric Pelloux-Prayer [Wed, 19 Jan 2022 10:36:45 +0000 (11:36 +0100)]
radeonsi: create prime buffers as uncached
8791e831b11 marked imported prime buffers as uncached (useful when prime
buffer is allocated by the display GPU), but they should also be created
as uncached (useful when allocated by the render GPU).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14615>
Pierre-Eric Pelloux-Prayer [Tue, 1 Feb 2022 16:40:55 +0000 (17:40 +0100)]
gallium: rename PIPE_BIND_DRI_PRIME
The new name PIPE_BIND_PRIME_BLIT_DST is more precise.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14615>
Pierre-Eric Pelloux-Prayer [Wed, 19 Jan 2022 10:32:22 +0000 (11:32 +0100)]
gallium/dri: add missing PIPE_BIND_DRI_PRIME handling
e9c3dbd0461 added PIPE_BIND_DRI_PRIME but it was only set when
importing a prime buffer.
This commit adds handling of this flag in the other codepath = the
one where the prime buffer is allocated by the render GPU.
With this change PIPE_BIND_DRI_PRIME is still only set for the
render GPU - the display GPU will never see this flag; a future
commit will rename it.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14615>
Kenneth Graunke [Mon, 7 Feb 2022 21:33:40 +0000 (13:33 -0800)]
ci/iris: Mark qbo tests as flakes
These appear to have some kind of race condition and usually fail,
but sometimes pass. We had already attempted to mark them as flakes
on amly, but need to mark them as flakes on KBL+ too.
See https://gitlab.freedesktop.org/mesa/mesa/-/jobs/
18522605 and
https://gitlab.freedesktop.org/mesa/mesa/-/jobs/
18527737 where these
unexpectedly passed on KBL, and also where the top-level test not
being caught by the regex led to failures.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14916>
Zoltán Böszörményi [Sat, 5 Feb 2022 06:47:44 +0000 (07:47 +0100)]
crocus: Enable compat profile the same way as core profile
Signed-off-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11756>
Kenneth Graunke [Fri, 4 Sep 2020 23:16:48 +0000 (16:16 -0700)]
iris: Add support for flushing the blitter (hackily)
To flush the blitter, we need to use MI_FLUSH_DW rather than the usual
PIPE_CONTROL we use on the 3D engine. Most of our code is set up to
suggest flushes via PIPE_CONTROL commands, however, so we hackily just
emit MI_FLUSH_DW when they ask for any kind of PIPE_CONTROL flush.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14912>
Kenneth Graunke [Thu, 3 Feb 2022 04:15:47 +0000 (20:15 -0800)]
blorp: Assert that blorp_copy() on the blitter can handle it
Safeguards against callers that don't guarantee the necessary things.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14912>
Kenneth Graunke [Mon, 24 Jan 2022 21:10:34 +0000 (13:10 -0800)]
intel/genxml: Add missing MI_FLUSH_DW::Flush CCS field
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14912>
Rhys Perry [Fri, 4 Feb 2022 19:02:54 +0000 (19:02 +0000)]
radv: fix R_02881C_PA_CL_VS_OUT_CNTL with mixed cull/clip distances
Matches radeonsi.
Seems Vulkan CTS doesn't really test cull distances. Removing
VARYING_SLOT_CULL_DIST0/VARYING_SLOT_CULL_DIST1 variables doesn't break
any of dEQP-VK.clipping.*, except for tests which read the variables in
the fragment shader.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5984
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14882>
Danylo Piliaiev [Wed, 27 Oct 2021 16:23:19 +0000 (19:23 +0300)]
tu: Implement VK_AMD_buffer_marker to support Graphics Flight Recorder
Graphics Flight Recorder is:
"The Graphics Flight Recorder (GFR) is a Vulkan layer to help
trackdown and identify the cause of GPU hangs and crashes.
It works by instrumenting command buffers with completion tags."
This is a nice little tool which could help quickly identify the call
which hanged. Or if command buffer is executed for too long.
The tiling nature of our GPU shouldn't be a big issue aside from
lower performance.
For non-segfault case, if:
- Hang happens at the same place in cmdbuf and draw/dispatch is not
finished at that point - it is likely that there is an infinite
loop in some of the shaders in this draw.
- Hang happens always in different place - likely there is nothing
wrong and command buffer just takes too long to execute and you
should try increasing hangcheck_period_ms. If it doesn't help
it is likely a synchronization issue.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13553>
Daniel Stone [Fri, 4 Feb 2022 18:17:51 +0000 (18:17 +0000)]
egl/wayland: Don't replace existing backbuffer in get_buffers
If the surface already has a current backbuffer - say through a
buffer_age query - we do not want to replace it in get_buffers, because
it means the result we'd previously returned them is stale.
If we already have a backbuffer set on the surface, keep it locked in no
matter what until we hit SwapBuffers.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14873>
Daniel Stone [Fri, 4 Feb 2022 10:42:19 +0000 (10:42 +0000)]
egl/wayland: Reset buffer age when destroying buffers
A buffer age of 0 means that the buffer is uninitialised or has unknown
content. We rely on the buffer age initially being 0 through zalloc when
the surface is first created; when they are first used for a swap, we
set their age to 1, and then we increment the age of every buffer in the
chain with a non-zero age when we swap.
Now that we can release buffers, both through dmabuf-feedback as well as
detecting when we're using a deeper swapchain than the compositor needs,
make sure to reset their age as they are released. Without doing this,
the age will stay as it was before it was released and be incremented,
returning the wrong age to the user the first time a previously-released
buffer slot has been reused.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5977
Fixes:
22d796feb828 ("egl/wayland: break double/tripple buffering feedback loops")
Fixes:
b5848b2dac14 ("egl/wayland: use surface dma-buf feedback to allocate surface buffers")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14873>
Emma Anholt [Mon, 7 Feb 2022 03:53:45 +0000 (19:53 -0800)]
ci/iris: Add skips and flakes notes for recent #intel-ci logs.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14904>
Emma Anholt [Mon, 7 Feb 2022 03:49:12 +0000 (19:49 -0800)]
ci/crocus: Add recent flakes from #intel-ci
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14904>
Emma Anholt [Mon, 7 Feb 2022 03:16:09 +0000 (19:16 -0800)]
ci/softpipe,llvmpipe: Disable Xvfb server reset on piglit runs.
The resets take time that we don't need to spend.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14904>
Samuel Pitoiset [Wed, 19 Jan 2022 15:19:11 +0000 (16:19 +0100)]
Revert "radv: re-apply "Do not access set layout during vkCmdBindDescriptorSets.""
The most famous RADV revert over the past months. This was an issue
in RADV and not an use-after-free (descriptor set layouts can be
destroyed almost at any time).
This reverts commit
b775aaff1ec86f4ebd50867a045695da1fbeb2e1.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14621>
Samuel Pitoiset [Wed, 19 Jan 2022 15:15:33 +0000 (16:15 +0100)]
radv: add reference counting for descriptor set layouts
The spec states that descriptor set layouts can be destroyed almost
at any time:
"VkDescriptorSetLayout objects may be accessed by commands that
operate on descriptor sets allocated using that layout, and those
descriptor sets must not be updated with vkUpdateDescriptorSets
after the descriptor set layout has been destroyed. Otherwise,
descriptor set layouts can be destroyed any time they are not in
use by an API command."
Based on ANV.
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5893
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14621>
Dave Airlie [Mon, 7 Feb 2022 06:19:15 +0000 (16:19 +1000)]
crocus: find correct relocation target for the bo.
If we have batch a + b, and writing to batch b, causes batch a
to flush, all the bo->index get reset, and we try to submit a -1
to the kernel.
Look the bo index up when creating relocations.
Fixes crash seen in KHR-GL46.compute_shader.pipeline-post-fs
and a trace from Wasteland 3
Fixes:
f3630548f1da ("crocus: initial gallium driver for Intel gfx 4-7")
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14905>
Zoltán Böszörményi [Sat, 5 Feb 2022 05:23:46 +0000 (06:23 +0100)]
crocus: enable GL46 tests for HSW in ci
Signed-off-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14889>
Alyssa Rosenzweig [Sun, 6 Feb 2022 20:44:35 +0000 (15:44 -0500)]
asahi: Fix memory unsafety in delete_sampler_state
The type is wrong, masked by a void*, meaning the free is completely
wrong. ASan is rightfully unhappy. Fixes crashes destroying the context.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14901>
Alyssa Rosenzweig [Sun, 6 Feb 2022 14:43:48 +0000 (09:43 -0500)]
agx: Don't kill helper threads in ld_var
Apparently this is yet another .kill bit. Fixes:
dEQP-GLES3.functional.shaders.derivate.dfdx.linear.*
dEQP-GLES3.functional.shaders.derivate.dfdy.linear.*
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14899>
Alyssa Rosenzweig [Tue, 18 Jan 2022 19:14:55 +0000 (14:14 -0500)]
agx: Handle texture array indices
These need to be converted to integers.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14899>
Alyssa Rosenzweig [Tue, 18 Jan 2022 14:48:36 +0000 (09:48 -0500)]
agx: Implement nir_op_txb
Like explicit LODs, biases must be 16-bit, so add a lowering rule for
this. With the LOD mode selection updated for txb, we can then ingest
biases like explicit LODs and allowlist txb. Passes:
dEQP-GLES2.functional.shaders.texture_functions.fragment.texture2d_bias
dEQP-GLES2.functional.texture.mipmap.2d.bias.*
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14899>
Alyssa Rosenzweig [Tue, 18 Jan 2022 14:48:13 +0000 (09:48 -0500)]
agx: Translate LOD modes more generically
Now includes support for auto_load_bias mode.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14899>
Alyssa Rosenzweig [Tue, 18 Jan 2022 14:47:44 +0000 (09:47 -0500)]
agx: Add AUTO_LOD_BIAS mode
Automatic load with a bias.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14899>
Alyssa Rosenzweig [Wed, 19 Jan 2022 01:07:12 +0000 (20:07 -0500)]
asahi: Correctly set IOGPU_ATTACHMENT::size
Not sure what this is used for, but let's not lie to the kernel.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14898>
Alyssa Rosenzweig [Wed, 19 Jan 2022 00:58:21 +0000 (19:58 -0500)]
asahi: Identify IOGPU_ATTACHMENT::size
Oops.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14898>
Charmaine Lee [Wed, 2 Feb 2022 23:12:12 +0000 (15:12 -0800)]
mesa: fix misaligned pointer returned by dlist_alloc
In cases where the to-be-allocated node size with padding exceeds BLOCK_SIZE
but without padding doesn't, a new block is not created and no padding is done
to the previous instruction, causing a misaligned pointer to be returned.
v2: Per Ilia Mirkin's suggestion, remove the extra condition in the first
if statement, let it unconditionally pad the last instruction if needed.
The updated currentPos will then be taken into account in the
block size checking.
This fixes crash seen with lightsmark and Optuma apitraces
Fixes:
05605d7f537c4 (' mesa: remove display list OPCODE_NOP')
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Tested-by: Neha Bhende <bhenden@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14871>
Neha Bhende [Thu, 3 Feb 2022 22:48:09 +0000 (14:48 -0800)]
svga: store shared_mem_size in svga_compute_shader instead of svga_context
When new context was created, shared_mem_size was getting overwritten.
This fixes glretrace failure seen with manhattan, aztec and BASS2_intro
apitraces
Fixes:
247c61f2d0454a ('svga: Add support for compute shader, shader buffers and image views')
Tested with glretrace, piglit
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
(cherry picked from commit
dd6793ec9218782b1b716a87582d7219bae4e75f)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14870>
Kenneth Graunke [Fri, 4 Feb 2022 09:13:52 +0000 (01:13 -0800)]
anv: Increase maxUniformBufferRange to 2^30 when not using the sampler
The limit here is from the RENDER_SURFACE_STATE height/width/depth
fields - it's 2^30 for ISL_FORMAT_RAW buffers, and 2^27 otherwise.
anv_isl_format_for_descriptor_type() uses ISL_FORMAT_R32G32B32A32_FLOAT
for uniform buffers when compiler->indirect_ubos_use_sampler is set
(Icelake and earlier), but ISL_FORMAT_RAW when it isn't (Tigerlake+).
So we can increase the limit on Tigerlake and later.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14892>
Pavel Ondračka [Fri, 21 Jan 2022 13:08:33 +0000 (14:08 +0100)]
r300: fix deadcode elimination in loops with breaks
We are updating the deadcode state while walking the program backwards.
When encountering ENDLOOP, we scan the loop, mark everything in the loop
as used and than continue as usuall. We were previously trying to be
smart with the breaks. This was however not working as expected.
Instead, save the most pesimistic deadcode state from the ENDLOOP and
just restore it anytime we see a break.
This keeps the code simple and more importantly does not touch the flat
and IF(-ELSE)-ENDIF paths at all so reduces the chances of regression.
No changes with my shader-db.
Fixes piglits on RV530:
shaders/ssa/fs-if-def-else-break.shader_test
spec/glsl-1.10/execution/vs-loop-array-index-unroll.shader_test
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5832
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14661>
Lionel Landwerlin [Sun, 30 Jan 2022 12:41:00 +0000 (14:41 +0200)]
anv: add dynamic rendering traces
v2: Get rid of subpass_count
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14798>
Lionel Landwerlin [Sun, 30 Jan 2022 12:40:19 +0000 (14:40 +0200)]
anv: flush utrace before at device destroy
Ensuring any remaining traces are displayed.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14798>
Mike Blumenkrantz [Fri, 4 Feb 2022 13:29:28 +0000 (08:29 -0500)]
zink: use scanout obj when returning resource param info
embarrassing typo since the base obj has no modifier data available
cc: mesa-stable
fixes #5980
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14875>
Boris Brezillon [Fri, 4 Jun 2021 12:44:56 +0000 (14:44 +0200)]
pan/midg: Support 8/16 bit load/store
Needed for panvk copy shaders to support 8 or 16bit formats.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14885>
Boris Brezillon [Wed, 9 Jun 2021 08:01:51 +0000 (10:01 +0200)]
pan/midg: Add a pass to lower non-logbase2 global/shared loads
Compute shaders might do vec3(Xbits) loads which are translated
to LD.<next_pow2(3 * X)> by the midgard compiler. This might cause
out-of-bound accesses potentially leading to pagefaults if the
access is at the end of a BO. One solution to avoid that (maybe not
the best) is to split non-log2 loads to make sure we only read what's
requested.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14885>
Boris Brezillon [Thu, 9 Sep 2021 08:38:20 +0000 (10:38 +0200)]
pan/midg: Fix swizzle packing on 64bit instructions with src-expansion + dst-shrinking
In that case, the mask is specified on 32bit lanes, so we need to shift
it if it's > 0x3. The expand modifier will take care of selecting the
right side of the 32bit vector.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14885>
Boris Brezillon [Thu, 9 Sep 2021 08:36:03 +0000 (10:36 +0200)]
pan/midg: Fix the upper/lower limit on 8bit vectors
If I'm correct, the lower/upper split on 8bit vectors is 8, not 4.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14885>
Boris Brezillon [Thu, 9 Sep 2021 08:31:18 +0000 (10:31 +0200)]
pan/midg: Fix 64-bit swizzle printer
Swizzling happens in 2 steps on Midgard:
1. Vector expansion/shuffling
2. Swizzling at the instruction-size granularity, but defined using
the source size. Those size are different if the source is expanded.
So, when we print 64 bit swizzles on an expanded source, we first need
to apply an offset if the high part of the 32bit vector was selected,
and then divide the result by 2 to account for vector expansion.
To sum-up, swizzling on midgard is complicated, and I'm not sure I got
it right, but it seems to print what I expect on the few compute
shaders using 64bit arithmetic I debugged.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14885>
Boris Brezillon [Mon, 6 Sep 2021 10:52:17 +0000 (12:52 +0200)]
pan/midg: Fix swizzling on 8-bit sources
Even though 8-bit ALUs are not supported, we can have [un]pack_32_4x8
instructions which translate to IMOVs, and those operate on 8-bit
vectors. The problem is, the swizzling granularity is 16 bit, which
means we don't support
MOV.i8 R0.xyzw, TMP0.xxxx, R1.zyxw
and the compiler doesn't even complain, it just applies 8 bit
swizzling directly, which obviously doesn't work.
This is probably not the right way to fix that, but I thought I'd
raised the issue with a hack to fix, so we can get the discussion
started.
(Found while debugging FB store lowering on Midgard).
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14885>
Boris Brezillon [Mon, 6 Sep 2021 11:05:00 +0000 (13:05 +0200)]
pan/midg: Prefix scalar immediates with '#' instead of '<'
We already do that for scalar instructions, so let's do it for
vector instructions with a single component too.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14885>
Boris Brezillon [Fri, 3 Sep 2021 08:20:56 +0000 (10:20 +0200)]
pan/midg: Remove spurious printf() in print_vector_constants()
Also tried to replace that one by an fprintf(fp, ...), but it pollutes
the dump too.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14885>
Boris Brezillon [Mon, 6 Sep 2021 09:49:10 +0000 (11:49 +0200)]
pan/midg: Add intra-bundle interferences
The register allocator assumes instructions are executed sequentially
and allows one instruction to overwrite a portion of a register written
by a previous instruction if this portion is never used. But scalar and
vector ALUs might be executed in parallel if they are part of the same
bundle, and when such instructions write to the same portion of the
register file, the result is undefined.
Let's add intra-bundle interferences to avoid this situation.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14885>
Danylo Piliaiev [Thu, 3 Feb 2022 16:07:21 +0000 (18:07 +0200)]
turnip: Unconditionaly remove descriptor set from pool's list on free
We didn't remove desc set from the pool's list if pool was
host_memory_base. On the other hand in there is no point in removing
desc set from the list in DestroyDescriptorPool/ResetDescriptorPool.
Fixes:
da7a4751
("turnip: Drop references to layout of all sets on pool reset/destruction")
Fixes cts tests:
dEQP-VK.api.buffer_marker.graphics.default_mem.bottom_of_pipe.memory_dep.draw
dEQP-VK.api.buffer_marker.graphics.default_mem.bottom_of_pipe.memory_dep.dispatch
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14855>
Jesse Natalie [Fri, 4 Feb 2022 19:24:05 +0000 (11:24 -0800)]
docs: Update d3d12 features
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14881>
Jesse Natalie [Fri, 4 Feb 2022 02:05:49 +0000 (18:05 -0800)]
d3d12: GL4.2
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14881>
Jesse Natalie [Fri, 4 Feb 2022 16:33:38 +0000 (08:33 -0800)]
d3d12: Allow RGB VS inputs without an alpha channel
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14881>
Jesse Natalie [Fri, 4 Feb 2022 16:24:02 +0000 (08:24 -0800)]
d3d12: When adding new output varyings, write 0s
This avoids undefined behavior in some cases, and in the case
where the new output varying is actually a sysval like viewport
index, the DXIL validator will require it to be written.
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14881>
Jesse Natalie [Fri, 4 Feb 2022 17:49:29 +0000 (09:49 -0800)]
d3d12: Don't add arrayed VS outputs when next stage uses per-vertex inputs
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14881>
Jesse Natalie [Fri, 4 Feb 2022 16:23:42 +0000 (08:23 -0800)]
d3d12: Don't force a GS to be added for 'flat' sysvals
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14881>
Jesse Natalie [Fri, 4 Feb 2022 16:22:08 +0000 (08:22 -0800)]
d3d12: Update nir varying bitmasks when linking stages
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14881>
Jesse Natalie [Fri, 4 Feb 2022 15:33:44 +0000 (07:33 -0800)]
d3d12: Fix location compares in MSAA disable
Locations can only be compared against SYSTEM_VALUE_* if the var
mode is system_value.
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14881>
Jesse Natalie [Fri, 4 Feb 2022 15:10:54 +0000 (07:10 -0800)]
d3d12: Update depth invert to deal with multi-viewport
Turn the context state and shader key into a bitmask. When lowering
the depth invert into the shader, scan for writes to viewport index.
If found, move position to the end of the function (or current vertex)
and check if the current viewport needs the depth invert before applying.
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14881>
Jesse Natalie [Fri, 4 Feb 2022 15:10:23 +0000 (07:10 -0800)]
d3d12: Fix linkage for viewport index
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14881>
Jesse Natalie [Fri, 4 Feb 2022 14:16:56 +0000 (06:16 -0800)]
d3d12: Bind 16 scissor rects when scissor disabled
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14881>
Jesse Natalie [Fri, 4 Feb 2022 02:05:43 +0000 (18:05 -0800)]
d3d12: Enable BPTC (BC6/BC7)
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14881>
Jesse Natalie [Fri, 4 Feb 2022 16:21:18 +0000 (08:21 -0800)]
microsoft/compiler: Set flag for VP/RT array index from VS/DS
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14881>
Jesse Natalie [Fri, 4 Feb 2022 14:16:05 +0000 (06:16 -0800)]
microsoft/compiler: Handle SV_ViewportArrayIndex
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14881>
Chia-I Wu [Fri, 4 Feb 2022 07:55:34 +0000 (23:55 -0800)]
zink: set needs_mesa_flush_wsi for venus
venus relies on wsi_image_create_info and wsi_memory_signal_submit_info.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14872>
Chia-I Wu [Fri, 4 Feb 2022 07:55:31 +0000 (23:55 -0800)]
zink: always chain wsi_image_create_info for scanout images
Chaining wsi_image_create_info tells the drivers that the image can use
VK_IMAGE_LAYOUT_PRESENT_SRC_KHR layout. We still use
wsi_image_create_info::scanout to indicate whether this is legacy
scanout or uses modifiers.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14872>
Chia-I Wu [Fri, 4 Feb 2022 07:55:23 +0000 (23:55 -0800)]
zink: set dma-buf bit for shared resources
Set the dma-buf bit when supported. This is done because
zink_resource_get_handle exports dma-bufs when WINSYS_HANDLE_TYPE_FD is
requested.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14872>