Mike Blumenkrantz [Tue, 4 Aug 2020 18:57:06 +0000 (14:57 -0400)]
zink: flag ssbo buffer resources as having pending writes on batch
ssbos are the only descriptor type we support (so far) that allows writes
during the draw, so we have to ensure that we set the right flag on the batch
reference to handle sync if the buffer is later read from
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8330>
Mike Blumenkrantz [Fri, 28 Aug 2020 13:17:37 +0000 (09:17 -0400)]
zink: split UBOs and samplers into 'read' batch references during draw
we have the technology, so now we can just flag these resources as being
read from instead of also being written to, freeing them up for concurrent reads
without requiring fencing
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8330>
Mike Blumenkrantz [Tue, 4 Aug 2020 18:28:50 +0000 (14:28 -0400)]
zink: start supporting atomic shader ops
this handles atomic_add, which is what atomic counters use
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8330>
Mike Blumenkrantz [Tue, 4 Aug 2020 18:24:54 +0000 (14:24 -0400)]
zink: modify ubo loading in ntv to work for ssbos
if ssbo variables are declared using the same structure as ubos, then
the mechanics here are identical, and we can just add a couple extra lines
to handle the atomic ops and different array usage
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8330>
Mike Blumenkrantz [Tue, 4 Aug 2020 18:26:22 +0000 (14:26 -0400)]
zink: emit ssbo variables in ntv
we're structuring these the same as ubos so we can reuse the same load
function later
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8330>
Mike Blumenkrantz [Tue, 4 Aug 2020 18:22:52 +0000 (14:22 -0400)]
zink: hook up ssbo shader bindings
this is just the struct zink_shader binding point stuff, but nothing is
using it yet
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8330>
Mike Blumenkrantz [Tue, 4 Aug 2020 18:21:00 +0000 (14:21 -0400)]
zink: add set_shader_buffers pipe_context method
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8330>
Mike Blumenkrantz [Tue, 4 Aug 2020 18:27:36 +0000 (14:27 -0400)]
zink: add util function for emitting ntv atomic ops
these all need specific memory params, but otherwise they're the same
as normal ops, so we can just make a helper function here to add in the memory
params
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8330>
Mike Blumenkrantz [Tue, 4 Aug 2020 18:20:19 +0000 (14:20 -0400)]
zink: add spirv builder function for runtime array type
we'll need this for ssbos
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8330>
Mike Blumenkrantz [Wed, 2 Dec 2020 16:40:33 +0000 (11:40 -0500)]
nir/lower_uniforms_to_ubo: set explicit_binding on uniform_0
this variable is always bound to buffer index 0, so the binding info
here is actually useful
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7935>
Mike Blumenkrantz [Wed, 13 Jan 2021 16:08:25 +0000 (11:08 -0500)]
zink: optimize renderpass hash table
only the existing render targets need to be used for table entries
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8487>
Mike Blumenkrantz [Thu, 7 Jan 2021 14:39:46 +0000 (09:39 -0500)]
util/set: split off create() into an init() function
this brings parity with the matching hash_table api
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8450>
Mike Blumenkrantz [Thu, 7 Jan 2021 14:38:52 +0000 (09:38 -0500)]
util/set: add the found param to search_or_add
this brings parity with the internal api
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8450>
Mike Blumenkrantz [Tue, 12 Jan 2021 17:20:41 +0000 (12:20 -0500)]
util/set: optimize rehash for empty table and no-func clears
if the table is filled with deleted entries, we don't need to rzalloc+free an identical
block of memory for the table, we can just memset the existing one
the same applies to table clears without a function passed in that the table
doesn't need to be iterated and can just be memset
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8450>
Mike Blumenkrantz [Tue, 12 Jan 2021 17:20:41 +0000 (12:20 -0500)]
util/hash_table: optimize rehash for empty table and no-func clears
if the table is filled with deleted entries, we don't need to rzalloc+free an identical
block of memory for the table, we can just memset the existing one
the same applies to table clears without a function passed in that the table
doesn't need to be iterated and can just be memset
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8450>
Pierre-Eric Pelloux-Prayer [Mon, 11 Jan 2021 19:40:09 +0000 (20:40 +0100)]
radeonsi: invalidate compute sgprs in si_rebind_buffer
If we don't tag compute sgpr as dirty they will point to the
ol buffer location.
This fixes arb_compute_shader-dlist with mcbp enabled.
Fixes:
85a6bcca615 ("radeonsi: pass at most 3 images and/or shader buffers via user SGPRs for compute")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8433>
Pierre-Eric Pelloux-Prayer [Mon, 11 Jan 2021 19:37:25 +0000 (20:37 +0100)]
ac: add ifdef __cplusplus guard to header
ac_shadowed_regs.h can be included from si_state_draw.cpp so this commit
adds the needed guards.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8433>
Michel Dänzer [Tue, 12 Jan 2021 17:39:03 +0000 (18:39 +0100)]
ci: Use meson test directly instead of ninja test
The former allows specifying how many processes to spawn for tests. The
latter seems to spawn (up to) as many test processes as there are CPU
cores.
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8451>
Michel Dänzer [Tue, 12 Jan 2021 17:27:31 +0000 (18:27 +0100)]
ci: Remove .gitlab-ci/meson-build.bat
Unused since
07885cbcdb0b "CI: Add native Windows VS2019 build"
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8451>
Lionel Landwerlin [Mon, 4 Jan 2021 12:47:37 +0000 (13:47 +0100)]
anv: add transfer usage for color/depth/stencil attachments
We sometimes use anv_layout_to_aux_state() to compute the aux state of
an image during the resolve operations at the end of a render
(sub)pass.
If we're dealing with a multisampled image that is created without a
transfer usage, our internal code might trigger a resolve using the
transfer layout (see genX_cmd_buffer.c:cmd_buffer_end_subpass), for
which the image doesn't the usage bit. The current code tries to AND
the 2 usages which won't have any bit in common, thus skipping all
checks below.
v2: Add the transfer usages depending on attachment usage (Lionel)
v3: Limit to samples > 1 (Jason) && DEPTH_STENCIL_ATTACHMENT_BIT (Lionel)
v4: Add transfer usage at image creation (Jason)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
54b525caf0aa99 ("anv: Rework anv_layout_to_aux_state")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4037
Reviewed-by: Reviewed-by: Tapani Pälli <tapani.palli@intel.com> (v1)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8307>
Danylo Piliaiev [Wed, 13 Jan 2021 14:39:41 +0000 (16:39 +0200)]
turnip/ir3: handle image load/stores produced by AtomicLoad/Store
SpvOpAtomicLoad and SpvOpAtomicStore are translated into
nir_intrinsic_image_deref_store/load instead of some separate
atomic intrinsics, however they don't have src or dest type
specified. Turnip doesn't support shaderImageFloat32Atomics
so type is just integer.
Fixes:
dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_local.image.guard_local.image.frag
dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.workgroup.payload_local.buffer.guard_local.image.comp
dEQP-VK.memory_model.write_after_read.core11.u32.coherent.fence_fence.atomicwrite.device.payload_local.buffer.guard_local.image.comp
dEQP-VK.memory_model.write_after_read.core11.u32.coherent.fence_fence.atomicwrite.workgroup.payload_local.image.guard_local.image.comp
dEQP-VK.memory_model.write_after_read.core11.u32.coherent.fence_fence.atomicwrite.workgroup.payload_nonlocal.workgroup.guard_local.image.comp
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8476>
Witold Baryluk [Fri, 8 Jan 2021 10:16:53 +0000 (10:16 +0000)]
lavapipe: Defer lavapipe warning to CreateDevice
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4055
Fixes:
b38879f8c5f57b7f1802e433e33181bdf5e72aef
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8377>
Vinson Lee [Sat, 9 Jan 2021 02:39:38 +0000 (18:39 -0800)]
panfrost: Fix typos.
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8400>
Eric Anholt [Thu, 7 Jan 2021 18:56:54 +0000 (10:56 -0800)]
gallium/tgsi: garbage collect unused TGSI_UTIL_SIGN_MODE.
Noticed while git grepping for abs/neg stuff.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8369>
Eric Anholt [Mon, 11 Jan 2021 19:22:53 +0000 (11:22 -0800)]
gallium/tgsi: Rewrite the docs on source modifiers.
Clarify what the rules are, and warn about the exceptions.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8369>
Eric Anholt [Thu, 7 Jan 2021 18:53:03 +0000 (10:53 -0800)]
gallium/tgsi: Remove support for f64 src modifiers.
The tgsi.rst was not very clear but didn't indicate that they were
supported, and llvmpipe only supported double abs and not negate.
glsl_to_tgsi never generated them, and neither did the new nir_to_tgsi, so
just garbage collect it.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8369>
Eric Anholt [Thu, 7 Jan 2021 18:20:57 +0000 (10:20 -0800)]
gallium/tgsi: Assert that we don't see integer abs modifiers.
tgsi.rst says it's not supported, and llvmpipe, r600, and virgl don't
support it. Make sure nobody else introduces them like I did while
testing only on softpipe.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8369>
Eric Anholt [Thu, 7 Jan 2021 18:04:03 +0000 (10:04 -0800)]
gallium/ntt: Stop lowering integer source mods.
While tgsi_exec.c (softpipe) implemented 32b integer src mods, the
tgsi.rst documentation says only 32b negate is supported and not abs.
llvmpipe implemented 32 and 64 negate but not abs, virgl implemented
negate incorrectly, and r600 apparently doesn't do any integer src mods.
glsl_to_tgsi has apparently never generated integer src mods.
Given that r600 can't do any integer src mods, just stop trying to
generate them for TGSI.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8369>
Eric Anholt [Sat, 9 Jan 2021 00:22:57 +0000 (16:22 -0800)]
gallium/ttn: Add support for TGSI_OPCODE_I64NEG/ABS.
Found when converting AMD's built-in TGSI shaders to not using 64-bit src
mods.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8369>
Ilia Mirkin [Wed, 13 Jan 2021 01:07:25 +0000 (20:07 -0500)]
nv50,nvc0: explicitly list recently-added caps
Some of these should be implemented, but that can be done in a later
change.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8461>
Ilia Mirkin [Tue, 12 Jan 2021 23:41:06 +0000 (18:41 -0500)]
nv50/ir: ignore FS_BLEND_EQUATION_ADVANCED
It's unsupported, but gets set unconditionally by the state tracker,
even when fbfetch is to be used.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8461>
Mike Blumenkrantz [Tue, 12 Jan 2021 21:40:41 +0000 (16:40 -0500)]
zink: clamp sampler+samplerview limits
* struct shader_info provides a 32bit mask for textures_used
* samplers and samplerviews are a 1:1 mapping for shader descriptors
* also according to spec this is always 32 per stage
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8457>
Jason Ekstrand [Wed, 17 Jun 2020 19:04:02 +0000 (14:04 -0500)]
intel/genxml,anv,iris: Drop the legacy compute path from gen125.xml
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
Jordan Justen [Wed, 13 Feb 2019 19:11:43 +0000 (11:11 -0800)]
iris: Add support for COMPUTE_WALKER
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
Jason Ekstrand [Mon, 4 May 2020 23:08:35 +0000 (18:08 -0500)]
anv: Enable push constants on gen12-hp
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
Jason Ekstrand [Mon, 4 May 2020 21:17:58 +0000 (16:17 -0500)]
intel/fs: Emit code for Gen12-HP indirect compute data
Reworks:
* Jordan: Apply to gen > 12
* Jordan: Adjust comment about loading constants
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
Jason Ekstrand [Mon, 4 May 2020 22:08:00 +0000 (17:08 -0500)]
anv: Add a general state pool
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
Jordan Justen [Thu, 15 Nov 2018 00:51:00 +0000 (16:51 -0800)]
anv: Use COMPUTE_WALKER for gen12-hp
Rework: Rafael Antognolli, Jason Ekstrand
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
Jordan Justen [Thu, 15 Nov 2018 00:48:57 +0000 (16:48 -0800)]
anv: Don't use MEDIA_INTERFACE_DESCRIPTOR_LOAD for gen12-hp
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
Jordan Justen [Wed, 14 Nov 2018 19:04:15 +0000 (11:04 -0800)]
anv: Emit CFE_STATE for gen12-hp
Rework:
* make scratch TODO. (Jason)
* emit_compute_cs_state => emit_compute_state. (Jason)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
Jason Ekstrand [Wed, 17 Jun 2020 04:06:25 +0000 (23:06 -0500)]
intel/fs: Allow compute dispatch without a pushed subgroup ID on Gen12-HP
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
Jordan Justen [Tue, 13 Nov 2018 22:26:23 +0000 (14:26 -0800)]
intel/compiler: Disable push constants on gen12-hp
We currently don't use push constants with the COMPUTE_WALKER command.
Make all uniforms to be pull constants.
The local group id previously was a push constant, but is now
available in R0.2[7:0].
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
Jason Ekstrand [Mon, 15 Jun 2020 22:33:54 +0000 (17:33 -0500)]
intel/tools: Decode COMPUTE_WALKER
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
Jordan Justen [Sun, 11 Nov 2018 10:14:53 +0000 (02:14 -0800)]
intel/genxml/gen125: Add CFE_STATE and COMPUTE_WALKER
Reworks:
* Jason: Captalize COMPUTE_WALKER::BTD mode
* Jason: Make COMPUTE_WALKER::InlineData an array
* Jason: Remove stale fields, uint=>bool, add missing enum values.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
Dylan Baker [Wed, 13 Jan 2021 18:28:20 +0000 (10:28 -0800)]
docs: update calendar for 21.0.0-rc1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8478>
Dylan Baker [Wed, 13 Jan 2021 18:27:45 +0000 (10:27 -0800)]
docs: update calendar and link releases notes for 20.3.3
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8478>
Dylan Baker [Wed, 13 Jan 2021 18:24:11 +0000 (10:24 -0800)]
docs: Add sha256sum for 20.3.3
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8478>
Dylan Baker [Wed, 13 Jan 2021 18:06:42 +0000 (10:06 -0800)]
docs: add release notes for 20.3.3
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8478>
Boris Brezillon [Wed, 13 Jan 2021 10:26:54 +0000 (11:26 +0100)]
panfrost: Don't skip the test with a 4k shader
Commit
bfcdc8f1747e ("pan/bi: Add some zero bytes after shaders on
Bifrost") should have fixed the problem.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8470>
Rhys Perry [Tue, 1 Sep 2020 10:55:58 +0000 (11:55 +0100)]
nir/loop_unroll: unroll more aggressively if it can improve load scheduling
Significantly improves performance of a Control compute shader. Also seems
to increase FPS at the very start of the game by ~5% (RX 580, 1080p,
medium settings, no MSAA).
fossil-db (Sienna):
Totals from 81 (0.06% of 139391) affected shaders:
SGPRs: 3848 -> 4362 (+13.36%); split: -0.99%, +14.35%
VGPRs: 4132 -> 4648 (+12.49%)
CodeSize: 275532 -> 659188 (+139.24%)
MaxWaves: 986 -> 906 (-8.11%)
Instrs: 54422 -> 126865 (+133.11%)
Cycles: 1057240 -> 750464 (-29.02%); split: -42.61%, +13.60%
VMEM: 26507 -> 61829 (+133.26%); split: +135.56%, -2.30%
SMEM: 4748 -> 5895 (+24.16%); split: +31.47%, -7.31%
VClause: 1933 -> 6802 (+251.89%); split: -0.72%, +252.61%
SClause: 1179 -> 1810 (+53.52%); split: -3.14%, +56.66%
Branches: 1174 -> 1157 (-1.45%); split: -23.94%, +22.49%
PreVGPRs: 3219 -> 3387 (+5.22%); split: -0.96%, +6.18%
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6538>
Rob Clark [Mon, 11 Jan 2021 18:30:12 +0000 (10:30 -0800)]
freedreno/ir3: Remove legacy packed-struct encoding
Note that we can't actually remove the packed structs themselves yet,
because tu still uses them in some hand-coded blit shaders.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997>
Rob Clark [Fri, 8 Jan 2021 22:32:33 +0000 (14:32 -0800)]
freedreno/ir3/decode: Switch over to new disasm
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997>
Rob Clark [Sat, 9 Jan 2021 20:36:08 +0000 (12:36 -0800)]
freedreno/ir3: Realign disasm shader stats
To better match up with what mesa shader-db stats look like, for easier
comparision.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997>
Rob Clark [Sat, 9 Jan 2021 20:12:37 +0000 (12:12 -0800)]
freedreno/ir3: Better sstall estimation
1) Take into account repeat/nop cycles
2) Clear sfu_delay after an (ss) sync
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997>
Rob Clark [Thu, 31 Dec 2020 20:19:45 +0000 (12:19 -0800)]
freedreno/ir3: Small resinfo disasm tweak
Add the 'type' field.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997>
Rob Clark [Wed, 30 Dec 2020 20:03:06 +0000 (12:03 -0800)]
freedreno/ir3: Switch over to new encoder/decoder
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997>
Rob Clark [Thu, 31 Dec 2020 19:42:12 +0000 (11:42 -0800)]
freedreno/ir3/tests: Switch disasm test over to new decoder
Also, uncomment the `stc` test vectors (since the new decoder decodes
these properly) and comment out an instruction which looks suspiciously
like -6.0 in hex.
This also switches the parser back to `atomic.b.op` from `atomic.op.b`
which was a short-term workaround to make it easier for the legacy
disassembler.
Also switch the binary encoding for ldib to clear b0, because the new
disassembler warns about unexpected dontcare bits (which cases the
disasm to not match).
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997>
Rob Clark [Tue, 15 Dec 2020 21:22:37 +0000 (13:22 -0800)]
freedreno/hw/isa: Add expression caching
Drops decoding an ~850KB collection of instructions from ~4min to ~1sec.
Granted for normal sized shaders, this probably doesn't matter.. but it
at reduces my cycle time for fixing things to match existing disasm
syntax using this massive collection of unique instructions.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997>
Rob Clark [Mon, 14 Dec 2020 00:20:40 +0000 (16:20 -0800)]
freedreno/hw/isa: Add description of ir3 ISA
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997>
Rob Clark [Mon, 14 Dec 2020 00:18:43 +0000 (16:18 -0800)]
freedreno/hw: Add isaspec mechanism for documenting/defining an ISA
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997>
Rob Clark [Wed, 30 Dec 2020 19:51:23 +0000 (11:51 -0800)]
freedreno/ir3: Add some new "logical" opcodes
Once we switch over to the xml based ir3 ISA definition, the opcodes
will be decoupled from instruction encoding. Which will let us better
handle cases where a single "opcode" (from instruction encoding stand-
point) means different things on different generations. And also cases
like the different variations of `b`ranch instructions, which share a
single hw "opcode" plus a separate "brtype" field. When we start using
these in ir3, we'd like to treat them as separate instructions and not
have to care about the details of how they are encoded.
For now, these are only used internally within the new xml generated
instruction encoding, but once the existing "packed struct" encoding/
decoding is replace, we'll update ir3 to start using the new opcode
enums directly (except for the `mov` variants).
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997>
Rob Clark [Tue, 29 Dec 2020 18:26:07 +0000 (10:26 -0800)]
freedreno/ir3: Decouple ir3_info collection from assembler
We'll want to re-use this when cutting over to the new XML based
instruction encoding. So untangle it from instruction packing.
Also, move handling of the appended constant data out of the
assembler, since this isn't much related to instruction encoding.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997>
Rob Clark [Mon, 4 Jan 2021 20:47:36 +0000 (12:47 -0800)]
freedreno/ir3: Fix ldg decoding/parsing
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997>
Tony Wasserka [Mon, 9 Nov 2020 10:12:13 +0000 (11:12 +0100)]
aco/ra: Use PhysRegInterval for count_zero
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7799>
Tony Wasserka [Mon, 9 Nov 2020 09:52:45 +0000 (10:52 +0100)]
aco/ra: Use PhysRegInterval for collect_vars parameters
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7799>
Tony Wasserka [Tue, 15 Dec 2020 19:49:11 +0000 (20:49 +0100)]
aco/ra: Use PhysReg when indexing into RegisterFile's containers
This gets rid of a lot of implicit/explicit conversions from PhysReg to
unsigned.
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7799>
Tony Wasserka [Thu, 29 Oct 2020 17:08:13 +0000 (18:08 +0100)]
aco/ra: Use PhysReg for member functions of PhysRegInterval
This replaces the various PhysReg{lb} casts that had been all over the place.
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7799>
Tony Wasserka [Thu, 29 Oct 2020 10:55:28 +0000 (11:55 +0100)]
aco/ra: Remove unused function parameter
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7799>
Tony Wasserka [Thu, 29 Oct 2020 10:43:51 +0000 (11:43 +0100)]
aco/ra: Use std::all_of to simplify a loop
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7799>
Tony Wasserka [Thu, 29 Oct 2020 10:41:11 +0000 (11:41 +0100)]
aco/ra: Add helpers to test for intersection/containment of reg intervals
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7799>
Tony Wasserka [Thu, 29 Oct 2020 10:39:39 +0000 (11:39 +0100)]
aco/ra: Move commonly repeated code to a helper function
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7799>
Tony Wasserka [Wed, 28 Oct 2020 22:49:18 +0000 (23:49 +0100)]
aco/ra: Conservatively refactor get_reg_specified to use PhysRegInterval
All expressions have been replaced by their closest equivalent. No major
simplification efforts have been made to minimize risk of regressions.
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7799>
Tony Wasserka [Wed, 28 Oct 2020 22:40:39 +0000 (23:40 +0100)]
aco/ra: Use std::all_of to simplify a loop
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7799>
Tony Wasserka [Wed, 28 Oct 2020 19:00:18 +0000 (20:00 +0100)]
aco/ra: Use std::find_if(_not) to clean up get_reg_simple
This makes for a more self-describing iteration behavior, and it gets rid
of the need for the duplicated "final check" at the bottom.
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7799>
Tony Wasserka [Wed, 28 Oct 2020 18:39:03 +0000 (19:39 +0100)]
aco/ra: Add iterator interface for PhysRegInterval
This enables various loops to use range-based for.
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7799>
Tony Wasserka [Wed, 28 Oct 2020 22:38:20 +0000 (23:38 +0100)]
aco/ra: Remove always-false conditions
All code paths that set "found" to true either break or return before the
loop header is reached again, so the checks are unnecessary.
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7799>
Tony Wasserka [Wed, 28 Oct 2020 17:46:01 +0000 (18:46 +0100)]
aco/ra: Conservatively refactor existing code to use PhysRegInterval
All expressions have been replaced by their closest equivalent. No major
simplification efforts have been made to minimize risk of regressions.
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7799>
Tony Wasserka [Wed, 28 Oct 2020 12:35:06 +0000 (13:35 +0100)]
aco/ra: Introduce PhysRegInterval helper class
This mainly clarifies the semantics of register bounds (inclusive vs
exclusive), and further groups related varaibles together to clarify
sliding-window-style loops.
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7799>
Tony Wasserka [Mon, 30 Nov 2020 11:40:02 +0000 (12:40 +0100)]
aco/ra: Update register use bounds before recursing in get_regs_for_copies
Delaying the call to adjust_max_used_regs until after get_regs_for_copies
returns puts the RA context into a state where registers past max_used_gpr
may be blocked. This isn't an issue on its own, but it adds a surprising
corner case to get_reg_simple that is easily avoided now.
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7799>
Daniel Schürmann [Thu, 26 Nov 2020 16:36:47 +0000 (17:36 +0100)]
aco: remove divergent branches which only jump over very few instructions
Totals from 18436 (13.23% of 139391) affected shaders (NAVI10):
CodeSize:
138428504 ->
138172588 (-0.18%)
Instrs:
26605127 ->
26541176 (-0.24%)
Cycles:
1624994088 ->
1622461620 (-0.16%)
VMEM: 3689892 -> 3689102 (-0.02%)
SMEM: 1131767 -> 1131761 (-0.00%)
Branches: 851796 -> 787852 (-7.51%)
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7814>
Daniel Schürmann [Thu, 7 Jan 2021 14:07:09 +0000 (15:07 +0100)]
aco: propagate swizzles when optimizing packed clamp & fma
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6680>
Daniel Schürmann [Wed, 16 Sep 2020 09:32:29 +0000 (10:32 +0100)]
aco: optimize v_pk_fma_f16 -> v_pk_fmac_f16 on GFX10
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6680>
Daniel Schürmann [Fri, 11 Sep 2020 15:20:21 +0000 (16:20 +0100)]
aco: optimize packed fneg
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6680>
Daniel Schürmann [Fri, 11 Sep 2020 14:54:39 +0000 (15:54 +0100)]
aco: optimize packed clamp
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6680>
Daniel Schürmann [Thu, 3 Sep 2020 11:02:55 +0000 (12:02 +0100)]
aco: optimize packed mul+add to v_pk_fma_f16
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6680>
Daniel Schürmann [Wed, 2 Sep 2020 14:19:21 +0000 (15:19 +0100)]
aco: simplify multiply-add combining
When both operands of a v_sub (same apply for v_add) are mul and one
already uses clamp/omod, pick the other operand to get a chance to
combine to a MAD.
No fossils-db changes.
Co-authored-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6680>
Daniel Schürmann [Mon, 31 Aug 2020 09:55:51 +0000 (10:55 +0100)]
radv: vectorize 16bit instructions
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6680>
Daniel Schürmann [Mon, 24 Aug 2020 19:36:06 +0000 (20:36 +0100)]
aco: emit packed 16bit instructions
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6680>
Daniel Schürmann [Mon, 24 Aug 2020 18:43:26 +0000 (19:43 +0100)]
aco: create helpers to emit vop3p instructions
Also make get_alu_src() capable to return
unswizzled multi-component SGPR sources.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6680>
Daniel Schürmann [Mon, 14 Sep 2020 10:53:33 +0000 (11:53 +0100)]
aco: change usesModifiers() considering opsel_hi on packed instructions
opsel_hi == 1 means that the high operand selects the
high bits of the input, which is the normal behavior.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6680>
Daniel Schürmann [Fri, 8 Jan 2021 22:14:16 +0000 (23:14 +0100)]
aco: allow SGPRs on every src position for VOP3P
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6680>
Daniel Schürmann [Fri, 4 Sep 2020 11:35:54 +0000 (12:35 +0100)]
aco: allow constants/literals on every src position for VOP3P
and prevent literals on VOP3P pre-GFX10.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6680>
Daniel Schürmann [Mon, 14 Sep 2020 10:59:58 +0000 (11:59 +0100)]
aco/RA: fix subdword operands on VOP3P instructions
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6680>
Daniel Schürmann [Thu, 3 Sep 2020 10:59:00 +0000 (11:59 +0100)]
aco: fix VOP3P assembly, VN and validation
aco/opcodes: rename v_pk_fma_mix* -> v_fma_mix*
and add modifier capabilities for VOP3P.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6680>
Dylan Baker [Wed, 13 Jan 2021 17:46:10 +0000 (09:46 -0800)]
VERSION: bump for 21.1.0 cycle
Samuel Pitoiset [Tue, 5 Jan 2021 15:47:17 +0000 (16:47 +0100)]
radv: enable DCC for MSAA on GFX10+
It should work fine now.
This gives +1-2% improvements with Control MSAA (2x and 4x)
on Sienna.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8413>
Boris Brezillon [Wed, 13 Jan 2021 10:18:11 +0000 (11:18 +0100)]
pan/bi: Fix the !immediate case in bi_emit_store_vary()
The base offset was ignored, take it into account.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8469>
Ilia Mirkin [Wed, 13 Jan 2021 05:38:10 +0000 (00:38 -0500)]
nouveau: trigger the current fence's work on destroy explicitly
Otherwise the delete yells at us that there's still work pending. This
isn't an actual problem, but annoying to see each time.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8462>
Timur Kristóf [Wed, 13 Jan 2021 12:19:01 +0000 (13:19 +0100)]
ci: Add an expected failures list for Oland (GFX6)
This is a copy of the expected failures list of Pitcairn (also GFX6)
with some Oland specific failures added.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8473>
Thong Thai [Mon, 4 Jan 2021 20:53:02 +0000 (15:53 -0500)]
frontends/va: Return an error if non-interlaced buffer is not supported
Add a check to vaDeriveImage to see if a non-interlaced buffer was
created successfully. Otherwise, return an error, since we won't be able
to derive an image from the interlaced buffer.
Prevents a null pointer dereference from occuring on some nVidia cards,
reported by Alexander Kapshuk.
v2: Check for PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE support (Ilia)
Fixes:
fcb558321e6 ("frontends/va: Derive image from interlaced buffers")
Signed-off-by: Thong Thai <thong.thai@amd.com>
Tested-by: Alexander Kapshuk <alexander.kapshuk@gmail.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8320>
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