Alexey Bataev [Tue, 18 Oct 2022 14:36:22 +0000 (07:36 -0700)]
[SLP][NFC]Try to fix MSVC buildbots with a workaround, NFC.
Qiongsi Wu [Tue, 18 Oct 2022 14:35:44 +0000 (10:35 -0400)]
[clang][LTO] Setting Desired Default AIX Debugging Options
On AIX, `strict-dwarf` defaults to `true`. This patch implement this default behaviour. Additionally, it adds debug tuning tests.
Reviewed By: shchenz
Differential Revision: https://reviews.llvm.org/D135908
bipmis [Tue, 18 Oct 2022 14:40:31 +0000 (15:40 +0100)]
Add test for combinations of four i8-loads spliced into a 32-bit value
Guillaume Chatelet [Tue, 18 Oct 2022 14:37:08 +0000 (16:37 +0200)]
[libc] Fix missing bazel dependency
This fixes breakage introduced in
a786096f9dd20acf29d8297e706ad96de063f612
uabkaka [Tue, 18 Oct 2022 13:48:26 +0000 (15:48 +0200)]
[SimplifyLibCalls] Add NoUndef/NonNull/Dereferenceable attributes to iprintf/siprintf
When SimplifyLibCalls fail to optimize printf and sprintf it add
NoUndef/NonNull/Dereferenceable attributes. This patch add the same attributes
if SimplifyLibCalls optimize printf/sprintf into the integer only
iprintf/siprintf.
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D136140
Guillaume Chatelet [Tue, 18 Oct 2022 14:32:21 +0000 (14:32 +0000)]
[libc][NFC] Cleanup and document utils.h
Guillaume Chatelet [Tue, 18 Oct 2022 14:30:04 +0000 (14:30 +0000)]
[libc][NFC] Use ASSERT instead of EXPECT in tests
Sanjay Patel [Tue, 18 Oct 2022 12:52:34 +0000 (08:52 -0400)]
[InstCombine] add tests for fmul nnan with 0.0; NFC
Alexey Bataev [Tue, 18 Oct 2022 13:42:00 +0000 (06:42 -0700)]
[SLP][NFC]Formatting of the getEntryCost function, NFC.
Florian Hahn [Tue, 18 Oct 2022 14:12:23 +0000 (15:12 +0100)]
[LoopUnroll] Forget exit values when making changes.
When unrolling, the exit values in LCSSA phis will get updated.
Invalidate cached SCEV values for those phis in case SCEV looked through
a exit phi.
Fixes #58340.
Stefan Pintilie [Tue, 18 Oct 2022 13:45:50 +0000 (08:45 -0500)]
[NFC][PowerPC] Add a test to check power 10 features.
This patch only adds a single test for Power 10 features.
Jialun Hu [Tue, 18 Oct 2022 13:56:13 +0000 (21:56 +0800)]
[clang] Fix crash upon stray coloncolon token in C2x mode
The parser assumes that the lexer never emits coloncolon token for C code, but this assumption no longer holds in C2x attribute namespaces. As a result, stray coloncolon tokens out of attributes cause assertion failures and hangs in release build, which this patch tries to handle.
Crash input minimal example: `T n::v`
Reviewed By: aaron.ballman
Differential Revision: https://reviews.llvm.org/D133248
Florian Hahn [Tue, 18 Oct 2022 13:56:44 +0000 (14:56 +0100)]
[LoopUnroll] Add test for mis-compile due to missing SCEV invalidation.
Test for #58340.
Aaron Ballman [Tue, 18 Oct 2022 13:39:17 +0000 (09:39 -0400)]
Add an additional time for monthly office hours
Office hours have gone so well for me that I've had requests to add a
second time slot which is later in the day so that folks on the US west
coast have a more reasonable time to meet. So now meeting at 10am and
2pm on the 2nd Monday of each month.
Ties Stuij [Tue, 18 Oct 2022 12:47:03 +0000 (13:47 +0100)]
[clang][ARM] follow GCC behavior for defining __SOFTFP__
GCC behavior regarding defining __SOFTFP__ when (implicitly) specifying
-mfloat-abi=softfp:
- compile without (implicit) FP: define __SOFTFP__
- compile with (implicit) FP: don't define __SOFTFP__
Currently Clang doesn't define __SOFTFP__ when softfp is specified, either with
or without FP. This patch brings Clang in line with GCC behavior.
This was raised by itaig1 over on Github:
https://github.com/llvm/llvm-project/issues/55755
Reviewed By: pratlucas
Differential Revision: https://reviews.llvm.org/D135680
Joseph Huber [Mon, 17 Oct 2022 20:53:31 +0000 (15:53 -0500)]
[OpenMP] Make device functions have hidden visibility
In OpenMP target offloading an in other offloading languages, we
maintain a difference between device functions and kernel functions.
Kernel functions must be visible to the host and act as the entry point
to the target device. Device functions however cannot be called directly
by the host and must be called by a kernel function. Currently, we make
all definitions on the device protected by default. Because device
functions cannot be called or used by the host they should have hidden
visibility. This allows for the definitions to be better optimized via
LTO or other passes.
This patch marks every device function in the AST as having `hidden`
visibility. The kernel function is generated later at code-gen and we
set its visibility explicitly so it should not be affected. This
prevents the user from overriding the visibility, but since the user
can't do anything with these symbols anyway there is no point exporting
them right now.
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D136111
Nikita Popov [Tue, 18 Oct 2022 09:11:20 +0000 (11:11 +0200)]
[lldb] Fix m_hwp_regs size for ppc64le (PR54520)
The size of the m_hwp_regs array should match the default value of
m_max_hwp_supported. This ensures that no out-of-bounds accesses
occur, even if the array is accessed prior to a call to
ReadHardwareDebugInfo().
Fixes https://github.com/llvm/llvm-project/issues/54520, see also
there for additional background.
Differential Revision: https://reviews.llvm.org/D136144
Erich Keane [Tue, 11 Oct 2022 13:16:41 +0000 (06:16 -0700)]
Stop evaluating trailing requires clause after overload resolution
Reported as it showed up as a constriants failure after the deferred
instantiation patch, we were checking constraints TWICE after overload
resolution. The first is during overload resolution, the second is when
diagnosing a use.
This patch modifies DiagnoseUseOfDecl to skip the trailing requires
clause check in some cases. First, of course, after choosing a candidate
after overload resolution.
The second is when evaluating a shadow using constructor, which had its
constraints checked when picking a constructor (as this is ALWAYS an
overload situation!).
Differential Revision: https://reviews.llvm.org/D135772
Jun Zhang [Tue, 18 Oct 2022 12:38:30 +0000 (20:38 +0800)]
[Clang] Fix crash when checking misaligned member with dependent type
If the type is dependent, we should just discard it and not checking its
alignment as it doesn't exisit yet.
Fixes https://github.com/llvm/llvm-project/issues/58370
Differential Revision: https://reviews.llvm.org/D136018
Anton Afanasyev [Tue, 18 Oct 2022 12:56:39 +0000 (15:56 +0300)]
Revert "[MachineCombiner][RISCV] Enable MachineCombiner for RISCV"
This reverts commit
3112cf3b00fe45a0911ec0c2e6706ef1f8a9b972.
Test breakage: https://lab.llvm.org/buildbot/#/builders/16/builds/36631
Andrew Ng [Mon, 26 Sep 2022 14:10:13 +0000 (15:10 +0100)]
[CMake] Add Python script to generate version script symbol exports
Using a Python script instead of the various shell commands means that
it is now possible to cross compile LLVM for Linux on Windows.
Differential Revision: https://reviews.llvm.org/D136092
Weining Lu [Tue, 18 Oct 2022 09:33:50 +0000 (17:33 +0800)]
[LoongArch] Fix codegen of atomicrmw nand
Fix invalid RISCV-like MI being emitted for performing the `not`
operation: the LoongArch `xori` zero-extends the immediate, hence is
not equivalent to RISCV `xori`. The LoongArch `not` is a `nor` with
zero.
Differential Revision: https://reviews.llvm.org/D136021
Jannik Silvanus [Tue, 18 Oct 2022 11:26:32 +0000 (13:26 +0200)]
[NFC][ADT] Clean up EnumeratedArray.h
As discussed in D135594, remove superfluous inline
attributes, and remove top-level consts on function arguments.
Anton Sidorenko [Mon, 17 Oct 2022 09:06:08 +0000 (12:06 +0300)]
[MachineCombiner][RISCV] Enable MachineCombiner for RISCV
Initial implementation to match basic FP reassociation patterns.
Differential Revision: https://reviews.llvm.org/D135264
Carlos Alberto Enciso [Tue, 18 Oct 2022 11:02:36 +0000 (12:02 +0100)]
[llvm-debuginfo-analyzer] Fix linking errors in buildbots.
The tool used the 'old' LLVM build information (LLVMBuild.txt),
which caused linking errors in:
https://lab.llvm.org/buildbot/#/builders/177/builds/10125
https://lab.llvm.org/buildbot/#/builders/196/builds/19699
Update the CMake configuration to support the new LLVM build
system that uses only CMakeLists.txt.
Reviewed By: jryans
Differential Revision: https://reviews.llvm.org/D136159
Ben Dunbobbin [Tue, 18 Oct 2022 11:47:56 +0000 (12:47 +0100)]
[LLD][ELF] --wrap: __real_foo references should trigger archive extraction for foo
A reference to __real_foo should trigger archive extraction of the input file that defines foo, otherwise a link using --wrap=foo might fail to link with an undefined reference to foo.
This matches bfd linker behaviour.
Differential Revision: https://reviews.llvm.org/D135897
Andrew Ng [Fri, 14 Oct 2022 15:06:34 +0000 (16:06 +0100)]
[CMake] Fix Findzstd module for shared DLL on Windows
Differential Revision: https://reviews.llvm.org/D136065
chenglin.bi [Tue, 18 Oct 2022 11:18:23 +0000 (19:18 +0800)]
[AArch64] add test case for pattern ((X >> C) - Y) + Z; NFC
Nico Weber [Mon, 17 Oct 2022 13:26:23 +0000 (09:26 -0400)]
[gn build] port
fe7a3cedf771 (llvm-debuginfo-analyzer)
Valentin Clement [Tue, 18 Oct 2022 10:12:11 +0000 (12:12 +0200)]
[flang] Reconstruct binding tables for fir.dispatch codegen
Binding tables are needed to perform the fir.dispatch code generation.
The binding tables are defined as fir.global from the initial lowering.
This patch adds the ability to reconstruct the binding tables information
and store the procedure name and binding index for later use by the
fir.dispatch code generation.
Tests will come with follow up patch that makes full use of this information.
Reviewed By: jeanPerier
Differential Revision: https://reviews.llvm.org/D136141
Anton Sidorenko [Thu, 15 Sep 2022 12:00:05 +0000 (15:00 +0300)]
[MachineCombiner][RISCV] Precommit test for D135264
Jean Perier [Tue, 18 Oct 2022 09:07:47 +0000 (11:07 +0200)]
[flang][NFC] Simplify mapSymbolAttributes in symbol lowering
mapSymbolAttributes currently has a lot of very similar code for
each kind of explicit shape and scalar symbols.
Refactor it so that the change to lower symbols with fir.declare
can be added in centralized places instead of being scattered.
This is a preparation patch and fir.declare is not yet added.
Differential Revision: https://reviews.llvm.org/D136061
Daniel Kiss [Tue, 18 Oct 2022 08:35:10 +0000 (10:35 +0200)]
[AArch64] Make ACLE intrinsics always available part MTE
Make MTE intrinsics available in function scope too.
Followup from D133359.
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D136062
Martin Storsjö [Tue, 18 Oct 2022 08:41:49 +0000 (08:41 +0000)]
[LLDB] Fix the build for ppc64le linux
812ad2167bd2e27f5d0dee07bb03a5910616e0b6 changed the signature of
RegisterValue::SetFromMemoryData.
Daniel Kiss [Tue, 18 Oct 2022 08:45:32 +0000 (10:45 +0200)]
Revert "[AArch64] Make ACLE intrinsics always available part MTE"
This reverts commit
09aaf190d93393d9e29d29a033cc3979589c5e84.
Daniel Kiss [Tue, 18 Oct 2022 08:35:10 +0000 (10:35 +0200)]
[AArch64] Make ACLE intrinsics always available part MTE
Make MTE intrinsics available in function scope too.
Followup from D133359.
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D136062
Tobias Gysi [Tue, 18 Oct 2022 08:01:07 +0000 (11:01 +0300)]
[mlir][llvm] Import matrix, vector, and assume intrinsics from LLVM IR.
The revision adds support to import:
- matrix intrinsics
- vector reduce fadd/fmul intrinsics
- assume intrinsics
from LLVM IR.
Reviewed By: ftynse
Differential Revision: https://reviews.llvm.org/D136137
Nikita Popov [Tue, 18 Oct 2022 08:05:12 +0000 (10:05 +0200)]
[CFG] Add const qualifier to isPotentiallyReachableFromMany() (NFC)
Accept a const pointer for StopBB. Unfortunately the worklist has
to use non-const pointers due to LoopInfo interaction.
Carlos Alberto Enciso [Tue, 18 Oct 2022 07:39:26 +0000 (08:39 +0100)]
Recommit [llvm-debuginfo-analyzer] (02/09) - Driver and documentation
Originally committed in
fe7a3cedf77125a6309150d85cecbc20b1a31775
Reverted in
26dd64ba9cfabe5474bb207f3b7099965f81fed7
Buildbot failures:
https://lab.llvm.org/buildbot#builders/139/builds/29663
- unittest trigger an invalid assertion.
https://lab.llvm.org/buildbot#builders/196/builds/19665
- 'has virtual functions but non-virtual destructor' warning as error.
Recommitted with fix:
- Removed the assertion.
- Added virtual destructor.
Dominik Adamski [Thu, 8 Sep 2022 11:39:18 +0000 (06:39 -0500)]
[OpenMP][OMPIRBuilder] Add generation of SIMD align assumptions to OMPIRBuilder
Currently generation of align assumptions for OpenMP simd construct is done
outside OMPIRBuilder for C code and it is not supported for Fortran.
According to OpenMP 5.0 standard (2.9.3) only pointers and arrays can be
aligned for C code.
If given aligned variable is pointer, then Clang generates the following set
of the LLVM IR isntructions to support simd align clause:
; memory allocation for pointer address:
%A.addr = alloca ptr, align 8
; some LLVM IR code
; Alignment instructions (alignment is equal to 32):
%0 = load ptr, ptr %A.addr, align 8
call void @llvm.assume(i1 true) [ "align"(ptr %0, i64 32) ]
If given aligned variable is array, then Clang generates the following set
of the LLVM IR isntructions to support simd align clause:
; memory allocation for array:
%B = alloca [10 x i32], align 16
; some LLVM IR code
; Alignment instructions (alignment is equal to 32):
%arraydecay = getelementptr inbounds [10 x i32], ptr %B, i64 0, i64 0
call void @llvm.assume(i1 true) [ "align"(ptr %arraydecay, i64 32) ]
OMPIRBuilder was modified to generate aligned assumptions. It generates only
llvm.assume calls. Frontend is responsible for generation of aligned pointer
and getting the default alignment value if user does not specify it in aligned
clause.
Unit and regression tests were added to check if aligned clause was handled correctly.
Differential Revision: https://reviews.llvm.org/D133578
Reviewed By: jdoerfert
Max Kazantsev [Tue, 18 Oct 2022 06:26:00 +0000 (13:26 +0700)]
[NFC] Reuse NonTrivialUnswitchCandidate instead of std::pair
Clement Courbet [Tue, 18 Oct 2022 06:47:21 +0000 (08:47 +0200)]
[doc] Fix invalid reference to `hasReturnArgument` matcher.
The matcher is called `hasReturnValue`.
Yuanfang Chen [Tue, 18 Oct 2022 06:05:35 +0000 (23:05 -0700)]
[Clang] add DR tests for D128745
Sheng [Tue, 18 Oct 2022 05:18:09 +0000 (05:18 +0000)]
[NFC][mlir] Remove redundant wording
"that provides" repeats two times.
Emilia Dreamer [Tue, 11 Oct 2022 19:16:48 +0000 (22:16 +0300)]
[clang-format] Correctly annotate star/amp in function pointer params
Inside the arguments part of a function pointer declaration,
`determineStarAmpUsage` results in a binary operator rather than
pointers, because said parens are assumed to be an expression.
This patch correctly marks the argument parens of a function
pointer type as not an expression. Note that this fix already
existed for Objective-C blocks as part of
f1f267b447f60528440d2c066b29ab014ae7f90f.
As Objective-C blocks and C/C++ function pointers share a lot
of the same logic, that fix also makes sense here.
Fixes https://github.com/llvm/llvm-project/issues/31659
Differential Revision: https://reviews.llvm.org/D135707
Chuanqi Xu [Tue, 18 Oct 2022 05:15:52 +0000 (13:15 +0800)]
[NFC] Add missing ABI requirement from the previous patch
bixia1 [Tue, 18 Oct 2022 04:41:50 +0000 (21:41 -0700)]
Add ::mlir:: prefix to Attribute type in the generated code.
Reviewed By: mehdi_amini
Differential Revision: https://reviews.llvm.org/D136129
YunQiang Su [Tue, 18 Oct 2022 04:49:25 +0000 (04:49 +0000)]
[CMake] Fix MIPSr6 build for compiler-rt
The current version pass -mips64r2 or -mips32r2 options,
which make it failed to build on r6 platform.
In this patch: we detect whether we are MIPSr6 by
_MIPS_ARCH_MIPS32R6/_MIPS_ARCH_MIPS64R6
The out and install path is set to the default triple instead of
hardcoded one, since the clang ask for it.
Differential Revision: https://reviews.llvm.org/D135735
Jez Ng [Tue, 18 Oct 2022 04:17:34 +0000 (00:17 -0400)]
[lld-macho][test] Rework map-file.s
Merge the checks done on the `c-string-literals` binary with those on
the main `test` binary. Also switch some checks to `-DAG` instead of
`-NEXT`. I'm about to extend this test, and this is easier to work with.
Reviewed By: #lld-macho, oontvoo
Differential Revision: https://reviews.llvm.org/D135999
Chuanqi Xu [Tue, 18 Oct 2022 03:32:34 +0000 (11:32 +0800)]
[NFC] [C++20] [Modules] Test if the functions in importee are generated
In O0, all the functions (except the always-inline-functions) in the importee
shouldn't be imported for compilation speeds.
But with optimizations, all the potentially called function in the
importee should be imported to not prevent any inter-procedural
optimizations (primarily inline), which is pretty important for runtime
performances.
This patch adds the tests for the feature.
Jeff Bailey [Tue, 18 Oct 2022 03:12:33 +0000 (03:12 +0000)]
[libc]Identify which processors are completed for Math
Switch from green checkmarks to the following legend:
X = x86_64
A = aarch64
a = arm32
Reviewed By: lntue
Differential Revision: https://reviews.llvm.org/D136020
Volodymyr Sapsai [Tue, 18 Oct 2022 01:48:24 +0000 (18:48 -0700)]
[ODRHash] Hash `ObjCMethodDecl` and diagnose discovered mismatches.
Differential Revision: https://reviews.llvm.org/D130325
Volodymyr Sapsai [Tue, 18 Oct 2022 01:23:28 +0000 (18:23 -0700)]
[ODRHash] Rename `isDeclToBeProcessed` to `isSubDeclToBeProcessed`. NFC intended.
The method is used only for sub-Decls, so reflect that in the name.
LiaoChunyu [Tue, 18 Oct 2022 01:21:47 +0000 (09:21 +0800)]
[RISCV] Optimize SELECT_CC when the true value of select is Constant
(select (setcc lhs, rhs, CC), constant, falsev) -> (select (setcc lhs, rhs, InverseCC), falsev, constant)
This patch removes unnecessary copies
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D129757
Aart Bik [Tue, 18 Oct 2022 00:02:25 +0000 (17:02 -0700)]
[mlir][sparse] implement simple codegen for insertion (and related ops)
This is a proof of concept insertion implementation that sets up
the basic framework and implements it with push backs for just
sparse vectors. It adds insertion/compression through SSA values,
so that we properly update the memref after after pushback operation.
Note that properly using SSA values in sparsification is still TBD
but I will wait until Peiming's loop emitter is in to avoid conflicts.
Reviewed By: wrengr
Differential Revision: https://reviews.llvm.org/D136008
Xiang Li [Tue, 18 Oct 2022 00:47:48 +0000 (17:47 -0700)]
[NFC] use llvm_unreachable instead of return on switch which all cases are covered.
Adrian Prantl [Fri, 14 Oct 2022 23:45:01 +0000 (16:45 -0700)]
Make sure Target::EvaluateExpression() passes up an error instead of silently dropping it.
When UserExpression::Evaluate() fails and doesn't return a ValueObject there is no vehicle for returning the error in the return value.
This behavior can be observed by applying the following patch:
diff --git a/lldb/source/Target/Target.cpp b/lldb/source/Target/Target.cpp
index
f1a311b7252c..
58c03ccdb068 100644
--- a/lldb/source/Target/Target.cpp
+++ b/lldb/source/Target/Target.cpp
@@ -2370,6 +2370,7 @@ UserExpression *Target::GetUserExpressionForLanguage(
Expression::ResultType desired_type,
const EvaluateExpressionOptions &options, ValueObject *ctx_obj,
Status &error) {
+ error.SetErrorStringWithFormat("Ha ha!"); return nullptr;
auto type_system_or_err = GetScratchTypeSystemForLanguage(language);
if (auto err = type_system_or_err.takeError()) {
error.SetErrorStringWithFormat(
and then running
$ lldb -o "p 1"
(lldb) p 1
(lldb)
This patch fixes this by creating an empty result ValueObject that wraps the error.
Differential Revision: https://reviews.llvm.org/D135998
Adrian Prantl [Tue, 18 Oct 2022 00:27:10 +0000 (17:27 -0700)]
Revert "Make sure Target::EvaluateExpression() passes up an error instead of silently dropping it."
This reverts commit
a31a5da3c7d7393749a43dbc678fd28fb94d07f6.
Nathan Ridge [Tue, 18 Oct 2022 00:15:40 +0000 (20:15 -0400)]
[clangd] Update 'using enum' semantic highlighting testcase to use the 'definition' modifier
Che-Yu Wu [Tue, 18 Oct 2022 00:03:47 +0000 (00:03 +0000)]
[MLIR] Vectorize tensor.extract on 1-d tensor
This patch implements the vectorization of tensor.extract for the
basic 1-d lookup case. It only vectorizes the tensor.extract to a
vector.gather when the op extracts value from an 1-d tensor.
Related discussion: https://github.com/iree-org/iree/issues/9198
Reviewed By: dcaballe
Differential Revision: https://reviews.llvm.org/D133786
Koakuma [Tue, 18 Oct 2022 00:01:55 +0000 (00:01 +0000)]
[SPARC] Make calls to function with big return values work
Implement CanLowerReturn and associated CallingConv changes for SPARC/SPARC64.
In particular, for SPARC64 there's new `RetCC_Sparc64_*` functions that handles the return case of the calling convention.
It uses the same analysis as `CC_Sparc64_*` family of funtions, but fails if the return value doesn't fit into the return registers.
This makes calls to functions with big return values converted to an sret function as expected, instead of crashing LLVM.
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D132465
Nathan Ridge [Mon, 17 Oct 2022 22:53:43 +0000 (18:53 -0400)]
[clangd] Update testcase for issue 1222 to use the 'definition' modifier
Jordan Rupprecht [Mon, 17 Oct 2022 23:54:37 +0000 (16:54 -0700)]
Dan Gohman [Mon, 17 Oct 2022 20:36:19 +0000 (13:36 -0700)]
[wasm-ld] Define a `__heap_end` symbol marking the end of allocated memory.
Define a `__heap_end` symbol that marks the end of the memory region
that starts at `__heap_base`. This will allow malloc implementations to
know how much memory they can use at `__heap_base` even if someone has
done a `memory.grow` before they can initialize their state.
Differential Revision: https://reviews.llvm.org/D136110
Arthur Eubanks [Mon, 17 Oct 2022 23:37:05 +0000 (16:37 -0700)]
[NFC][SROA] Update comment to use opaque pointers for clarity
Volodymyr Sapsai [Mon, 17 Oct 2022 23:21:59 +0000 (16:21 -0700)]
[ODRHash] Hash `ObjCProtocolDecl` and diagnose discovered mismatches.
Differential Revision: https://reviews.llvm.org/D130324
Michael Jones [Fri, 14 Oct 2022 21:03:46 +0000 (14:03 -0700)]
[libc] add putc, fputc, and putchar
These three functions are simple, but needed for libc build testing.
Reviewed By: lntue
Differential Revision: https://reviews.llvm.org/D135990
Jacques Pienaar [Mon, 17 Oct 2022 23:28:46 +0000 (16:28 -0700)]
[mlir][quant] Initial bytecode encoding for quantized types
Add bytecode encoding for quantized types. These mostly follow the
storage representation of these.
Differential Revision: https://reviews.llvm.org/D136004
Maksim Panchenko [Mon, 17 Oct 2022 21:15:52 +0000 (14:15 -0700)]
[BOLT][NFCI] Avoid calling registerName() twice
Calling registerName() for the same symbol twice, even with a different
size, has no effect other than the lookup overhead. Avoid the
redundancy.
Fixes facebookincubator/BOLT#299
Reviewed By: Amir
Differential Revision: https://reviews.llvm.org/D136115
Xiang Li [Mon, 17 Oct 2022 22:50:49 +0000 (15:50 -0700)]
[NFC] Fix warning on no return after switch.
Artem Belevich [Wed, 12 Oct 2022 23:41:28 +0000 (16:41 -0700)]
Do not append terminating NUL to the binary string with embedded fatbin.
Extra NUL does not impact functionality of the generated code, but it confuses
various NVIDIA tools used to examine embedded GPU binaries.
Differential Revision: https://reviews.llvm.org/D135832
Louis Dionne [Tue, 11 Oct 2022 18:53:14 +0000 (14:53 -0400)]
[libc++] Fix std::function's handling of blocks under Objc ARC
Previously, some uses of std::function with blocks would crash when ARC was enabled.
rdar://
100907096
Differential Revision: https://reviews.llvm.org/D135706
Joe Loser [Mon, 17 Oct 2022 00:47:26 +0000 (18:47 -0600)]
[libc++] Fix missing requires clause on variant operator<=>
`std::variant::operator<=>` is missing a requires clause ensuring that
`operator<=>` only exists when all of the types in the variant are
`three_way_comparable`.
Add the missing requires clause and adjust the existing test which was
incorrect.
Fixes https://github.com/llvm/llvm-project/issues/58192.
Differential Revision: https://reviews.llvm.org/D136050
Daniel Sanders [Mon, 17 Oct 2022 18:25:56 +0000 (11:25 -0700)]
[instsimplify] Move (extelt (inselt Vec, Value, Index), Index) -> Value from InstCombine
As requested in https://reviews.llvm.org/D135625#3858141
Differential Revision: https://reviews.llvm.org/D136099
Adrian Prantl [Fri, 14 Oct 2022 23:45:01 +0000 (16:45 -0700)]
Make sure Target::EvaluateExpression() passes up an error instead of silently dropping it.
When UserExpression::Evaluate() fails and doesn't return a ValueObject there is no vehicle for returning the error in the return value.
This behavior can be observed by applying the following patch:
diff --git a/lldb/source/Target/Target.cpp b/lldb/source/Target/Target.cpp
index
f1a311b7252c..
58c03ccdb068 100644
--- a/lldb/source/Target/Target.cpp
+++ b/lldb/source/Target/Target.cpp
@@ -2370,6 +2370,7 @@ UserExpression *Target::GetUserExpressionForLanguage(
Expression::ResultType desired_type,
const EvaluateExpressionOptions &options, ValueObject *ctx_obj,
Status &error) {
+ error.SetErrorStringWithFormat("Ha ha!"); return nullptr;
auto type_system_or_err = GetScratchTypeSystemForLanguage(language);
if (auto err = type_system_or_err.takeError()) {
error.SetErrorStringWithFormat(
and then running
$ lldb -o "p 1"
(lldb) p 1
(lldb)
This patch fixes this by creating an empty result ValueObject that wraps the error.
Differential Revision: https://reviews.llvm.org/D135998
Jeremy Furtek [Mon, 17 Oct 2022 21:02:09 +0000 (14:02 -0700)]
[mlir][LLVMIR] Update LLVMIR fastmath to use EnumAttr tblgen classes
This diff updates the `fastmath` attribute in the LLVMIR dialect to use `tblgen`
classes that were developed after the initial LLVMIR `fastmath` implementation.
Using the `EnumAttr` `tblgen` classes brings the LLVMIR `fastmath` attribute in
line with other dialects, and eliminates some of the custom printing and parsing
code in the LLVMIR dialect.
Subsequent commits will further reduce the custom processing code for the LLVMIR
`fastmath` attribute by unifying printing/parsing functionality between the
LLVMIR and `arith` `fastmath` attributes. (The actual attributes will remain
separate, but the printing and parsing will be made generic, and will be usable
by other dialects/attributes.)
Reviewed By: ftynse
Differential Revision: https://reviews.llvm.org/D135289
Arthur Eubanks [Mon, 17 Oct 2022 21:29:30 +0000 (14:29 -0700)]
Revert "llvm-reduce: Color output of child processes"
This reverts commit
86e9181ded7c5b6aa67a3a84089fce850c84f27a.
Seems to be causing bot failures: https://lab.llvm.org/buildbot#builders/5/builds/28313
Plus as noted on D135632 it seems to interact badly with parallel reduction.
Xiang Li [Sun, 16 Oct 2022 00:36:29 +0000 (17:36 -0700)]
[HLSL] CodeGen hlsl resource binding.
''register(ID, space)'' like register(t3, space1) will be translated into
i32 3, i32 1 as the last 2 operands for resource annotation metadata.
NamedMetadata for CBuffers and SRVs are added as "hlsl.srvs" and "hlsl.cbufs".
Reviewed By: beanz
Differential Revision: https://reviews.llvm.org/D130951
Arthur Eubanks [Wed, 12 Oct 2022 23:18:44 +0000 (16:18 -0700)]
[lldb] Print newline between found types
Or else multiple entries end up overlapping on the same line.
Reviewed By: DavidSpickett
Differential Revision: https://reviews.llvm.org/D135827
Christian Kandeler [Mon, 17 Oct 2022 21:12:39 +0000 (17:12 -0400)]
[clangd] Implement semantic token modifier "definition"
Reviewed By: sammccall
Differential Revision: https://reviews.llvm.org/D127403
Jeremy Furtek [Mon, 17 Oct 2022 18:16:38 +0000 (11:16 -0700)]
[mlir][ods] Do not print default-valued attributes when the value is equal to the default
This diff causes the `tblgen`-erated print() function to skip printing a
`DefaultValuedAttr` attribute when the value is equal to the default.
This feature will reduce the amount of custom printing code that needs to be
written by users a relatively common scenario. As a motivating example, for the
fastmath flags in the LLVMIR dialect, we would prefer to print this:
```
%0 = llvm.fadd %arg0, %arg1 : f32
```
instead of this:
```
%0 = llvm.fadd %arg0, %arg1 {fastmathFlags = #llvm.fastmath<none>} : f32
```
This diff makes the handling of print functionality for default-valued attributes
standard.
This is an updated version of https://reviews.llvm.org/D135398, without the per-attribute bit to control printing.
Reviewed By: Mogball
Differential Revision: https://reviews.llvm.org/D135993
Craig Topper [Mon, 17 Oct 2022 19:40:32 +0000 (12:40 -0700)]
[RISCV] Add basic support for the sifive-7-series short forward branch optimization.
sifive-7-series has macrofusion support to convert a branch over
a single instruction into a conditional instruction. This can be
an improvement if the branch is hard to predict.
This patch adds support for the most basic case, a branch over a
move instruction. This is implemented as a pseudo instruction so
we can hide the control flow until all code motion passes complete.
I've disabled a recent select optimization if this feature is enabled
in the subtarget.
Related gcc patch for the same optimization https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg211045.html
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D135814
Chia-hung Duan [Sat, 15 Oct 2022 20:34:51 +0000 (20:34 +0000)]
[scudo] Change region size from 1 MB to 2 MB in tests
In SizeClassAllocator64, the RegionBeg is determined by RegionBase +
random offset. The offset is n pages, where n is a random number less or
equal to 16. However, on certain platforms which have large page size,
it may end up immediately OOM without mapping any block pages. For
example,
PageSize = 64 KB, RegionSize = 1 MB
Suppose the random number n is 16, then the random offset will be
64 * 16 = 1024 KB which is equal to the RegionSize.
On most platforms we don't have such large page size and we have
different PRNG(pseudo random number generator) behaviors, thus we didn't
hit any failures before. Given that this now only affects the tests,
only increase the region size is enough.
Will revisit the logic of calculating the random offset.
Differential Revision: https://reviews.llvm.org/D136025
Matthias Braun [Mon, 12 Sep 2022 16:17:38 +0000 (09:17 -0700)]
ControlHeightReduction: Remove assert check in shouldApply
Remove assertion checking for non-empty `ProfileSummaryInfo`.
Differential Revision: https://reviews.llvm.org/D133706
Fangrui Song [Mon, 17 Oct 2022 20:09:39 +0000 (13:09 -0700)]
[ELF] Inline computeAddend. NFC
Florian Hahn [Mon, 17 Oct 2022 19:30:42 +0000 (20:30 +0100)]
[ConstraintElim] Use helper to allow overflow for coefficients of GEPs
If the arithmetic for indices of inbounds GEPs overflows, the result is
poison. This means it is also OK for the coefficients to overflow. GEP
decomposition is limited to cases where the index size is <= 64 bit,
which can be represented by int64_t used for the coefficients in the
constraint system.
Fangrui Song [Mon, 17 Oct 2022 18:57:17 +0000 (11:57 -0700)]
[ELF] Move ELFT-agnostic relocation code to processAux
Renaud Kauffmann [Mon, 17 Oct 2022 18:41:35 +0000 (11:41 -0700)]
Document for Aliasing analysis in FIR
Fangrui Song [Mon, 17 Oct 2022 18:44:28 +0000 (11:44 -0700)]
[ELF] Move ELFT-agnostic relocation code to processAux. NFC
Han Zhu [Thu, 22 Sep 2022 01:01:49 +0000 (18:01 -0700)]
[X86] Lower vector interleave into unpck and perm
[This Godbolt link](https://godbolt.org/z/s17Kv1s9T) shows different codegen between clang and gcc for a transpose operation.
clang result:
```
vmovdqu xmm0, xmmword ptr [rcx + rax]
vmovdqu xmm1, xmmword ptr [rcx + rax + 16]
vmovdqu xmm2, xmmword ptr [r8 + rax]
vmovdqu xmm3, xmmword ptr [r8 + rax + 16]
vpunpckhbw xmm4, xmm2, xmm0
vpunpcklbw xmm0, xmm2, xmm0
vpunpcklbw xmm2, xmm3, xmm1
vpunpckhbw xmm1, xmm3, xmm1
vmovdqu xmmword ptr [rdi + 2*rax + 48], xmm1
vmovdqu xmmword ptr [rdi + 2*rax + 32], xmm2
vmovdqu xmmword ptr [rdi + 2*rax], xmm0
vmovdqu xmmword ptr [rdi + 2*rax + 16], xmm4
```
gcc result:
```
vmovdqu ymm3, YMMWORD PTR [rdi+rax]
vpunpcklbw ymm1, ymm3, YMMWORD PTR [rsi+rax]
vpunpckhbw ymm0, ymm3, YMMWORD PTR [rsi+rax]
vperm2i128 ymm2, ymm1, ymm0, 32
vperm2i128 ymm1, ymm1, ymm0, 49
vmovdqu YMMWORD PTR [rcx+rax*2], ymm2
vmovdqu YMMWORD PTR [rcx+32+rax*2], ymm1
```
clang's code is roughly 15% slower than gcc's when evaluated on an internal compression benchmark.
The loop vectorizer generates the following shufflevector intrinsic:
```
%interleaved.vec = shufflevector <32 x i8> %a, <32 x i8> %b, <64 x i32> <i32 0, i32 32, i32 1, i32 33, i32 2, i32 34, i32 3, i32 35, i32 4, i32 36, i32 5, i32 37, i32 6, i32 38, i32 7, i32 39, i32 8, i32 40, i32 9, i32 41, i32 10, i32 42, i32 11, i32 43, i32 12, i32 44, i32 13, i32 45, i32 14, i32 46, i32 15, i32 47, i32 16, i32 48, i32 17, i32 49, i32 18, i32 50, i32 19, i32 51, i32 20, i32 52, i32 21, i32 53, i32 22, i32 54, i32 23, i32 55, i32 24, i32 56, i32 25, i32 57, i32 26, i32 58, i32 27, i32 59, i32 28, i32 60, i32 29, i32 61, i32 30, i32 62, i32 31, i32 63>
```
which is lowered to SelectionDAG:
```
t2: v32i8,ch = CopyFromReg t0, Register:v32i8 %0
t6: v64i8 = concat_vectors t2, undef:v32i8
t4: v32i8,ch = CopyFromReg t0, Register:v32i8 %1
t7: v64i8 = concat_vectors t4, undef:v32i8
t8: v64i8 = vector_shuffle<0,64,1,65,2,66,3,67,4,68,5,69,6,70,7,71,8,72,9,73,10,74,11,75,12,76,13,77,14,78,15,79,16,80,17,81,18,82,19,83,20,84,21,85,22,86,23,87,24,88,25,89,26,90,27,91,28,92,29,93,30,94,31,95> t6, t7
```
So far this `vector_shuffle` is good enough for us to pattern-match and transform, but as we go down the SelectionDAG pipeline, it got split into smaller shuffles. During dagcombine1, the shuffle is split by `foldShuffleOfConcatUndefs`.
```
// shuffle (concat X, undef), (concat Y, undef), Mask -->
// concat (shuffle X, Y, Mask0), (shuffle X, Y, Mask1)
t2: v32i8,ch = CopyFromReg t0, Register:v32i8 %0
t4: v32i8,ch = CopyFromReg t0, Register:v32i8 %1
t19: v32i8 = vector_shuffle<0,32,1,33,2,34,3,35,4,36,5,37,6,38,7,39,8,40,9,41,10,42,11,43,12,44,13,45,14,46,15,47> t2, t4
t15: ch,glue = CopyToReg t0, Register:v32i8 $ymm0, t19
t20: v32i8 = vector_shuffle<16,48,17,49,18,50,19,51,20,52,21,53,22,54,23,55,24,56,25,57,26,58,27,59,28,60,29,61,30,62,31,63> t2, t4
t17: ch,glue = CopyToReg t15, Register:v32i8 $ymm1, t20, t15:1
```
With `foldShuffleOfConcatUndefs` commented out, the vector is still split later by the type legalizer, which comes after dagcombine1, because v64i8 is not a legal type in AVX2 (64 * 8 = 512 bits while ymm = 256 bits). There doesn't seem to be a good way to avoid this split. Lowering the `vector_shuffle` into unpck and perm during dagcombine1 is too early. Therefore, although somewhat inconvenient, we decided to go with pattern-matching a pair vector shuffles later in the SelectionDAG pipeline, as part of `lowerV32I8Shuffle`.
The code looks at the two operands of the first shuffle it encounters, iterates through the users of the operands, and tries to find two shuffles that are consecutive interleaves. Once the pattern is found, it lowers them into unpcks and perms. It returns the perm for the shuffle that's currently being lowered (have ISel modify the DAG), and replaces the other shuffle in place.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D134477
Philip Reames [Mon, 17 Oct 2022 17:09:58 +0000 (10:09 -0700)]
[clang][RISCV] Set vscale_range attribute based on presence of "v" extension
This follows the path that AArch64 SVE has taken. Doing this via a function attribute set in the frontend is basically a workaround for the fact that several analyzes which need the information (i.e. known bits, lvi, scev) can't easily use TTI without significant amounts of plumbing changes.
This patch hard codes "v" numbers, and directly follows the SVE precedent as a result. In a follow up, I hope to drive this from RISCVISAInfo.h/cpp instead, but the MinVLen number being returned from that interface seemed to always be 0 (which is wrong), and I haven't figured out what's going wrong there.
Differential Revision: https://reviews.llvm.org/D135894
Zahira Ammarguellat [Mon, 17 Oct 2022 13:36:18 +0000 (09:36 -0400)]
Fix LIT test func-attr.c added by https://reviews.llvm.org/D135097.
Differential Revision: https://reviews.llvm.org/D136084
Fangrui Song [Mon, 17 Oct 2022 18:01:10 +0000 (11:01 -0700)]
[ELF] Make relocateAlloc target specific. NFC
The target-specific code (AArch64, PPC64) does not fit into the generic code and
adds virtual function overhead. Move relocateAlloc into ELF/Arch/ instead. This
removes many virtual functions (relaxTls*). In addition, this helps get rid of
getRelocTargetVA dispatch and many RelExpr members in the future.
Sjoerd Meijer [Mon, 17 Oct 2022 17:53:38 +0000 (23:23 +0530)]
Recommit "[LoopFlatten] Enable it by default"
The sanitizer bots turned green again after another change went in, i.e.
revert
26dd64ba9cfabe5474bb207f3b7099965f81fed7, so I don't think this
patch was causing the problems.
Arthur Eubanks [Mon, 17 Oct 2022 05:10:58 +0000 (22:10 -0700)]
[llvm-reduce] Reduce comdats
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D136054
Craig Topper [Mon, 17 Oct 2022 17:00:24 +0000 (10:00 -0700)]
[TargetLowering][RISCV][Sparc] Don't emit zero check in CTTZTableLookup for CTTZ_ZERO_UNDEF.
The code incorrectly checked for CTLZ_ZERO_UNDEF instead of
CTTZ_ZERO_UNDEF.
While I was there I flipped the condition into an early out.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D136010
Kazu Hirata [Mon, 17 Oct 2022 17:15:10 +0000 (10:15 -0700)]
[IR] Rename FuncletPadInst::getNumArgOperands to arg_size (NFC)
This patch renames FuncletPadInst::getNumArgOperands to arg_size for
consistency with CallBase, where getNumArgOperands was removed in
favor of arg_size in commit
3e1c787b3160bed4146d3b2b5f922aeed3caafd7
Differential Revision: https://reviews.llvm.org/D136048
Fangrui Song [Mon, 17 Oct 2022 17:08:47 +0000 (10:08 -0700)]
[ELF] Move PPC64 above. NFC
Prepare for a refactoring.
Fangrui Song [Mon, 17 Oct 2022 16:58:51 +0000 (16:58 +0000)]
[AArch64] Fix warnings
Sjoerd Meijer [Mon, 17 Oct 2022 16:41:41 +0000 (22:11 +0530)]
Revert "[LoopFlatten] Enable it by default"
This reverts commit
233659c7ae9b83b64a9f739d340736bca39c3d2e.
I see some sanitizer build bot failures. Not sure if it is change
causing it, but let's see if a revert returns the bots to green...