Mircea Trofin [Tue, 16 Nov 2021 17:28:50 +0000 (09:28 -0800)]
Revert "[benchmarks] Move libcxx's fork of google/benchmark and llvm/utils'"
This reverts commit
c6f7b720ecfa6db40c648eb05e319f8a817110e9.
Some buildbots are failing, will investigate and reland.
Example:
https://lab.llvm.org/buildbot#builders/138/builds/14067
https://lab.llvm.org/buildbot#builders/73/builds/20159
Philip Reames [Tue, 16 Nov 2021 17:23:41 +0000 (09:23 -0800)]
[tests] Add coverage for different forms of X - urem X, Y
Philip Reames [Tue, 16 Nov 2021 17:22:18 +0000 (09:22 -0800)]
autogen a SCEV test file
Adrian Prantl [Tue, 16 Nov 2021 17:17:32 +0000 (09:17 -0800)]
fix decorator
Mircea Trofin [Thu, 14 Oct 2021 05:43:08 +0000 (22:43 -0700)]
[benchmarks] Move libcxx's fork of google/benchmark and llvm/utils'
under third-party
This change:
- moves the libcxx copy of `google/benchmark` to
`third-party/benchmkark`
- points the 2 uses of the library (libcxx and llvm/utils) to this copy
We picked the licxx copy because it is the most up to date.
Differential Revision: https://reviews.llvm.org/D112012
Adrian Prantl [Tue, 16 Nov 2021 17:09:49 +0000 (09:09 -0800)]
Skip tests on older versions of clang
Adrian Prantl [Tue, 16 Nov 2021 16:45:40 +0000 (08:45 -0800)]
Increase gdbremote timeout.
I'm still seeing random timeouts on green dragon.
Adrian Prantl [Tue, 16 Nov 2021 16:44:15 +0000 (08:44 -0800)]
typo
Kazu Hirata [Tue, 16 Nov 2021 17:01:56 +0000 (09:01 -0800)]
[llvm] Use range-for loops (NFC)
William S. Moses [Tue, 16 Nov 2021 01:13:33 +0000 (20:13 -0500)]
[MLIR][LLVM] Permit integer types in switch other than i32
LLVM switchop currently only permits i32. Both LLVM IR and MLIR Standard switch permit other integer types leading to an illegal state when lowering an i8 switch from MLIR standard
Reviewed By: mehdi_amini
Differential Revision: https://reviews.llvm.org/D113955
Philip Reames [Tue, 16 Nov 2021 16:48:16 +0000 (08:48 -0800)]
Add a hasPoisonGeneratingFlags proxy wrapper to Instruction [NFC]
This just cuts down on casts to Operator.
Nilay Vaish [Tue, 16 Nov 2021 16:37:55 +0000 (11:37 -0500)]
[libc++] Add introsort to avoid O(n^2) behavior
This commit adds a benchmark that tests std::sort on an adversarial inputs,
and uses introsort in std::sort to avoid O(n^2) behavior on adversarial
inputs.
Inputs where partitions are unbalanced even after 2 log(n) pivots have
been selected, the algorithm switches to heap sort to avoid the
possibility of spending O(n^2) time on sorting the input.
Benchmark results show that the intro sort implementation does
significantly better.
Benchmarking results before this change. Time represents the sorting
time required per element:
----------------------------------------------------------------------------------------------------------
Benchmark Time CPU Iterations
----------------------------------------------------------------------------------------------------------
BM_Sort_uint32_QuickSortAdversary_1 3.75 ns 3.74 ns
187432960
BM_Sort_uint32_QuickSortAdversary_4 3.05 ns 3.05 ns
231211008
BM_Sort_uint32_QuickSortAdversary_16 2.45 ns 2.45 ns
288096256
BM_Sort_uint32_QuickSortAdversary_64 32.8 ns 32.8 ns
21495808
BM_Sort_uint32_QuickSortAdversary_256 132 ns 132 ns 5505024
BM_Sort_uint32_QuickSortAdversary_1024 498 ns 497 ns 1572864
BM_Sort_uint32_QuickSortAdversary_16384 3846 ns 3845 ns 262144
BM_Sort_uint32_QuickSortAdversary_262144 61431 ns 61400 ns 262144
BM_Sort_uint64_QuickSortAdversary_1 3.93 ns 3.92 ns
181141504
BM_Sort_uint64_QuickSortAdversary_4 3.10 ns 3.09 ns
222560256
BM_Sort_uint64_QuickSortAdversary_16 2.50 ns 2.50 ns
283639808
BM_Sort_uint64_QuickSortAdversary_64 33.2 ns 33.2 ns
21757952
BM_Sort_uint64_QuickSortAdversary_256 132 ns 132 ns 5505024
BM_Sort_uint64_QuickSortAdversary_1024 478 ns 477 ns 1572864
BM_Sort_uint64_QuickSortAdversary_16384 3932 ns 3930 ns 262144
BM_Sort_uint64_QuickSortAdversary_262144 61646 ns 61615 ns 262144
Benchmarking results after this change:
----------------------------------------------------------------------------------------------------------
Benchmark Time CPU Iterations
----------------------------------------------------------------------------------------------------------
BM_Sort_uint32_QuickSortAdversary_1 6.31 ns 6.30 ns
107741184
BM_Sort_uint32_QuickSortAdversary_4 4.51 ns 4.50 ns
158859264
BM_Sort_uint32_QuickSortAdversary_16 3.00 ns 3.00 ns
223608832
BM_Sort_uint32_QuickSortAdversary_64 44.8 ns 44.8 ns
15990784
BM_Sort_uint32_QuickSortAdversary_256 69.0 ns 68.9 ns 9961472
BM_Sort_uint32_QuickSortAdversary_1024 118 ns 118 ns 6029312
BM_Sort_uint32_QuickSortAdversary_16384 175 ns 175 ns 4194304
BM_Sort_uint32_QuickSortAdversary_262144 210 ns 210 ns 3407872
BM_Sort_uint64_QuickSortAdversary_1 6.75 ns 6.73 ns
103809024
BM_Sort_uint64_QuickSortAdversary_4 4.53 ns 4.53 ns
160432128
BM_Sort_uint64_QuickSortAdversary_16 2.98 ns 2.97 ns
234356736
BM_Sort_uint64_QuickSortAdversary_64 44.3 ns 44.3 ns
15990784
BM_Sort_uint64_QuickSortAdversary_256 69.2 ns 69.2 ns
10223616
BM_Sort_uint64_QuickSortAdversary_1024 119 ns 119 ns 6029312
BM_Sort_uint64_QuickSortAdversary_16384 173 ns 173 ns 4194304
BM_Sort_uint64_QuickSortAdversary_262144 212 ns 212 ns 3407872
Differential Revision: https://reviews.llvm.org/D113413
Louis Dionne [Tue, 16 Nov 2021 16:26:56 +0000 (11:26 -0500)]
[libc++] Add missed comment in https://reviews.llvm.org/D113910
Mark de Wever [Tue, 16 Nov 2021 15:04:29 +0000 (16:04 +0100)]
[libc++][nfc] Improve standard conformance.
The return type of the deleted functions doesn't match the synopsis in
the standard.
Reviewed By: #libc, ldionne
Differential Revision: https://reviews.llvm.org/D114000
David Spickett [Thu, 11 Nov 2021 12:28:39 +0000 (12:28 +0000)]
[libcxxabi/runtimes] Set LLVM_HOST_TRIPLE in runtimes build
This allows tests to tell if they're running natively.
Those tests are libcxxabi/test/native/arm-linux-eabi.
Which were running on Linaro's bots but became unsupported
when we switched to the runtimes build.
Reviewed By: #libc_abi, phosek
Differential Revision: https://reviews.llvm.org/D113663
Mark de Wever [Tue, 16 Nov 2021 16:29:40 +0000 (17:29 +0100)]
[libc++][doc] Update format implementation status.
Nilay Vaish [Tue, 16 Nov 2021 16:25:42 +0000 (11:25 -0500)]
[libc++] Remove not needed call to __is_long()
The string is known to be long since __grow_by unconditionally calls
__set_long_cap().
Differential Revision: https://reviews.llvm.org/D113910
David Sherwood [Tue, 16 Nov 2021 14:19:18 +0000 (14:19 +0000)]
[AArch64] Fix TypeSize->uint64_t implicit conversion in AArch64ISelLowering::hasAndNot
For now I've just changed the code to only return true from
AArch64ISelLowering::hasAndNot if the vector is fixed-length.
Once we have the right patterns or DAG combines to use bic/bif
we can also enable this for SVE.
Test added here:
CodeGen/AArch64/vselect-constants.ll
Differential Revision: https://reviews.llvm.org/D113994
Matheus Izvekov [Mon, 15 Nov 2021 23:32:48 +0000 (00:32 +0100)]
[libcxx] CI: only build native target for bootstrapping-build
Signed-off-by: Matheus Izvekov <mizvekov@gmail.com>
Reviewed By: #libc, ldionne
Differential Revision: https://reviews.llvm.org/D113950
Quinn Pham [Mon, 15 Nov 2021 22:22:00 +0000 (16:22 -0600)]
[NFC][clang] Inclusive language: replace master with main in convert_arm_neon.py
[NFC] As part of using inclusive language within the llvm project and to
match the renamed master branch, this patch replaces master with main in
`convert_arm_neon.py`.
Reviewed By: kristof.beyls
Differential Revision: https://reviews.llvm.org/D113942
Dmitry Vyukov [Tue, 16 Nov 2021 13:45:07 +0000 (14:45 +0100)]
tsan: disable bench_threads.cpp on aarch64
The new test started failing on bots with:
CHECK failed: tsan_rtl.cpp:327 "((addr + size)) <= ((TraceMemEnd()))"
(0xf06200e03010, 0xf06200000000) (tid=4073872)
https://lab.llvm.org/buildbot#builders/179/builds/1761
This is a latent bug in aarch64 virtual address space layout,
there is not enough address space to fit traces for all threads.
But since the trace space is going away with the new tsan runtime
(D112603), disable the test.
Reviewed By: melver
Differential Revision: https://reviews.llvm.org/D113990
Dmitry Vyukov [Tue, 16 Nov 2021 13:29:02 +0000 (14:29 +0100)]
tsan: fix crash during thread exit
Use of gethostent provokes caching of some resources inside of libc.
They are freed in __libc_thread_freeres very late in thread lifetime,
after our ThreadFinish. __libc_thread_freeres calls free which
previously crashed in malloc hooks.
Fix it by setting ignore_interceptors for finished threads,
which in turn prevents malloc hooks.
Reviewed By: melver
Differential Revision: https://reviews.llvm.org/D113989
Andrzej Warzynski [Thu, 11 Nov 2021 14:54:00 +0000 (14:54 +0000)]
[flang][fir] Add missing `HasParent` in `fir_DTEntryOp`
Differential Revision: https://reviews.llvm.org/D113674
Florian Hahn [Tue, 16 Nov 2021 15:39:12 +0000 (15:39 +0000)]
[llvm-reduce] Move code to check chunk to function, to enable reuse (NFC).
This patch moves the logic to clone and check a new chunk into a new
function, to allow re-use in a follow-up patch that implements parallel
reductions.
Reviewed By: dblaikie
Differential Revision: https://reviews.llvm.org/D113856
Christian Kühnel [Mon, 15 Nov 2021 14:37:20 +0000 (14:37 +0000)]
[NFC] disabling clang-tidy check readability-identifier-naming in Protocol.h
The file follows the LSP syntax, so we're intentially deviating
from the LLVM coding standard.
Differential Revision: https://reviews.llvm.org/D113889
Ahsan Saghir [Fri, 29 Oct 2021 12:05:11 +0000 (07:05 -0500)]
[PowerPC] Allow MMA built-ins to accept non-void pointers and arrays
Calls to MMA builtins that take pointer to void
do not accept other pointers/arrays whereas normal
functions with the same parameter do. This patch
allows MMA built-ins to accept non-void pointers
and arrays.
Reviewed By: nemanjai
Differential Revision: https://reviews.llvm.org/D113306
Christian Kühnel [Mon, 15 Nov 2021 15:10:13 +0000 (15:10 +0000)]
[NFC][clangd] fix llvm-namespace-comment finding
Fixing the clang-tidy finding.
Differential Revision: https://reviews.llvm.org/D113895
Mark de Wever [Tue, 16 Nov 2021 15:02:26 +0000 (16:02 +0100)]
[libc++][format][nfc] Remove dead code.
This was an early part of the prototype. This has never been shipped
enabled and the final version of this code looks completely different.
Dmitry Vyukov [Tue, 16 Nov 2021 08:18:00 +0000 (09:18 +0100)]
tsan: de-hardcode number of unused bits in trace events
Precisely specifying the unused parts of the bitfield is critical for
performance. If we don't specify them, compiler will generate code to load
the old value and shuffle it to extract the unused bits to apply to the new
value. If we specify the unused part and store 0 in there, all that
unnecessary code goes away (store of the 0 const is combined with other
constant parts).
I don't see a good way to ensure we cover all of u64 bits with fields.
So at least introduce named kUnusedBits consts and check that bits
sum up to 64.
Depends on D113978.
Reviewed By: melver
Differential Revision: https://reviews.llvm.org/D113979
Dmitry Vyukov [Tue, 16 Nov 2021 08:14:09 +0000 (09:14 +0100)]
tsan: use smaller trace parts for Go
In the old runtime we used to use different number of trace parts
for C++ and Go to reduce trace memory consumption for Go.
But now it's easier and better to use smaller parts because
we already use minimal possible number of parts for C++ (3).
Reviewed By: melver
Differential Revision: https://reviews.llvm.org/D113978
Mark de Wever [Tue, 16 Nov 2021 14:56:59 +0000 (15:56 +0100)]
[libc++][doc] Fix copy pasted comment.
Mark de Wever [Tue, 16 Nov 2021 14:55:17 +0000 (15:55 +0100)]
[libc++][doc] Add a todo.
As suggested in D113831.
LLVM GN Syncbot [Tue, 16 Nov 2021 14:52:00 +0000 (14:52 +0000)]
[gn build] Port
5baa4ee30b5c
Mark de Wever [Sat, 13 Nov 2021 18:43:32 +0000 (19:43 +0100)]
[libc++][NFC] Move format_to_n_result.
Places `format_to_n_result` to its own file. While working on D112361 it
turns out the type will be used outside the format header.
Reviewed By: #libc, Quuxplusone, Mordante
Differential Revision: https://reviews.llvm.org/D113831
Nicolas Vasilache [Tue, 16 Nov 2021 10:06:15 +0000 (10:06 +0000)]
[mlir][LLVM] Fix folding of LLVM::ExtractValueOp
Limit the backtracking along def-use chains when a prefix is encountered as it would generate incorrect foldings.
Differential Revision: https://reviews.llvm.org/D113975
Matt Devereau [Tue, 16 Nov 2021 14:36:13 +0000 (14:36 +0000)]
[AArch64][SVE] Remove arm-registered-target requirement on bfloat tests
Changes in https://reviews.llvm.org/D113489 caused buildbot failures
Jon Chesterfield [Tue, 16 Nov 2021 14:36:06 +0000 (14:36 +0000)]
[amdgpu] Don't crash on empty global ctor/dtor
Global ctor/dtor can be an empty array, which is a Constant not a
ConstantArray. The cast<ConstantArray> therefore asserts / crashes.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D113800
Sanjay Patel [Tue, 16 Nov 2021 14:18:18 +0000 (09:18 -0500)]
[InstCombine] canonicalize icmp with trunc op into mask and cmp, part 2
If C is a high-bit mask:
(trunc X) u< C --> (X & C) != C (are any masked-high-bits clear?)
If C is low-bit mask:
(trunc X) u> C --> (X & ~C) != 0 (are any masked-high-bits set?)
If C is not-of-power-of-2 (one clear bit):
(trunc X) u> C --> (X & (C+1)) == C+1 (are all masked-high-bits set?)
This extends the fold added with:
acabad9ff6bf (https://alive2.llvm.org/ce/z/aFr7qV)
Using decomposeBitTestICmp() to generalize this is a planned follow-up, but that requires removing an inverse fold.
Here are Alive2 generalizations for these folds:
https://alive2.llvm.org/ce/z/u-ZpC_ (ult, the previous patch)
https://alive2.llvm.org/ce/z/YsuAu2 (ult, this patch)
https://alive2.llvm.org/ce/z/ekktQP (ugt, low bitmask)
https://alive2.llvm.org/ce/z/pJY9wR (ugt, one clear bit)
Differential Revision: https://reviews.llvm.org/D112634
Alexey Bataev [Fri, 12 Nov 2021 14:21:47 +0000 (06:21 -0800)]
[SLP]Improve cost of the gather nodes.
No need to count the final shuffle cost for the constants, gathering of
the constants is just a constant vector + extra inserts, if required.
Differential Revision: https://reviews.llvm.org/D113770
Jake Egan [Tue, 16 Nov 2021 14:14:43 +0000 (09:14 -0500)]
[AIX] XFAIL lto-comp-dir.ll for lack of .file directive support
This test explicitly checks for .file directives, which is not currently supported on AIX. This patch sets this test to XFAIL on AIX for now.
Reviewed By: shchenz
Differential Revision: https://reviews.llvm.org/D113640
Alexey Bataev [Tue, 16 Nov 2021 14:08:48 +0000 (06:08 -0800)]
[SLP]Fix windows build, NFC.
Need to put `IndexIdx` var to the list of captures.
Greg McGary [Fri, 5 Nov 2021 03:55:31 +0000 (20:55 -0700)]
[lld-macho][nfc] rename parsed-section types & variables
This is an NFC diff that prepares for pruning & relocating `__eh_frame`.
Along the way, I made the following changes to ...
* clarify usage of `section` vs. `subsection`
* remove `map` & `vec` from type names
* disambiguate class `Section` from template parameter `SectionHeader`.
Differential Revision: https://reviews.llvm.org/D113241
Jean Perier [Tue, 16 Nov 2021 13:52:35 +0000 (14:52 +0100)]
[flang] Allow write after non advancing read in IO runtime
1. To avoid overwriting the part of the record read in the non advancing read,
the furtherPositionInRecord field must be set to the max of the
furtherPositionInRecord and the positionInRecord at the beginning of the
IO write.
2. To allow any further read to succeed after the write, the unit
beganReadingRecord_ must be set to false when resetting the recordLength
during the write, otherwise, recordLength will not be computed in further
read and an assert is hit (at unit.cpp(398)).
The added unit test exercises both of these scenarios.
Differential Revision: https://reviews.llvm.org/D113740
Zbigniew Sarbinowski [Fri, 29 Oct 2021 18:35:17 +0000 (18:35 +0000)]
[SystemZ][z/OS] Fix warnings from unsigned int to long in 32-bit mode
This patch fixes the warnings which shows up when libcxx library started to be compiled in 32-bit mode on z/OS.
More specifically, the assignment from unsigned int to time_t aka long was flags as follows:
```
libcxx/include/c++/v1/__support/ibm/nanosleep.h:31:11: warning: implicit conversion changes signedness: 'unsigned int' to 'time_t' (aka 'long') [-Wsign-conversion]
__sec = sleep(static_cast<unsigned int>(__sec));
~ ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
libcxx/include/c++/v1/__support/ibm/nanosleep.h:36:36: warning: implicit conversion changes signedness: 'unsigned int' to 'long' [-Wsign-conversion]
__rem->tv_nsec = __micro_sec * 1000;
~ ~~~~~~~~~~~~^~~~~~
libcxx/include/c++/v1/__support/ibm/nanosleep.h:47:36: warning: implicit conversion changes signedness: 'unsigned int' to 'long' [-Wsign-conversion]
__rem->tv_nsec = __micro_sec * 1000;
~ ~~~~~~~~~~~~^~~~~~
3 warnings generated.
```
Here is a small test case illustrating the issue:
```
typedef long time_t ;
unsigned int sleep(unsigned int );
int main() {
time_t sec = 0;
#ifdef FIX
sec = static_cast<time_t>(sleep(static_cast<unsigned int>(sec)));
#else
sec = sleep(static_cast<unsigned int>(sec));
#endif
}
```
clang++ -c -Wsign-conversion -m32 t.C
```
t.C:8:9: warning: implicit conversion changes signedness: 'unsigned int' to 'time_t' (aka 'long') [-Wsign-conversion]
sec = sleep(static_cast<unsigned int>(sec));
~ ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Reviewed By: ldionne, #libc, Quuxplusone, Mordante
Differential Revision: https://reviews.llvm.org/D112837
Andrzej Warzynski [Fri, 12 Nov 2021 13:25:42 +0000 (13:25 +0000)]
[flang][CodeGen] Transform `fir.boxchar_len` to a sequence of LLVM MLIR
This patch extends the `FIRToLLVMLowering` pass in Flang by adding a
hook to transform `fir.boxchar_len` to a sequence of LLVM MLIR
instructions.
This is part of the upstreaming effort from the `fir-dev` branch in [1].
[1] https://github.com/flang-compiler/f18-llvm-project
Differential Revision: https://reviews.llvm.org/D113763
Originally written by:
Co-authored-by: Eric Schweitz <eschweitz@nvidia.com>
Alexey Bataev [Fri, 12 Nov 2021 19:22:12 +0000 (11:22 -0800)]
[SLP]Adjust GEP indices types when trying to build entries.
Need to adjust the types of GEPs indices when building the tree
entries/operands. Otherwise some of the nodes might differ and
vectorizer is unable to correctly find them and count their cost.
Differential Revision: https://reviews.llvm.org/D113792
Alexey Bataev [Tue, 16 Nov 2021 13:41:32 +0000 (05:41 -0800)]
[SLP][NFC]Add more tests for shuffles that can be optimized after SLP,
NFC.
Valentin Clement [Tue, 16 Nov 2021 13:37:05 +0000 (14:37 +0100)]
[fir] Add fir.gentypedesc conversion
Add conversion pattern for the GenTypeDescOp.
Convert to a global constant with an addressof.
This patch is part of the upstreaming effort from fir-dev branch.
Reviewed By: kiranchandramohan
Differential Revision: https://reviews.llvm.org/D113766
Co-authored-by: Eric Schweitz <eschweitz@nvidia.com>
Co-authored-by: Jean Perier <jperier@nvidia.com>
Joseph Huber [Tue, 16 Nov 2021 04:04:55 +0000 (23:04 -0500)]
[OpenMP] Fix initializer not working on AMDGPU
The RAII class used for debugging RTL entry used a shared variable to
keep track of the current depth. This used a global initializer, which
isn't supported on AMDGPU. This patch removes the initializer and
instead sets it to zero when the state is initialized in the runtime.
Reviewed By: jdoerfert, JonChesterfield
Differential Revision: https://reviews.llvm.org/D113963
Christian Kühnel [Mon, 15 Nov 2021 14:52:07 +0000 (14:52 +0000)]
[NFC][clangd] cleaning up unused "using"
Cleaning up unused "using" declarations.
This patch was generated from automatically applyning clang-tidy fixes.
Differential Revision: https://reviews.llvm.org/D113891
Florian Hahn [Tue, 16 Nov 2021 12:48:21 +0000 (12:48 +0000)]
[llvm-reduce] Add new BitWriter dependency after
28d95a26109e.
Sander.DeSmalen@arm.com [Tue, 16 Nov 2021 11:14:04 +0000 (11:14 +0000)]
[IndVarSimplify] Reduce nondeterministic behaviour in visitIVCast.
rGf39978b84f1d3a1da6c32db48f64c8daae64b3ad led to and/or exposed
an issue with IndVarSimplification for a loop where a i32 phi node is
no longer replaced by a widened (i64) phi node, because the SCEVs of a
sign-extend no longer folded the same way. I'm unsure how to properly
explain this because it's all rather complicated, but in short: SCEVs
don't fold as nicely as they used to and this caused a difference.
While investigating this, I found that IndVarSimplify can actually
optimise the case in the way we want to if it chooses the widened IV to
be 'signed' (the i32 IV is both sign and zero-extended). Oddly enough,
there is some level of indeterminism in the way the algorithm works,
it just picks the sign of the 'first' zext/sext user, where the order of
the users-iterator is not guaranteed to be the same on each invocation
of the pass (e.g. shown by first running loop-rotate, which puts the
users in a different order).
While I think the fix is valid in the sense that consistently picking
_any_ order is better than having an nondeterministic order, I can
use a bit of advice from people more familiar in this area of the
code-base.
For example, I'm not sure if this fix is hiding another issue where the
IndVarSimplify pass could actually draw the same conclusions (i.e. that
it only needs an i64 phi node) if it does a bit more work, regardless
of whether it chooses the induction variable to be signed or unsigned.
I'm also not sure if choosing signed is better than unsigned, or whether
that just happens to be beneficial only in this individual case.
Any feedback would be much appreciated!
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D112573
Florian Hahn [Tue, 16 Nov 2021 12:39:32 +0000 (12:39 +0000)]
[llvm-reduce] Allow writing temporary files as bitcode.
Textual LLVM IR files are much bigger and take longer to write to disk.
To avoid the extra cost incurred by serializing to text, this patch adds
an option to save temporary files as bitcode instead.
Reviewed By: aeubanks
Differential Revision: https://reviews.llvm.org/D113858
Diana Picus [Tue, 16 Nov 2021 10:17:29 +0000 (10:17 +0000)]
[fir] Add fir.cmpc conversion
This patch adds the codegen for fir.cmpc. The real and imaginary parts
are extracted and compared separately. For the .EQ. predicate the
results are AND'd, for the .NE. predicate the results are OR'd, and for
other predicates we keep only the result on the real parts.
This patch is part of the upstreaming effort from fir-dev.
Differential Revision: https://reviews.llvm.org/D113976
Co-authored-by: Eric Schweitz <eschweitz@nvidia.com>
Co-authored-by: Jean Perier <jperier@nvidia.com>
Fabian Wolff [Tue, 16 Nov 2021 12:09:17 +0000 (07:09 -0500)]
Fix false positive in `bugprone-throw-keyword-missing` check
Fixes PR#52400. The tests for bugprone-throw-keyword-missing actually
already contain exceptions as class members, but not as members with
initializers, which was probably just an oversight.
Pavel Labath [Tue, 9 Nov 2021 15:32:57 +0000 (16:32 +0100)]
[lldb] Refactor Platform::ResolveExecutable
Module resolution is probably the most complex piece of lldb [citation
needed], with numerous levels of abstraction, each one implementing
various retry and fallback strategies.
It is also a very repetitive, with only small differences between
"host", "remote-and-connected" and "remote-but-not-(yet)-connected"
scenarios.
The goal of this patch (first in series) is to reduce the number of
abstractions, and deduplicate the code.
One of the reasons for this complexity is the tension between the desire
to offload the process of module resolution to the remote platform
instance (that's how most other platform methods work), and the desire
to keep it local to the outer platform class (its easier to subclass the
outer class, and it generally makes more sense).
This patch resolves that conflict in favour of doing everything in the
outer class. The gdb-remote (our only remote platform) implementation of
ResolveExecutable was not doing anything gdb-specific, and was rather
similar to the other implementations of that method (any divergence is
most likely the result of fixes not being applied everywhere rather than
intentional).
It does this by excising the remote platform out of the resolution
codepath. The gdb-remote implementation of ResolveExecutable is moved to
Platform::ResolveRemoteExecutable, and the (only) call site is
redirected to that. On its own, this does not achieve (much), but it
creates new opportunities for layer peeling and code sharing, since all
of the code now lives closer together.
Differential Revision: https://reviews.llvm.org/D113487
Butygin [Thu, 28 Oct 2021 16:04:35 +0000 (19:04 +0300)]
[mlir][spirv] add AtomicFAddEXTOp
Differential Revision: https://reviews.llvm.org/D113764
Florian Hahn [Tue, 16 Nov 2021 11:16:07 +0000 (11:16 +0000)]
[SCEV] Support rewriting ZExt expressions with loop guard info.
So far, applying loop guard information has been restricted to
SCEVUnknown. In a few cases, like PR40961 and PR52464, this leads to
SCEV failing to determine tight upper bounds for the backedge taken
count.
This patch adjusts SCEVLoopGuardRewriter and applyLoopGuards to support
re-writing ZExt expressions.
This is a first step towards fixing PR40961 and PR52464.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D113577
Matt Devereau [Thu, 4 Nov 2021 16:10:55 +0000 (16:10 +0000)]
[AArch64][SVE] Instcombine SVE LD1/ST1 to stock LLVM IR
InstCombine AArch64 LD1/ST1 to llvm.masked.load/llvm.masked.store
and LD1/ST1 to load/store when a ptrue all predicate pattern operand
is present.
This allows existing IR optimizations such as dead-load removal to
occur.
Differential Revision: https://reviews.llvm.org/D113489
Frederik Gossen [Tue, 16 Nov 2021 11:03:59 +0000 (12:03 +0100)]
Fix unused variable warning in LoadStoreOpt.cpp with (void)
Frederik Gossen [Tue, 16 Nov 2021 11:00:17 +0000 (12:00 +0100)]
Revert "Fix unused variable in llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp"
This reverts commit
40a609aebe4ab51174a164852b6399f322bf6d9a.
Frederik Gossen [Tue, 16 Nov 2021 10:59:34 +0000 (11:59 +0100)]
Revert "Fix unused variable warning."
This reverts commit
a062e2a8ca27b615cf3d02ed5c551ca85efc0325.
Frederik Gossen [Tue, 16 Nov 2021 10:58:02 +0000 (11:58 +0100)]
Revert "Fix another unused variable error."
This reverts commit
5b84ae7c48083bd0f40199837990cf915a2053b8.
Pavel Labath [Wed, 10 Nov 2021 16:44:37 +0000 (17:44 +0100)]
[lldb] Simplify specifying of platform supported architectures
The GetSupportedArchitectureAtIndex pattern forces the use of
complicated patterns in both the implementations of the function and in
the various callers.
This patch creates a new method (GetSupportedArchitectures), which
returns a list (vector) of architectures. The
GetSupportedArchitectureAtIndex is kept in order to enable incremental
rollout. Base Platform class contains implementations of both of these
methods, using the other method as the source of truth. Platforms
without infinite stacks should implement at least one of them.
This patch also ports Linux, FreeBSD and NetBSD platforms to the new
API. A new helper function (CreateArchList) is added to simplify the
common task of creating a list of ArchSpecs with the same OS but
different architectures.
Differential Revision: https://reviews.llvm.org/D113608
Pavel Labath [Thu, 11 Nov 2021 19:11:14 +0000 (20:11 +0100)]
[lldb/test] Move gdb client utils into the packages tree
This infrastructure has proven proven its worth, so give it a more
prominent place.
My immediate motivation for this is the desire to reuse this
infrastructure for qemu platform testing, but I believe this move makes
sense independently of that. Moving this code to the packages tree will
allow as to add more structure to the gdb client tests -- currently they
are all crammed into the same test folder as that was the only way they
could access this code.
I'm splitting the code into two parts while moving it. The first once
contains just the generic gdb protocol wrappers, while the other one
contains the unit test glue. The reason for that is that for qemu
testing, I need to run the gdb code in a separate process, so I will
only be using the first part there.
Differential Revision: https://reviews.llvm.org/D113893
Adrian Kuegel [Tue, 16 Nov 2021 10:31:57 +0000 (11:31 +0100)]
Fix another unused variable error.
Butygin [Thu, 28 Oct 2021 16:04:35 +0000 (19:04 +0300)]
[mlir] spirv: Add scf.while spirv conversion
* It works similar to scf.for coversion, but convert condition and yield ops as part of scf.whille pattern so it don't need to maintain external state
Differential Revision: https://reviews.llvm.org/D113007
Adrian Kuegel [Tue, 16 Nov 2021 10:17:33 +0000 (11:17 +0100)]
Fix unused variable warning.
Adrian Kuegel [Tue, 16 Nov 2021 09:58:14 +0000 (10:58 +0100)]
[mlir] Support multi-dimensional vectors in MathToLibm conversion.
Differential Revision: https://reviews.llvm.org/D113969
Arnab Dutta [Tue, 16 Nov 2021 09:36:45 +0000 (15:06 +0530)]
[MLIR] Simplify semi-affine expressions using flattening
For the semi affine expressions, whenever rhs of a floordiv, ceildiv, mod
or product expression is a symbolic expression, we introduce a local variable
representing the result, and store the floordiv/ceildiv, mod or product
affine expression in LocalExprs. In this way the expression is flattened,
and trivial addition and subtraction related simplifications are performed.
Also rule based matching for detecting and transforming "expr - q * (expr floordiv q)"
to "expr mod q", where q is a symbolic exxpression, in simplifyAdd function.
Differential Revision: https://reviews.llvm.org/D112808
Frederik Gossen [Tue, 16 Nov 2021 10:04:45 +0000 (11:04 +0100)]
Fix unused variable in llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp
David Green [Tue, 16 Nov 2021 09:49:42 +0000 (09:49 +0000)]
[ARM] Add datalayout to costmodel tests. NFC
This adds a sensible datalayout to the ARM cost model tests, to prevent
the costs reported being incorrect for the size of pointers.
Groverkss [Tue, 16 Nov 2021 08:42:13 +0000 (14:12 +0530)]
[MLIR] FlatAffineConstraints: Allow extraction of explicit representation of local variables
This patch extends the existing functionality of computing an explicit
representation for local variables, to also get the explicit representation,
instead of only the inequality pairs.
This is required for a future patch to remove redundant local ids based on
their explicit representation.
Reviewed By: arjunp
Differential Revision: https://reviews.llvm.org/D113814
Kai Luo [Tue, 16 Nov 2021 09:16:54 +0000 (09:16 +0000)]
[CGP][PowerPC] Pre-commit test case for D113872. NFC.
Amara Emerson [Tue, 16 Nov 2021 08:48:07 +0000 (00:48 -0800)]
Remove unnecessary <any> include.
Carlos Galvez [Sun, 14 Nov 2021 17:09:54 +0000 (17:09 +0000)]
[clang-tidy][NFC] Simplify ClangTidyStats
- Use NSDMI and remove constructor.
Differential Revision: https://reviews.llvm.org/D113847
jacquesguan [Tue, 9 Nov 2021 02:15:46 +0000 (10:15 +0800)]
[RISCV] Refactor some rvv instructions' definition with foreach.
Simplify rvv instructions that use eew in their mnemonic and encoding with foreach. And fix a scheduling bug.
Differential Revision: https://reviews.llvm.org/D113453
Dmitry Vyukov [Mon, 15 Nov 2021 18:44:34 +0000 (19:44 +0100)]
tsan: use pthread_equal instead of direct pthread_t comparison
man pthread_equal:
The pthread_equal() function is necessary because thread IDs
should be considered opaque: there is no portable way for
applications to directly compare two pthread_t values.
Depends on D113916.
Reviewed By: vitalybuka
Differential Revision: https://reviews.llvm.org/D113919
Dmitry Vyukov [Mon, 15 Nov 2021 18:00:31 +0000 (19:00 +0100)]
tsan: speed up pthread_setname_np
pthread_setname_np does linear search over all thread descriptors
to map pthread_t to the thread descriptor. This has O(N^2) complexity
and becomes much worse in the new tsan runtime that keeps all ever
existed threads in the thread registry.
Replace linear search with direct access if pthread_setname_np
is called for the current thread (a very common case).
Reviewed By: vitalybuka
Differential Revision: https://reviews.llvm.org/D113916
LLVM GN Syncbot [Tue, 16 Nov 2021 06:15:54 +0000 (06:15 +0000)]
[gn build] Port
2e6ae1d3f2de
Chuanqi Xu [Tue, 16 Nov 2021 06:05:34 +0000 (14:05 +0800)]
[libcxx] [Coroutine] Conform Coroutine Implementation
Since coroutine is merged in C++ standard and the support for coroutine
seems relatively stable. It's the time to move the implementation of
coroutine out of the experimental directory and the std::experimental
namespace. This patch creates header <coroutine> with conformed
implementation with C++ standard. To avoid breaking user's code too
fast, the <experimental/coroutine> header is remained. Note that
<experimental/coroutine> is deprecated and it would be removed in
LLVM15.
Reviewed By: Quuxplusone, ldionne
Differential Revision: https://reviews.llvm.org/D109433
Mehdi Amini [Tue, 16 Nov 2021 05:59:12 +0000 (05:59 +0000)]
Revert "[MLIR][LLVM] Permit integer types in switch other than i32"
This reverts commit
94992670fcc59d12d7f97cb08beb8d2eb15110ed.
Build is broken with:
tools/mlir/include/mlir/Dialect/LLVMIR/LLVMOps.cpp.inc:23996:3: error: no matching function for call to 'printSwitchOpCases'
printSwitchOpCases(_odsPrinter, *this, getValue().getType(), getCaseValuesAttr(), getCaseDestinations(), getCaseOperands(), getCaseOperands().getTypes());
^~~~~~~~~~~~~~~~~~
Serguei Katkov [Tue, 5 Oct 2021 04:00:53 +0000 (11:00 +0700)]
[STATEPOINT] Force implicit-def for lr register.
STATEPOINT instruction behavior is similar to call instruction.
In aarch64 BL instruction implicitly define lr register, so
STATEPOINT instruction should do the same.
However STATEPOINT is a general pseudo instruction and I could not find
a way to override list of implicit defs for specific target.
So this patch post processes inserting STATEPOINT instruction by
adding implisit dead def for lr.
Reviewers: reames, loicottet, ostannard
Reviewed By: reames
Subscribers: danilaml, hiraditya, kristof.beyls, llvm-commits, yrouban
Differential Revision: https://reviews.llvm.org/D111114
William S. Moses [Tue, 16 Nov 2021 01:13:33 +0000 (20:13 -0500)]
[MLIR][LLVM] Permit integer types in switch other than i32
LLVM switchop currently only permits i32. Both LLVM IR and MLIR Standard switch permit other integer types leading to an illegal state when lowering an i8 switch from MLIR standard
Reviewed By: mehdi_amini
Differential Revision: https://reviews.llvm.org/D113955
Kazu Hirata [Tue, 16 Nov 2021 05:28:46 +0000 (21:28 -0800)]
[llvm] Use make_early_inc_range (NFC)
LLVM GN Syncbot [Tue, 16 Nov 2021 05:11:06 +0000 (05:11 +0000)]
[gn build] Port
dc84770d559b
Amara Emerson [Mon, 15 Nov 2021 22:45:30 +0000 (14:45 -0800)]
[GlobalISel] Add a store-merging optimization pass and enable for AArch64.
This is a first attempt at a constant value consecutive store merging pass,
a counterpart to the DAGCombiner's store merging optimization.
The high level goals of this pass:
* Have a simple and efficient algorithm. As close to linear time as we can get.
Thus, prioritizing scalability of the algorithm over merging every corner case
we can find. The DAGCombiner's store merging code has been the source of
compile time and complexity issues in the past and I wanted to avoid that.
* Don't introduce any new data structures for ordering memory operations. In MIR,
we don't have the concept of chains like we do in the DAG, and the instruction
order is stricter than enforcing ordering with graph edges. Although I
considered adding something similar, I couldn't justify the overhead.
The pass is current split into 3 main parts. The main store merging code focuses
on identifying candidate stores and managing the candidate group that's under
consideration for merging. Analyzing addressing of stores is a potentially
complex part and for now there's just a basic implementation to identify easy
cases. Finally, the other main bit of complexity is the alias analysis, which
tries to follow the same logic as the DAG's AA.
Currently this implementation only supports merging of constant stores. Stores
of arbitrary variables are technically possible with a very small change, but
the DAG chooses not to do this. Doing so here makes most code worse since
there's extra overhead in merging values into wider registers.
On AArch64 -Os, this optimization results in very minor savings on CTMark.
Differential Revision: https://reviews.llvm.org/D109131
Wenlei He [Fri, 12 Nov 2021 02:28:47 +0000 (18:28 -0800)]
[llvm-profgen] Add switch to allow use of first loadable segment for calculating offset
Adding `-use-loadable-segment-as-base` to allow use of first loadable segment for calculating offset. By default first executable segment is used for calculating offset. The switch helps compatibility with unsymbolized profile generated from older tools.
Differential Revision: https://reviews.llvm.org/D113727
Greg Clayton [Fri, 12 Nov 2021 23:26:27 +0000 (15:26 -0800)]
Add the stop count to "statistics dump" in each target's dictionary.
It is great to know how many times the target has stopped over its lifetime as each time the target stops, and possibly resumes without the user seeing it for things like shared library loading and signals that are not notified and auto continued, to help explain why a debug session might be slow. This is now included as "stopCount" inside each target JSON.
Differential Revision: https://reviews.llvm.org/D113810
Craig Topper [Tue, 16 Nov 2021 01:45:16 +0000 (17:45 -0800)]
[RISCV] Override TargetLowering::hasAndNot for Zbb.
Differential Revision: https://reviews.llvm.org/D113937
Craig Topper [Tue, 16 Nov 2021 01:32:15 +0000 (17:32 -0800)]
[RISCV] Add test cases to prepare for overring TargetLowering::hasAndNot. NFC
These test files are copied directly from AArch64. Some of the cases
may benefit from ANDN with the Zbb extension. Somes cases already
improve use ANDN.
selectcc-to-shiftand.ll also contains tests that test select->and
conversion even when a ANDN isn't needed. I think this improves our
coverage of these optimizations.
Differential Revision: https://reviews.llvm.org/D113935
Fabian Wolff [Tue, 16 Nov 2021 00:54:31 +0000 (08:54 +0800)]
[X86] Fix crash with inline asm using wrong register name
Fixes PR#48678. `X86TargetLowering::getRegForInlineAsmConstraint()` can adjust the register class to match the type, e.g. change `VR128X` to `VR256X` if the type needs 256 bits. However, the function currently returns the unadjusted register and the adjusted register class, e.g. `xmm15` and `VR256X`, which then causes an assertion failure later because the register class does not contain that register. This patch fixes this behavior.
Reviewed By: pengfei
Differential Revision: https://reviews.llvm.org/D113834
Matt Arsenault [Sat, 13 Nov 2021 17:03:44 +0000 (12:03 -0500)]
AMDGPU: Mark prolog/epilog SCC defs as dead
A future change will add SCC liveness checks. Since we are still
relying on forward register scavenging, add dead flags to avoid
spuriously detecting SCC as live.
Matt Arsenault [Sat, 13 Nov 2021 17:13:58 +0000 (12:13 -0500)]
AMDGPU: Regenerate test checks
Matthias Springer [Tue, 16 Nov 2021 02:10:57 +0000 (11:10 +0900)]
[mlir][linalg][bufferize][NFC] Clean up tensor op bufferization
Differential Revision: https://reviews.llvm.org/D113730
Matheus Izvekov [Tue, 16 Nov 2021 00:49:30 +0000 (01:49 +0100)]
[clang] NFC: rename internal `IsPossiblyOpaquelyQualifiedType` overload
Rename `IsPossiblyOpaquelyQualifiedType` overload taking a Type*
as `IsPossiblyOpaquelyQualifiedTypeInternal` instead.
Signed-off-by: Matheus Izvekov <mizvekov@gmail.com>
Differential Revision: https://reviews.llvm.org/D113954
Duncan P. N. Exon Smith [Tue, 16 Nov 2021 01:18:07 +0000 (17:18 -0800)]
DebugInfo: Make DWARFExpression::iterator::skipBytes() const, NFC
Given that DWARFExpression::iterator::skipBytes() doesn't change any
state (it returns a new `iterator`), it might as well be
`const`-qualified.
Duncan P. N. Exon Smith [Tue, 16 Nov 2021 01:05:09 +0000 (17:05 -0800)]
DebugInfo: const-qualify accessors of DWARFExpression::Operation
Add `const` to DWARFExpression::Operation's accessors and make
Operation::extract() private, since it's only used by the friend class
DWARFExpression::iterator.
Duncan P. N. Exon Smith [Tue, 16 Nov 2021 00:42:48 +0000 (16:42 -0800)]
DebugInfo: Make DWARFExpression::iterator::operator++ return itself
Looks like an accident that `operator++` was returning `Operator&`
instead of `iterator&`. Update to match standard iterator behaviour.
Craig Topper [Mon, 15 Nov 2021 23:16:37 +0000 (15:16 -0800)]
[DAGCombiner] Prevent unfoldMaskedMerge from creating an AND with two inverted inputs.
It's possible that the mask is already a NOT. At least if InstCombine
hasn't canonicalized the input. In that case we will form an ANDN with
X instead of with Y. So we don't need to worry about Y being a constant.
We might need to check that X isn't a constant instead, but we don't
have a test case for that yet.
This fixes a size regression found when trying to enable this combine
for RISCV in D113937.
Differential Revision: https://reviews.llvm.org/D113948