Erik Faye-Lund [Mon, 15 May 2023 12:39:37 +0000 (14:39 +0200)]
zink: fix bad indent
This was indented too much
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23027>
Konstantin Seurer [Tue, 18 Apr 2023 07:34:48 +0000 (09:34 +0200)]
nir/inline_uniforms: Handle num_components > 1
Vulkan UBO loads can have a buffer_index source with more than one component.
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23016>
Konstantin Seurer [Mon, 15 May 2023 07:38:20 +0000 (09:38 +0200)]
gallium/nir: Handle unified atomics in nir_to_tgsi_info
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23016>
Alyssa Rosenzweig [Fri, 12 May 2023 18:09:49 +0000 (14:09 -0400)]
radv: Use common GetPhysicalDeviceFeatures2
This is a big delete-the-code win. Tested by diff'ing vulkaninfo output
before/after the patch and confirming no changes (other than the driverInfo git
sha and the pipelineCacheUUID).
Note: removes handling for VkDeviceMemoryOverallocationCreateInfoAMD. This was
surely added as a mistake.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22999>
Alyssa Rosenzweig [Fri, 12 May 2023 18:29:37 +0000 (14:29 -0400)]
radv: Constify radv_device_supports_etc
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22999>
Luigi Santivetti [Thu, 20 Apr 2023 08:10:00 +0000 (09:10 +0100)]
pvr: fixup stack overflow in {start,end}_sub_cmd
Signed-off-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22955>
Mike Blumenkrantz [Mon, 15 May 2023 11:34:46 +0000 (07:34 -0400)]
zink: add some ci flakes
roundup from recent ci jobs
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23021>
Rhys Perry [Fri, 12 May 2023 14:30:02 +0000 (15:30 +0100)]
amd/drm-shim: add navi10
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22989>
Rhys Perry [Fri, 12 May 2023 14:28:49 +0000 (15:28 +0100)]
amd/drm-shim: add vega10
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22989>
Rhys Perry [Fri, 12 May 2023 14:28:42 +0000 (15:28 +0100)]
amd/drm-shim: add polaris10
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22989>
Rhys Perry [Fri, 12 May 2023 14:23:11 +0000 (15:23 +0100)]
amd/drm-shim: move device list to external file
This is already pretty large.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22989>
antonino [Fri, 5 May 2023 16:19:54 +0000 (18:19 +0200)]
zink: don't create invalid inputs in `zink_create_quads_emulation_gs`
The helper was creating input locations for some builtin bariables.
This caused validation errors in zink because those builtins can't be
used as input.
Fixes:
e2220ee55e4 ("zink: filled quad emulation gs generation function")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22871>
antonino [Fri, 5 May 2023 16:13:32 +0000 (18:13 +0200)]
nir: make var arrays large enough in `nir_create_passthrough_gs`
Because each location has 4 possible different values for location_frac
the arrays need to br 4x the size.
Fixes:
d0342e28 ("nir: Add helper to create passthrough GS shader")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22871>
antonino [Fri, 5 May 2023 15:40:32 +0000 (17:40 +0200)]
zink: handle interface blocks in `copy_vars`
Fixes:
edaf49160e5 ("zink: fix array copying in pv lowering")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22871>
antonino [Fri, 5 May 2023 15:39:38 +0000 (17:39 +0200)]
nir: handle interface blocks in `copy_vars`
Fixes:
99121c9b779 ("nir/gs: fix array type copying for passthrough gs")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22871>
antonino [Fri, 5 May 2023 11:57:54 +0000 (13:57 +0200)]
zink: don't replace non generated gs
Zink replaced the gs emulation shader when the primitive type changes,
however it didn't check whether the gs being replaced was generated.
Fixes:
eedbf9046e7 ("zink: handle switching between primitives")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22871>
antonino [Fri, 5 May 2023 09:53:55 +0000 (11:53 +0200)]
nir: don't create invalid inputs in `nir_create_passthrough_gs`
The helper was creating input locations for some builtin bariables.
This caused validation errors in zink because those builtins can't be
used as input.
Fixes:
d0342e28b32 ("nir: Add helper to create passthrough GS shader")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22871>
antonino [Fri, 5 May 2023 09:20:55 +0000 (11:20 +0200)]
nir: use `nir_variable_clone` in `nir_create_passthrough_gs`
Some stream out properties where not being copied causing problems in
zink.
Use the appropiate helper instead of copying fields by hand.
Fixes:
d0342e28b32 ("nir: Add helper to create passthrough GS shader")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22871>
Matt Coster [Thu, 4 May 2023 08:53:32 +0000 (09:53 +0100)]
pvr: Remove unneeded assert in pvr_get_hw_clear_color()
Fixes: dEQP-VK.synchronization.op.single_queue.fence
.write_draw_read_image_compute.image_128x128_r8_unorm
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reported-by: James Glanville <james.glanville@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22868>
Matt Coster [Thu, 4 May 2023 08:49:16 +0000 (09:49 +0100)]
pvr: Fix off-by-one in pvr_cmd_buffer_upload_desc_set_table() assert
Fixes: dEQP-VK.pipeline.monolithic.dynamic_offset.compute.multiset
.uniform_buffer.numcmdbuffers_1.sameorder.numdescriptorsetbindings_1
.numdynamicbindings_2.numnondynamicbindings_1
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reported-by: James Glanville <james.glanville@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22868>
Matt Coster [Tue, 2 May 2023 15:06:17 +0000 (16:06 +0100)]
pvr: Correctly compile graphics pipelines without a fragment shader
Fixes: dEQP-VK.pipeline.monolithic.stencil.nocolor.format.s8_uint
.states.fail_keep.pass_keep.dfail_repl.comp_greater_or_equal
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reported-by: James Glanville <james.glanville@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22868>
Matt Coster [Tue, 2 May 2023 13:28:28 +0000 (14:28 +0100)]
pvr: Initialize aspect_mask when creating buffer views
Fixes random aborts in CSB handling.
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reported-by: James Glanville <james.glanville@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22868>
Matt Coster [Tue, 2 May 2023 13:21:39 +0000 (14:21 +0100)]
pvr: Actually check for depth load when setting up load op constants
Fixes: Assorted tests in dEQP-VK.draw.renderpass.*
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reported-by: James Glanville <james.glanville@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22868>
Samuel Pitoiset [Fri, 12 May 2023 08:03:14 +0000 (10:03 +0200)]
radv: stop using the pipeline for determining the null export workaround
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22981>
Samuel Pitoiset [Fri, 12 May 2023 07:48:18 +0000 (09:48 +0200)]
radv: remove unused pipeline param in radv_generate_ps_epilog_key()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22981>
Samuel Pitoiset [Fri, 12 May 2023 07:45:20 +0000 (09:45 +0200)]
radv: reset the emitted PS epilog when a new fragment shader is bound
When a new fragment shader is bound, the PS epilog needs to be
re-emitted, and this allows us to avoid tracking if the pipeline is
dirty.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22981>
David Heidelberg [Fri, 5 May 2023 20:32:47 +0000 (22:32 +0200)]
panvk: drop path from panvk_physical_device struct
Unnecessary. Only produces warning:
```
../src/panfrost/vulkan/panvk_device.c:437:4: warning: 'strncpy' specified bound 20 equals destination size [-Wstringop-truncation]
437 | strncpy(device->path, path, ARRAY_SIZE(device->path));
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
```
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22880>
Konstantin Seurer [Wed, 1 Mar 2023 21:26:03 +0000 (22:26 +0100)]
radv/ci: Test ray tracing pipelines
Since we expose them for a few games by default now, it would make sense
to have test coverage for them.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21638>
Samuel Pitoiset [Thu, 11 May 2023 07:48:00 +0000 (09:48 +0200)]
radv: advertise VK_EXT_tooling_info
This small extension just returns active tools running like RGP.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22954>
Iago Toral Quiroga [Wed, 10 May 2023 07:11:06 +0000 (09:11 +0200)]
broadcom/compiler: use unified atomics
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22939>
Samuel Pitoiset [Thu, 4 May 2023 06:54:53 +0000 (08:54 +0200)]
radv: stop compiling a noop FS when the application doesn't provide a FS
This is unnecessary because the hardware doesn't execute a FS when it
has no effect and it's possible to execute pre-rasterization stages
without a FS.
This might improve depth-only pass performance very slightly because
the number of packets emitted is reduced a bit.
No fossils-db changes.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22848>
Samuel Pitoiset [Fri, 12 May 2023 11:04:45 +0000 (13:04 +0200)]
radv: allow to determine NGG settings with a NULL fragment shader
This shouldn't change anything because a noop FS doesn't read any
inputs.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22848>
Samuel Pitoiset [Fri, 12 May 2023 10:57:30 +0000 (12:57 +0200)]
radv: rework the checks for implicit exports with GPL
No logical changes but this allows us to distinguish between noop FS
and unknown FS with GPL.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22848>
Samuel Pitoiset [Thu, 4 May 2023 07:06:01 +0000 (09:06 +0200)]
radv: handle NULL fragment shaders when creating graphics pipelines
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22848>
Samuel Pitoiset [Thu, 4 May 2023 07:05:34 +0000 (09:05 +0200)]
radv: handle NULL fragment shaders when recording cmdbuf
This will be useful for shader objects and also because creating and
emitting a noop FS is useless, the hardware doesn't execute it.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22848>
Samuel Pitoiset [Wed, 10 May 2023 15:29:29 +0000 (17:29 +0200)]
radv: implement dynamic sample locations enable
VK_EXT_sample_locations is only supported on < GFX10 due to some weird
issues on recent GPUs. extendedDynamicState3SampleLocationsEnable is
only enabled on GFX6-GFX9 for the same reason.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22947>
Filip Gawin [Fri, 21 Apr 2023 08:25:53 +0000 (10:25 +0200)]
glx: fix build with APPLEGL
fixes:
1eab7e69e2ba84244f551f6901f4307a687a9504
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8885
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22621>
Qiang Yu [Thu, 27 Apr 2023 11:55:25 +0000 (19:55 +0800)]
radeonsi: be able to use aco compiler for mono ps
Need to set AMD_DEBUG=useaco environment variable.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Mon, 24 Apr 2023 08:42:11 +0000 (16:42 +0800)]
radeonsi: fixup sampler desc for tg4 in nir
For ACO which won't do this for us. But we still can't
remove the same code in llvm because non-uniform sampler
is keept as index in nir.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Mon, 24 Apr 2023 08:33:02 +0000 (16:33 +0800)]
ac/llvm,radeonsi: enable lower_array_layer_round_even
ACO need this to be done in nir. Remove the llvm round code
because both radv and radeonsi do this in nir for both aco
and llvm.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Tue, 18 Apr 2023 08:01:08 +0000 (16:01 +0800)]
radeonsi: clamp shadow texture reference in nir for aco
This is ported from the LLVM ac_shader_abi->clamp_shadow_reference
code.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Thu, 27 Apr 2023 11:45:11 +0000 (19:45 +0800)]
radeonsi: pass use_aco to ac_nir_lower_ps
For dual source blend code emition in aco.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Thu, 27 Apr 2023 11:30:21 +0000 (19:30 +0800)]
radeonsi: adjust ps args for aco
aco need explicite args including PS arg compaction and
scratch_offset.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Wed, 26 Apr 2023 08:31:44 +0000 (16:31 +0800)]
radeonsi: resolve aco scratch addr symbols
Used for scratch buffer operation and reg spill when aco.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Wed, 26 Apr 2023 02:40:58 +0000 (10:40 +0800)]
radeonsi: add symbols to si_shader_binary
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Fri, 14 Apr 2023 09:21:45 +0000 (17:21 +0800)]
radeonsi: add initial aco compile code
Only for monolithic PS.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Thu, 27 Apr 2023 11:33:32 +0000 (19:33 +0800)]
radeonsi: lower non uniform texture access when aco
aco need all resource have been lowered to descriptor.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Fri, 14 Apr 2023 10:41:00 +0000 (18:41 +0800)]
radeonsi: add has_non_uniform_tex_access shader info
Can be used to skip nir_lower_non_uniform_access pass.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Thu, 27 Apr 2023 11:41:24 +0000 (19:41 +0800)]
radeonsi: lower vector const to scalar at last for aco
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Tue, 9 May 2023 09:52:30 +0000 (17:52 +0800)]
radeonsi: lower some 64bit ops aco does not support
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Mon, 17 Apr 2023 10:01:09 +0000 (18:01 +0800)]
ac/llvm,radeonsi: lower nir_fpow for aco and llvm
aco does not implement fpow, need nir to lower it
first. llvm will do by itself in the same way, so
we always lower fpow in nir now.
Remove the llvm fpow implementation that has special
handling for the muliplication. It's not used any
more and does not match GLSL spec as fpow(0,0)=NaN
but here we get 0.
There's some pixel changes for gl-radeonsi-stoney:
ror-default 2 (no tolerance), 0 (1% tol.)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Fri, 14 Apr 2023 07:58:31 +0000 (15:58 +0800)]
ac/llvm,radeonsi: lower some pack/unpack ops not supported by aco
aco only support the split vertion of these instructions.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Tue, 9 May 2023 09:48:24 +0000 (17:48 +0800)]
ac/llvm,radeonsi: lower ineg in nir
aco does not implement it.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Sat, 15 Apr 2023 08:10:57 +0000 (16:10 +0800)]
ac/llvm,radeonsi: lower txf offset in nir
aco will complain if txf has offset. Not if other
texture ops.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Fri, 14 Apr 2023 13:05:05 +0000 (21:05 +0800)]
ac/llvm,radeonsi: lower fsin/fcos in nir
ACO only support nir_fsin/cos_amd.
There's some pixel changes for gl-radeonsi-stoney trace.
Different pixels:
furmark 61 (no tolerance), 0 (1% tol.)
gimark 93867 (no tolerance), 888 (1% tol.)
tessmark 39 (no tolerance), 0 (1% tol.)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Sat, 15 Apr 2023 06:35:27 +0000 (14:35 +0800)]
ac/llvm,radeonsi: lower idiv in nir
aco does not implement these idiv ops.
nir_lower_idiv is for idiv ops <= 32bit and ported from
llvm amdgpu, so llvm do the same.
nir_lower_divmod64 is for 64bit idiv ops.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Tue, 9 May 2023 09:01:19 +0000 (17:01 +0800)]
tgsi_to_nir: call nir_lower_int64 when required
Use case: radeonsi will generate internal tgsi shader
with 64bit udiv instruction, and we want all 64bit udiv
to be lowered in nir by lower_int64_options.
For GLSL shaders, this is done in glsl to nir, so we do
the same for tgsi here.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Thu, 13 Apr 2023 06:19:19 +0000 (14:19 +0800)]
radeonsi: remove ps vgpr index save when args init
They will be set by ac_get_fs_input_vgpr_cnt() later anyway.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Fri, 14 Apr 2023 08:54:03 +0000 (16:54 +0800)]
radeonsi: support print raw shader binary
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Thu, 13 Apr 2023 00:54:44 +0000 (08:54 +0800)]
radeonsi: support raw shader binary upload
Only monolithic shader.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Sun, 23 Apr 2023 09:23:23 +0000 (17:23 +0800)]
ac/binary: pack prefech align code to a function
To be used by radeonsi raw shader binary.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Wed, 12 Apr 2023 13:44:13 +0000 (21:44 +0800)]
radeonsi: add a raw shader binary type
It's the output of ACO compiler. To share the si_shader_binary
struct with ELF type:
* add a type field to indicate RAW or ELF
* rename elf_buffer/size to code_buffer/size
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Wed, 12 Apr 2023 10:38:18 +0000 (18:38 +0800)]
radeonsi: init spi ps input shader config when aco
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Wed, 12 Apr 2023 10:24:12 +0000 (18:24 +0800)]
radeonsi: pack spi ps input fixup to a function
To be shared with ACO spi ps input construction.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Wed, 12 Apr 2023 07:37:06 +0000 (15:37 +0800)]
radeonsi: add shader info uses_sampleid
Used by ACO to set spi_ps_intput.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Wed, 12 Apr 2023 06:53:47 +0000 (14:53 +0800)]
radeonsi: add shader info for frag coord and sample pos read
To construct spi_ps_input when ACO compilation.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Wed, 12 Apr 2023 02:05:18 +0000 (10:05 +0800)]
radeonsi: add use_aco field for struct si_shader
We are going to use aco for monolithic ps first.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Wed, 5 Apr 2023 11:50:43 +0000 (19:50 +0800)]
radeonsi: add aco debug option
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
Qiang Yu [Wed, 5 Apr 2023 11:44:19 +0000 (19:44 +0800)]
meson: build radeonsi with aco
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>
David Heidelberg [Tue, 2 May 2023 23:01:36 +0000 (01:01 +0200)]
ci/skqp: handle all warnings printed with clang >= 14
Useful for the https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21977
Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22808>
Konstantin Seurer [Thu, 11 May 2023 17:03:11 +0000 (19:03 +0200)]
radv: Stop running constant folding during ray query lowering
Now that committed is an intrinsic index, there is no need for constant
folding.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22963>
Konstantin Seurer [Thu, 11 May 2023 17:00:51 +0000 (19:00 +0200)]
nir: Make rq_load committed src an index
committed has to be a constant so there is no need to have a src and
depend on constant folding to remove the i2b.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22963>
David Heidelberg [Fri, 28 Apr 2023 10:23:22 +0000 (12:23 +0200)]
gtest: Update to 1.13.0
Fix msan issue found with recent GCC on Debian 12.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8915
Acked-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22814>
David Heidelberg [Fri, 28 Apr 2023 10:51:59 +0000 (12:51 +0200)]
util/tests: adjust for new gtest
GTest deprecated the GTEST_ARRAY_SIZE_ macro.
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22814>
M Henning [Fri, 12 May 2023 19:39:28 +0000 (15:39 -0400)]
nv50: Fix return type of nv50_blit_is_array
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22997>
M Henning [Fri, 12 May 2023 17:16:49 +0000 (13:16 -0400)]
nvc0: Free blitter->vp
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22997>
M Henning [Fri, 12 May 2023 17:14:51 +0000 (13:14 -0400)]
nv50,nvc0: Free nir from blitter fp shader
Fixes:
d11145e837 ("nv50,nvc0: Use nir in nv50_blitter_make_fp")
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22997>
Jesse Natalie [Fri, 12 May 2023 16:14:06 +0000 (09:14 -0700)]
dxil: Use unified atomics
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22993>
Jesse Natalie [Thu, 11 May 2023 20:23:34 +0000 (13:23 -0700)]
microsoft/compiler: Back-propagate type requirement information
For ALU ops where input types are known, we can store that info on
the input sources. This can be used to produce the correct overloads
of load instructions that don't immediately need to be followed by
bitcasts, or similarly to produce a constant value which can be directly
consumed by the relevant instruction without needing a bitcast.
Similarly for values that will be stored in an output, we know type
information. And using that info, we can use more-correct information
for phis instead of forcing all phi sources to be bitcast to int just
to be bitcast back to float on the other side for an alu or an output
store.
One missing piece is SSBO stores, where we can support int or float.
If the input is coming from a phi, we don't influence the phi's type,
so it'll be int, even though the incoming sources might've been float.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22972>
Jesse Natalie [Thu, 11 May 2023 17:58:25 +0000 (10:58 -0700)]
microsoft/compiler: Duplicate some SSA values to simplify SSA typing
For each phi src, ensure that it's only used as a phi src.
This lets us give each phi their own unique types without worrying
about them stomping on each other. Also scalarize phis.
For each constant, ensure that it's only used once. The DXIL backend
will already dedupe these consts within the module, but this lets a
single load_const have multiple types depending on how it's used.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22972>
Jesse Natalie [Thu, 11 May 2023 16:58:01 +0000 (09:58 -0700)]
microsoft/compiler: Remove alu type info from store_dest()
We pass in a *typed* value, we don't need to pass in additional
type info. That's just more opportunities to get it wrong.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22972>
Marek Olšák [Thu, 27 Apr 2023 07:49:10 +0000 (03:49 -0400)]
ac/llvm: rewrite and unify how GLC, DLC, SLC are set
Use ACCESS_* flags in call sites instead of GLC/DLC/SLC.
ACCESS_* flags are extended to describe other aspects of memory instructions
like load/store/atomic/smem.
Then add a function that converts the access flags to GLC, DLC, SLC.
The new functions are also usable by ACO.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22770>
Marek Olšák [Fri, 28 Apr 2023 04:11:32 +0000 (00:11 -0400)]
ac/llvm: don't treat ACCESS_NON_READABLE as ACCESS_COHERENT
... and expect it to behave like ACCESS_NON_TEMPORAL.
Handling ACCESS_NON_TEMPORAL is sufficient.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22770>
Marek Olšák [Fri, 28 Apr 2023 04:11:32 +0000 (00:11 -0400)]
aco: don't treat ACCESS_NON_READABLE as ACCESS_COHERENT
... and expect it to behave like ACCESS_NON_TEMPORAL.
Handling ACCESS_NON_TEMPORAL is sufficient.
This was copied from ac_nir_to_llvm.c.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22770>
Felix DeGrood [Tue, 9 May 2023 00:11:46 +0000 (00:11 +0000)]
intel: Secondary CB print primary CB's renderpass
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22723>
Felix DeGrood [Wed, 26 Apr 2023 20:13:58 +0000 (20:13 +0000)]
intel: batch consecutive dispatches into implicit renderpasses
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22723>
Felix DeGrood [Wed, 26 Apr 2023 18:52:21 +0000 (18:52 +0000)]
intel: refactor INTEL_MEASURE pointer dumping
Refactor framebuffer to renderpass to mirror previous INTEL_MEASURE
changes.
We dump hashes/pointers for shaders and framebuffer/renderpass.
Reduce from 64bit to 32bit pointers. We don't benefit from the
extra precision and reduced output size is convenient.
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22723>
Felix DeGrood [Wed, 26 Apr 2023 18:26:06 +0000 (18:26 +0000)]
anv: re-enable RT data in INTEL_MEASURE
Per-RenderTarget analysis was removed from anv's INTEL_MEASURE
previously, probably after switching to dynamic rendering model.
Restore capability by tracking count of beginRenderPass calls.
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22723>
Felix DeGrood [Wed, 26 Apr 2023 17:10:24 +0000 (17:10 +0000)]
anv: fix INTEL_MEASURE on MTL
Ensure counter buffer is coherent. Required for MTL which changes
coherence policy.
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22723>
Alyssa Rosenzweig [Fri, 12 May 2023 14:56:07 +0000 (10:56 -0400)]
nir/validate: Handle unified atomics
nir_validate checks that the format of an atomic (if specified) is compatible
with the atomic operation. For example, we can't fadd R64_UINT texels. The logic
can't be extended as-is to unified atomics because it's split across different
switch cases for different atomic-op intrinsics. So we add our own validation
case, porting over the logic from the separate existing cases below.
(The redundant logic will be deleted once we delete legacy atomics.)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
Alyssa Rosenzweig [Fri, 12 May 2023 14:55:28 +0000 (10:55 -0400)]
nir/opt_uniform_atomics: Handle unified atomics
This is the one place where using nir_atomic_op instead of nir_op directly is a
little annoying, since we need to translate between the two enums, but it's not
a big deal.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
Alyssa Rosenzweig [Fri, 12 May 2023 14:54:05 +0000 (10:54 -0400)]
nir/lower_ssbo: Handle unified atomics
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
Alyssa Rosenzweig [Fri, 12 May 2023 14:53:41 +0000 (10:53 -0400)]
nir/lower_io: Handle unified atomics
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
Alyssa Rosenzweig [Fri, 12 May 2023 17:16:18 +0000 (13:16 -0400)]
nir/lower_task_shader: Handle unified atomics
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
Jesse Natalie [Fri, 12 May 2023 16:13:37 +0000 (09:13 -0700)]
nir: Load/store atomic op indices when lowering image intrinsics
They might not be stored in the same const index after lowering
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
Alyssa Rosenzweig [Fri, 12 May 2023 14:52:57 +0000 (10:52 -0400)]
nir: Handle unified atomics in simple cases
Lots of passes can be made unified-atomics-aware simply by adding extra cases in
their switch statements. This commit fixes a bunch of passes.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
Alyssa Rosenzweig [Thu, 11 May 2023 13:58:39 +0000 (09:58 -0400)]
ir3: Use unified atomics
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
Karol Herbst [Tue, 9 May 2023 16:15:37 +0000 (18:15 +0200)]
nv50/ir: Use unified atomics
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: M Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
Alyssa Rosenzweig [Tue, 9 May 2023 13:02:00 +0000 (09:02 -0400)]
zink: Use unified atomics
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
Alyssa Rosenzweig [Wed, 10 May 2023 23:16:28 +0000 (19:16 -0400)]
aco,radv: Use unified atomics
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
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