andrey.konovalov@linaro.org [Tue, 22 Apr 2014 17:23:49 +0000 (21:23 +0400)]
exynos: usb: Fix data abort on boards w/o vbus-gpio node in the DT
Commit
4a271cb1b4ff doesn't take into account that fdtdec_setup_gpio()
returns success when the gpio passed to it is FDT_GPIO_NONE (no
gpio node found in the fdtdec_decode_gpio() call). This results in
calling gpio_direction_output() on invalid gpio. For this reason
executing "usb start" command on Arndale causes data abort in the
ehci-exynos driver.
Add the fdt_gpio_isvalid() check to fix that problem.
Signed-off-by: Andrey Konovalov <andrey.konovalov@linaro.org>
Cc: Julius Werner <jwerner@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Rob Herring [Fri, 18 Apr 2014 13:54:30 +0000 (08:54 -0500)]
usb: musb: fill in usb_gadget_unregister_driver
Add missing missing disconnect and unbind calls to the musb gadget driver's
usb_gadget_unregister_driver function. Otherwise, any gadget drivers fail
to uninitialize and run a 2nd time.
Signed-off-by: Rob Herring <robh@kernel.org>
Rob Herring [Fri, 18 Apr 2014 13:54:28 +0000 (08:54 -0500)]
usb: handle NULL table in usb_gadget_get_string
Allow a NULL table to be passed to usb_gadget_get_string for cases
when a string table may not be populated.
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Tom Rini <trini@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Przemyslaw Marczak [Fri, 18 Apr 2014 07:48:25 +0000 (09:48 +0200)]
usb:gadget:f_thor: fix write to filesystem by add dfu_flush()
Since dfu read/write operations needs to be flushed manually,
writing to filesystem on MMC by thor was broken. MMC raw write
actually is working fine because current dfu_flush() function
writes filesystem only. This commit adds dfu_flush() to f_thor
and now filesystem write is working.
This change was tested on Trats2 board.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>
Przemyslaw Marczak [Fri, 18 Apr 2014 07:48:24 +0000 (09:48 +0200)]
usb:gadget:f_thor: code cleanup in function download_tail()
In thor's download_tail() function, dfu_get_entity() is called
before each dfu_write() call and the returned entity pointers
are the same. So dfu_get_entity() can be called just once and
this patch changes this.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>
Adrian Cox [Thu, 10 Apr 2014 13:02:44 +0000 (14:02 +0100)]
usb: Fix USB keyboard polling via control endpoint
USB keyboard polling failed for some keyboards on PowerPC 5020.
This was caused by requesting only 4 bytes of data from keyboards that
produce an 8 byte HID report.
Signed-off-by: Adrian Cox <adrian@humboldt.co.uk>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Marek Vasut <marex@denx.de>
Adrian Cox [Thu, 10 Apr 2014 12:29:45 +0000 (13:29 +0100)]
usb: Add endian support macros to interrupt transfers in the EHCI driver.
Update the EHCI driver to support interrupt transfers on PowerPC.
Signed-off-by: Adrian Cox <adrian@humboldt.co.uk>
Nobuhiro Iwamatsu [Thu, 3 Apr 2014 04:55:54 +0000 (13:55 +0900)]
usb: ehci: rmobile: Add support ehci host driver of rmobile SoCs
The rmobile SoC has usb host controller.
This supports USB controllers listed in the R8A7790, R8A7791 and R8A7740.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Shaveta Leekha [Thu, 24 Apr 2014 09:21:23 +0000 (14:51 +0530)]
drivers/i2c/fsl_i2c: modify i2c_read to handle multi-byte write
Most of the I2C slaves support accesses in the typical style
that is : read/write series of bytes at particular address offset.
These transactions look like:"
(1) START:Address:Tx:Offset:RESTART:Address[0..4]:Tx/Rx:data[0..n]:STOP"
However there are certain devices which support accesses in
terms of the transactions as follows:
(2) "START:Address:Tx:Txdata[0..n1]:Clock_stretching:
RESTART:Address:Rx:data[0..n2]"
Here Txdata is typically a command and some associated data,
similarly Rxdata could be command status plus some data received
as a response to the command sent.
Type (1) transactions are currently supportd in the
i2c driver using i2c_read and i2c_write APIs. I2C EEPROMs,
RTC, etc fall in this category.
To handle type (2) along with type (1) transactions,
i2c_read() function has been modified.
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
York Sun [Mon, 10 Feb 2014 22:02:52 +0000 (14:02 -0800)]
driver/mxc_i2c: Move static data structure to global_data
This driver needs a data structure in SRAM before SDRAM is available.
This is not alway the case using .data section. Moving this data
structure to global_data guarantees it is writable.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Troy Kisky <troy.kisky@boundarydevices.com>
Tom Rini [Fri, 25 Apr 2014 19:08:43 +0000 (15:08 -0400)]
Merge branch 'master' of git://denx.de/git/u-boot-arc
Tom Rini [Fri, 25 Apr 2014 19:06:51 +0000 (15:06 -0400)]
Merge branch 'master' of git://denx.de/git/u-boot-ppc4xx
Tom Rini [Fri, 25 Apr 2014 18:57:58 +0000 (14:57 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx
Tom Rini [Fri, 25 Apr 2014 18:53:51 +0000 (14:53 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Alexey Brodkin [Thu, 27 Mar 2014 15:30:18 +0000 (19:30 +0400)]
axs101: bump DDR size from 256 to 512 Mb
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Alexey Brodkin [Mon, 24 Mar 2014 13:15:50 +0000 (17:15 +0400)]
axs101: increase EEPROM page write delay from 32 to 64 msec
With 32 milliseconds delay on some boards EEMPROM got written inconsistently.
With 64 msec all of our existig boards show properly written EEPROM.
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Matthias Fuchs [Tue, 25 Mar 2014 21:00:00 +0000 (22:00 +0100)]
ppc4xx: add support for new PMC440 revision with cleanup
This patch adds support for the new PMC440 hardware revision 1.4.
The board now uses Micrel KSZ9031 phys.
Add missing i2c initialization before reading bootstrap eeprom.
Fix a couple of coding style issues.
Make local functions static.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
Heiko Schocher [Sat, 25 Jan 2014 06:53:48 +0000 (07:53 +0100)]
mpc83xx: add ids8313 support
add support for the ids8313 board.
CPU: e300c3, MPC8313, Rev: 2.1 at 396 MHz, CSB: 132 MHz
I2C: ready
SPI: ready
DRAM: 128 MiB (DDR2, 32-bit, ECC off, 264 MHz)
Flash: 8 MiB
NAND: 128 MiB
Net: TSEC0, TSEC1 [PRIME]
public key on NOR flash start
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Heiko Schocher [Sat, 25 Jan 2014 06:53:47 +0000 (07:53 +0100)]
mpc8313, bootcount: mpc8313 has no qe muram
mpc831x has no muram, so muram cannot be used for bootcounter
function.
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Heiko Schocher [Sat, 25 Jan 2014 06:53:46 +0000 (07:53 +0100)]
powerpc, ids8247: create vendor board dir ids
create vendor board directory ids and move ids8247 board to it.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Tom Rini [Wed, 23 Apr 2014 15:07:11 +0000 (11:07 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-mips
Masahiro Yamada [Mon, 21 Apr 2014 02:33:07 +0000 (11:33 +0900)]
Revert "build: Use filechk rules to create and update u-boot.lds"
This reverts commit
a8b993eb81c142a439c24b871a2317f765fe5397.
Commit
a8b993eb claims it fixes u-boot.lds rule by replacing
$(call if_changed) with $(call filechk).
But the problem had already been fixed by commit
395e60cd
a few days before commit
a8b993eb was posted.
There is no reason to apply commit
a8b993eb. What is worse is
$(call filechk) is too strong to fix the problem and looks weird.
Date of the two patches:
[1] commit
395e60cdc292dc0183c6867d34b43f14a373df55
Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
AuthorDate: Wed Apr 9 20:10:43 2014 +0900
Commit: Tom Rini <trini@ti.com>
CommitDate: Fri Apr 11 10:08:42 2014 -0400
replaces $(call if_changed) -> $(call if_changed_dep)
[2] commit
a8b993eb81c142a439c24b871a2317f765fe5397
Author: Jon Loeliger <jon.loeliger@oracle.com>
AuthorDate: Tue Apr 15 16:09:37 2014 -0500
Commit: Tom Rini <trini@ti.com>
CommitDate: Fri Apr 18 16:14:16 2014 -0400
replaces $(call if_changed) -> $(call filechk)
A conflict must have happened when applying [2], but somehow it was
applied, sadly.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Jon Loeliger <jon.loeliger@oracle.com>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Tom Rini <trini@ti.com>
Zhao Qiang [Mon, 21 Apr 2014 02:29:24 +0000 (10:29 +0800)]
ar8031: modify the config func of ar8031 to ar8021_config
ar8031 has the same config steps with ar8021, so change its
config func to ar8021_config instead of genphy_config.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Shaohui Xie [Tue, 22 Apr 2014 07:10:44 +0000 (15:10 +0800)]
powerpc/T4QDS: add two stage boot of nand/sd
Add support of 2 stage NAND/SD boot loader using SPL framework.
PBL initialise the internal SRAM and copy SPL, this further
initialise DDR using SPD and environment and copy u-boot from
NAND/SD to DDR, finally SPL transfer control to u-boot.
NOR uses CS1 instead of CS2 when NAND boot, fix it.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Shaohui Xie [Mon, 21 Apr 2014 03:21:03 +0000 (11:21 +0800)]
powerpc/t4240: updated RCW and PBI for rev2.0
Updated the RCW for rev2.0 which uses new frequency settings as below:
Clock Configuration:
CPU0:1666.667 MHz, CPU1:1666.667 MHz, CPU2:1666.667 MHz, CPU3:1666.667 MHz,
CPU4:1666.667 MHz, CPU5:1666.667 MHz, CPU6:1666.667 MHz, CPU7:1666.667 MHz,
CPU8:1666.667 MHz, CPU9:1666.667 MHz, CPU10:1666.667 MHz, CPU11:1666.667MHz,
CCB:733.333 MHz,
DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:183.333 MHz
FMAN1: 733.333 MHz
FMAN2: 733.333 MHz
QMAN: 366.667 MHz
PME: 533.333 MHz
Remove workaround of IFC bus speed and SERDES A-006031 of rev1.0.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Prabhakar Kushwaha [Mon, 21 Apr 2014 05:17:41 +0000 (10:47 +0530)]
powerpc/mpc85xx:Update FM1 clock select and shift for B4420
B4420 is a personality of B4860.
It should have same FM1_CLK_SEK and FM1_CLK_SHIFT as B4860
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Shengzhou Liu [Fri, 18 Apr 2014 08:43:41 +0000 (16:43 +0800)]
board/t2080rdb: some update for t2080rdb
- update readme.
- add CONFIG_SYS_CORTINA_FW_IN_* for loading Cortina PHY CS4315
ucode from NOR/NAND/SPI/SD/REMOTE.
- update cpld vbank with SW3[5:7]=000 as default vbank0 instead of
previous SW3[5:7]=111 as default vbank.
- fix CONFIG_SYS_I2C_EEPROM_ADDR_LEN to 2.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Shengzhou Liu [Fri, 18 Apr 2014 08:43:40 +0000 (16:43 +0800)]
board/t208xrdb: Add support of 2-stage NAND/SPI/SD boot
Add support of 2-stage NAND/SPI/SD boot loader using SPL framework.
PBL initializes the internal CPC-SRAM and copy SPL(160K) to it,
SPL further initializes DDR using SPD and environment and copy
u-boot(768K) from SPI/SD/NAND to DDR, finally SPL transfers control
to u-boot.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Shengzhou Liu [Fri, 18 Apr 2014 08:43:39 +0000 (16:43 +0800)]
board/t208xqds: Add support of 2-stage NAND/SPI/SD boot
Add support of 2-stage NAND/SPI/SD boot loader using SPL framework.
PBL initializes the internal CPC-SRAM and copy SPL(160K) to it,
SPL further initializes DDR using SPD and environment and copy
u-boot(768 KB) from SPI/SD/NAND to DDR, finally SPL transfers
control to u-boot.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: fix boards.cfg for T2081QDS_SDCARD and _SPIFLASH]
Reviewed-by: York Sun <yorksun@freescale.com>
Nikhil Badola [Tue, 15 Apr 2014 09:14:52 +0000 (14:44 +0530)]
powerpc/mpc85xx: Add Differential SYSCLK config support T1040
Adds support for clock sourcing from sysclk(100MHz) for usb
on T104xRDB and T1040QDS. This requires changing reference divisor
and multiplication factor to derive usb clock from sysclk.
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
vijay rai [Tue, 15 Apr 2014 06:04:12 +0000 (11:34 +0530)]
powerpc/85xx: Enhance get_sys_info() to check clocking mode
T1040 and it's variants provide "Single Oscillator Source" Reference Clock Mode.
In this mode, single onboard oscillator(DIFF_SYSCLK) can provide the reference clock
(100MHz) to the following PLLs:
• Platform PLL
• Core PLLs
• USB PLL
• DDR PLL, etc
The cfg_eng_use0 of porsr1 register identifies whether the SYSCLK (single-ended) or
DIFF_SYSCLK (differential) is selected as the clock input to the chip.
get_sys_info has been enhanced to add the diff_sysclk so that the
various drivers can be made aware of ths diff sysclk configuration and
act accordingly.
Other changes:
-single_src to ddr_refclk_sel, as it is use for checking ddr reference clock
-Removed the print of single_src from get_sys_info as this will be
-printed whenever somebody calls get_sys_info which is not appropriate.
-Add print of single_src in checkcpu as it is called only once during initialization
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Shaohui Xie [Fri, 11 Apr 2014 04:12:30 +0000 (12:12 +0800)]
powerpc/t1040rdb: added a break in switch case
There should be a break for case PHY_INTERFACE_MODE_SGMII, otherwise it
will fall into case PHY_INTERFACE_MODE_RGMII.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Haijun.Zhang [Thu, 10 Apr 2014 03:16:30 +0000 (11:16 +0800)]
Powerpc/mpc8536DS: Increase SPI/SD uboot Image size to 768K
u-boot binary size for Freescale mpc8536DS platforms is 512KB.
This has been reached to upper limit of the platforms and causig
linker error. So increase the u-boot binary size to 768KB.
Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Prabhakar Kushwaha [Mon, 31 Mar 2014 10:01:48 +0000 (15:31 +0530)]
powerpc/mpc85xx:Update MONITOR_LEN for 768KB u-boot size
U-boot binary size has been increased from 512KB to 768KB.
So update CONFIG_SYS_MONITOR_LEN to reflect the same.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Prabhakar Kushwaha [Mon, 31 Mar 2014 10:01:34 +0000 (15:31 +0530)]
powerpc/mpc85xx:Avoid fix address of bootpg section
It is not necessary for bootpg to be present at text + 512KB.
With increase of u-boot size (768KB), bootpg section's address
cannot be fixed.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Prabhakar Kushwaha [Tue, 8 Apr 2014 13:43:56 +0000 (19:13 +0530)]
board/t104xrdb: Add support of NAND, SD, SPI boot for T104xRDB
Add support of 2 stage NAND, SD, SPI boot loader using SPL framework.
here, PBL initialise the internal SRAM and copy SPL(160KB). This further
initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR.
Finally SPL transer control to u-boot.
Initialise/create followings required for SPL framework
- Add spl.c which defines board_init_f, board_init_r
- update tlb and ddr accordingly
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Prabhakar Kushwaha [Tue, 8 Apr 2014 13:43:44 +0000 (19:13 +0530)]
board/b4qds:Add support of 2 stage NAND boot-loader
Add support of 2 stage NAND boot loader using SPL framework.
here, PBL initialise the internal SRAM and copy SPL(160KB). This further
initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR.
Finally SPL transer control to u-boot.
Initialise/create followings required for SPL framework
- Add spl.c which defines board_init_f, board_init_r
- update tlb and ddr accordingly
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Prabhakar Kushwaha [Tue, 8 Apr 2014 13:43:34 +0000 (19:13 +0530)]
Makefile: Add support of CONFIG_SPL_FSL_PBL
Objective of this target to have concatenate binary having
- SPL binary in PBL command format
- U-boot binary
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Prabhakar Kushwaha [Tue, 8 Apr 2014 13:43:22 +0000 (19:13 +0530)]
driver: Add support of image load for MMC & SPI in SPL
Add support of loading image, binary for MMC and SPI during SPL boot.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Prabhakar Kushwaha [Tue, 8 Apr 2014 13:43:11 +0000 (19:13 +0530)]
driver/mtd/spi:Read 8KB data chunk during u-boot load in SPL
SPI driver perform its operation(read/write) on 64KB buffer chunk for data
greater than 64KB. This buffer chunk is allocated from system heap.
During SPL boot, 768KB of data is read from SPI flash.
Here, heap size may not be sufficient enough to full-fill 64KB buffer
requirement of SPI driver. So break down u-boot read operation at 8KB of chunk.
Also, fix a warning i.e. "unused variable buf" during CONFIG_FSL_CORENET
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Prabhakar Kushwaha [Tue, 8 Apr 2014 13:42:58 +0000 (19:12 +0530)]
driver/ifc: define nand_spl_load_image() for SPL
nand_spl_load_image() can also be used for non TPL framework.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Prabhakar Kushwaha [Tue, 8 Apr 2014 13:42:46 +0000 (19:12 +0530)]
powerpc/mpc85xx:Disable non DDR LAWs before init_law
Before parsing LAW table i.e. init_law, boot loader should disable all
previous LAWs except DDR LAWs which has been created by previous
pre boot loader during DDR initialization.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Prabhakar Kushwaha [Tue, 8 Apr 2014 13:42:31 +0000 (19:12 +0530)]
powerpc:Add support of SPL non-relocation
Current SPL code base has BSS section placed after reset_vector. This means
they have to relocate to use the global variables. This put an implicit
requirement of having SPL size = Memory/2.
To avoid relocation:
- Move bss_section within SPL range
- Modify relocate_code()
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Prabhakar Kushwaha [Tue, 8 Apr 2014 13:42:19 +0000 (19:12 +0530)]
powerpc/mpc85xx: Avoid hardcoding in SPL linker script
SPL linker has fix location of bootpg and reset vector with respect to text base.
It is not necessary to have fixed locations.
Avoid such hardcoding.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Prabhakar Kushwaha [Tue, 8 Apr 2014 13:42:05 +0000 (19:12 +0530)]
powerpc/mpc85xx: Move LAW_EN define outside of config
LAW_EN is only defined if CONFIG_SYS_CCSRBAR_DEFAULT is not equal to
CONFIG_SYS_CCSRBAR_PHYS. in SPL framework CCSRBAR is not relocated hence
both are same. This cause compilation error.
So LAW_EN define outside of configs
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Prabhakar Kushwaha [Mon, 21 Apr 2014 05:17:25 +0000 (10:47 +0530)]
board/t1042rdb_pi: Disable CONFIG_QE and CONFIG_U_QE
T1042RDB_PI board does not have QE connector.
So disable CONFIG_QE and CONFIG_U_QE for T1042RDB_PI
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Prabhakar Kushwaha [Mon, 21 Apr 2014 05:16:59 +0000 (10:46 +0530)]
powerpc/mpc85xx: Remove QE firmware copy from NAND
qe_init() does not use data copied from NAND. Thise code is not tested or
complied causing compilation error during NAND boot
So, remove QE firmware copy from NAND to ddr.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Zhao Qiang [Fri, 21 Mar 2014 08:21:46 +0000 (16:21 +0800)]
T1040QDS/U-QE: Add u-qe support to t1040qds
Add u-qe support for t1040qds
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Tang Yuantian [Thu, 17 Apr 2014 07:33:45 +0000 (15:33 +0800)]
mpc85xx: Add deep sleep support on T104xRDB
Add deep sleep support on T104xRDB platforms.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Tang Yuantian [Thu, 17 Apr 2014 07:33:44 +0000 (15:33 +0800)]
mpc85xx: Add deep sleep support on T1040QDS
Add deep sleep support on T1040QDS platform.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Tang Yuantian [Thu, 17 Apr 2014 07:33:46 +0000 (15:33 +0800)]
mpc85xx/t104x: Add deep sleep framework support
When T104x soc wakes up from deep sleep, control is passed to the
primary core that starts executing uboot. After re-initialized some
IP blocks, like DDRC, kernel will take responsibility to continue
to restore environment it leaves before.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Tang Yuantian [Wed, 26 Mar 2014 08:08:05 +0000 (16:08 +0800)]
mpc85xx: Add support for the supplement configuration unit register
The supplement configuration unit (SCFG) provides chip-specific
configuration and status registers for the device. It is the chip
defined module for extending the device configuration unit (DCFG)
module. It provides a set of CCSR registers in addition to those
available in the device configuration unit.
The base address for this unit is 0x0F_C000.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
York Sun [Tue, 1 Apr 2014 21:20:49 +0000 (14:20 -0700)]
drivers/ddr: Fix possible out of bounds error
This is a theoretical possible out of bounds error in DDR driver. Adding
check before using array index. Also change some runtime conditions to
pre-compiling conditions.
Signed-off-by: York Sun <yorksun@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Priyanka Jain [Tue, 8 Apr 2014 05:25:49 +0000 (10:55 +0530)]
driver/net/fm/memac_phy: Initialize mdio_clock for SoCs wih FMANv3
MDIO clock needs to be initialized in u-boot code for SoCs
having FMAN-v3(v3H or v3L) controller due to below reasons
-On SoCs that have FMAN-v3H like B4860, default value of
MDIO_CLK_DIV bits in mdio_stat(mdio_cfg) register generates
mdio clock too high (much higher than 2.5MHz), violating the
IEEE specs.
-On SOCs that have FMAN-v3L like T1040, default value of
MDIO_CLK_DIV bits is zero, so MDIO clock is disabled.
So, for proper functioninig of MDIO, MDIO_CLK_DIV bits needs to
be properly initialized.
Also this type of initialization is generally done in
PBI(pre-bootloader) phase using rcw.But for chips like T1040
which support deep-sleep, such type of initialization cannot be
done in PBI phase due to the limitation that during deep-sleep
resume, FMAN (MDIO) registers are not accessible in PBI phase.
So, mdio clock initailization must be done as part of u-boot.
This initialization code is implemented in memac_phy.c which
gets compiled only for SoCs having FMANv3, so no extra compilation
flag is required.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Nikhil Badola [Mon, 7 Apr 2014 03:16:14 +0000 (08:46 +0530)]
fsl/usb: Increase TXFIFOTHRESH value for usb write in T4 Rev 2.0
Increase TXFIFOTHRES field value in TXFILLTUNING register of usb for T4 Rev 2.0.
This decreases data burst rate with which data packets are posted from the TX
latency FIFO to compensate for latencies in DDR pipeline during DMA.
This avoids Tx buffer underruns and leads to successful usb writes
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Prabhakar Kushwaha [Thu, 3 Apr 2014 11:20:05 +0000 (16:50 +0530)]
board/t104xrdb: Add support of CPLD
T1040RDB and T1042RDB_PI has CPLD. Here CPLD controls board mux/features.
This support of CPLD includes
- files and register defintion
- Commands to swtich alternate bank and default bank
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Codrin Ciubotariu [Fri, 28 Mar 2014 16:57:29 +0000 (18:57 +0200)]
powerpc/cpu/mpc85xx: Add MAC address for layer 2 switch
T1040RDB and T1040QDS boards have an integrated l2 switch.
The switch needs a MAC address for Layer 2 protocols
(MSTP, LLDP, LACP, etc). Setting a MAC address on l2switchaddr will add
a MAC in device-tree, under node l2switch.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Prabhakar Kushwaha [Wed, 2 Apr 2014 11:56:23 +0000 (17:26 +0530)]
powerpc/T1040: add mtdparts suppport for T104xRDB and T1040QDS
We use dynamical mtdparts partition instead of directly puting
mtd partitions nodes in device tree.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Shengzhou Liu [Wed, 2 Apr 2014 06:28:35 +0000 (14:28 +0800)]
powerpc/T208xRDB: add mtdparts suppport
We use dynamical mtdparts partition instead of directly puting
mtd partitions nodes in device tree.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Shengzhou Liu [Wed, 2 Apr 2014 06:28:34 +0000 (14:28 +0800)]
powerpc/T208xQDS: add mtdparts suppport
We use dynamical mtdparts partition instead of directly puting
mtd partitions nodes in device tree.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
vijay rai [Mon, 31 Mar 2014 06:16:34 +0000 (11:46 +0530)]
powerpc/t104xrdb: Unification of T104xRDB header files
T1040RDB, T1042RDB header files are very similar so merged into new header file T104xRDB.
T104xRDB header file can support both T1040RDB and T1042RDB_PI header.
Patch makes following changes
-Update Boards.cfg file for T1040RDB and T1042RDB_PI
-Add new T104xRDB header file
-Delete T1040RDB, T1042RDB_PI header file
Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Prabhakar Kushwaha [Mon, 31 Mar 2014 10:02:03 +0000 (15:32 +0530)]
driver/mmc: fix compile warnings
Fix following compile warnings
fsl_esdhc_spl.c: In function 'mmc_boot':
fsl_esdhc_spl.c:35:10: warning: unused variable 'byte_num' [-Wunused-variable]
fsl_esdhc_spl.c:35:7: warning: unused variable 'i' [-Wunused-variable]
fsl_esdhc_spl.c:34:8: warning: unused variable 'val' [-Wunused-variable]
fsl_esdhc_spl.c:33:6: warning: unused variable 'blklen' [-Wunused-variable]
fsl_esdhc_spl.c:105:7: warning: 'tmp_buf' may be used uninitialized in this
function [-Wuninitialized]
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
York Sun [Fri, 28 Mar 2014 22:07:27 +0000 (15:07 -0700)]
powerpc/mpc85xx: Add workaround for erratum A007212
Erratum A007212 for DDR is about a runaway condition for DDR PLL
oscilliator. Please refer to erratum document for detail.
For this workaround to work, DDR PLL needs to be disabled in RCW.
However, u-boot needs to know the expected PLL ratio. We put the
ratio in a reserved field RCW[18:23]. U-boot will skip this workaround
if DDR PLL ratio is set, or the reserved field is not set.
Workaround for erratum A007212 applies to selected versions of
B4/T4 SoCs. It is safe to apply the workaround to all versions. It
is helpful for upgrading SoC without changing u-boot. In case DDR
PLL is disabled by RCW (part of the erratum workaround), we need this
u-boot workround to bring up DDR clock.
Signed-off-by: York Sun <yorksun@freescale.com>
Shengzhou Liu [Thu, 13 Mar 2014 02:19:00 +0000 (10:19 +0800)]
powerpc/t208xqds: fix nor chip selection when nand boot
NOR flash is on CS1 instead of CS2 when NAND boot.
So correct NOR chip selection to CS1 from CS2.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Nikhil Badola [Wed, 26 Feb 2014 12:13:15 +0000 (17:43 +0530)]
fsl/usb: Workaround for USB erratum-A007075
Put a delay of 5 millisecond after reset so that ULPI phy
gets enough time to come out of reset. Erratum A007075 applies
to following SOCs and their variants, if any
P1010 rev 1.0
B4860 rev 1.0, 2.0
P4080 rev 2.0, 3.0
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
York Sun [Fri, 28 Mar 2014 00:54:48 +0000 (17:54 -0700)]
mpc85xx/T1040QDS_D4: Add DDR4 support
T1040QDS_D4 is a variant of T1040QDS, with additional circuit to support
DDR4 memory. Tested with MTA9ASF51272AZ-2G1AYESZG.
Signed-off-by: York Sun <yorksun@freescale.com>
York Sun [Fri, 28 Mar 2014 00:54:47 +0000 (17:54 -0700)]
driver/ddr/fsl: Add DDR4 support to Freescale DDR driver
Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register
calculation and programming.
Signed-off-by: York Sun <yorksun@freescale.com>
Scott Wood [Thu, 27 Mar 2014 01:30:56 +0000 (20:30 -0500)]
powerpc/85xx: Fix e6500 L2 cache stash IDs
The value written to L2CSR1 didn't match the value written to the
device tree.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Codrin Ciubotariu [Wed, 26 Mar 2014 16:13:14 +0000 (18:13 +0200)]
net/phy: Fix PHY id for VSC8514
In the current Datasheet for VSC8514 there is a mistake, saying that
the PHY id is 0x70570. The real value in the identifier registers is
0x70670. Linux PHY driver uses 0x70670 also.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
York Sun [Wed, 19 Mar 2014 20:52:34 +0000 (13:52 -0700)]
driver/fsl_ifc: Add a function to finalize CS0 address binding
For fsl-lsch3 NOR flash boot, IFC CS0 needs to be binded with address
within 32-bit at fist. After u-boot relocates to DDR, CS0 can be binded
to higher address to support large space.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Prabhakar Kushwaha <prabhakar@freescale.com>
Prabhakar Kushwaha [Sat, 8 Mar 2014 11:15:04 +0000 (16:45 +0530)]
board/b4860qds:Slow MDC clock to comply IEEE specs in PBI config
The MDC generate by default value of MDIO_CLK_DIV is too high i.e. higher
than 2.5 MHZ. It violates the IEEE specs.
So Slow MDC clock to comply IEEE specs
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Zhao Qiang [Fri, 14 Mar 2014 02:11:03 +0000 (10:11 +0800)]
t1040rdb/qe: add QE support for T1040RDB
add CONFIG_QE, CONFIG_U_QE and CONFIG_SYS_QE_FW_ADDR into
"include/configs/T1040RDB.h"
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Zhao Qiang [Fri, 21 Mar 2014 08:21:45 +0000 (16:21 +0800)]
QE/U-QE: Add U-QE support
Modify code to adapt to both u-qe and qe.
U_QE is a kind of cutted QE.
the differences between U_QE and QE
1. UCC: U_QE supports 2 UCCs while QE supports up to 8 UCCs.
2. IMMR: have different immr base addr.
3. iopin: U_QE doesn't need to config iopin.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Zhao Qiang [Fri, 21 Mar 2014 08:21:44 +0000 (16:21 +0800)]
QE/FMAN: modify CONFIG_SYS_QE_FMAN_FW_ADDR to CONFIG_SYS_FMAN_FW_ADDR and CONFIG_SYS_QE_FW_ADDR
CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address.
Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address,
and CONFIG_SYS_QE_FW_ADDR for QE microcode address.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Aneesh Bansal [Tue, 18 Mar 2014 18:11:14 +0000 (23:41 +0530)]
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T1040QDS and T1040RDB
Secure Boot Target is added for T1040QDS and T1040RDB
Changes:
For Secure boot, CPC is configured as SRAM and used as house
keeping area which needs to be disabled.
So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T1040QDS and
CONFIG_T1040RDB
Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Aneesh Bansal [Tue, 18 Mar 2014 18:10:59 +0000 (23:40 +0530)]
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T2080QDS
Secure Boot Target is added for T2080QDS
Changes:
For Secure boot, CPC is configured as SRAM and used as house
keeping area which needs to be disabled.
So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080QDS.
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Aneesh Bansal [Tue, 18 Mar 2014 18:10:42 +0000 (23:40 +0530)]
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T4240QDS and T4160QDS
Secure Boot Target is added for T4240QDS and T4160QDS
Changes:
For Secure boot, CPC is configured as SRAM and used as house
keeping area which needs to be disabled.
So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T4240QDS.
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Aneesh Bansal [Tue, 18 Mar 2014 18:10:26 +0000 (23:40 +0530)]
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS
Changes:
1. L2 cache is being invalidated by Boot ROM code for e6500 core.
So removing the invalidation from start.S
2. Clear the LAW and corresponding configuration for CPC. Boot ROM
code uses it as hosekeeping area.
3. For Secure boot, CPC is configured as SRAM and used as house
keeping area. This configuration is to be disabled once in uboot.
Earlier this disabling of CPC as SRAM was happening in cpu_init_r.
As a result cache invalidation function was getting skipped in
case CPC is configured as SRAM.This was causing random crashes.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Aneesh Bansal [Wed, 12 Mar 2014 16:30:18 +0000 (22:00 +0530)]
powerpc/mpc85xx: SECURE BOOT- Add NAND secure boot target for BSC9132QDS
In case of secure boot from NAND, the DDR is initialized by the
BootROM using the config words (CF_WORDS) in the CF_HEADER
and u-boot image is copied from NAND to DDR by the BootROM.
So, CONFIG_SYS_RAMBOOT has been defined for Secure Boot from NAND
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Aneesh Bansal [Tue, 11 Mar 2014 18:37:27 +0000 (00:07 +0530)]
powerpc/mpc85xx: SECURE BOOT- Add secure boot target for BSC9132QDS
Add NOR, SPI and SD secure boot targets for BSC9132QDS.
Changes:
- Debug TLB entry is not required for Secure Boot Target.
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Aneesh Bansal [Tue, 11 Mar 2014 17:51:45 +0000 (23:21 +0530)]
powerpc/mpc8xxx: SECURE BOOT- Disable law 0 for non PBL platforms
ISBC creates a LAW 0 entry for non PBL platforms, which is not
disabled before transferring the control to uboot.
The LAW 0 entry has to be disabled.
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Aneesh Bansal [Mon, 20 Jan 2014 09:27:03 +0000 (14:57 +0530)]
powerpc/p1010rdb: SECURE BOOT- enable workaround for IFC errata A003399
The workaround for IFC errata A003399 was not enabled
in case of secure boot. So, secure boot from NOR was not
working.
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Aneesh Bansal [Fri, 7 Mar 2014 13:42:09 +0000 (19:12 +0530)]
powerpc/p1010rdb: SECURE BOOT enabled for NAND
In case of secure boot from NAND, the DDR is initialized by the
BootROM using the config words (CF_WORDS) in the CF_HEADER
and u-boot image is copied from NAND to DDR by the BootROM.
So, CONFIG_SYS_RAMBOOT has been defined for Secure Boot from NAND.
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Nikhil Badola [Thu, 19 Dec 2013 05:38:46 +0000 (11:08 +0530)]
fsl/usb: Fix phy type for Second USB controller
Set correct phy_type value for second USB controller.
This is required for supporting SOCs having 2 USB controllers
working simultaneously, one with UTMI phy and other with ULPI phy
Signed-off-by: Nikhil Badola <B46172@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Alexander Graf [Fri, 11 Apr 2014 15:09:45 +0000 (17:09 +0200)]
PPC 85xx: Add qemu-ppce500 machine
For KVM we have a special PV machine type called "ppce500". This machine
is inspired by the MPC8544DS board, but implements a lot less features
than that one.
It also provides more PCI slots and is supposed to be enumerated by
device tree only.
This patch adds support for the generic ppce500 machine and tries to
rely solely on device tree for device enumeration.
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Alexander Graf [Fri, 11 Apr 2014 15:09:44 +0000 (17:09 +0200)]
PPC 85xx: Add ELF entry point
We want to be able to directly execute the ELF binary without going
through the u-boot.bin one.
To know where we have to start executing this ELF binary we have to
tell the linker where our entry point is.
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Alexander Graf [Fri, 11 Apr 2014 15:09:43 +0000 (17:09 +0200)]
PPC: 85xx: Generalize DDR TLB mapping function
The DDR mapping function really is just a generic virtual -> physical
mapping function. Generalize it so it can support any virtual starting
offset and IO maps just the same.
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Alexander Graf [Fri, 11 Apr 2014 15:09:42 +0000 (17:09 +0200)]
PPC: 85xx: Remove IVOR reset
There is no need to set IVORs to anything but their default values,
so let's leave them where they are.
Suggested-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Scott Wood <scottwood@freescale.com>
[York Sun: Add back $(obj)start.S section in mpc8572ds/Makefile]
Reviewed-by: York Sun <yorksun@freescale.com>
Alexander Graf [Fri, 11 Apr 2014 15:09:41 +0000 (17:09 +0200)]
fdt_support: Add helper function to read "ranges" property
This patch adds a helper function that can be used to interpret most
"ranges" properties in the device tree.
It reads the n'th range out of a "ranges" array and returns the node's
virtual address of the range, the physical address that range starts at
and the size of the range.
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Alexander Graf [Fri, 11 Apr 2014 15:09:40 +0000 (17:09 +0200)]
fdt_support: split fdt_getprop_u32_default
We already have a nice helper to give us a property cell value with default
fall back from a path. Split that into two helpers - one for the old path
based lookup and one to give us a value based on a node offset.
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Daniel Schwierzeck [Thu, 17 Apr 2014 19:45:59 +0000 (21:45 +0200)]
MAKEALL: remove hard-coded MIPS boards
Remove all MIPS boards and use $(targets_by_arch mips) for
filling list_MIPS.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Daniel Schwierzeck [Wed, 9 Apr 2014 22:39:28 +0000 (00:39 +0200)]
MIPS: drop incaip board
This is dead hardware and no one is interested in making the
necessary changes for upcoming features like generic board or
driver model.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Paul Burton [Mon, 7 Apr 2014 09:11:23 +0000 (10:11 +0100)]
MIPS: Malta: convert to generic board
This patch converts the MIPS Malta development board to make use of the
generic board code now that it is supported on MIPS.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Mon, 7 Apr 2014 09:11:22 +0000 (10:11 +0100)]
MIPS: allow use of generic board
This patch allows MIPS boards to make use of generic board, replacing
arch/mips/lib/board.c with common/board_{f,r}.c and struct bd_info with
the asm-generic version.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Mon, 7 Apr 2014 09:11:21 +0000 (10:11 +0100)]
board_f: call timer_init on MIPS
MIPS needs a call to timer_init to preserve its current behaviour
ensuring that the cop0 compare register is initialised appropriately.
Reported-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Mon, 7 Apr 2014 09:11:20 +0000 (10:11 +0100)]
board_f: call init_func_ram on MIPS
Assigning gd->ram_size the return value of initdram matches the existing
MIPS board behaviour.
Suggested-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Mon, 7 Apr 2014 09:11:19 +0000 (10:11 +0100)]
MIPS: define __init_end in u-boot.lds
The generic board code uses the __init_end symbol to calculate
monitor_flash_len. Define said symbol for MIPS, equivalent to
__image_copy_end which is used for the same purpose in
arch/mips/lib/board.c.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Mon, 7 Apr 2014 09:11:18 +0000 (10:11 +0100)]
MIPS: move mips_io_port_base out of board.c
Move the definition of this variable out of arch/mips/lib/board.c in
preparation for allowing use of generic board on MIPS, which will lead
to this file not being compiled.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Paul Burton [Mon, 7 Apr 2014 09:11:17 +0000 (10:11 +0100)]
MIPS: stub interrupt_init function
interrupt_init is called unconditionally by the generic board code.
Define a stub for it on MIPS like the enable & disable functions.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Masahiro Yamada [Fri, 7 Mar 2014 09:02:02 +0000 (18:02 +0900)]
cosmetic: README: add some entries to Directory Hierarchy
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>