radeonsi: implement get_compute_state_info

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19232>

zink: unroll array loop when copying vars for passthrough shaders

wildcard derefs aren't supported in ntv

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22376>

d3d12: Video processor to only promote resources to permanent residency when there is work to be flushed

This fixes some cases where flush is called from the app without work being scheduled before, causing d3d12_promote_to_permanent_residency
to be called with garbage pointers/arguments.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22415>

vulkan: Sanitize pSampleMask in CmdSetSampleMaskEXT

ms.sample_mask is only 16b, while VkSampleMask is 32b and it is allowed
to have all of them set even if maximum 16 samples are supported.

E.g. happens with Zink running supertuxkart:
 supertuxkart: ../../../source/mesa/src/vulkan/runtime/vk_graphics_state.c:2346: vk_common_CmdSetSampleMaskEXT: Assertion `(dyn)->ms.sample_mask == (*pSampleMask)' failed.

  vk_common_CmdSetSampleMaskEXT (commandBuffer=0x5556e903f0, samples=VK_SAMPLE_COUNT_1_BIT, pSampleMask=0x5556819ccc) at vk_graphics_state.c:2346
  zink_draw<(zink_multidraw)1, (zink_dynamic_state)5, true, false> (...) at zink_draw.cpp:639
  zink_draw_vbo<(zink_multidraw)1, (zink_dynamic_state)5, true> (...) at zink_draw.cpp:922

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22360>

zink: block oom flushes during unordered blits

this is broken beyond space and time

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22412>

radv/amdgpu: Place secondary CS without IB2 in non-WC GTT.

When using a secondary CS without IB2, we have to memcpy the
contents into the primary CS. Use these flags to improve perf
by preventing memcpy from VRAM.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22354>

radv/amdgpu: Extract radv_amdgpu_cs_bo_create function.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22354>

radv/amdgpu: Add bool is_secondary argument to cs_create function.

Also save is_secondary to the CS object.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22354>

radv: Allow task/mesh shaders with RADV_DEBUG=noibs.

The new submit code path should now be able to handle gang submit
even when chaining is not enabled.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22354>

radv/amdgpu: Respect maximum number of submitted IBs per IP type.

In a gang submit, the maximum number of IBs is per IP type,
and is different for each queue. Let's respect that.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22354>

radv/amdgpu: Clean up submission functions.

Remove a useless extra function call, and rename fallback to
internal because it is the only code path left.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22354>

radv/amdgpu: Use fallback submit for queues that can't use IBs.

This commit consolidates the queue submit code paths into one.

Now we always allocate BOs for every CS, but when IBs aren't
allowed, we simply submit every BO to the kernel.

A microbenchmark done by Bas indicated that submitting more IBs to
the kernel only adds a negligible overhead. Additionally, this
allows us to stop copying the command buffer contents in system
memory and get rid of a lot of legacy code.

In order to be able to submit every BO, we make sure to add the
last BO to the old_ib_buffers array on cs_finalize. This also
necessitates some changes in cs_execute_secondary and other
functions.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22354>

radv: Split submission in winsys instead of radv_queue.

This will still make it so that RADV_DEBUG=hang will only submit
one command buffer at a time, but otherwise let's pass all CS
objects into one submission and let the winsys split them if
necessary.

The winsys can do a better job at splitting them because
radv_queue has no knowledge of IBs and ignores chaining in the
splitting logic.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22354>

radv: Fill continue preambles and postambles properly.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22354>

radv/amdgpu: Split gang submissions correctly when not chained.

In a gang submit, the follower (typically ACE) and leader
(typically GFX) can have synchronization between each other.
We must ensure that these end up in the same submission,
otherwise we can deadlock the GPU.

We rely on radv_queue here to order follower before the leader
in the submitted CS array.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22354>

radv/amdgpu: Add ability to submit non-chained CS to fallback.

When submitting a CS whose IP type doesn't support chaining,
let's submit all the IBs that this CS allocated.

This is going to be better than the sysmem code path because it
doesn't require the winsys to memcpy the contents of the command
buffers.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22354>

radv/amdgpu: Add postambles to fallback submit.

Some new features, such as perf counters and gang submit use
postambles. Implement these properly.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22354>

radv/amdgpu: Add continue preambles to fallback submit.

When splitting a larger submission into several smaller ones,
the flushing at the beginning of the initial preambles is not
really necessary, so it'll be better to use the continue
preambles for this purpose.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22354>

radv/amdgpu: Allow multiple continue preambles.

For feature parity with initial preambles.
Previously, continue preambles were for GFX6 only, but this is
about to change in the next commits.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22354>

radv/amdgpu: Rewrite fallback code path so it can split submissions.

Currently, radv_queue already splits submissions but we want to
change this and be able to split them in the winsys code as well.
Necessary because we want to split based on number of actual
IBs not number of command buffers, but radv_queue is not
aware of IBs.

Note that this commit does not actually take this new split into
use yet, that will be done in a following commit when it is ready,
this is why we set the max IB count higher than radv_queue here.

This commit is the first step in making "fallback" the default and
only submission code path.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22354>

radv/amdgpu: Remove hw_can_chain in favour of use_ib.

They have the same meaning, but use_ib makes more sense because it
also takes the gfx_level into account.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22354>

radv/amdgpu: Add a few assertions during submit.

These are useful when debugging the submission code.

- Ensure correct IB alignment
- Ensure we don't submit empty IBs

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22354>

radv/amdgpu: Extract radv_amdgpu_cs_add_old_ib_buffer.

This function will be used elsewhere in a following commit.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22354>

radv/amdgpu: Use correct alignment when creating CS BOs.

Shouldn't matter in practice because the kernel will likely
give us a page-aligned BO, but better to specify it just
in case.

Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22354>

radv/amdgpu: Only allow IB BOs on graphics and compute queues.

This disallows IB BOs on eg. SDMA queues which was previously
mistakenly left out.

Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22354>

radv/amdgpu: Fix mismatching return type of radv_amdgpu_cs_submit.

Fixes a warning that is reported by GCC 13.

Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22354>

ac: Add maximum number of submitted IBs.

The number of IBs per submit isn't infinite, it depends on the IP type
(ie. some initial setup needed for a submit) and the packet size.
It can be calculated according to the kernel source code as:
(ring->max_dw - emit_frame_size) / emit_ib_size

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22354>

radv: Create continue preamble on GFX6 even when no shader rings are used.

Skipping the continue preamble can allow other processes to mess
up some registers set by the current process.

Originally, we could omit generating the continue preamble when
no shader rings were used, because the register initialization
happened at the beginning of every main cmdbuf. However, this
isn't the case anymore.

Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22354>

zink: bs->dd.push_pool[1].pool should be freed

cc: mesa-stable

Signed-off-by: xurui <xurui@kylinos.cn>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22389>

egl: fix memory leak related to _eglRefreshDeviceList()

Indeed, the unnecessary drmDevice objects were not freed.

For instance, this issue could be triggered with: "piglit/bin/egl_ext_platform_device -auto -fbo":
SUMMARY: AddressSanitizer: 2796 byte(s) leaked in 12 allocation(s).

Fixes: e39d72aec203 ("egl: only take render nodes into account when listing DRM devices")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22408>

ci/amd: add draw.dynamic_rendering flake

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22411>

v3dv/ci: mark known dEQP-VK.wsi.xlib.surface.query_formats failure

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22410>

radv: Align atomic values.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22121>

util/disk_cache: Align atomic size.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22121>

util: Add aligned int64_t types for x86(non 64).

To avoid split locks.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22121>

radv: fix re-emitting vertex user SGPRs when binding a graphics pipeline

The base SGPR and the number of SGPRs can be equal but it was incorrect
because one VS can have draw_id and one can have base_instance. Fix
this by invalidating the vertex user SGPRs unconditionally.

Though they should also be invalidated after executing secondaries,
otherwise nothing is invalidated if the same pipeline is bind to the
primary again.

This fixes dEQP-VK.dynamic_rendering.primary_cmd_buff.random.seed*.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21652>

radv/ci: add 2 more Flakes for Navi21

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22030>

radv: clean up pipeline-cache interface

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22030>

radv: use vk_pipeline_cache

Replaces the RADV pipeline cache with an implementation
based on the common vk_pipeline_cache.

We use a dual-layer approach with two types of cache entries.

  1. radv_shader:
    - serialized as radv_shader_binary
    - uses SHA1 of the binary as key
  2. radv_pipeline_cache_object:
    - contains pointers to associated radv_shaders
    - serialized as list of SHA1
    - uses the pipeline hash as key

In combination with single-file disk-cache, this reduces the cache size by ~60%.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22030>

radv: implement radv_shader_create_cached()

This function takes a radv_shader_binary and writes it to the
disk cache before creating and returning a radv_shader cache entry.
The key of the cache entry is the full SHA1 hash of the binary.
This way, we will be able to deduplicate identical shaders.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22030>

radv: add struct radv_pipeline_cache_object

This patch implements a per pipeline cache-entry which contains
pointers to the associated shaders.
The serialized format contains the binary hashes of the shaders.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22030>

radv: add radv_shader_serialize() and radv_shader_deserialize() functions

These functions convert between radv_shader and radv_shader_binary.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22030>

radv: unconditionally store the binary code in radv_shader

We will (temporarily) use it to serialize shader binaries
with the common vk_pipeline_cache.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22030>

radv: derive struct radv_shader from vk_pipeline_cache_object

We will use radv_shader directly as cache entries.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22030>

intel/fs: use nomask for setting cr0 for float controls

The instructions manipulation cr0 use the default mask on lane0. So if
for some reason that lane is disabled in some of the dispatchs, we can
end up not executing the instructions.

Fixes flakyness in dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_32_to_16.uniform_matrix_float_rtz_frag

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22314>

mesa: Add EXT_instanced_arrays support

The support for ARB_instanced_arrays already exists for big GL, reuse the same
PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR for this extension.

The OES_draw_elements_base_vertex and EXT_draw_elements_base_vertex both define
the DrawElementsInstancedBaseVertex method when EXT_instanced_arrays is defined.

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22167>

glapi: Make EXT_draw_instanced functions available for GLES 2.0

The EXT suffixed functions should be available in the GLES 2.0 context.

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22167>

mesa: OpenGL ES 3.0 requires EXT_instanced_arrays

Add it to the list of the required extensions.

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22167>

anv: fixup streamout write barriers

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8796
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22336>

radv: Remove radv_bvh_aabb_node::aabb

It was only read by RRA which can infer it from the parenbt internal
node.

Change in average build time (Control):
84.69471 ms -> 84.25319 ms

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22400>

radv/bvh: Remove calculate_node_bounds

It is unused and will prevent removing the aabb field from
radv_bvh_aabb_node.

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22400>

radv: Pack and encode geometry id and flags on the CPU

There is no need to do it on the GPU.

Change in average build time (Control):
84.80691 ms -> 84.69471 ms

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22400>

radv: Remove has_previous_stage

MESA_SHADER_NONE implies that has_previous_stage is false.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22382>

aco: Remove is_gs_copy_shader

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22382>

radv: Remove some dead radv_shader_args setup

radv_declare_shader_args already sets them up.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22382>

radv: Add radv_shader_type to fix gs_copy and trap handler handling

is_gs_copy_shader and is_trap_handler_shader were cleared in
radv_init_shader_args. This restores the original behaviour.

Fixes: 67635bb ("radv: zero-initialize radv_shader_args right before declaring them")
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22382>

nir/lower_blend: Enable per-sample shading

Loading output require per-sample blending, so enable per-sample execution of
the shader as a whole so the right sample values are blended. Affects:

dEQP-GLES31.functional.multisample.default_framebuffer.sample_mask_sum_of_inverses

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22385>

nir/lower_blend: Set uses_fbfetch_output conservatively

Only insert a load_output if we're going to use it, don't rely on it getting
DCE'd since that will mess up the shader info. This does require a bit of logic
to figure out whether we do need it.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22385>

mesa/st: Set uses_sample_shading when forcing per-sample

In addition to requiring per-sample interpolation, sample shading
changes the behaviour of gl_SampleMaskIn, so we need per-sample shading
even if there are no shader-in variables at all. In that case,
uses_sample_shading won't be set by glsl_to_nir. We need to do so here.

Affected dEQP test on asahi:

   dEQP-GLES31.functional.shaders.sample_variables.sample_mask_in.bits_unique_per_two_samples.multisample_texture_4

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22402>

d3d12: Support creating PSOs with no attachments with MSAA without TIR

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22402>

venus: forward ARM driverVersion for ANGLE workarounds

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22242>

ci/amd: raven is currently downgraded to 2 machines only, adapt

Revert when all 5 machines are back online.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22403>

ci/amd: update device status

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22403>

Revert "mesa: Enable NV_texture_barrier in GLES2+"

Fixes failing skqp GLES test:
 - gles_lcdblendmodes

This reverts commit c7da969f8fe1b78d2479623e2510e52827c3035a.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22403>

radv: Add RT stages to radv_mesa_to_rgp_shader_stages

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22367>

lavapipe: implement inline variant caching

inlining is great, but it's less great if a new variant must be created
for every draw

to avoid this, cache inlined variants for reuse

Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22363>

lavapipe: don't double-inline ubo0

this was already handled above and causes negative indexing

cc: mesa-stable

Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22363>

ci: Run clang-format on panfrost

So we don't regress formatting in the future. This should never really trigger
if people configure their editors correctly, but it can help avoid regressing
the formatting from drive-by patches.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22372>

panvk: Clang-format

We're going to enforce clang-format in CI, so get with the program! This doesn't
change a *ton* all considered, because panvk was already aiming for the style we
have in the panfrost clang-format file.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22372>

panfrost: Re-run clang-format

We've regressed the clang-formatting in a few places, since we're not enforcing
formatting in CI yet and I think at one point my editor wasn't quite right.
Reapply so we can get to clang-format-clean.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22372>

pan/decode: Move comment out of designated initializer

clang-format chokes on this.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22372>

panfrost/winsys: Clang-format

This was missed in the original clang-format commit because I touch this code so
infrequently, lol.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22372>

panfrost/winsys: Add .clang-format for winsys folder

Last place where Panfrost code hides.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22372>

panfrost: Symlink gallium .clang-format to common

So we only have one .clang-format file to worry about.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22372>

mailmap: Update my e-mail

https://rosenzweig.io/blog/passing-reins-panfrost.html

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22399>

lavapipe: refactor/consolidate GPL shader copying

this is easier to read/modify

also add asserts for members that should be null

Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22352>

lavapipe: copy fragment shader when merging GPL pipelines

this otherwise loses access data and causes flakiness with atomic ops

Fixes: 6e5fe71599b ("lavapipe: split out shader struct members into their own struct")

Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22352>

radv: Don't include nir.h in radv_shader.h

Avoid recompiling some RADV files when something changes in NIR.
Also clean up a few other includes.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22241>

aco: Only include nir.h in instruction selection.

Don't recompile entire ACO when something changes in NIR.
Instead, only use some headers which are actually needed,
include these in ACO files instead of relying on nir.h to
include them.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22241>

aco: Don't use nir_selection_control in aco_ir.

We don't want to rely on any NIR structures in ACO, because
we would like to avoid the need to include nir.h in aco_ir.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22241>

aco: Fix optimization of v_cmp with subgroup invocation.

There was a typo in this optimization which went unnoticed.

Fixes: 2c40215ab9d20890efb88e7b3e26ca909d7fd74b
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22393>

venus: move exp feature init back to ring and remove unused function

This mostly undos 476c771e34fefaf2aab12ca3417d04a5be4ce46d and removes
the unused vn_renderer_submit_simple_sync.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22323>

venus: requires ringMonitoring

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22323>

venus: requires asyncRoundtrip

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22323>

dzn: Don't enable bindless by default

There's bad interactions with dynamic buffers at this point:
* Perf issues due to allocating and freeing the buffer to store indices/offsets
* Large dynamic uniform buffer offsets (above 65K) cause out-of-bounds reads

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22371>

dzn: Never set STATE_RENDER_TARGET on a compute command list

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22371>

dzn: Ignore unnormalized sampling flag if driver doesn't support it

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22371>

dzn: Use a linear allocator for upload data on command buffers

Significantly improves performance for apps that heavily use
dynamic descriptors.

Still needs caching so they can be re-used after command buffer reset.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22371>

dzn: Changes to descriptor set dirty flag handling

The scenario of:
* App binds multiple descriptor sets
* App binds a pipeline that uses a subset of them
* App binds a pipeline that uses more of them

was broken. We were only copying the descriptors for the accessible
subset before, but then clearing all dirty bits, so simply changing
the pipeline wouldn't result in more descriptors being copied.

When running not-bindless, the right thing to do is to copy *all*
descriptors if we're copying any. When running bindless, each parameter
is set separately, and more importantly, *can't* be set on the command
list if the root signature can't access them.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22371>

microsoft/compiler: Don't split loads/stores that will be split by lower_explicit_io

Otherwise we can end up splitting push constant loads, which currently require
an unbroken (no-cast) deref chain up to the variable.

Fixes: 4c527f4f ("spirv2dxil: Lower unaligned loads and stores")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22371>

docs: add more release notes for RADV

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22390>

nir: make nir_fisnan helper exact

Floating point ALU assume no NaNs unless
FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FPn or (for some opcodes)
exact=true.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Fixes: bf9c1699cd7 ("nir: add nir_fisnan helper function")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22206>

radv: Set DB_Z_INFO.NUM_SAMPLES to MSAA_EXPOSED_SAMPLES without Z/S

This case is a new addition in GFX11, and according to PAL, when no
depth/stencil attachment is bound, it must be set to the number of coverage
samples (the number of SampleMask bits - which is MSAA_EXPOSED_SAMPLES):

https://github.com/GPUOpen-Drivers/pal/blob/4640888b579bc9b0951c586b08a4552f71780d0d/src/core/hw/gfxip/gfx9/gfx9UniversalCmdBuffer.cpp#L6978

Without this change, the maximum of depth/stencil and color sample counts
is used, and if there are no depth/stencil or color attachments (target-
independent rasterization), the Depth Block assumes 1 coverage sample, and
thus Primitive Ordered Pixel Shading doesn't work correctly (and fails 4xAA
fragment shader interlock CTS tests), and occlusion queries don't count the
correct number of samples (according to the "Sample Counting" section of
the Vulkan specification, "the occlusion query sample counter increments by
one for each sample with a coverage value of 1...")

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22375>

zink: try to prune resources from barrier jit on fb unbind

if a resource has no binds remaining then it should not remain in
the queue for barrier updates on the next draw

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22398>

winsys/amdgpu: Fix amdgpu_cs_query_reset_state2 error log

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: André Almeida <andrealmeid@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22253>

radv: Implement vk.check_status

Implement check_status function so the driver can check if the GPU has
been reset by the application, and thus if it's still available.

AMDGPU_CTX_QUERY ioctls work by asking amdgpu if this context was the
cause of a previous GPU reset.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: André Almeida <andrealmeid@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22253>

radv/ci: update expected failures with BONAIRE

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22391>

radv/ci: remove no longer existing tests for PITCAIRN

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22366>

radv/ci: update expected failures for PITCAIRN

These have been recently fixed.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22366>

radv: enable VK_EXT_graphics_pipeline_library by default

You won't get your money back!

It's been a very long time but everything should be working great now.

This replaces RADV_PERFTEST=gpl by RADV_DEBUG=nogpl to disable the
extension for debugging purposes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22362>