lhutton1 [Wed, 18 Mar 2020 17:21:05 +0000 (17:21 +0000)]
[RELAY] Codegen_c.h should include relay.function (#5093)
Change-Id: I015b2c66a50b64d0eb2e9efe336f6c18ea1fdc67
Samuel [Wed, 18 Mar 2020 16:06:00 +0000 (21:36 +0530)]
Description updated for pooling attributes (#5091)
MORITA Kazutaka [Wed, 18 Mar 2020 16:05:49 +0000 (01:05 +0900)]
[CODEGEN][OPENCL] Explicitly cast min/max operands (#5090)
* [CODEGEN][OPENCL] Explicitly cast min/max operands
* retrigger CI
Zhi [Wed, 18 Mar 2020 15:56:55 +0000 (08:56 -0700)]
create function.py (#5087)
Zhi [Wed, 18 Mar 2020 03:01:15 +0000 (20:01 -0700)]
Replace UseDefaultCompiler with GetAttr (#5088)
Tianqi Chen [Tue, 17 Mar 2020 20:23:43 +0000 (13:23 -0700)]
Change Azure pipeline badge to GH actions (#5081)
Tianqi Chen [Tue, 17 Mar 2020 17:59:23 +0000 (10:59 -0700)]
[RELAY][PY] Fix relay node registration after refactor (#5083)
Zhi [Tue, 17 Mar 2020 15:33:10 +0000 (08:33 -0700)]
[Refactor][Relay] Refactor Relay Python to use new FFI (#5077)
* refactor relay python
* revert relay/ir/*.py to relay
* Address comments
* remove direct access to analysis and transform namespace
Mahesh Ambule [Tue, 17 Mar 2020 06:54:32 +0000 (12:24 +0530)]
[Relay, TF Frontend] Dilation2D operator support (#5033)
* update docs for dilation 2d
* dilation2d compute
* dilation2d register
* dilation2d rel compute
* dilation2d strategy
* dilation2d attrs
* dilation2d generic schedule
* dilation2d tf frontend support
* dilation2d tf frontend test case
* dilation2d test cases
* pylint fixes
* add exception for cuda target
* Update docstring
* Update docstring
* change rates to dilations
* removed unused param
* merge master
* Update nn.py
* Update nn.py
Samuel [Mon, 16 Mar 2020 19:57:06 +0000 (01:27 +0530)]
[TFLITE]DepthToSpace and SpaceToDepth support (#5041)
* [TFLITE]DepthToSpace and SpaceToDepth op parser support
* DepthToSpace and SpaceToDepth testcases
* Review comments fixed
Samuel [Mon, 16 Mar 2020 19:55:48 +0000 (01:25 +0530)]
Tensorflow script upgrade from 1.13.1 to 2.0.0, so that it can run in both versionsw (#4963)
Ruizhe Zhao [Mon, 16 Mar 2020 19:52:45 +0000 (19:52 +0000)]
Return empty CSourceModule when no lowered_funcs exists in Relay mod (#4847)
* Use dummy func when no lowered_funcs exists in Relay mod
* Dummy func -> CSourceModule with empty code str
* Added comments describing the empty CSouceModule
* Always import external modules w/o assertions
* Use CSourceModule as a fallback for LLVMModule
* Changed cond for target == llvm
* Create an empty LLVM module w/o using dummy func
* Avoid using IR str concat to create LLVM module
* Improved comments for codegen.LLVMModuleCreate
* Satisfy the linter for LLVMModuleCreate
Yizhi Liu [Mon, 16 Mar 2020 10:01:54 +0000 (03:01 -0700)]
[Team] jwfromm -> reviewer (#5076)
Tianqi Chen [Sun, 15 Mar 2020 22:39:47 +0000 (15:39 -0700)]
[IR] Update the type_keys to reflect the code-org (#5074)
masahi [Sun, 15 Mar 2020 20:43:48 +0000 (05:43 +0900)]
[Relay, TOPI] Refactor Adaptive pool and add 3d support (#5049)
* add stub for nd impl
* refactored indices compute
* refactored divide step
* remove unused variables, add doc
* fix lint
* add relay op def
* add python registration
* refactor topi test
* update relay tests, but test result is weird
* workaround for weird bug
* add relay adaptive pool 3d test
* add topi tests
* update doc for 3d
* typo fix
* fix lint
* add more tests including NDHWC
ojotoxy [Sun, 15 Mar 2020 19:02:59 +0000 (12:02 -0700)]
Add support for FusedBatchNormV3 (#5065)
No changes seem to be needed to _fused_batch_norm. It just works.
Tianqi Chen [Sun, 15 Mar 2020 04:40:50 +0000 (21:40 -0700)]
[TESTS] Triage the testcases to fit the the new namespaces (#5071)
* [TESTS] Triage the testcases to fit the naming convention of the new namespaces
* Remove multiple usage of system lib to avoid test problems
Tianqi Chen [Sat, 14 Mar 2020 21:26:23 +0000 (14:26 -0700)]
[TIR] Introduce tir::PrimFunc (#5070)
This PR introduces tir::PrimFunc which will be used as the TIR function
container in the unified IR.
Also streamlined the function attributes a bit further.
- All common attributes are under tvm::attr
- TIR specific attributes are under tvm::tir::attr and comes with a tir prefix
- Use stl_style for attributes for now
Jared Roesch [Sat, 14 Mar 2020 04:02:03 +0000 (21:02 -0700)]
[COMMUNITY] Add @abergeron -> reviewer (#5064)
masahi [Fri, 13 Mar 2020 22:11:32 +0000 (07:11 +0900)]
[Torch, QNN] Remove FP32 piggy back and use QNN add/mul/concatenate (#5061)
* use qnn add/mul/concatenate
* remove logging
Bernhard [Fri, 13 Mar 2020 21:44:14 +0000 (22:44 +0100)]
[Relay][AutoTVM] Bug Fix for ARM CPUs. Lower strict assumption. (#5063)
anwang2009 [Fri, 13 Mar 2020 20:58:49 +0000 (13:58 -0700)]
[Relay][Pass] Add submodule extraction pass (#4960)
* rebased
* fix lint
zhen-jia [Fri, 13 Mar 2020 17:07:06 +0000 (10:07 -0700)]
[Graph tuner]Add opt out operator for has_multiple_inputs for graph tuner (#5000)
* consider layout_transform in has_multiple_inputs
* refactor code
* remove debug info
* remove subclass assignment
* refactoring a little bit
* remove default value
* remove trailing whitespace
* modify test for has_multiple_inputs
Co-authored-by: Ubuntu <ubuntu@ip-172-31-40-194.us-west-2.compute.internal>
Tianqi Chen [Fri, 13 Mar 2020 03:23:56 +0000 (20:23 -0700)]
[DOCS] Move git_howto to rst, add Stage documents to te (#5055)
Tianqi Chen [Fri, 13 Mar 2020 03:22:38 +0000 (20:22 -0700)]
[PY] Require python3.6 (#5057)
Andrew Liu [Fri, 13 Mar 2020 00:22:19 +0000 (17:22 -0700)]
maintenance (#5058)
Tianqi Chen [Thu, 12 Mar 2020 23:29:06 +0000 (16:29 -0700)]
[Bugfix][IR][ATTRS] Fix AttrEqual for Array and StrMap, double (#5054)
- Use fuzzy comparison for double.
- Removed the hack for BatchNormAttrs and DictAttr.
Also removed a warning from text printer printing.
Tianqi Chen [Thu, 12 Mar 2020 22:31:56 +0000 (15:31 -0700)]
[C++] Require c++14 by default (#5056)
Marcus Shawcroft [Thu, 12 Mar 2020 17:13:22 +0000 (17:13 +0000)]
CI: Install apt-transport-https (#5053)
The ubuntu_install_llvm.sh script started failing because of a http to
https redirect. This patch adds the package that allows apt to handle
https transport.
Change-Id: I70bcba32a9fc75d02c54f4f21f288b2f46226689
Haichen Shen [Thu, 12 Mar 2020 17:01:22 +0000 (10:01 -0700)]
[Autotvm] Fix autotvm customized template (#5034)
* init
* fix template
* tweak naming
Animesh Jain [Thu, 12 Mar 2020 16:51:09 +0000 (09:51 -0700)]
[Strategy] Support for Int8 schedules - CUDA/x86 (#5031)
* [CUDA] Op strategy changes for Int8 schedules.
* Applying Haichen's suggestions.
* Make 4D output work for task extraction.
* Make x86 work.
* Fix lint.
* Lint fixes.
* Tests, comments, out channel a multiple of 4.
* Topi test.
Co-authored-by: Ubuntu <ubuntu@ip-172-31-38-96.us-west-2.compute.internal>
ANSHUMAN TRIPATHY [Thu, 12 Mar 2020 16:50:13 +0000 (22:20 +0530)]
[1] Test case modified for int type (#5012)
pankratz [Thu, 12 Mar 2020 16:35:36 +0000 (10:35 -0600)]
Fixed div by zero core dump. Fixed rounding intrinsics on int crash (#5026)
Tianqi Chen [Thu, 12 Mar 2020 15:33:47 +0000 (08:33 -0700)]
[REFACTOR] Streamline Function Attr interface. (#5045)
* [REFACTOR] Streamline Function Attr interface.
There has been quite a few recent changes that depends heavily on
the function attr interface. This PR streamlines that interface by introducing
two APIs that covers most of the usages.
- GetAttr which gets a typed object for a given key
- HasNonzeroAttr is a quick helper that calls GetAttr to quickly check an attribute
- WithAttr that creates a new function object with the given attr
- The API comes with copy on write optimization to avoid multiple copies
- We deliberately pick the prefix With(instead of Set) to indicate this
function does not mutate the original input.
On the python side:
- We allow read access via func.attrs (which is a DictAttr)
- func.with_attrs to create a new instance with updated attrs.
We also get rid of the small wrapper functions and make sure the API centered around
the GetAttr and HasNonzeroAttr interface.
This PR also changes the function construction to follow the new convention.
* Address review comments
* Address review comments
* Fix doxygen path
Samuel [Thu, 12 Mar 2020 07:11:37 +0000 (12:41 +0530)]
[TFLITE][FRONTEND]Reduce_any op parsing support (#4926)
* [TFLITE][FRONTEND]Reduce_any op parsing support
* Testcase check added to run in tf version above 1.14.0 & review comments
* Review comment, checked updated to 1.15
Samuel [Thu, 12 Mar 2020 07:09:45 +0000 (12:39 +0530)]
[TFLITE]Round op parsing support added (#5022)
Fernand Pajot [Thu, 12 Mar 2020 07:09:00 +0000 (01:09 -0600)]
Support for AddV2 in Relay Tensorflow frontend converter. (#5046)
yongfeng-nv [Thu, 12 Mar 2020 03:59:23 +0000 (23:59 -0400)]
Set split node's range to minimum of ext and split factor or split nparts, but only when PassDownDomain is called with allow_missing == false, i.e. by InferBound. Add a helper PassUpThreadBinding() to get a map telling whether an IterVar has at least one leaf IterVar deriving from it binding to a thread. Add two unit tests. (#5044)
Thierry Moreau [Thu, 12 Mar 2020 03:59:03 +0000 (20:59 -0700)]
[VTA] VTA hardware/software codebase re-org (#5037)
Zhi [Thu, 12 Mar 2020 03:47:21 +0000 (20:47 -0700)]
[refactor][relay pass] Separate analysis and transform passes (#5035)
* [refactor][relay pass] Separate analysis and transform passes into different subfolders
* remove pass folder
Wei Chen [Wed, 11 Mar 2020 22:53:01 +0000 (06:53 +0800)]
[Object] Add String container (#4628)
ANSHUMAN TRIPATHY [Wed, 11 Mar 2020 21:36:39 +0000 (03:06 +0530)]
Conditions updated to cover better user scenarios[Re-raised] (#5043)
* Conditions updated to cover better user scenarios
* [1] New test case added
* [2] New test case added
* [3] Proper variable name used
* [4] Review Comments handled
* [5] Review comments handled
* [6] Review comments handled
Wei Chen [Wed, 11 Mar 2020 19:26:28 +0000 (03:26 +0800)]
[Relay][VM] Fix compilation of If-Elses (#5040)
Matthew Brookhart [Wed, 11 Mar 2020 16:03:30 +0000 (09:03 -0700)]
Conv3D ONNX support and conv3D_ncdhw x86 schedules (#4949)
* Support 3d Convolution with the ONNX frontend
* add unit tests for conv3d in onnx frontend
respond to PR formatting requests
add x86 schedules to conv3d ncdhw test
fix a doc string format issue
refactor for changed upsream API
* first attempt at conv3d autotuning
add default schedule for conv3d_ncdhw
fill in autotvm integration
add a fallback for invalid schedules
fix fallback
fix reduction order to get simd working correctly
Bing Xu [Wed, 11 Mar 2020 15:58:20 +0000 (08:58 -0700)]
[Intrin] Adding a few missing math intrin (#5011)
* [intrin] exp2
* [intrin] exp10
* [intrin] log2/10
* [intrins] exp10
* [test] math intrin
Lianmin Zheng [Wed, 11 Mar 2020 15:57:30 +0000 (08:57 -0700)]
Revert "Tighten split's extent (#4931)" (#5027)
This reverts commit
585f9ce6e7bef7d0e8902b1c1e55dcb3bbe84eed.
Tianqi Chen [Wed, 11 Mar 2020 15:56:03 +0000 (08:56 -0700)]
Revert "Conditions updated to cover better user scenarios (#4951)" (#5032)
This reverts commit
fe74b37ab578e6d3c540b0f6ac187a220ccc028a.
Animesh Jain [Wed, 11 Mar 2020 15:30:13 +0000 (08:30 -0700)]
[QNN] Support 4D padding. (#5036)
* [QNN] Support 4D padding.
* Empty commit.
Co-authored-by: Ubuntu <ubuntu@ip-172-31-38-96.us-west-2.compute.internal>
Samuel [Wed, 11 Mar 2020 03:08:48 +0000 (08:38 +0530)]
[TFLITE]Activation functions support (#4978)
* [TFLITE]elu, leaky_relu, lrn, log_softmax activation functions
* removed ops present in pr 4805
* review_comments updated
Wei Pan [Wed, 11 Mar 2020 02:16:59 +0000 (19:16 -0700)]
[CodeGen][CUDA] Enhance CUDA codegen for SelectNode (#4983)
- This patch allows CUDA backend to emit correct code for
selects with vector conditions, which may be produced
by floordiv op lowering etc..
- This already works for llvm BE, as llvm select instruction
supports vector conditions.
Signed-off-by: Wei Pan <weip@nvidia.com>
notoraptor [Wed, 11 Mar 2020 01:24:04 +0000 (21:24 -0400)]
[topi][relay] new PR to re-add tan to TVM (#5025)
* Add relay operation relay.op.tan.
* Update tan implementation in TVM.
* Update tests.
* Add shape function for tan.
* Add missing main test to python/frontend/tensorflow/test_forward.
* Revert, back to sin/cos.
* Revert "Revert, back to sin/cos."
This reverts commit
4da5b503b921585ba9d80944b29136142b575c40.
* Fix implementation of tan in cuda. Do not support tan for float16.
Simplify topi/tests/python/test_topi_math. Add testing for tan with float32 and float64.
Finally implement tan as sin/cos in llvm.
Tianqi Chen [Tue, 10 Mar 2020 18:46:56 +0000 (11:46 -0700)]
[CI] Temporary disable rust test (#5029)
masahi [Tue, 10 Mar 2020 17:59:09 +0000 (02:59 +0900)]
[Torch] Add initial control flow support (#4964)
* Add support for prim::If and prim::Loop with test cases
* rebase and fix tests
* add some comments
* simplifying, fix float cast
* parse -> convert
* recursivly retrive ops in get_all_op_names
* use multiple return values from block correctly, simplify loop convert
* choose dtype properly for zeros and ones
* simplifying, replace convert_inputs with _get_relay_input_vars
* fix for while loop with non input dependent init cond
* add assert on loop var update
* move the condition around
* better testing for seg models
* rebase fix, disable inception v3 in quant test as it is too slow to
load with torch-1.4 + torchvision 0.5
* simplify and add more comparison op converter
Yao Wang [Tue, 10 Mar 2020 09:37:12 +0000 (02:37 -0700)]
Revert "[topi][relay] add operation tan to TVM (#4938)" (#5017)
This reverts commit
d992468d80af816f0413fc43c2ee1c02f7fe19c3.
lhutton1 [Tue, 10 Mar 2020 08:10:07 +0000 (08:10 +0000)]
[RELAY] Remove primitive attribute from composite function (#5014)
* A composite function should not be primitive since we still may need to perform passes on it.
Change-Id: If62d06d265234861a6ec0df7749dc1c339c1055c
ANSHUMAN TRIPATHY [Tue, 10 Mar 2020 04:23:18 +0000 (09:53 +0530)]
Early checking added and new test cases added for schedule fuse (#5010)
* [1] New test case added for fuse
* [2] New test case added for fuse
* [3] New test case added for fuse
* [4] New test case added for fuse
* [5] Early check added
jmorrill [Tue, 10 Mar 2020 02:39:41 +0000 (19:39 -0700)]
Implemented kDLCPUPinned (cudaMallocHost) (#4985)
* implement kDLCPUPinned
* Fix line endings
* Fix whitespace for linter
* cleanup up allocdataspace method
Jared Roesch [Tue, 10 Mar 2020 02:35:20 +0000 (19:35 -0700)]
Revive the Rust + SGX refactor (#4976)
* Add Nick's changes's squashed
* Fix frontend compilation
* Re-enable Rust CI
* Add changes with conflicted badly
* Restructure import_module! macro in order to avoid unstable features
* Kill old unstable feature enablement
* Refactor common to use new APIs
* Move the code to stable
* Fix warning
Co-authored-by: Nick Hynes <nhynes@oasislabs.com>
masahi [Tue, 10 Mar 2020 01:36:50 +0000 (10:36 +0900)]
[REDO AFTER GH BUG] Add support for quantized models via QNN (#5016)
This reverts commit
f346c60287b50950275e20db9e6d84b3fc568a00.
Animesh Jain [Mon, 9 Mar 2020 20:14:58 +0000 (13:14 -0700)]
Revert "[Torch, QNN] Add support for quantized models via QNN (#4977)" (#5013)
This reverts commit
fc7f0783940c362bf48cd46817956381196201e2.
雾雨魔理沙 [Mon, 9 Mar 2020 19:50:23 +0000 (12:50 -0700)]
typo (#5008)
Liangfu Chen [Mon, 9 Mar 2020 18:21:28 +0000 (02:21 +0800)]
[Runtime] MISRA-C compliant TVM runtime (#3934)
* implement of MISRA-C compliant TVM runtime;
* working on bundle_deploy_c demo
* move header files into include dir
* fix compatibility issues
* fix compatibility issues
* resolve most of the warnings and errros
* implement c_backend_api
* introduce bridge
* working well
* move to header files and bundle.c into src/runtime/crt
* clean up
* satisfy linter
* clean up
* test with the cat image
* remove synset
* refactoring
* refactoring
* refactoring
* initial crt_runtime_api.c
* improved compatibility with g++
* using exposed API in c_runtime_api.h
* call from c_runtime_api.h
* clean up
* lint
* merge into apps/bundle_deploy directory
Change-Id: I51904db81b8589e65d107d8ca77b47452e3812b5
* make the demo runs in ci
Change-Id: I2c24f8b592508833d3555311c2b24d1931f19385
* address review comments
Change-Id: I027ddff15c31fb4da0bd0e461427dce619de1f93
* release
Change-Id: I5ad5bb8426468aac9fc8d074e56ddea358a7fd91
* fix ci testing
Change-Id: Ic2e82fb3051b6c254ef32a964f976b61e3e5fe4d
* add test case for misra c runtime
Change-Id: Ie0dfd0ade6be4665b4384db7d260a6c69b35010f
* fread files in testing to avoid calling xxd
Change-Id: Ie7fbc16b4b0b9509918d986a841f443900813bef
Pasquale Cocchini [Mon, 9 Mar 2020 17:09:13 +0000 (10:09 -0700)]
[VTA][Chisel,de10nano] Chisel fixes and de10nano support (#4986)
* [VTA][de10nano] Enable user defined target frequency.
Issue:
The VTA target frequency on the DE10-Nano is hardcoded to 50MHz
unnecessarily limiting performance.
Solution:
Add a PLL to the FPGA sub-system along with support for the
selection of a user specified frequency at build time. The board
successfully builds and runs at 100MHz.
* Added a PLL in the soc_system.tcl platform designer generator
script.
* Modified the Makefile to automatically set the target frequency
from that specified in the pkg_config.py file.
* Modified the Makefile to generate a bitstream with an RBF
format that enables programming of the FPGA directly from
the on-board processor. Specifically, the RBF is generated in
FastParallel32 mode with compression, which corresponds to the
default MSEL switch setting on the board, i.e. 01010.
* Added a false path override to file set_clocks.sdc to turn off
unconstrained path warnings on the VTA pulse LED.
* [VTA][TSIM] Add more debug and tracing options.
* Modified Makefile to change default config to DafaultDe10Config.
* Added option in Makefile to produce more detailed tracing
for extra observability in debugging complex scenarios.
* Added option in Makefile to produce traces in FST format which
are 2 orders of magnitude smaller, although much slower to
generate.
* Added option in Makefile to build the simulator with GCC address
sanitizer.
* Modified Makefile to not lint the scala code by default avoiding
unintended wrong indentation. Linting should be better performed
manually on a per-need basis.
* [VTA][de10nano] Enable remote programming of FPGA.
Issue:
The Cyclone V FPGA on board of the DE10-Nano can only be programmed
using the JTAG port, which is a limiting option for users.
Solution:
Add support for the remote programming of the FPGA implementing
the FPGA programming manager protocol published in the Cyclone V
user manual.
* Added file de10nano_mgr.h implementing an FPGA manager class
that supports handling of control and status registers as well
as a push-button option to program the FPGA. The class can be
easily extended to include more registers if needed.
* Used an instance of the FPGA manager to implement function
VTAProgram also warning users when incompatible bitstream
files are used.
* Registered VTAProgram as a global function and modified
the program_bitstream python class to use it.
* [VTA][de10nano] Enhance de10nano runtime support.
Issue:
The de10nano target has incomplete, non-working support
for runtime reconfiguration, bitstream programming, and
examples of usage.
Solution:
Complete runtime support for the de10nano target.
* Modified VTA.cmake to comment out a default override for
VTA_MAX_XFER to 21 bit wide.
* Modified VTA.cmake to add needed de10nano include dirs.
* Modified relevant files to support de10nano same way as
other targets for VTA runtime reconfiguration and FPGA
programming.
* Added test_program_rpc.py example as a runtime FPGA
programming example. Note that unlike the pynq target
no bitstream is either downloaded or programmed when
the bitstream argument is set to None.
* Cosmetic changes to vta config files.
* [VTA][Chisel] LoadUop FSM bug fix.
Issue:
The LoadUop FSM incorrectly advances the address of the next
uop to read from DRAM when the DRAM data valid bit is deasserted
and asserted at the end of a read. This is caused by a mismatch
in the logic of the state and output portions of the FSM.
This is one of two issues that was gating the correct operation
of VTA on the DE10-Nano target.
Solution:
Modify the logic of the output section of the FSM to include
a check on the DRAM read valid bit or fold the output assignemnt
into the state section.
* Folded the assignemnt of the next uop address in the state
section of the FSM.
* [VTA][Chisel] Dynamically adjust DMA tranfer size.
Issue:
In the DE10-Nano target and possibly in others, DMA transfers that
cross the boundaries of memory pages result in incorrect reads and
writes from and to DRAM. When this happens depending on different
input values, VTA loads and stores exhibit incorrect results for
DMA pulses at the end of a transfer. This is one of two issues that
were gating the DE10-Nano target from functioning correctly, but may
affect other Chisel based targets.
Solution:
Add support for dynamically adjustble DMA transfer sizes in load
and store operations. For a more elegant and modular implementation
the feature can be enabled at compile time with a static constant
that can be passed as a configuration option.
* Modified the load and store finite state machines to dynamically
adjust the size of initial and stride DMA transfers. The feature
is enabled by default by virtue of the static constant
ADAPTIVE_DMA_XFER_ENABLE.
* [VTA][Chisel] Improve FSIM/TSIM/FPGA xref debug.
Issue:
Cross reference between FSIM, TSIM, and Chisel based FPGA traces
is an invaluable instrument that enables fast analysis on FSIM,
and analysis/debug on TSIM and FPGA, especially for complex flows
like conv2d or full inferences. Currently this cannot be done
easily since a suitable reference is missing. The clock cycle
event counter cannot be used since it is undefined in FSIM and
not reliable between TSIM and FPGA because of different latencies.
Solution:
Introduce a new event counter that preserves a program order across
FSIM, TSIM, FPGA. We propose adding the accumulator write event
counter in the Chisel EventCounter class and a simple instrumentation
in the FSIM runtime code. Note that this technique enabled finding the
Chisel issues reportes in the PR, which would have been otherwise
far more difficult.
* Added the acc_wr_count event counter and changed interfaces
accordingly.
* [VTA][de10nano] Comply with linting rules.
* [VTA] Appease make lint.
* [VTA] Disable pylint import not top level error.
* [VTA][Chisel,de10nano] Linting changes.
* Use CamelCase class names.
* Use C++ style C include header files.
* Add comments to Chisel makefile.
* [VTA][de10nano]
* Reorder C and C++ includes in de10nano_mgr.h.
* Restore lint as default target in Chisel Makefile.
* [VTA][de10nano] Do not use f string in pkg_config.py.
* [VTA][de10nano] Remove overlooked f strings in pkg_config.py.
* [VTA][de10nano] Fixed typo.
* [VTA][TSIM] Check if gcc has align-new.
* [VTA][Chisel] Make adaptive DMA transfer default.
* [VTA][RPC] Renamed VTA_PYNQ_RPC_* to VTA_RPC_*.
Issue:
With more FPGA targets coming online the initial method of
using individual environment variables to specify target IP and port
does not scale well.
Solution:
Use a single VTA_RPC_HOST, VTA_RPC_PORT pair to be changed
every time a different target is used. For instance in a script
used to benchmark all targets.
* Replaced every instance of VTA_PYNQ_RPC_HOST and VTA_PYNQ_RPC_PORT
with VTA_RPC_HOST and VTA_RPC_PORT, respectively.
* [VTA][Chisel] Comply with new linter.
ANSHUMAN TRIPATHY [Sun, 8 Mar 2020 16:01:18 +0000 (21:31 +0530)]
Docs and Readme updated as per new namespace change (#4989)
Haichen Shen [Sun, 8 Mar 2020 11:51:02 +0000 (04:51 -0700)]
lower plevel of conv2d winograd on cuda (#4987)
Michal Jamroz [Sun, 8 Mar 2020 06:31:11 +0000 (07:31 +0100)]
kill from tvm import te (#5007)
Co-authored-by: Michal Jamroz <jamroz@chem.uw.edu.pl>
zhengdi [Sun, 8 Mar 2020 06:27:56 +0000 (14:27 +0800)]
[FRONTEND][TENSORFLOW] support multiply outputs (#4980)
* [FRONTEND][TENSORFLOW] support multiply outputs
* [TENSORFLOW][TEST] add tf_testing.AddShapesToGraphDef test
* update frontend test
* retrigger CI
lfengad [Sun, 8 Mar 2020 04:46:12 +0000 (12:46 +0800)]
Add BN support with run-time mean and variance calculation (#4990)
Liangfu Chen [Sat, 7 Mar 2020 18:42:44 +0000 (02:42 +0800)]
[VTA][Chisel] Change Scala Linter scalafmt => scalastyle (#4998)
* scalafmt => scalastyle
Change-Id: Ifc590e7cb63585f35dfdc9efcf3c6287b1afb1dd
* scalafmt => scalastyle
Change-Id: I8aff2632dadda05d2896e28bdaf6f780a160a15a
* add indentation constraint
Change-Id: Ibeb00c11a5718ea47322ea2b82e757828af8af91
* trigger ci again
Tianqi Chen [Sat, 7 Mar 2020 07:19:38 +0000 (01:19 -0600)]
[COMMUNITY] @optima2005 -> reviewer (#5004)
Zhi [Sat, 7 Mar 2020 04:30:13 +0000 (20:30 -0800)]
[relay][external codegen] outline and inline lifted functions for external codegen (#4996)
* outline and inline lifted functions for external codegen
* add batch_norm test
* test batch_norm inline
Thomas Viehmann [Sat, 7 Mar 2020 00:44:24 +0000 (01:44 +0100)]
fix ROCm strategy for winograd conv selection (#5001)
Jeremy Johnson [Sat, 7 Mar 2020 00:40:50 +0000 (00:40 +0000)]
[Frontend][Torch] Check graph inputs match expected (#4992)
* [Frontend][Torch] Check graph inputs match expected
* error/warn when missing/unused graph inputs
* Change to use get_graph_input_names
pyjhzwh [Sat, 7 Mar 2020 00:39:33 +0000 (19:39 -0500)]
Fix stride default value None in torch.nn.functional.avg_pool (#4984)
* fix unordered dictionary problem for python version 3.5
* modify style
* default value of stride in torch.nn.functional.avg_pool is None
* delete prev modifications
* add testcase for nn.functional.avg_pool2d
Jon Soifer [Fri, 6 Mar 2020 23:54:03 +0000 (15:54 -0800)]
[Runtime] Export GraphRuntime in tvm_runtime.dll (#5002)
Co-authored-by: Jon Soifer <jonso@microsoft.com>
Yao Wang [Fri, 6 Mar 2020 01:17:35 +0000 (17:17 -0800)]
[topi][relay] add operation tan to TVM (#4938)
* Add relay operation relay.op.tan.
* Update tan implementation in TVM.
* Update tests.
* Add shape function for tan.
* Add missing main test to python/frontend/tensorflow/test_forward.
* Revert, back to sin/cos.
* Revert "Revert, back to sin/cos."
This reverts commit
4da5b503b921585ba9d80944b29136142b575c40.
* Fix implementation of tan in cuda. Do not support tan for float16.
Simplify topi/tests/python/test_topi_math. Add testing for tan with float32 and float64.
Try again to implement tan as sin/cos in llvm.
Tianqi Chen [Fri, 6 Mar 2020 01:15:19 +0000 (19:15 -0600)]
Adding Hua Jiang as reviewer. (#4993)
Zhi [Thu, 5 Mar 2020 23:56:44 +0000 (15:56 -0800)]
hotfix gcn tutorial fail (#4994)
Zhi [Thu, 5 Mar 2020 15:37:26 +0000 (07:37 -0800)]
refactor build module to take IRModule (#4988)
Tianqi Chen [Thu, 5 Mar 2020 00:35:38 +0000 (18:35 -0600)]
Conditions updated to cover better user scenarios (#4951)
* Conditions updated to cover better user scenarios
* [1] New test case added
* [2] New test case added
* [3] Proper variable name used
* [4] Review Comments handled
* [5] Review comments handled
* [6] Review comments handled
Tianqi Chen [Thu, 5 Mar 2020 00:34:08 +0000 (18:34 -0600)]
Fix gpu not found when running TVM docker (#4975)
Animesh Jain [Wed, 4 Mar 2020 19:24:56 +0000 (11:24 -0800)]
[Torch, QNN] Add support for quantized models via QNN (#4977)
* qnn support initial import
* fix upsampling num input
* imagenet tests added
* add qunatized module tests
* quantized module tests working
* imagenet test working
* fix lint
* remove top level torch import to fix ci error
* disable lint warning on outside toplevel import
* revert parse -> convert change
* add comments to qnn translation
* address comments, add sample outputs
* add more comments
* refactor bias add and requantize step
Lianmin Zheng [Wed, 4 Mar 2020 18:52:02 +0000 (10:52 -0800)]
Tighten split's extent (#4931)
* Set split node's range to minimum of ext and split factor or split nparts, but only when PassDownDomain is called with allow_missing == false, i.e. by InferBound. Add a helper PassUpThreadBinding() to get a map telling whether an IterVar has at least one leaf IterVar deriving from it binding to a thread. Add two unit tests.
* Enhance LoopVectorizer for vectorizing by 0. Found at least one case from testtopi/tests/python/test_topi_transform.py::test_tile.
* Revert changes vectorize_loop.cc; when parent's ext is zero, set split's range to the factor or nparts.
* Update with comments.
* Refactor the ext tightening predicate.
* Fix reference types.
* Integrate tvm.te changes.
* Trivial comment change to trigger CI.
* Trivial comment correction to trigger testing.
pyjhzwh [Wed, 4 Mar 2020 09:40:37 +0000 (04:40 -0500)]
[Torch] fix unordered dictionary problem for python version under 3.6 (#4982)
* fix unordered dictionary problem for python version 3.5
* modify style
Zhi [Tue, 3 Mar 2020 09:30:28 +0000 (01:30 -0800)]
[Relay] Target annotation for external codegen (#4933)
* op based external compiler annotation
* Use TVM register directly
* Small fix
* test graph
Co-authored-by: Cody Yu <comaniac0422@gmail.com>
Leandro Nunes [Tue, 3 Mar 2020 03:41:31 +0000 (03:41 +0000)]
Pin xgboost dependency version to 0.90 (#4965)
* Sets xgboost dependency to be 0.90, preventing
segfaults during TVM python unit tests execution
* This is discussed in issue #4953
maheshambule [Mon, 2 Mar 2020 20:57:40 +0000 (02:27 +0530)]
[Frontend] [Tensorflow] ReadVariableOp operator support (#4952)
* tf frontend read variable op
* pylint fix
* tf frontend freezed graph pruned ops
Zhi [Mon, 2 Mar 2020 06:23:46 +0000 (22:23 -0800)]
[Relay][Pass] Add inline pass (#4927)
* add inline pass
* IsInline -> IsMarkedInlined
* fix comment
Ethan-Yan27 [Mon, 2 Mar 2020 06:00:08 +0000 (14:00 +0800)]
[Doc]refine the example description of max/min/sum/tag_scope (#4974)
Samuel [Mon, 2 Mar 2020 03:16:46 +0000 (08:46 +0530)]
[TFLITE]FLOOR_MOD & FLOOR_DIV support (#4971)
* TFLite Floor_div & floor_mod parsing code
* Review comment updated
Animesh Jain [Sun, 1 Mar 2020 21:57:24 +0000 (13:57 -0800)]
[Relay][FastMath] Relay pass to use fast exp/tanh (#4873)
* [Relay][FastMath] Relay pass to use fast exp/tanh
* Adding required_pass to the tests.
* FastMath test changes.
zhengdi [Sun, 1 Mar 2020 16:33:59 +0000 (00:33 +0800)]
[TOPI] fix docs errors (#4973)
masahi [Sun, 1 Mar 2020 00:51:49 +0000 (09:51 +0900)]
[Torch] Upsampling op support and enable registering a user defined op conversion map (#4961)
* add custom conversion map
* add roi align test using custom convert map
* refactor test
* add support for upsampling op and test on segmentation models
* remove redundant no_grad
* add upsampling test case
* make the default custom map None, instead of empty dict
* updated tests, remove packaging and drop PT 1.2 support
* add better support for aten::to and tests
* add a note on dilation in x86
jmorrill [Sat, 29 Feb 2020 21:52:22 +0000 (13:52 -0800)]
Added CopyFromBytes and CopyToBytes convenience methods to NDArray. Fixed typos. (#4970)
* Added CopyFromBytes and CopyToBytes convenience methods. Fixed typos.
* Removed unneed argument check
* Use TVMArrayCopyFrom/ToBytes methods
* Moved CopyFrom/ToBytes to ndarray.cc
* CopyToBytes impl was using CopyFromBytes. Fixed
* changed inline to TVM_DLL
* Used impl from TVMArrayCopyTo/FromBytes into NDArray CopyTo/FromBytes
* Move implementation of all CopyFrom/ToBytes into a common impls
* make arg const
* simplify method impl
Ina Dobreva [Sat, 29 Feb 2020 21:30:16 +0000 (23:30 +0200)]
[Frontend][TFLite] Add parser support for l2_normalization (#4966)
* [Frontend][TFLite] Add parser support for l2_normalization
* TF doesn't provide uint8 support
* TFL does the normalization only if it's over the last axis
* TFL uses only the default value for expilon
* Change error message
Tianqi Chen [Fri, 28 Feb 2020 21:20:04 +0000 (13:20 -0800)]
[DOCS] Fix sphinx precheck (#4967)
* [DOCS] Fix sphinx precheck
* ignore keras warnings
* Remove more warnings
masahi [Fri, 28 Feb 2020 02:59:15 +0000 (11:59 +0900)]
[Relay, Torch] Clean up and refactor PyTorch frontend (#4944)
* The initial import of refactored implementation, all tests passed
* enable mobilenet v2 test
* minor cleanup
* reorg
* fix lint
* use input names that come with torch IR
* fix typo
* introduce parse_operators
* fix lint
* add _ prefix
Tianqi Chen [Fri, 28 Feb 2020 02:57:18 +0000 (18:57 -0800)]
[CI] Add pre-check script to check sphinx doc build. (#4956)
Introduce the check stage to the unittest stage for now
so we don't have to rebuild CI images.
As we make additional CPU images to make use of the sphinx,
consider move it to an earlier stage.
Cody Yu [Fri, 28 Feb 2020 02:57:07 +0000 (18:57 -0800)]
fix doc warning (#4959)
Tianqi Chen [Thu, 27 Feb 2020 22:27:37 +0000 (14:27 -0800)]
[DOCS] Sphinx -- Introduce alias detection. (#4954)
* [DOCS] Sphinx -- Introduce alias detection.
Background: some of our namespaces import function from another
namespace. For example tvm.te imports most of the operators from tvm.tir.
Previously we manually exclude these aliases from the doc.
However that means we can not link them by the alias name.
This PR adds a sphinx callback plugin to detect such aliases, and create a rubric block
on the button of its current docstring `Alias of the original class`.
It is done in a way so that we can refer to the generated docs.
We also fixed a few docs errors.
* Fix most of the issues