Rob Clark [Thu, 17 Nov 2022 21:53:07 +0000 (13:53 -0800)]
freedreno/drm: Add optimized path for freeing many BOs
Submits tend to hold references to a lot of BOs, which get unref'd when
the submit is destroyed/retired. For now, all this does is reduce lock
aquire/release, but the next commit will build on it.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19832>
Alyssa Rosenzweig [Thu, 17 Nov 2022 23:10:11 +0000 (18:10 -0500)]
asahi: Add batch tracking logic
We already have the notion of an agx_batch, which encapsulates a render
pass. Extend the logic to allow multiple in-flight batches per context, avoiding
a flush in set_framebuffer_state and improving performance for certain
applications designed for IMRs that ping-pong unnecessarily between FBOs. I
don't have such an application immediately in mind, but I wanted to get this
flag-day out of the way while the driver is still small and flexible.
The driver was written from day 1 with batch tracking in mind, so this is a
relatively small change to actually wire it up, but there are lots of little
details to get right.
The code itself is mostly a copy/paste of panfrost, which in turn draws
inspiration from freedreno and v3d.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19865>
Alyssa Rosenzweig [Thu, 17 Nov 2022 23:31:41 +0000 (18:31 -0500)]
asahi: Use the batch for submission
So we can submit background batches.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19865>
Alyssa Rosenzweig [Thu, 17 Nov 2022 23:31:11 +0000 (18:31 -0500)]
asahi: Use batch_reads for sysvals
Required for proper resource tracking.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19865>
Alyssa Rosenzweig [Thu, 17 Nov 2022 23:23:23 +0000 (18:23 -0500)]
asahi: Use a pipe_framebuffer_state batch key
More convenient for batch tracking.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19865>
Alyssa Rosenzweig [Thu, 17 Nov 2022 23:17:50 +0000 (18:17 -0500)]
asahi: Use batch instead of ctx for pipelines
So we can support multiple batches later.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19865>
Alyssa Rosenzweig [Thu, 17 Nov 2022 22:22:45 +0000 (17:22 -0500)]
asahi: Hide ctx->batch
This will make it easier to support multiple batches.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19865>
Alyssa Rosenzweig [Thu, 17 Nov 2022 18:37:36 +0000 (13:37 -0500)]
asahi: Factor out prepare_for_map
This will be expanded, let's expand in the direction of less spaghetti.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19865>
Lionel Landwerlin [Mon, 14 Nov 2022 13:54:01 +0000 (15:54 +0200)]
intel/fs: put scratch surface in the surface state heap
In
4ceaed7839af we made scratch surface state allocations part of the
internal heap (mapped to STATE_BASE_ADDRESS::SurfaceStateBaseAddress)
so that it doesn't uses slots in the application's expected 1M
descriptors (especially with vkd3d-proton).
But all our compiler code relies on BSS
(STATE_BASE_ADDRESS::BindlessSurfaceStateBaseAddress).
The additional issue is that there is only 26bits of surface offset
available in CS instruction (CFE_STATE, 3DSTATE_VS, etc...) for
scratch surfaces. So we need the drivers to put the scratch surfaces
in the first chunk of STATE_BASE_ADDRESS::SurfaceStateBaseAddress
(hence all the driver changes).
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
4ceaed7839af ("anv: split internal surface states from descriptors")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7687
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19727>
Lionel Landwerlin [Tue, 15 Nov 2022 12:26:38 +0000 (14:26 +0200)]
iris: move bindless surface state heap inside the surface state heap
We're about to make scratch surface states part of the surface state
heap. Because those are required to be in the low 26bits parts surface
state heap (we're limited in bits handed in the CFE_STATE, 3DSTATE_VS,
etc... instructions), this change splits the 32bit surface state heap
as follow:
- 8Mb of surface states for scratch
- 1Gb - 8Mb of binding tables
- 3Gb of surface states
That way all of the surfaces are located within a 4Gb region visible
from STATE_BASE_ADDRESS::SurfaceStateBaseAddress
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19727>
Lionel Landwerlin [Thu, 17 Nov 2022 10:42:16 +0000 (12:42 +0200)]
iris: prevent crash in decoder
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19727>
Bas Nieuwenhuizen [Sun, 13 Nov 2022 02:13:55 +0000 (03:13 +0100)]
radv: Convert instance bvh address to node in bvh build.
So we don't have to do it in the traversal loop. Should 2 and
instructions and a 64-bit shift, so 4/8 cycles per instance node
visit.
Totals from 7 (0.01% of 134913) affected shaders:
CodeSize: 208460 -> 208292 (-0.08%)
Instrs: 38276 -> 38248 (-0.07%)
Latency: 803181 -> 803142 (-0.00%)
InvThroughput: 165384 -> 165376 (-0.00%)
Copies: 4912 -> 4905 (-0.14%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19706>
Bas Nieuwenhuizen [Sat, 12 Nov 2022 01:52:25 +0000 (02:52 +0100)]
radv: Fiddle with opaque flag positions to reduce instructions.
Totals from 7 (0.01% of 134913) affected shaders:
CodeSize: 209076 -> 208460 (-0.29%)
Instrs: 38374 -> 38276 (-0.26%)
Latency: 803899 -> 803181 (-0.09%)
InvThroughput: 165530 -> 165384 (-0.09%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19706>
Bas Nieuwenhuizen [Sat, 12 Nov 2022 01:13:17 +0000 (02:13 +0100)]
radv: Skip and for node_to_addr with bvh_base.
Cause the bvh base is always 64 byte aligned.
Totals from 7 (0.01% of 134913) affected shaders:
CodeSize: 209216 -> 209076 (-0.07%)
Instrs: 38402 -> 38374 (-0.07%)
Latency: 804537 -> 803899 (-0.08%)
InvThroughput: 165663 -> 165530 (-0.08%)
Copies: 4919 -> 4912 (-0.14%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19706>
Bas Nieuwenhuizen [Fri, 11 Nov 2022 21:43:25 +0000 (22:43 +0100)]
radv: Move ray flag compares out of the loop.
To save on and+cmp combos with VALU instructions.
Totals from 7 (0.01% of 134913) affected shaders:
CodeSize: 208476 -> 209216 (+0.35%)
Instrs: 38384 -> 38402 (+0.05%)
Latency: 805725 -> 804537 (-0.15%)
InvThroughput: 165906 -> 165663 (-0.15%)
Copies: 4936 -> 4919 (-0.34%)
PreSGPRs: 393 -> 430 (+9.41%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19706>
Lionel Landwerlin [Wed, 16 Nov 2022 13:23:35 +0000 (15:23 +0200)]
Revert "nir/lower_shader_calls: put inserted instructions into a dummy block"
This reverts commit
35d82ecf1ee117bef575731100fa6ae532f225fc.
Cc: mesa-stable
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19820>
Lionel Landwerlin [Wed, 16 Nov 2022 15:34:08 +0000 (17:34 +0200)]
nir/lower_shader_calls: wrap only jumps rather than entire code blocks
Moving entire chunks of code into a dummy if block is causing issues
in some situations. To work around the issue that we tried to fix in
35d82ecf1e ("nir/lower_shader_calls: put inserted instructions into a
dummy block") which is that we cannot cut and past a block of
instruction that ends with a jump if there are more instruction behind
where we're going to past. We can instead just wraps the jumps into
dummy if blocks.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19820>
Lionel Landwerlin [Wed, 16 Nov 2022 15:36:19 +0000 (17:36 +0200)]
nir/lower_shader_calls: update metadata before validation
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19820>
Konstantin Seurer [Tue, 15 Nov 2022 17:36:09 +0000 (18:36 +0100)]
radv/bvh: Adjust sah cost based on depth
Adds a cost field to radv_ir_node and uses it to model the cost of tree
depth. This improves framerates by 2% if my benchmarking is correct.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19756>
Ian Romanick [Thu, 17 Nov 2022 20:47:59 +0000 (12:47 -0800)]
nir/range_analysis: Set higher default maximum for max_workgroup_count
Fixes:
c2a81ebe19f ("nir: Add default unsigned upper bound configuration.")
Closes: #7676
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19835>
Caio Oliveira [Fri, 18 Nov 2022 00:16:06 +0000 (16:16 -0800)]
iris: Pass devinfo directly in iris_setup_uniforms
Instead of reaching through brw_compiler. This will make easy
future changes on brw_compiler side.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19836>
Michael Skorokhodov [Thu, 17 Nov 2022 22:59:38 +0000 (00:59 +0200)]
intel/compiler: Require C++17
Fixes:
6c194ddd18f ("intel/compiler: Prepare SIMD selection helpers to handle different prog_datas")
Signed-off-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19833>
Alyssa Rosenzweig [Thu, 17 Nov 2022 17:12:29 +0000 (12:12 -0500)]
asahi: Don't support 16-bit vertex attributes
Currently broken, let vbuf deal with it. "Fixes" sysprof.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
Alyssa Rosenzweig [Thu, 17 Nov 2022 16:22:25 +0000 (11:22 -0500)]
asahi: Fix logic ops
Need to set colour mask correctly. Fixes spec@!opengl 1.0@gl-1.0-logicop@GL_AND,
at least the non-MSAA portion.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
Alyssa Rosenzweig [Tue, 8 Nov 2022 20:18:28 +0000 (15:18 -0500)]
asahi: Restrict rendering to what we support
Noticed with Kodi that tries to use rgb10a2.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
Alyssa Rosenzweig [Thu, 17 Nov 2022 22:44:27 +0000 (17:44 -0500)]
asahi: Don't validate WSI (twiddled) strides
These are made up and won't necessarily be aligned.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
Alyssa Rosenzweig [Thu, 10 Nov 2022 03:41:04 +0000 (22:41 -0500)]
asahi: Split out agx_usc.h into a common file
So the tilebuffer helpers can build the "shared" USC word. Also because Ella
will probably want to use these O:)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
Alyssa Rosenzweig [Thu, 10 Nov 2022 01:17:42 +0000 (20:17 -0500)]
asahi: Note some magic bits used with memoryless RTs
Obviously there can't *actually* be memoryless render targets, because
how would partial renders work? The control stream with memoryless looks
like everything would if it went to memory (e.g. full 2D MSAA
attachments for the partial loads/stores even if only a resolved
2D image for the final store). Except the memoryless attachments all
load from the same address 0xeeee0000. Clearly that's not actually what
happens, so what gives? Unclear... but I see the magic bits mentioned
here set, and I assume there are some firmware (or kernel) shenanigans
used to JIT allocate the backing storage for partial renders.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
Alyssa Rosenzweig [Sun, 23 Oct 2022 20:50:00 +0000 (16:50 -0400)]
asahi: Identify "Sample mask after depth/stencil" bit
Corresponds to Metal [[sample_mask,post_depth_coverage]].
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
Alyssa Rosenzweig [Sun, 23 Oct 2022 17:43:25 +0000 (13:43 -0400)]
asahi: Identify the pass type enum
Via PowerVR.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
Alyssa Rosenzweig [Sun, 23 Oct 2022 16:28:48 +0000 (12:28 -0400)]
asahi: Identify PBE sample count
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
Alyssa Rosenzweig [Sun, 23 Oct 2022 16:20:52 +0000 (12:20 -0400)]
asahi: Identify Dimension for Render Target
Metal uses when rendering to multisampled 2D.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
Alyssa Rosenzweig [Sun, 23 Oct 2022 14:54:33 +0000 (10:54 -0400)]
asahi: Fix agx_set_framebuffer_state for MRT
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
Alyssa Rosenzweig [Sun, 23 Oct 2022 14:54:12 +0000 (10:54 -0400)]
asahi: Set data_valid for the correct level
By inspection.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
Alyssa Rosenzweig [Sat, 22 Oct 2022 15:36:47 +0000 (11:36 -0400)]
asahi: Implement stencil texturing
Stencil texturing is easy: S8_UINT is textured like R8_UINT (with a
little swizzle fixup), and stencil is always S8_UINT thanks to
u_transfer_helper. So we just need to do some fixups to make
u_transfer_helper's seperate_stencil work and everything will work out.
Passes dEQP-GLES31.functional.stencil_texturing.*
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
Alyssa Rosenzweig [Sun, 23 Oct 2022 03:37:43 +0000 (23:37 -0400)]
asahi: Add internal formats for RGB10A2
We need to use I16 as the interchange format here. Fixes:
dEQP-GLES3.functional.fragment_out.basic.uint.rgb10_a2ui*
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
Alyssa Rosenzweig [Sun, 13 Nov 2022 02:22:00 +0000 (21:22 -0500)]
asahi: Implement perf_debug
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
Alyssa Rosenzweig [Sun, 13 Nov 2022 01:28:34 +0000 (20:28 -0500)]
asahi: Free the scanout resource
Fixes memory leaks with renderonly.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
Alyssa Rosenzweig [Sat, 12 Nov 2022 16:51:21 +0000 (11:51 -0500)]
agx: Handle collects in backwards isel
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
Alyssa Rosenzweig [Sat, 12 Nov 2022 16:37:49 +0000 (11:37 -0500)]
agx: Assert more invariants in RA
Was helpful for debugging.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
Alyssa Rosenzweig [Sat, 12 Nov 2022 16:35:26 +0000 (11:35 -0500)]
agx: Validate part of SSA form
To debug backend pass problems.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
Alyssa Rosenzweig [Tue, 8 Nov 2022 01:51:36 +0000 (20:51 -0500)]
agx: Split off NIR preprocessing from compiling
So we can specialize after lowering I/O.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
Alyssa Rosenzweig [Thu, 10 Nov 2022 14:49:42 +0000 (09:49 -0500)]
agx: Handle scalar texture destinations
Fixes dEQP-GLES3.functional.shaders.texture_functions.texturelod.sampler2dshadow_fragment.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
Alyssa Rosenzweig [Tue, 8 Nov 2022 01:36:35 +0000 (20:36 -0500)]
agx: Don't depend on GenXML
Separation of concerns, unused #include.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
Alyssa Rosenzweig [Tue, 8 Nov 2022 01:00:17 +0000 (20:00 -0500)]
agx: Lower packs/unpacks and bitfields
Needed for GLES3. These could be optimized.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
Yonggang Luo [Wed, 16 Nov 2022 15:49:50 +0000 (23:49 +0800)]
util: Move src/gallium/include/pipe/p_format.h to src/util/format/u_formats.h
Because p_format.h shared between vulkan drivers and opengl drivers
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19629>
David Heidelberg [Sat, 19 Nov 2022 00:09:20 +0000 (01:09 +0100)]
ci/freedreno: disable flaking Civilization V
See: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7491
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19862>
Yonggang Luo [Sun, 13 Nov 2022 02:47:55 +0000 (10:47 +0800)]
util: Rename PIPE_ALIGN_STACK to UTIL_ALIGN_STACK and moved into util/compiler.h
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19676>
Yonggang Luo [Mon, 7 Nov 2022 06:43:20 +0000 (14:43 +0800)]
llvmpipe: fixes error: ‘enum pipe_blendfactor’ declared in lp_test_blend.c
error message:
In file included from ../../src/gallium/drivers/llvmpipe/lp_test_blend.c:44:
../../src/gallium/drivers/llvmpipe/lp_bld_blend.h:47:21: error: ‘enum pipe_blendfactor’ declared inside parameter list will not be visible outside of this definition or declaration [-Werror]
47 | enum pipe_blendfactor factor_src,
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19676>
Yonggang Luo [Mon, 7 Nov 2022 09:43:20 +0000 (17:43 +0800)]
util: convert usage of uint to unsigned in u_format.h
Because uint comes from pipe/p_compiler.h, and that depends will be removed in future
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19676>
Yonggang Luo [Mon, 7 Nov 2022 06:12:11 +0000 (14:12 +0800)]
util: use void * instead of byte * for util_copy_rect in u_format.h
As ubyte comes from p_compiler.h, so do not use it,
and the code calles util_copy_rect may use args with type uint8_t*, ubyte* or unsigned char*,
so use the type void* that consistence with memcpy
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19676>
Yonggang Luo [Mon, 7 Nov 2022 05:53:53 +0000 (13:53 +0800)]
tgsi: fixes error: ‘enum pipe_shader_type’ declared in tgsi_info.h
error message:
../../src/gallium/auxiliary/tgsi/tgsi_info.h:92:30: error: ‘enum pipe_shader_type’ declared inside parameter list will not be visible outside of this definition or declaration [-Werror]
92 | tgsi_get_processor_name(enum pipe_shader_type processor);
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19676>
Yonggang Luo [Mon, 7 Nov 2022 10:05:40 +0000 (18:05 +0800)]
aco: fixes error: 'uint' was not declared in aco_instruction_selection.cpp
uint is from pipe/p_compiler.h
error message:
../../src/amd/compiler/aco_instruction_selection.cpp:11061:4: error: 'uint' was not declared in this scope; did you mean 'rint'?
11061 | uint en_mask = 1;
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19676>
Yonggang Luo [Sun, 6 Nov 2022 13:31:35 +0000 (21:31 +0800)]
util: Remove the usage of enum pipe_error in u_hash_table.*
Use 0 instead of PIPE_OK in u_hash_table.c
Because pipe_error and PIPE_OK is comes from pipe/p_defines.h that doesn't belong
to src/util/
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19676>
Yonggang Luo [Sun, 6 Nov 2022 13:21:41 +0000 (21:21 +0800)]
util: Remove redundant #include "util/u_inlines.h" in u_trace.c
util/u_inlines.h is comes from src/gallium/auxiliary/util/u_inlines.h,
so when possible, do not use it under src/util folder
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19676>
Caio Oliveira [Thu, 17 Nov 2022 22:49:56 +0000 (14:49 -0800)]
intel/compiler: Remove redundant argument from brw_nir_create_passthrough_tcs
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19831>
Mark Janes [Fri, 18 Nov 2022 18:59:41 +0000 (10:59 -0800)]
intel/perf: fix printf formatting of size_t for 32bit builds
Fixes:
bdacd6df5adc ("intel/perf: add a non installable tool to print metrics")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7736
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19856>
David Heidelberg [Fri, 18 Nov 2022 21:17:21 +0000 (22:17 +0100)]
ci/dzn: add flake
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19858>
David Heidelberg [Wed, 16 Nov 2022 23:13:12 +0000 (00:13 +0100)]
docs: update Python requirement to 3.7
Reported in https://gitlab.freedesktop.org/mesa/mesa/-/issues/7716
Reviewed-by: Eric Engestrom <eric@igalia.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19791>
Jason Ekstrand [Thu, 17 Nov 2022 17:06:53 +0000 (11:06 -0600)]
include: Update the OpenCL headers
This syncs all our headers with their canonical versions from Khronos.
Of particular note, CL headers repo does not have cl.hpp and cl2.hpp has
been depricated all in favor of opencl.hpp which is the new canonical
header. Fortunately, nothing in Mesa uses any of the C++ headers so
this shouldn't break anything.
Acked-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19816>
Jason Ekstrand [Thu, 17 Nov 2022 17:55:08 +0000 (11:55 -0600)]
clover: Use braces arround a union initializer
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19816>
Jason Ekstrand [Thu, 17 Nov 2022 16:21:50 +0000 (10:21 -0600)]
scripts: Fix khronos-update.py to use main for OpenCL headers
Also, cl.hpp no longer exists in OpenCL-Headers to fix it at the last
commit where it did exist.
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19816>
Jim Wu [Wed, 9 Nov 2022 14:54:56 +0000 (14:54 +0000)]
Update 00-mesa-defaults.conf
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19619>
Lionel Landwerlin [Wed, 16 Nov 2022 13:53:26 +0000 (15:53 +0200)]
nir/lower_explicit_io: fix metadata preserve
This pass can insert if blocks, therefore no dominance/block_index for
you.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19818>
Rhys Perry [Wed, 2 Nov 2022 16:49:18 +0000 (16:49 +0000)]
nir/lower_bit_size: lower uadd_sat/iadd_sat/isub_sat to unsaturated alu
The unsaturated arithmetic won't overflow/borrow, and may be faster.
No fossil-db changes.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19473>
Rhys Perry [Thu, 3 Nov 2022 13:05:41 +0000 (13:05 +0000)]
nir/lower_bit_size: optimize usub_sat lowering
The result should never be larger than uint_max. This doesn't need a
special path.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19473>
Rhys Perry [Wed, 2 Nov 2022 16:45:41 +0000 (16:45 +0000)]
nir/algebraic: optimize open-coded uadd_sat/usub_sat
fossil-db (navi21):
Totals from 19 (0.01% of 135636) affected shaders:
Instrs: 40730 -> 40688 (-0.10%)
CodeSize: 217708 -> 217568 (-0.06%)
Latency: 261466 -> 261373 (-0.04%)
InvThroughput: 74944 -> 74896 (-0.06%)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19473>
Rhys Perry [Wed, 2 Nov 2022 16:45:27 +0000 (16:45 +0000)]
radv: lower 8/16-bit uadd_carry/usub_borrow
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7615
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19473>
Rhys Perry [Wed, 2 Nov 2022 16:45:08 +0000 (16:45 +0000)]
nir/lower_bit_size: lower uadd_carry
8/16-bit uadd_carry can exist in SPIR-V.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7615
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19473>
Caio Oliveira [Thu, 17 Nov 2022 23:16:37 +0000 (15:16 -0800)]
crocus: Pass devinfo directly in crocus_setup_uniforms
Instead of reaching through brw_compiler. This will make easy
future changes on brw_compiler side.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19834>
Samuel Pitoiset [Mon, 7 Nov 2022 09:25:36 +0000 (10:25 +0100)]
radv: advertise extendedDynamicState3ColorBlendEnable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19579>
Samuel Pitoiset [Mon, 7 Nov 2022 12:21:22 +0000 (13:21 +0100)]
radv: add support for dynamic color blend enable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19579>
David Heidelberg [Fri, 18 Nov 2022 01:03:27 +0000 (02:03 +0100)]
ci/freedreno: temporarily disable godot-trive
Test if this trace impact surrounding traces causing rendering changes.
Ref: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7732
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19838>
David Heidelberg [Fri, 18 Nov 2022 01:00:43 +0000 (02:00 +0100)]
ci/panfrost: drop glmark2 traces, useless
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19838>
David Heidelberg [Fri, 18 Nov 2022 00:59:59 +0000 (01:59 +0100)]
ci/iris: drop glmark2 traces, useless
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19838>
David Heidelberg [Fri, 18 Nov 2022 00:59:07 +0000 (01:59 +0100)]
ci/llvmpipe: drop glmark2 traces, useless
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19838>
David Heidelberg [Fri, 18 Nov 2022 00:58:02 +0000 (01:58 +0100)]
ci/virgl: drop glmark2 traces, useless
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19838>
David Heidelberg [Fri, 18 Nov 2022 00:57:17 +0000 (01:57 +0100)]
ci/broadcom: drop glmark2 traces, useless
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19838>
David Heidelberg [Fri, 18 Nov 2022 00:56:49 +0000 (01:56 +0100)]
ci/freedreno: drop glmark2 traces, useless
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19838>
David Heidelberg [Fri, 18 Nov 2022 00:56:04 +0000 (01:56 +0100)]
ci/amd: drop glmark2 traces, useless
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19838>
Konstantin Seurer [Tue, 15 Nov 2022 14:33:29 +0000 (15:33 +0100)]
nir/lower_shader_calls: Get rid of any brw occurences
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19749>
Connor Abbott [Fri, 16 Sep 2022 14:24:17 +0000 (16:24 +0200)]
tu: Rewrite inline uniform implementation
Now we always push the inline uniforms, using an indirect CP_LOAD_STATE.
There is just enough space to be able to always push them if we expose
the minimum possible per-stage limits. This aligns us with Qualcomm and
removes the need to setup a uniform descriptor which will be
problematic.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18703>
Connor Abbott [Fri, 16 Sep 2022 14:00:07 +0000 (16:00 +0200)]
nir: Fix nir_chase_binding() vecN handling
In the comments we claimed to handle vecN instructions, for the case
where an offset is trimmed from the descriptor, but we didn't ignore the
offset itself and in effect only handled identity vecN's (which copy
propagation would normally remove already!), so the handling of vecN was
useless and this relied on copy propagation cleaning things up. Fix it
to ignore everything except the components in the original source.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18703>
Matt Coster [Fri, 21 Oct 2022 14:15:23 +0000 (15:15 +0100)]
pvr: Minor cleanup around pvr_emit_vdm_index_list()
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19802>
Michel Dänzer [Thu, 17 Nov 2022 09:12:59 +0000 (10:12 +0100)]
vulkan/wsi/wayland: Set num_modifier_lists = 0 if num_drm_modifiers == 0
This case was missed in
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18826 ,
resulting in native Wayland apps failing with
../src/vulkan/wsi/wsi_common_drm.c:452: wsi_configure_native_image: Assertion `!"Failed to find a supported modifier! This should never " "happen because LINEAR should always be available"' failed.
if the Wayland compositor advertises only the INVALID modifier.
Fixes:
c315e20d6198 ("vulkan/wsi/wayland: Configure images via params passed to wsi_swapchain_init()")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19795>
Matt Coster [Mon, 31 Oct 2022 11:03:10 +0000 (11:03 +0000)]
pvr: Support clear colours with more than 32 bits
The support for this seems to already exist, but was blocked by a
conditional. Replace with an assert to ensure the format can be packed
into 4x32 bit words (true for all currently supported formats).
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19799>
Karmjit Mahil [Wed, 16 Nov 2022 09:19:56 +0000 (09:19 +0000)]
pvr: Fix clang-format error.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19798>
Feng Jiang [Thu, 22 Sep 2022 07:48:09 +0000 (15:48 +0800)]
virgl/video: Check driver supported profiles and entrypoints
Since the support of video by the device and the driver may be
different, it is necessary to check on the driver side as well.
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18831>
Feng Jiang [Tue, 20 Sep 2022 08:43:43 +0000 (16:43 +0800)]
virgl/video: Add support for H.265 encoding
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Signed-off-by: Weishi Li <liweishi@kylinos.cn>
Signed-off-by: Liming Sun <sunliming@kylinos.cn>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18831>
Feng Jiang [Thu, 29 Sep 2022 03:38:20 +0000 (11:38 +0800)]
virgl/video: Add support for H.264 encoding
Implement encoding framework and support H.264 encoding.
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Signed-off-by: Ming Xie <xieming@kylinos.cn>
Signed-off-by: Liming Sun <sunliming@kylinos.cn>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18831>
Boyuan Zhang [Thu, 29 Sep 2022 03:26:25 +0000 (11:26 +0800)]
virgl/video: Pass "max_references" to backend when creating a video codec
The "max_references" is an important value in sequence parameters,
which will be used when encoding SPS headers.
Signed-off-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18831>
Feng Jiang [Thu, 29 Sep 2022 03:36:46 +0000 (11:36 +0800)]
frontends/va/enc: save intra_idr_period in the context
The va frontend loses some information when processing parameter
buffers, but the virgl video encoding driver needs it to work.
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18831>
Feng Jiang [Thu, 29 Sep 2022 03:35:58 +0000 (11:35 +0800)]
virgl/video: Move hardware-related definitions from virgl_video.h to virgl_video_hw.h
Considering the increasing number of hardware-related definitions,
it is better to put them in a separate file.
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18831>
Kenneth Graunke [Thu, 17 Nov 2022 20:20:30 +0000 (12:20 -0800)]
iris: Increase the maximum grid size
I had simply copied these values from another driver when adding initial
compute support to iris. The actual hardware limit is UINT32_MAX (see
the GPGPU_WALKER/COMPUTE_WALKER ThreadGroupID{X,Y,Z}Dimension fields).
Thanks to Karol Herbst for noticing the unnecessarily low limit.
References: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7676
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19826>
Chia-I Wu [Tue, 8 Nov 2022 19:59:43 +0000 (11:59 -0800)]
turnip: set ycbcr feature bits properly
Set ycbcr feature bits only for ycbcr formats. Besides, we can control
chroma locations only for planar formats and we support
VK_FORMAT_FEATURE_SAMPLED_IMAGE_YCBCR_CONVERSION_SEPARATE_RECONSTRUCTION_FILTER_BIT
on newer gens.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19609>
Chia-I Wu [Tue, 8 Nov 2022 19:15:54 +0000 (11:15 -0800)]
freedreno: add has_separate_chroma_filter to fd_dev_info
The blob driver does not support
VK_FORMAT_FEATURE_SAMPLED_IMAGE_YCBCR_CONVERSION_SEPARATE_RECONSTRUCTION_FILTER_BIT
before a6xx_gen3. It still sets CHROMA_LINEAR bit according to
chromaFilter, but the bit has no effect before a6xx_gen3 (confirmed on
a618 with blob version 512.490.0).
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19609>
Jami Kettunen [Thu, 10 Nov 2022 23:46:10 +0000 (01:46 +0200)]
freedreno: Find curses properly for building fdperf
Upstream ncurses doesn't ship any legacy ncurses.pc pkg-config symlinks
(just ncursesw.pc) which Void Linux strictly follows[1] for example.
Meson (since 0.54) has a generic curses dependency which works perfectly
in this case[2], thus also bump the toplevel minimum meson version from
0.53.
[1] https://github.com/void-linux/void-packages/tree/master/srcpkgs/ncurses
[2] https://mesonbuild.com/Dependencies.html#curses
Signed-off-by: Jami Kettunen <jami.kettunen@protonmail.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19664>
Yonggang Luo [Thu, 17 Nov 2022 20:47:36 +0000 (04:47 +0800)]
ci: Update dozen flakes
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7549
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19824>
Yonggang Luo [Fri, 4 Nov 2022 11:31:22 +0000 (19:31 +0800)]
svga: Fixes -Werror,-Wunused-but-set-variable for clang-15 in svga/svga_tgsi_vgpu10.c
error message:
../../src/gallium/drivers/svga/svga_tgsi_vgpu10.c:5199:13: error: variable 'indicesMask' set but not used [-Werror,-Wunused-but-set-variable] unsigned indicesMask = 0;
^
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19527>
Yonggang Luo [Fri, 4 Nov 2022 12:45:44 +0000 (20:45 +0800)]
softpipe: fixes -Werror,-Wunused-but-set-variable for clang-15 in sp_tile_cache.c
error message:
../../src/gallium/drivers/softpipe/sp_tile_cache.c:346:9: error: variable 'numCleared' set but not used [-Werror,-Wunused-but-set-variable]
uint numCleared = 0;
^
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19527>
projects / platform / upstream / mesa.git / log